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1/*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#include <linux/bitops.h>
22#include <linux/bug.h>
23#include <linux/compiler.h>
24#include <linux/delay.h>
25#include <linux/device.h>
26#include <linux/dma-mapping.h>
27#include <linux/firewire.h>
28#include <linux/firewire-constants.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/io.h>
32#include <linux/kernel.h>
33#include <linux/list.h>
34#include <linux/mm.h>
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/mutex.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/slab.h>
41#include <linux/spinlock.h>
42#include <linux/string.h>
43#include <linux/time.h>
44#include <linux/vmalloc.h>
45
46#include <asm/byteorder.h>
47#include <asm/page.h>
48#include <asm/system.h>
49
50#ifdef CONFIG_PPC_PMAC
51#include <asm/pmac_feature.h>
52#endif
53
54#include "core.h"
55#include "ohci.h"
56
57#define DESCRIPTOR_OUTPUT_MORE 0
58#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
59#define DESCRIPTOR_INPUT_MORE (2 << 12)
60#define DESCRIPTOR_INPUT_LAST (3 << 12)
61#define DESCRIPTOR_STATUS (1 << 11)
62#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
63#define DESCRIPTOR_PING (1 << 7)
64#define DESCRIPTOR_YY (1 << 6)
65#define DESCRIPTOR_NO_IRQ (0 << 4)
66#define DESCRIPTOR_IRQ_ERROR (1 << 4)
67#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
68#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
69#define DESCRIPTOR_WAIT (3 << 0)
70
71struct descriptor {
72 __le16 req_count;
73 __le16 control;
74 __le32 data_address;
75 __le32 branch_address;
76 __le16 res_count;
77 __le16 transfer_status;
78} __attribute__((aligned(16)));
79
80#define CONTROL_SET(regs) (regs)
81#define CONTROL_CLEAR(regs) ((regs) + 4)
82#define COMMAND_PTR(regs) ((regs) + 12)
83#define CONTEXT_MATCH(regs) ((regs) + 16)
84
85#define AR_BUFFER_SIZE (32*1024)
86#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
87/* we need at least two pages for proper list management */
88#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
89
90#define MAX_ASYNC_PAYLOAD 4096
91#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
92#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
93
94struct ar_context {
95 struct fw_ohci *ohci;
96 struct page *pages[AR_BUFFERS];
97 void *buffer;
98 struct descriptor *descriptors;
99 dma_addr_t descriptors_bus;
100 void *pointer;
101 unsigned int last_buffer_index;
102 u32 regs;
103 struct tasklet_struct tasklet;
104};
105
106struct context;
107
108typedef int (*descriptor_callback_t)(struct context *ctx,
109 struct descriptor *d,
110 struct descriptor *last);
111
112/*
113 * A buffer that contains a block of DMA-able coherent memory used for
114 * storing a portion of a DMA descriptor program.
115 */
116struct descriptor_buffer {
117 struct list_head list;
118 dma_addr_t buffer_bus;
119 size_t buffer_size;
120 size_t used;
121 struct descriptor buffer[0];
122};
123
124struct context {
125 struct fw_ohci *ohci;
126 u32 regs;
127 int total_allocation;
128 bool running;
129 bool flushing;
130
131 /*
132 * List of page-sized buffers for storing DMA descriptors.
133 * Head of list contains buffers in use and tail of list contains
134 * free buffers.
135 */
136 struct list_head buffer_list;
137
138 /*
139 * Pointer to a buffer inside buffer_list that contains the tail
140 * end of the current DMA program.
141 */
142 struct descriptor_buffer *buffer_tail;
143
144 /*
145 * The descriptor containing the branch address of the first
146 * descriptor that has not yet been filled by the device.
147 */
148 struct descriptor *last;
149
150 /*
151 * The last descriptor in the DMA program. It contains the branch
152 * address that must be updated upon appending a new descriptor.
153 */
154 struct descriptor *prev;
155
156 descriptor_callback_t callback;
157
158 struct tasklet_struct tasklet;
159};
160
161#define IT_HEADER_SY(v) ((v) << 0)
162#define IT_HEADER_TCODE(v) ((v) << 4)
163#define IT_HEADER_CHANNEL(v) ((v) << 8)
164#define IT_HEADER_TAG(v) ((v) << 14)
165#define IT_HEADER_SPEED(v) ((v) << 16)
166#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
167
168struct iso_context {
169 struct fw_iso_context base;
170 struct context context;
171 int excess_bytes;
172 void *header;
173 size_t header_length;
174
175 u8 sync;
176 u8 tags;
177};
178
179#define CONFIG_ROM_SIZE 1024
180
181struct fw_ohci {
182 struct fw_card card;
183
184 __iomem char *registers;
185 int node_id;
186 int generation;
187 int request_generation; /* for timestamping incoming requests */
188 unsigned quirks;
189 unsigned int pri_req_max;
190 u32 bus_time;
191 bool is_root;
192 bool csr_state_setclear_abdicate;
193 int n_ir;
194 int n_it;
195 /*
196 * Spinlock for accessing fw_ohci data. Never call out of
197 * this driver with this lock held.
198 */
199 spinlock_t lock;
200
201 struct mutex phy_reg_mutex;
202
203 void *misc_buffer;
204 dma_addr_t misc_buffer_bus;
205
206 struct ar_context ar_request_ctx;
207 struct ar_context ar_response_ctx;
208 struct context at_request_ctx;
209 struct context at_response_ctx;
210
211 u32 it_context_support;
212 u32 it_context_mask; /* unoccupied IT contexts */
213 struct iso_context *it_context_list;
214 u64 ir_context_channels; /* unoccupied channels */
215 u32 ir_context_support;
216 u32 ir_context_mask; /* unoccupied IR contexts */
217 struct iso_context *ir_context_list;
218 u64 mc_channels; /* channels in use by the multichannel IR context */
219 bool mc_allocated;
220
221 __be32 *config_rom;
222 dma_addr_t config_rom_bus;
223 __be32 *next_config_rom;
224 dma_addr_t next_config_rom_bus;
225 __be32 next_header;
226
227 __le32 *self_id_cpu;
228 dma_addr_t self_id_bus;
229 struct tasklet_struct bus_reset_tasklet;
230
231 u32 self_id_buffer[512];
232};
233
234static inline struct fw_ohci *fw_ohci(struct fw_card *card)
235{
236 return container_of(card, struct fw_ohci, card);
237}
238
239#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
240#define IR_CONTEXT_BUFFER_FILL 0x80000000
241#define IR_CONTEXT_ISOCH_HEADER 0x40000000
242#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
243#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
244#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
245
246#define CONTEXT_RUN 0x8000
247#define CONTEXT_WAKE 0x1000
248#define CONTEXT_DEAD 0x0800
249#define CONTEXT_ACTIVE 0x0400
250
251#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
252#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
253#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
254
255#define OHCI1394_REGISTER_SIZE 0x800
256#define OHCI1394_PCI_HCI_Control 0x40
257#define SELF_ID_BUF_SIZE 0x800
258#define OHCI_TCODE_PHY_PACKET 0x0e
259#define OHCI_VERSION_1_1 0x010010
260
261static char ohci_driver_name[] = KBUILD_MODNAME;
262
263#define PCI_DEVICE_ID_AGERE_FW643 0x5901
264#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
265#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
266#define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
267
268#define QUIRK_CYCLE_TIMER 1
269#define QUIRK_RESET_PACKET 2
270#define QUIRK_BE_HEADERS 4
271#define QUIRK_NO_1394A 8
272#define QUIRK_NO_MSI 16
273
274/* In case of multiple matches in ohci_quirks[], only the first one is used. */
275static const struct {
276 unsigned short vendor, device, revision, flags;
277} ohci_quirks[] = {
278 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
279 QUIRK_CYCLE_TIMER},
280
281 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
282 QUIRK_BE_HEADERS},
283
284 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
285 QUIRK_NO_MSI},
286
287 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
288 QUIRK_NO_MSI},
289
290 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
291 QUIRK_CYCLE_TIMER},
292
293 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
294 QUIRK_NO_MSI},
295
296 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
297 QUIRK_CYCLE_TIMER},
298
299 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
300 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
301
302 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
303 QUIRK_RESET_PACKET},
304
305 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
306 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
307};
308
309/* This overrides anything that was found in ohci_quirks[]. */
310static int param_quirks;
311module_param_named(quirks, param_quirks, int, 0644);
312MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
313 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
314 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
315 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
316 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
317 ", disable MSI = " __stringify(QUIRK_NO_MSI)
318 ")");
319
320#define OHCI_PARAM_DEBUG_AT_AR 1
321#define OHCI_PARAM_DEBUG_SELFIDS 2
322#define OHCI_PARAM_DEBUG_IRQS 4
323#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
324
325#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
326
327static int param_debug;
328module_param_named(debug, param_debug, int, 0644);
329MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
330 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
331 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
332 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
333 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
334 ", or a combination, or all = -1)");
335
336static void log_irqs(u32 evt)
337{
338 if (likely(!(param_debug &
339 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
340 return;
341
342 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
343 !(evt & OHCI1394_busReset))
344 return;
345
346 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
347 evt & OHCI1394_selfIDComplete ? " selfID" : "",
348 evt & OHCI1394_RQPkt ? " AR_req" : "",
349 evt & OHCI1394_RSPkt ? " AR_resp" : "",
350 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
351 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
352 evt & OHCI1394_isochRx ? " IR" : "",
353 evt & OHCI1394_isochTx ? " IT" : "",
354 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
355 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
356 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
357 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
358 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
359 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
360 evt & OHCI1394_busReset ? " busReset" : "",
361 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
362 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
363 OHCI1394_respTxComplete | OHCI1394_isochRx |
364 OHCI1394_isochTx | OHCI1394_postedWriteErr |
365 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
366 OHCI1394_cycleInconsistent |
367 OHCI1394_regAccessFail | OHCI1394_busReset)
368 ? " ?" : "");
369}
370
371static const char *speed[] = {
372 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
373};
374static const char *power[] = {
375 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
376 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
377};
378static const char port[] = { '.', '-', 'p', 'c', };
379
380static char _p(u32 *s, int shift)
381{
382 return port[*s >> shift & 3];
383}
384
385static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
386{
387 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
388 return;
389
390 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
391 self_id_count, generation, node_id);
392
393 for (; self_id_count--; ++s)
394 if ((*s & 1 << 23) == 0)
395 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
396 "%s gc=%d %s %s%s%s\n",
397 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
398 speed[*s >> 14 & 3], *s >> 16 & 63,
399 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
400 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
401 else
402 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
403 *s, *s >> 24 & 63,
404 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
405 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
406}
407
408static const char *evts[] = {
409 [0x00] = "evt_no_status", [0x01] = "-reserved-",
410 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
411 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
412 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
413 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
414 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
415 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
416 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
417 [0x10] = "-reserved-", [0x11] = "ack_complete",
418 [0x12] = "ack_pending ", [0x13] = "-reserved-",
419 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
420 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
421 [0x18] = "-reserved-", [0x19] = "-reserved-",
422 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
423 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
424 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
425 [0x20] = "pending/cancelled",
426};
427static const char *tcodes[] = {
428 [0x0] = "QW req", [0x1] = "BW req",
429 [0x2] = "W resp", [0x3] = "-reserved-",
430 [0x4] = "QR req", [0x5] = "BR req",
431 [0x6] = "QR resp", [0x7] = "BR resp",
432 [0x8] = "cycle start", [0x9] = "Lk req",
433 [0xa] = "async stream packet", [0xb] = "Lk resp",
434 [0xc] = "-reserved-", [0xd] = "-reserved-",
435 [0xe] = "link internal", [0xf] = "-reserved-",
436};
437
438static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
439{
440 int tcode = header[0] >> 4 & 0xf;
441 char specific[12];
442
443 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
444 return;
445
446 if (unlikely(evt >= ARRAY_SIZE(evts)))
447 evt = 0x1f;
448
449 if (evt == OHCI1394_evt_bus_reset) {
450 fw_notify("A%c evt_bus_reset, generation %d\n",
451 dir, (header[2] >> 16) & 0xff);
452 return;
453 }
454
455 switch (tcode) {
456 case 0x0: case 0x6: case 0x8:
457 snprintf(specific, sizeof(specific), " = %08x",
458 be32_to_cpu((__force __be32)header[3]));
459 break;
460 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
461 snprintf(specific, sizeof(specific), " %x,%x",
462 header[3] >> 16, header[3] & 0xffff);
463 break;
464 default:
465 specific[0] = '\0';
466 }
467
468 switch (tcode) {
469 case 0xa:
470 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
471 break;
472 case 0xe:
473 fw_notify("A%c %s, PHY %08x %08x\n",
474 dir, evts[evt], header[1], header[2]);
475 break;
476 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
477 fw_notify("A%c spd %x tl %02x, "
478 "%04x -> %04x, %s, "
479 "%s, %04x%08x%s\n",
480 dir, speed, header[0] >> 10 & 0x3f,
481 header[1] >> 16, header[0] >> 16, evts[evt],
482 tcodes[tcode], header[1] & 0xffff, header[2], specific);
483 break;
484 default:
485 fw_notify("A%c spd %x tl %02x, "
486 "%04x -> %04x, %s, "
487 "%s%s\n",
488 dir, speed, header[0] >> 10 & 0x3f,
489 header[1] >> 16, header[0] >> 16, evts[evt],
490 tcodes[tcode], specific);
491 }
492}
493
494#else
495
496#define param_debug 0
497static inline void log_irqs(u32 evt) {}
498static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
499static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
500
501#endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
502
503static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
504{
505 writel(data, ohci->registers + offset);
506}
507
508static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
509{
510 return readl(ohci->registers + offset);
511}
512
513static inline void flush_writes(const struct fw_ohci *ohci)
514{
515 /* Do a dummy read to flush writes. */
516 reg_read(ohci, OHCI1394_Version);
517}
518
519/*
520 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
521 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
522 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
523 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
524 */
525static int read_phy_reg(struct fw_ohci *ohci, int addr)
526{
527 u32 val;
528 int i;
529
530 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
531 for (i = 0; i < 3 + 100; i++) {
532 val = reg_read(ohci, OHCI1394_PhyControl);
533 if (!~val)
534 return -ENODEV; /* Card was ejected. */
535
536 if (val & OHCI1394_PhyControl_ReadDone)
537 return OHCI1394_PhyControl_ReadData(val);
538
539 /*
540 * Try a few times without waiting. Sleeping is necessary
541 * only when the link/PHY interface is busy.
542 */
543 if (i >= 3)
544 msleep(1);
545 }
546 fw_error("failed to read phy reg\n");
547
548 return -EBUSY;
549}
550
551static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
552{
553 int i;
554
555 reg_write(ohci, OHCI1394_PhyControl,
556 OHCI1394_PhyControl_Write(addr, val));
557 for (i = 0; i < 3 + 100; i++) {
558 val = reg_read(ohci, OHCI1394_PhyControl);
559 if (!~val)
560 return -ENODEV; /* Card was ejected. */
561
562 if (!(val & OHCI1394_PhyControl_WritePending))
563 return 0;
564
565 if (i >= 3)
566 msleep(1);
567 }
568 fw_error("failed to write phy reg\n");
569
570 return -EBUSY;
571}
572
573static int update_phy_reg(struct fw_ohci *ohci, int addr,
574 int clear_bits, int set_bits)
575{
576 int ret = read_phy_reg(ohci, addr);
577 if (ret < 0)
578 return ret;
579
580 /*
581 * The interrupt status bits are cleared by writing a one bit.
582 * Avoid clearing them unless explicitly requested in set_bits.
583 */
584 if (addr == 5)
585 clear_bits |= PHY_INT_STATUS_BITS;
586
587 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
588}
589
590static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
591{
592 int ret;
593
594 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
595 if (ret < 0)
596 return ret;
597
598 return read_phy_reg(ohci, addr);
599}
600
601static int ohci_read_phy_reg(struct fw_card *card, int addr)
602{
603 struct fw_ohci *ohci = fw_ohci(card);
604 int ret;
605
606 mutex_lock(&ohci->phy_reg_mutex);
607 ret = read_phy_reg(ohci, addr);
608 mutex_unlock(&ohci->phy_reg_mutex);
609
610 return ret;
611}
612
613static int ohci_update_phy_reg(struct fw_card *card, int addr,
614 int clear_bits, int set_bits)
615{
616 struct fw_ohci *ohci = fw_ohci(card);
617 int ret;
618
619 mutex_lock(&ohci->phy_reg_mutex);
620 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
621 mutex_unlock(&ohci->phy_reg_mutex);
622
623 return ret;
624}
625
626static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
627{
628 return page_private(ctx->pages[i]);
629}
630
631static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
632{
633 struct descriptor *d;
634
635 d = &ctx->descriptors[index];
636 d->branch_address &= cpu_to_le32(~0xf);
637 d->res_count = cpu_to_le16(PAGE_SIZE);
638 d->transfer_status = 0;
639
640 wmb(); /* finish init of new descriptors before branch_address update */
641 d = &ctx->descriptors[ctx->last_buffer_index];
642 d->branch_address |= cpu_to_le32(1);
643
644 ctx->last_buffer_index = index;
645
646 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
647}
648
649static void ar_context_release(struct ar_context *ctx)
650{
651 unsigned int i;
652
653 if (ctx->buffer)
654 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
655
656 for (i = 0; i < AR_BUFFERS; i++)
657 if (ctx->pages[i]) {
658 dma_unmap_page(ctx->ohci->card.device,
659 ar_buffer_bus(ctx, i),
660 PAGE_SIZE, DMA_FROM_DEVICE);
661 __free_page(ctx->pages[i]);
662 }
663}
664
665static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
666{
667 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
668 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
669 flush_writes(ctx->ohci);
670
671 fw_error("AR error: %s; DMA stopped\n", error_msg);
672 }
673 /* FIXME: restart? */
674}
675
676static inline unsigned int ar_next_buffer_index(unsigned int index)
677{
678 return (index + 1) % AR_BUFFERS;
679}
680
681static inline unsigned int ar_prev_buffer_index(unsigned int index)
682{
683 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
684}
685
686static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
687{
688 return ar_next_buffer_index(ctx->last_buffer_index);
689}
690
691/*
692 * We search for the buffer that contains the last AR packet DMA data written
693 * by the controller.
694 */
695static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
696 unsigned int *buffer_offset)
697{
698 unsigned int i, next_i, last = ctx->last_buffer_index;
699 __le16 res_count, next_res_count;
700
701 i = ar_first_buffer_index(ctx);
702 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
703
704 /* A buffer that is not yet completely filled must be the last one. */
705 while (i != last && res_count == 0) {
706
707 /* Peek at the next descriptor. */
708 next_i = ar_next_buffer_index(i);
709 rmb(); /* read descriptors in order */
710 next_res_count = ACCESS_ONCE(
711 ctx->descriptors[next_i].res_count);
712 /*
713 * If the next descriptor is still empty, we must stop at this
714 * descriptor.
715 */
716 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
717 /*
718 * The exception is when the DMA data for one packet is
719 * split over three buffers; in this case, the middle
720 * buffer's descriptor might be never updated by the
721 * controller and look still empty, and we have to peek
722 * at the third one.
723 */
724 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
725 next_i = ar_next_buffer_index(next_i);
726 rmb();
727 next_res_count = ACCESS_ONCE(
728 ctx->descriptors[next_i].res_count);
729 if (next_res_count != cpu_to_le16(PAGE_SIZE))
730 goto next_buffer_is_active;
731 }
732
733 break;
734 }
735
736next_buffer_is_active:
737 i = next_i;
738 res_count = next_res_count;
739 }
740
741 rmb(); /* read res_count before the DMA data */
742
743 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
744 if (*buffer_offset > PAGE_SIZE) {
745 *buffer_offset = 0;
746 ar_context_abort(ctx, "corrupted descriptor");
747 }
748
749 return i;
750}
751
752static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
753 unsigned int end_buffer_index,
754 unsigned int end_buffer_offset)
755{
756 unsigned int i;
757
758 i = ar_first_buffer_index(ctx);
759 while (i != end_buffer_index) {
760 dma_sync_single_for_cpu(ctx->ohci->card.device,
761 ar_buffer_bus(ctx, i),
762 PAGE_SIZE, DMA_FROM_DEVICE);
763 i = ar_next_buffer_index(i);
764 }
765 if (end_buffer_offset > 0)
766 dma_sync_single_for_cpu(ctx->ohci->card.device,
767 ar_buffer_bus(ctx, i),
768 end_buffer_offset, DMA_FROM_DEVICE);
769}
770
771#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
772#define cond_le32_to_cpu(v) \
773 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
774#else
775#define cond_le32_to_cpu(v) le32_to_cpu(v)
776#endif
777
778static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
779{
780 struct fw_ohci *ohci = ctx->ohci;
781 struct fw_packet p;
782 u32 status, length, tcode;
783 int evt;
784
785 p.header[0] = cond_le32_to_cpu(buffer[0]);
786 p.header[1] = cond_le32_to_cpu(buffer[1]);
787 p.header[2] = cond_le32_to_cpu(buffer[2]);
788
789 tcode = (p.header[0] >> 4) & 0x0f;
790 switch (tcode) {
791 case TCODE_WRITE_QUADLET_REQUEST:
792 case TCODE_READ_QUADLET_RESPONSE:
793 p.header[3] = (__force __u32) buffer[3];
794 p.header_length = 16;
795 p.payload_length = 0;
796 break;
797
798 case TCODE_READ_BLOCK_REQUEST :
799 p.header[3] = cond_le32_to_cpu(buffer[3]);
800 p.header_length = 16;
801 p.payload_length = 0;
802 break;
803
804 case TCODE_WRITE_BLOCK_REQUEST:
805 case TCODE_READ_BLOCK_RESPONSE:
806 case TCODE_LOCK_REQUEST:
807 case TCODE_LOCK_RESPONSE:
808 p.header[3] = cond_le32_to_cpu(buffer[3]);
809 p.header_length = 16;
810 p.payload_length = p.header[3] >> 16;
811 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
812 ar_context_abort(ctx, "invalid packet length");
813 return NULL;
814 }
815 break;
816
817 case TCODE_WRITE_RESPONSE:
818 case TCODE_READ_QUADLET_REQUEST:
819 case OHCI_TCODE_PHY_PACKET:
820 p.header_length = 12;
821 p.payload_length = 0;
822 break;
823
824 default:
825 ar_context_abort(ctx, "invalid tcode");
826 return NULL;
827 }
828
829 p.payload = (void *) buffer + p.header_length;
830
831 /* FIXME: What to do about evt_* errors? */
832 length = (p.header_length + p.payload_length + 3) / 4;
833 status = cond_le32_to_cpu(buffer[length]);
834 evt = (status >> 16) & 0x1f;
835
836 p.ack = evt - 16;
837 p.speed = (status >> 21) & 0x7;
838 p.timestamp = status & 0xffff;
839 p.generation = ohci->request_generation;
840
841 log_ar_at_event('R', p.speed, p.header, evt);
842
843 /*
844 * Several controllers, notably from NEC and VIA, forget to
845 * write ack_complete status at PHY packet reception.
846 */
847 if (evt == OHCI1394_evt_no_status &&
848 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
849 p.ack = ACK_COMPLETE;
850
851 /*
852 * The OHCI bus reset handler synthesizes a PHY packet with
853 * the new generation number when a bus reset happens (see
854 * section 8.4.2.3). This helps us determine when a request
855 * was received and make sure we send the response in the same
856 * generation. We only need this for requests; for responses
857 * we use the unique tlabel for finding the matching
858 * request.
859 *
860 * Alas some chips sometimes emit bus reset packets with a
861 * wrong generation. We set the correct generation for these
862 * at a slightly incorrect time (in bus_reset_tasklet).
863 */
864 if (evt == OHCI1394_evt_bus_reset) {
865 if (!(ohci->quirks & QUIRK_RESET_PACKET))
866 ohci->request_generation = (p.header[2] >> 16) & 0xff;
867 } else if (ctx == &ohci->ar_request_ctx) {
868 fw_core_handle_request(&ohci->card, &p);
869 } else {
870 fw_core_handle_response(&ohci->card, &p);
871 }
872
873 return buffer + length + 1;
874}
875
876static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
877{
878 void *next;
879
880 while (p < end) {
881 next = handle_ar_packet(ctx, p);
882 if (!next)
883 return p;
884 p = next;
885 }
886
887 return p;
888}
889
890static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
891{
892 unsigned int i;
893
894 i = ar_first_buffer_index(ctx);
895 while (i != end_buffer) {
896 dma_sync_single_for_device(ctx->ohci->card.device,
897 ar_buffer_bus(ctx, i),
898 PAGE_SIZE, DMA_FROM_DEVICE);
899 ar_context_link_page(ctx, i);
900 i = ar_next_buffer_index(i);
901 }
902}
903
904static void ar_context_tasklet(unsigned long data)
905{
906 struct ar_context *ctx = (struct ar_context *)data;
907 unsigned int end_buffer_index, end_buffer_offset;
908 void *p, *end;
909
910 p = ctx->pointer;
911 if (!p)
912 return;
913
914 end_buffer_index = ar_search_last_active_buffer(ctx,
915 &end_buffer_offset);
916 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
917 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
918
919 if (end_buffer_index < ar_first_buffer_index(ctx)) {
920 /*
921 * The filled part of the overall buffer wraps around; handle
922 * all packets up to the buffer end here. If the last packet
923 * wraps around, its tail will be visible after the buffer end
924 * because the buffer start pages are mapped there again.
925 */
926 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
927 p = handle_ar_packets(ctx, p, buffer_end);
928 if (p < buffer_end)
929 goto error;
930 /* adjust p to point back into the actual buffer */
931 p -= AR_BUFFERS * PAGE_SIZE;
932 }
933
934 p = handle_ar_packets(ctx, p, end);
935 if (p != end) {
936 if (p > end)
937 ar_context_abort(ctx, "inconsistent descriptor");
938 goto error;
939 }
940
941 ctx->pointer = p;
942 ar_recycle_buffers(ctx, end_buffer_index);
943
944 return;
945
946error:
947 ctx->pointer = NULL;
948}
949
950static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
951 unsigned int descriptors_offset, u32 regs)
952{
953 unsigned int i;
954 dma_addr_t dma_addr;
955 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
956 struct descriptor *d;
957
958 ctx->regs = regs;
959 ctx->ohci = ohci;
960 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
961
962 for (i = 0; i < AR_BUFFERS; i++) {
963 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
964 if (!ctx->pages[i])
965 goto out_of_memory;
966 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
967 0, PAGE_SIZE, DMA_FROM_DEVICE);
968 if (dma_mapping_error(ohci->card.device, dma_addr)) {
969 __free_page(ctx->pages[i]);
970 ctx->pages[i] = NULL;
971 goto out_of_memory;
972 }
973 set_page_private(ctx->pages[i], dma_addr);
974 }
975
976 for (i = 0; i < AR_BUFFERS; i++)
977 pages[i] = ctx->pages[i];
978 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
979 pages[AR_BUFFERS + i] = ctx->pages[i];
980 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
981 -1, PAGE_KERNEL);
982 if (!ctx->buffer)
983 goto out_of_memory;
984
985 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
986 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
987
988 for (i = 0; i < AR_BUFFERS; i++) {
989 d = &ctx->descriptors[i];
990 d->req_count = cpu_to_le16(PAGE_SIZE);
991 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
992 DESCRIPTOR_STATUS |
993 DESCRIPTOR_BRANCH_ALWAYS);
994 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
995 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
996 ar_next_buffer_index(i) * sizeof(struct descriptor));
997 }
998
999 return 0;
1000
1001out_of_memory:
1002 ar_context_release(ctx);
1003
1004 return -ENOMEM;
1005}
1006
1007static void ar_context_run(struct ar_context *ctx)
1008{
1009 unsigned int i;
1010
1011 for (i = 0; i < AR_BUFFERS; i++)
1012 ar_context_link_page(ctx, i);
1013
1014 ctx->pointer = ctx->buffer;
1015
1016 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1017 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1018}
1019
1020static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1021{
1022 __le16 branch;
1023
1024 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1025
1026 /* figure out which descriptor the branch address goes in */
1027 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1028 return d;
1029 else
1030 return d + z - 1;
1031}
1032
1033static void context_tasklet(unsigned long data)
1034{
1035 struct context *ctx = (struct context *) data;
1036 struct descriptor *d, *last;
1037 u32 address;
1038 int z;
1039 struct descriptor_buffer *desc;
1040
1041 desc = list_entry(ctx->buffer_list.next,
1042 struct descriptor_buffer, list);
1043 last = ctx->last;
1044 while (last->branch_address != 0) {
1045 struct descriptor_buffer *old_desc = desc;
1046 address = le32_to_cpu(last->branch_address);
1047 z = address & 0xf;
1048 address &= ~0xf;
1049
1050 /* If the branch address points to a buffer outside of the
1051 * current buffer, advance to the next buffer. */
1052 if (address < desc->buffer_bus ||
1053 address >= desc->buffer_bus + desc->used)
1054 desc = list_entry(desc->list.next,
1055 struct descriptor_buffer, list);
1056 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1057 last = find_branch_descriptor(d, z);
1058
1059 if (!ctx->callback(ctx, d, last))
1060 break;
1061
1062 if (old_desc != desc) {
1063 /* If we've advanced to the next buffer, move the
1064 * previous buffer to the free list. */
1065 unsigned long flags;
1066 old_desc->used = 0;
1067 spin_lock_irqsave(&ctx->ohci->lock, flags);
1068 list_move_tail(&old_desc->list, &ctx->buffer_list);
1069 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1070 }
1071 ctx->last = last;
1072 }
1073}
1074
1075/*
1076 * Allocate a new buffer and add it to the list of free buffers for this
1077 * context. Must be called with ohci->lock held.
1078 */
1079static int context_add_buffer(struct context *ctx)
1080{
1081 struct descriptor_buffer *desc;
1082 dma_addr_t uninitialized_var(bus_addr);
1083 int offset;
1084
1085 /*
1086 * 16MB of descriptors should be far more than enough for any DMA
1087 * program. This will catch run-away userspace or DoS attacks.
1088 */
1089 if (ctx->total_allocation >= 16*1024*1024)
1090 return -ENOMEM;
1091
1092 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1093 &bus_addr, GFP_ATOMIC);
1094 if (!desc)
1095 return -ENOMEM;
1096
1097 offset = (void *)&desc->buffer - (void *)desc;
1098 desc->buffer_size = PAGE_SIZE - offset;
1099 desc->buffer_bus = bus_addr + offset;
1100 desc->used = 0;
1101
1102 list_add_tail(&desc->list, &ctx->buffer_list);
1103 ctx->total_allocation += PAGE_SIZE;
1104
1105 return 0;
1106}
1107
1108static int context_init(struct context *ctx, struct fw_ohci *ohci,
1109 u32 regs, descriptor_callback_t callback)
1110{
1111 ctx->ohci = ohci;
1112 ctx->regs = regs;
1113 ctx->total_allocation = 0;
1114
1115 INIT_LIST_HEAD(&ctx->buffer_list);
1116 if (context_add_buffer(ctx) < 0)
1117 return -ENOMEM;
1118
1119 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1120 struct descriptor_buffer, list);
1121
1122 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1123 ctx->callback = callback;
1124
1125 /*
1126 * We put a dummy descriptor in the buffer that has a NULL
1127 * branch address and looks like it's been sent. That way we
1128 * have a descriptor to append DMA programs to.
1129 */
1130 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1131 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1132 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1133 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1134 ctx->last = ctx->buffer_tail->buffer;
1135 ctx->prev = ctx->buffer_tail->buffer;
1136
1137 return 0;
1138}
1139
1140static void context_release(struct context *ctx)
1141{
1142 struct fw_card *card = &ctx->ohci->card;
1143 struct descriptor_buffer *desc, *tmp;
1144
1145 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1146 dma_free_coherent(card->device, PAGE_SIZE, desc,
1147 desc->buffer_bus -
1148 ((void *)&desc->buffer - (void *)desc));
1149}
1150
1151/* Must be called with ohci->lock held */
1152static struct descriptor *context_get_descriptors(struct context *ctx,
1153 int z, dma_addr_t *d_bus)
1154{
1155 struct descriptor *d = NULL;
1156 struct descriptor_buffer *desc = ctx->buffer_tail;
1157
1158 if (z * sizeof(*d) > desc->buffer_size)
1159 return NULL;
1160
1161 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1162 /* No room for the descriptor in this buffer, so advance to the
1163 * next one. */
1164
1165 if (desc->list.next == &ctx->buffer_list) {
1166 /* If there is no free buffer next in the list,
1167 * allocate one. */
1168 if (context_add_buffer(ctx) < 0)
1169 return NULL;
1170 }
1171 desc = list_entry(desc->list.next,
1172 struct descriptor_buffer, list);
1173 ctx->buffer_tail = desc;
1174 }
1175
1176 d = desc->buffer + desc->used / sizeof(*d);
1177 memset(d, 0, z * sizeof(*d));
1178 *d_bus = desc->buffer_bus + desc->used;
1179
1180 return d;
1181}
1182
1183static void context_run(struct context *ctx, u32 extra)
1184{
1185 struct fw_ohci *ohci = ctx->ohci;
1186
1187 reg_write(ohci, COMMAND_PTR(ctx->regs),
1188 le32_to_cpu(ctx->last->branch_address));
1189 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1190 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1191 ctx->running = true;
1192 flush_writes(ohci);
1193}
1194
1195static void context_append(struct context *ctx,
1196 struct descriptor *d, int z, int extra)
1197{
1198 dma_addr_t d_bus;
1199 struct descriptor_buffer *desc = ctx->buffer_tail;
1200
1201 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1202
1203 desc->used += (z + extra) * sizeof(*d);
1204
1205 wmb(); /* finish init of new descriptors before branch_address update */
1206 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1207 ctx->prev = find_branch_descriptor(d, z);
1208}
1209
1210static void context_stop(struct context *ctx)
1211{
1212 u32 reg;
1213 int i;
1214
1215 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1216 ctx->running = false;
1217
1218 for (i = 0; i < 1000; i++) {
1219 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1220 if ((reg & CONTEXT_ACTIVE) == 0)
1221 return;
1222
1223 if (i)
1224 udelay(10);
1225 }
1226 fw_error("Error: DMA context still active (0x%08x)\n", reg);
1227}
1228
1229struct driver_data {
1230 u8 inline_data[8];
1231 struct fw_packet *packet;
1232};
1233
1234/*
1235 * This function apppends a packet to the DMA queue for transmission.
1236 * Must always be called with the ochi->lock held to ensure proper
1237 * generation handling and locking around packet queue manipulation.
1238 */
1239static int at_context_queue_packet(struct context *ctx,
1240 struct fw_packet *packet)
1241{
1242 struct fw_ohci *ohci = ctx->ohci;
1243 dma_addr_t d_bus, uninitialized_var(payload_bus);
1244 struct driver_data *driver_data;
1245 struct descriptor *d, *last;
1246 __le32 *header;
1247 int z, tcode;
1248
1249 d = context_get_descriptors(ctx, 4, &d_bus);
1250 if (d == NULL) {
1251 packet->ack = RCODE_SEND_ERROR;
1252 return -1;
1253 }
1254
1255 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1256 d[0].res_count = cpu_to_le16(packet->timestamp);
1257
1258 /*
1259 * The DMA format for asyncronous link packets is different
1260 * from the IEEE1394 layout, so shift the fields around
1261 * accordingly.
1262 */
1263
1264 tcode = (packet->header[0] >> 4) & 0x0f;
1265 header = (__le32 *) &d[1];
1266 switch (tcode) {
1267 case TCODE_WRITE_QUADLET_REQUEST:
1268 case TCODE_WRITE_BLOCK_REQUEST:
1269 case TCODE_WRITE_RESPONSE:
1270 case TCODE_READ_QUADLET_REQUEST:
1271 case TCODE_READ_BLOCK_REQUEST:
1272 case TCODE_READ_QUADLET_RESPONSE:
1273 case TCODE_READ_BLOCK_RESPONSE:
1274 case TCODE_LOCK_REQUEST:
1275 case TCODE_LOCK_RESPONSE:
1276 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1277 (packet->speed << 16));
1278 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1279 (packet->header[0] & 0xffff0000));
1280 header[2] = cpu_to_le32(packet->header[2]);
1281
1282 if (TCODE_IS_BLOCK_PACKET(tcode))
1283 header[3] = cpu_to_le32(packet->header[3]);
1284 else
1285 header[3] = (__force __le32) packet->header[3];
1286
1287 d[0].req_count = cpu_to_le16(packet->header_length);
1288 break;
1289
1290 case TCODE_LINK_INTERNAL:
1291 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1292 (packet->speed << 16));
1293 header[1] = cpu_to_le32(packet->header[1]);
1294 header[2] = cpu_to_le32(packet->header[2]);
1295 d[0].req_count = cpu_to_le16(12);
1296
1297 if (is_ping_packet(&packet->header[1]))
1298 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1299 break;
1300
1301 case TCODE_STREAM_DATA:
1302 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1303 (packet->speed << 16));
1304 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1305 d[0].req_count = cpu_to_le16(8);
1306 break;
1307
1308 default:
1309 /* BUG(); */
1310 packet->ack = RCODE_SEND_ERROR;
1311 return -1;
1312 }
1313
1314 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1315 driver_data = (struct driver_data *) &d[3];
1316 driver_data->packet = packet;
1317 packet->driver_data = driver_data;
1318
1319 if (packet->payload_length > 0) {
1320 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1321 payload_bus = dma_map_single(ohci->card.device,
1322 packet->payload,
1323 packet->payload_length,
1324 DMA_TO_DEVICE);
1325 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1326 packet->ack = RCODE_SEND_ERROR;
1327 return -1;
1328 }
1329 packet->payload_bus = payload_bus;
1330 packet->payload_mapped = true;
1331 } else {
1332 memcpy(driver_data->inline_data, packet->payload,
1333 packet->payload_length);
1334 payload_bus = d_bus + 3 * sizeof(*d);
1335 }
1336
1337 d[2].req_count = cpu_to_le16(packet->payload_length);
1338 d[2].data_address = cpu_to_le32(payload_bus);
1339 last = &d[2];
1340 z = 3;
1341 } else {
1342 last = &d[0];
1343 z = 2;
1344 }
1345
1346 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1347 DESCRIPTOR_IRQ_ALWAYS |
1348 DESCRIPTOR_BRANCH_ALWAYS);
1349
1350 /* FIXME: Document how the locking works. */
1351 if (ohci->generation != packet->generation) {
1352 if (packet->payload_mapped)
1353 dma_unmap_single(ohci->card.device, payload_bus,
1354 packet->payload_length, DMA_TO_DEVICE);
1355 packet->ack = RCODE_GENERATION;
1356 return -1;
1357 }
1358
1359 context_append(ctx, d, z, 4 - z);
1360
1361 if (ctx->running)
1362 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1363 else
1364 context_run(ctx, 0);
1365
1366 return 0;
1367}
1368
1369static void at_context_flush(struct context *ctx)
1370{
1371 tasklet_disable(&ctx->tasklet);
1372
1373 ctx->flushing = true;
1374 context_tasklet((unsigned long)ctx);
1375 ctx->flushing = false;
1376
1377 tasklet_enable(&ctx->tasklet);
1378}
1379
1380static int handle_at_packet(struct context *context,
1381 struct descriptor *d,
1382 struct descriptor *last)
1383{
1384 struct driver_data *driver_data;
1385 struct fw_packet *packet;
1386 struct fw_ohci *ohci = context->ohci;
1387 int evt;
1388
1389 if (last->transfer_status == 0 && !context->flushing)
1390 /* This descriptor isn't done yet, stop iteration. */
1391 return 0;
1392
1393 driver_data = (struct driver_data *) &d[3];
1394 packet = driver_data->packet;
1395 if (packet == NULL)
1396 /* This packet was cancelled, just continue. */
1397 return 1;
1398
1399 if (packet->payload_mapped)
1400 dma_unmap_single(ohci->card.device, packet->payload_bus,
1401 packet->payload_length, DMA_TO_DEVICE);
1402
1403 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1404 packet->timestamp = le16_to_cpu(last->res_count);
1405
1406 log_ar_at_event('T', packet->speed, packet->header, evt);
1407
1408 switch (evt) {
1409 case OHCI1394_evt_timeout:
1410 /* Async response transmit timed out. */
1411 packet->ack = RCODE_CANCELLED;
1412 break;
1413
1414 case OHCI1394_evt_flushed:
1415 /*
1416 * The packet was flushed should give same error as
1417 * when we try to use a stale generation count.
1418 */
1419 packet->ack = RCODE_GENERATION;
1420 break;
1421
1422 case OHCI1394_evt_missing_ack:
1423 if (context->flushing)
1424 packet->ack = RCODE_GENERATION;
1425 else {
1426 /*
1427 * Using a valid (current) generation count, but the
1428 * node is not on the bus or not sending acks.
1429 */
1430 packet->ack = RCODE_NO_ACK;
1431 }
1432 break;
1433
1434 case ACK_COMPLETE + 0x10:
1435 case ACK_PENDING + 0x10:
1436 case ACK_BUSY_X + 0x10:
1437 case ACK_BUSY_A + 0x10:
1438 case ACK_BUSY_B + 0x10:
1439 case ACK_DATA_ERROR + 0x10:
1440 case ACK_TYPE_ERROR + 0x10:
1441 packet->ack = evt - 0x10;
1442 break;
1443
1444 case OHCI1394_evt_no_status:
1445 if (context->flushing) {
1446 packet->ack = RCODE_GENERATION;
1447 break;
1448 }
1449 /* fall through */
1450
1451 default:
1452 packet->ack = RCODE_SEND_ERROR;
1453 break;
1454 }
1455
1456 packet->callback(packet, &ohci->card, packet->ack);
1457
1458 return 1;
1459}
1460
1461#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1462#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1463#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1464#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1465#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1466
1467static void handle_local_rom(struct fw_ohci *ohci,
1468 struct fw_packet *packet, u32 csr)
1469{
1470 struct fw_packet response;
1471 int tcode, length, i;
1472
1473 tcode = HEADER_GET_TCODE(packet->header[0]);
1474 if (TCODE_IS_BLOCK_PACKET(tcode))
1475 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1476 else
1477 length = 4;
1478
1479 i = csr - CSR_CONFIG_ROM;
1480 if (i + length > CONFIG_ROM_SIZE) {
1481 fw_fill_response(&response, packet->header,
1482 RCODE_ADDRESS_ERROR, NULL, 0);
1483 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1484 fw_fill_response(&response, packet->header,
1485 RCODE_TYPE_ERROR, NULL, 0);
1486 } else {
1487 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1488 (void *) ohci->config_rom + i, length);
1489 }
1490
1491 fw_core_handle_response(&ohci->card, &response);
1492}
1493
1494static void handle_local_lock(struct fw_ohci *ohci,
1495 struct fw_packet *packet, u32 csr)
1496{
1497 struct fw_packet response;
1498 int tcode, length, ext_tcode, sel, try;
1499 __be32 *payload, lock_old;
1500 u32 lock_arg, lock_data;
1501
1502 tcode = HEADER_GET_TCODE(packet->header[0]);
1503 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1504 payload = packet->payload;
1505 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1506
1507 if (tcode == TCODE_LOCK_REQUEST &&
1508 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1509 lock_arg = be32_to_cpu(payload[0]);
1510 lock_data = be32_to_cpu(payload[1]);
1511 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1512 lock_arg = 0;
1513 lock_data = 0;
1514 } else {
1515 fw_fill_response(&response, packet->header,
1516 RCODE_TYPE_ERROR, NULL, 0);
1517 goto out;
1518 }
1519
1520 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1521 reg_write(ohci, OHCI1394_CSRData, lock_data);
1522 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1523 reg_write(ohci, OHCI1394_CSRControl, sel);
1524
1525 for (try = 0; try < 20; try++)
1526 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1527 lock_old = cpu_to_be32(reg_read(ohci,
1528 OHCI1394_CSRData));
1529 fw_fill_response(&response, packet->header,
1530 RCODE_COMPLETE,
1531 &lock_old, sizeof(lock_old));
1532 goto out;
1533 }
1534
1535 fw_error("swap not done (CSR lock timeout)\n");
1536 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1537
1538 out:
1539 fw_core_handle_response(&ohci->card, &response);
1540}
1541
1542static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1543{
1544 u64 offset, csr;
1545
1546 if (ctx == &ctx->ohci->at_request_ctx) {
1547 packet->ack = ACK_PENDING;
1548 packet->callback(packet, &ctx->ohci->card, packet->ack);
1549 }
1550
1551 offset =
1552 ((unsigned long long)
1553 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1554 packet->header[2];
1555 csr = offset - CSR_REGISTER_BASE;
1556
1557 /* Handle config rom reads. */
1558 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1559 handle_local_rom(ctx->ohci, packet, csr);
1560 else switch (csr) {
1561 case CSR_BUS_MANAGER_ID:
1562 case CSR_BANDWIDTH_AVAILABLE:
1563 case CSR_CHANNELS_AVAILABLE_HI:
1564 case CSR_CHANNELS_AVAILABLE_LO:
1565 handle_local_lock(ctx->ohci, packet, csr);
1566 break;
1567 default:
1568 if (ctx == &ctx->ohci->at_request_ctx)
1569 fw_core_handle_request(&ctx->ohci->card, packet);
1570 else
1571 fw_core_handle_response(&ctx->ohci->card, packet);
1572 break;
1573 }
1574
1575 if (ctx == &ctx->ohci->at_response_ctx) {
1576 packet->ack = ACK_COMPLETE;
1577 packet->callback(packet, &ctx->ohci->card, packet->ack);
1578 }
1579}
1580
1581static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1582{
1583 unsigned long flags;
1584 int ret;
1585
1586 spin_lock_irqsave(&ctx->ohci->lock, flags);
1587
1588 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1589 ctx->ohci->generation == packet->generation) {
1590 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1591 handle_local_request(ctx, packet);
1592 return;
1593 }
1594
1595 ret = at_context_queue_packet(ctx, packet);
1596 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1597
1598 if (ret < 0)
1599 packet->callback(packet, &ctx->ohci->card, packet->ack);
1600
1601}
1602
1603static void detect_dead_context(struct fw_ohci *ohci,
1604 const char *name, unsigned int regs)
1605{
1606 u32 ctl;
1607
1608 ctl = reg_read(ohci, CONTROL_SET(regs));
1609 if (ctl & CONTEXT_DEAD) {
1610#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
1611 fw_error("DMA context %s has stopped, error code: %s\n",
1612 name, evts[ctl & 0x1f]);
1613#else
1614 fw_error("DMA context %s has stopped, error code: %#x\n",
1615 name, ctl & 0x1f);
1616#endif
1617 }
1618}
1619
1620static void handle_dead_contexts(struct fw_ohci *ohci)
1621{
1622 unsigned int i;
1623 char name[8];
1624
1625 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1626 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1627 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1628 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1629 for (i = 0; i < 32; ++i) {
1630 if (!(ohci->it_context_support & (1 << i)))
1631 continue;
1632 sprintf(name, "IT%u", i);
1633 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1634 }
1635 for (i = 0; i < 32; ++i) {
1636 if (!(ohci->ir_context_support & (1 << i)))
1637 continue;
1638 sprintf(name, "IR%u", i);
1639 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1640 }
1641 /* TODO: maybe try to flush and restart the dead contexts */
1642}
1643
1644static u32 cycle_timer_ticks(u32 cycle_timer)
1645{
1646 u32 ticks;
1647
1648 ticks = cycle_timer & 0xfff;
1649 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1650 ticks += (3072 * 8000) * (cycle_timer >> 25);
1651
1652 return ticks;
1653}
1654
1655/*
1656 * Some controllers exhibit one or more of the following bugs when updating the
1657 * iso cycle timer register:
1658 * - When the lowest six bits are wrapping around to zero, a read that happens
1659 * at the same time will return garbage in the lowest ten bits.
1660 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1661 * not incremented for about 60 ns.
1662 * - Occasionally, the entire register reads zero.
1663 *
1664 * To catch these, we read the register three times and ensure that the
1665 * difference between each two consecutive reads is approximately the same, i.e.
1666 * less than twice the other. Furthermore, any negative difference indicates an
1667 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1668 * execute, so we have enough precision to compute the ratio of the differences.)
1669 */
1670static u32 get_cycle_time(struct fw_ohci *ohci)
1671{
1672 u32 c0, c1, c2;
1673 u32 t0, t1, t2;
1674 s32 diff01, diff12;
1675 int i;
1676
1677 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1678
1679 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1680 i = 0;
1681 c1 = c2;
1682 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1683 do {
1684 c0 = c1;
1685 c1 = c2;
1686 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1687 t0 = cycle_timer_ticks(c0);
1688 t1 = cycle_timer_ticks(c1);
1689 t2 = cycle_timer_ticks(c2);
1690 diff01 = t1 - t0;
1691 diff12 = t2 - t1;
1692 } while ((diff01 <= 0 || diff12 <= 0 ||
1693 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1694 && i++ < 20);
1695 }
1696
1697 return c2;
1698}
1699
1700/*
1701 * This function has to be called at least every 64 seconds. The bus_time
1702 * field stores not only the upper 25 bits of the BUS_TIME register but also
1703 * the most significant bit of the cycle timer in bit 6 so that we can detect
1704 * changes in this bit.
1705 */
1706static u32 update_bus_time(struct fw_ohci *ohci)
1707{
1708 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1709
1710 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1711 ohci->bus_time += 0x40;
1712
1713 return ohci->bus_time | cycle_time_seconds;
1714}
1715
1716static void bus_reset_tasklet(unsigned long data)
1717{
1718 struct fw_ohci *ohci = (struct fw_ohci *)data;
1719 int self_id_count, i, j, reg;
1720 int generation, new_generation;
1721 unsigned long flags;
1722 void *free_rom = NULL;
1723 dma_addr_t free_rom_bus = 0;
1724 bool is_new_root;
1725
1726 reg = reg_read(ohci, OHCI1394_NodeID);
1727 if (!(reg & OHCI1394_NodeID_idValid)) {
1728 fw_notify("node ID not valid, new bus reset in progress\n");
1729 return;
1730 }
1731 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1732 fw_notify("malconfigured bus\n");
1733 return;
1734 }
1735 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1736 OHCI1394_NodeID_nodeNumber);
1737
1738 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1739 if (!(ohci->is_root && is_new_root))
1740 reg_write(ohci, OHCI1394_LinkControlSet,
1741 OHCI1394_LinkControl_cycleMaster);
1742 ohci->is_root = is_new_root;
1743
1744 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1745 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1746 fw_notify("inconsistent self IDs\n");
1747 return;
1748 }
1749 /*
1750 * The count in the SelfIDCount register is the number of
1751 * bytes in the self ID receive buffer. Since we also receive
1752 * the inverted quadlets and a header quadlet, we shift one
1753 * bit extra to get the actual number of self IDs.
1754 */
1755 self_id_count = (reg >> 3) & 0xff;
1756 if (self_id_count == 0 || self_id_count > 252) {
1757 fw_notify("inconsistent self IDs\n");
1758 return;
1759 }
1760 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1761 rmb();
1762
1763 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1764 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1765 fw_notify("inconsistent self IDs\n");
1766 return;
1767 }
1768 ohci->self_id_buffer[j] =
1769 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1770 }
1771 rmb();
1772
1773 /*
1774 * Check the consistency of the self IDs we just read. The
1775 * problem we face is that a new bus reset can start while we
1776 * read out the self IDs from the DMA buffer. If this happens,
1777 * the DMA buffer will be overwritten with new self IDs and we
1778 * will read out inconsistent data. The OHCI specification
1779 * (section 11.2) recommends a technique similar to
1780 * linux/seqlock.h, where we remember the generation of the
1781 * self IDs in the buffer before reading them out and compare
1782 * it to the current generation after reading them out. If
1783 * the two generations match we know we have a consistent set
1784 * of self IDs.
1785 */
1786
1787 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1788 if (new_generation != generation) {
1789 fw_notify("recursive bus reset detected, "
1790 "discarding self ids\n");
1791 return;
1792 }
1793
1794 /* FIXME: Document how the locking works. */
1795 spin_lock_irqsave(&ohci->lock, flags);
1796
1797 ohci->generation = -1; /* prevent AT packet queueing */
1798 context_stop(&ohci->at_request_ctx);
1799 context_stop(&ohci->at_response_ctx);
1800
1801 spin_unlock_irqrestore(&ohci->lock, flags);
1802
1803 /*
1804 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1805 * packets in the AT queues and software needs to drain them.
1806 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1807 */
1808 at_context_flush(&ohci->at_request_ctx);
1809 at_context_flush(&ohci->at_response_ctx);
1810
1811 spin_lock_irqsave(&ohci->lock, flags);
1812
1813 ohci->generation = generation;
1814 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1815
1816 if (ohci->quirks & QUIRK_RESET_PACKET)
1817 ohci->request_generation = generation;
1818
1819 /*
1820 * This next bit is unrelated to the AT context stuff but we
1821 * have to do it under the spinlock also. If a new config rom
1822 * was set up before this reset, the old one is now no longer
1823 * in use and we can free it. Update the config rom pointers
1824 * to point to the current config rom and clear the
1825 * next_config_rom pointer so a new update can take place.
1826 */
1827
1828 if (ohci->next_config_rom != NULL) {
1829 if (ohci->next_config_rom != ohci->config_rom) {
1830 free_rom = ohci->config_rom;
1831 free_rom_bus = ohci->config_rom_bus;
1832 }
1833 ohci->config_rom = ohci->next_config_rom;
1834 ohci->config_rom_bus = ohci->next_config_rom_bus;
1835 ohci->next_config_rom = NULL;
1836
1837 /*
1838 * Restore config_rom image and manually update
1839 * config_rom registers. Writing the header quadlet
1840 * will indicate that the config rom is ready, so we
1841 * do that last.
1842 */
1843 reg_write(ohci, OHCI1394_BusOptions,
1844 be32_to_cpu(ohci->config_rom[2]));
1845 ohci->config_rom[0] = ohci->next_header;
1846 reg_write(ohci, OHCI1394_ConfigROMhdr,
1847 be32_to_cpu(ohci->next_header));
1848 }
1849
1850#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1851 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1852 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1853#endif
1854
1855 spin_unlock_irqrestore(&ohci->lock, flags);
1856
1857 if (free_rom)
1858 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1859 free_rom, free_rom_bus);
1860
1861 log_selfids(ohci->node_id, generation,
1862 self_id_count, ohci->self_id_buffer);
1863
1864 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1865 self_id_count, ohci->self_id_buffer,
1866 ohci->csr_state_setclear_abdicate);
1867 ohci->csr_state_setclear_abdicate = false;
1868}
1869
1870static irqreturn_t irq_handler(int irq, void *data)
1871{
1872 struct fw_ohci *ohci = data;
1873 u32 event, iso_event;
1874 int i;
1875
1876 event = reg_read(ohci, OHCI1394_IntEventClear);
1877
1878 if (!event || !~event)
1879 return IRQ_NONE;
1880
1881 /*
1882 * busReset and postedWriteErr must not be cleared yet
1883 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
1884 */
1885 reg_write(ohci, OHCI1394_IntEventClear,
1886 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
1887 log_irqs(event);
1888
1889 if (event & OHCI1394_selfIDComplete)
1890 tasklet_schedule(&ohci->bus_reset_tasklet);
1891
1892 if (event & OHCI1394_RQPkt)
1893 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1894
1895 if (event & OHCI1394_RSPkt)
1896 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1897
1898 if (event & OHCI1394_reqTxComplete)
1899 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1900
1901 if (event & OHCI1394_respTxComplete)
1902 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1903
1904 if (event & OHCI1394_isochRx) {
1905 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1906 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1907
1908 while (iso_event) {
1909 i = ffs(iso_event) - 1;
1910 tasklet_schedule(
1911 &ohci->ir_context_list[i].context.tasklet);
1912 iso_event &= ~(1 << i);
1913 }
1914 }
1915
1916 if (event & OHCI1394_isochTx) {
1917 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1918 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1919
1920 while (iso_event) {
1921 i = ffs(iso_event) - 1;
1922 tasklet_schedule(
1923 &ohci->it_context_list[i].context.tasklet);
1924 iso_event &= ~(1 << i);
1925 }
1926 }
1927
1928 if (unlikely(event & OHCI1394_regAccessFail))
1929 fw_error("Register access failure - "
1930 "please notify linux1394-devel@lists.sf.net\n");
1931
1932 if (unlikely(event & OHCI1394_postedWriteErr)) {
1933 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
1934 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
1935 reg_write(ohci, OHCI1394_IntEventClear,
1936 OHCI1394_postedWriteErr);
1937 fw_error("PCI posted write error\n");
1938 }
1939
1940 if (unlikely(event & OHCI1394_cycleTooLong)) {
1941 if (printk_ratelimit())
1942 fw_notify("isochronous cycle too long\n");
1943 reg_write(ohci, OHCI1394_LinkControlSet,
1944 OHCI1394_LinkControl_cycleMaster);
1945 }
1946
1947 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1948 /*
1949 * We need to clear this event bit in order to make
1950 * cycleMatch isochronous I/O work. In theory we should
1951 * stop active cycleMatch iso contexts now and restart
1952 * them at least two cycles later. (FIXME?)
1953 */
1954 if (printk_ratelimit())
1955 fw_notify("isochronous cycle inconsistent\n");
1956 }
1957
1958 if (unlikely(event & OHCI1394_unrecoverableError))
1959 handle_dead_contexts(ohci);
1960
1961 if (event & OHCI1394_cycle64Seconds) {
1962 spin_lock(&ohci->lock);
1963 update_bus_time(ohci);
1964 spin_unlock(&ohci->lock);
1965 } else
1966 flush_writes(ohci);
1967
1968 return IRQ_HANDLED;
1969}
1970
1971static int software_reset(struct fw_ohci *ohci)
1972{
1973 u32 val;
1974 int i;
1975
1976 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1977 for (i = 0; i < 500; i++) {
1978 val = reg_read(ohci, OHCI1394_HCControlSet);
1979 if (!~val)
1980 return -ENODEV; /* Card was ejected. */
1981
1982 if (!(val & OHCI1394_HCControl_softReset))
1983 return 0;
1984
1985 msleep(1);
1986 }
1987
1988 return -EBUSY;
1989}
1990
1991static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1992{
1993 size_t size = length * 4;
1994
1995 memcpy(dest, src, size);
1996 if (size < CONFIG_ROM_SIZE)
1997 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1998}
1999
2000static int configure_1394a_enhancements(struct fw_ohci *ohci)
2001{
2002 bool enable_1394a;
2003 int ret, clear, set, offset;
2004
2005 /* Check if the driver should configure link and PHY. */
2006 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2007 OHCI1394_HCControl_programPhyEnable))
2008 return 0;
2009
2010 /* Paranoia: check whether the PHY supports 1394a, too. */
2011 enable_1394a = false;
2012 ret = read_phy_reg(ohci, 2);
2013 if (ret < 0)
2014 return ret;
2015 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2016 ret = read_paged_phy_reg(ohci, 1, 8);
2017 if (ret < 0)
2018 return ret;
2019 if (ret >= 1)
2020 enable_1394a = true;
2021 }
2022
2023 if (ohci->quirks & QUIRK_NO_1394A)
2024 enable_1394a = false;
2025
2026 /* Configure PHY and link consistently. */
2027 if (enable_1394a) {
2028 clear = 0;
2029 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2030 } else {
2031 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2032 set = 0;
2033 }
2034 ret = update_phy_reg(ohci, 5, clear, set);
2035 if (ret < 0)
2036 return ret;
2037
2038 if (enable_1394a)
2039 offset = OHCI1394_HCControlSet;
2040 else
2041 offset = OHCI1394_HCControlClear;
2042 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2043
2044 /* Clean up: configuration has been taken care of. */
2045 reg_write(ohci, OHCI1394_HCControlClear,
2046 OHCI1394_HCControl_programPhyEnable);
2047
2048 return 0;
2049}
2050
2051static int ohci_enable(struct fw_card *card,
2052 const __be32 *config_rom, size_t length)
2053{
2054 struct fw_ohci *ohci = fw_ohci(card);
2055 struct pci_dev *dev = to_pci_dev(card->device);
2056 u32 lps, seconds, version, irqs;
2057 int i, ret;
2058
2059 if (software_reset(ohci)) {
2060 fw_error("Failed to reset ohci card.\n");
2061 return -EBUSY;
2062 }
2063
2064 /*
2065 * Now enable LPS, which we need in order to start accessing
2066 * most of the registers. In fact, on some cards (ALI M5251),
2067 * accessing registers in the SClk domain without LPS enabled
2068 * will lock up the machine. Wait 50msec to make sure we have
2069 * full link enabled. However, with some cards (well, at least
2070 * a JMicron PCIe card), we have to try again sometimes.
2071 */
2072 reg_write(ohci, OHCI1394_HCControlSet,
2073 OHCI1394_HCControl_LPS |
2074 OHCI1394_HCControl_postedWriteEnable);
2075 flush_writes(ohci);
2076
2077 for (lps = 0, i = 0; !lps && i < 3; i++) {
2078 msleep(50);
2079 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2080 OHCI1394_HCControl_LPS;
2081 }
2082
2083 if (!lps) {
2084 fw_error("Failed to set Link Power Status\n");
2085 return -EIO;
2086 }
2087
2088 reg_write(ohci, OHCI1394_HCControlClear,
2089 OHCI1394_HCControl_noByteSwapData);
2090
2091 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2092 reg_write(ohci, OHCI1394_LinkControlSet,
2093 OHCI1394_LinkControl_cycleTimerEnable |
2094 OHCI1394_LinkControl_cycleMaster);
2095
2096 reg_write(ohci, OHCI1394_ATRetries,
2097 OHCI1394_MAX_AT_REQ_RETRIES |
2098 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2099 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2100 (200 << 16));
2101
2102 seconds = lower_32_bits(get_seconds());
2103 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2104 ohci->bus_time = seconds & ~0x3f;
2105
2106 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2107 if (version >= OHCI_VERSION_1_1) {
2108 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2109 0xfffffffe);
2110 card->broadcast_channel_auto_allocated = true;
2111 }
2112
2113 /* Get implemented bits of the priority arbitration request counter. */
2114 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2115 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2116 reg_write(ohci, OHCI1394_FairnessControl, 0);
2117 card->priority_budget_implemented = ohci->pri_req_max != 0;
2118
2119 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2120 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2121 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2122
2123 ret = configure_1394a_enhancements(ohci);
2124 if (ret < 0)
2125 return ret;
2126
2127 /* Activate link_on bit and contender bit in our self ID packets.*/
2128 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2129 if (ret < 0)
2130 return ret;
2131
2132 /*
2133 * When the link is not yet enabled, the atomic config rom
2134 * update mechanism described below in ohci_set_config_rom()
2135 * is not active. We have to update ConfigRomHeader and
2136 * BusOptions manually, and the write to ConfigROMmap takes
2137 * effect immediately. We tie this to the enabling of the
2138 * link, so we have a valid config rom before enabling - the
2139 * OHCI requires that ConfigROMhdr and BusOptions have valid
2140 * values before enabling.
2141 *
2142 * However, when the ConfigROMmap is written, some controllers
2143 * always read back quadlets 0 and 2 from the config rom to
2144 * the ConfigRomHeader and BusOptions registers on bus reset.
2145 * They shouldn't do that in this initial case where the link
2146 * isn't enabled. This means we have to use the same
2147 * workaround here, setting the bus header to 0 and then write
2148 * the right values in the bus reset tasklet.
2149 */
2150
2151 if (config_rom) {
2152 ohci->next_config_rom =
2153 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2154 &ohci->next_config_rom_bus,
2155 GFP_KERNEL);
2156 if (ohci->next_config_rom == NULL)
2157 return -ENOMEM;
2158
2159 copy_config_rom(ohci->next_config_rom, config_rom, length);
2160 } else {
2161 /*
2162 * In the suspend case, config_rom is NULL, which
2163 * means that we just reuse the old config rom.
2164 */
2165 ohci->next_config_rom = ohci->config_rom;
2166 ohci->next_config_rom_bus = ohci->config_rom_bus;
2167 }
2168
2169 ohci->next_header = ohci->next_config_rom[0];
2170 ohci->next_config_rom[0] = 0;
2171 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2172 reg_write(ohci, OHCI1394_BusOptions,
2173 be32_to_cpu(ohci->next_config_rom[2]));
2174 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2175
2176 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2177
2178 if (!(ohci->quirks & QUIRK_NO_MSI))
2179 pci_enable_msi(dev);
2180 if (request_irq(dev->irq, irq_handler,
2181 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2182 ohci_driver_name, ohci)) {
2183 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2184 pci_disable_msi(dev);
2185
2186 if (config_rom) {
2187 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2188 ohci->next_config_rom,
2189 ohci->next_config_rom_bus);
2190 ohci->next_config_rom = NULL;
2191 }
2192 return -EIO;
2193 }
2194
2195 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2196 OHCI1394_RQPkt | OHCI1394_RSPkt |
2197 OHCI1394_isochTx | OHCI1394_isochRx |
2198 OHCI1394_postedWriteErr |
2199 OHCI1394_selfIDComplete |
2200 OHCI1394_regAccessFail |
2201 OHCI1394_cycle64Seconds |
2202 OHCI1394_cycleInconsistent |
2203 OHCI1394_unrecoverableError |
2204 OHCI1394_cycleTooLong |
2205 OHCI1394_masterIntEnable;
2206 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2207 irqs |= OHCI1394_busReset;
2208 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2209
2210 reg_write(ohci, OHCI1394_HCControlSet,
2211 OHCI1394_HCControl_linkEnable |
2212 OHCI1394_HCControl_BIBimageValid);
2213
2214 reg_write(ohci, OHCI1394_LinkControlSet,
2215 OHCI1394_LinkControl_rcvSelfID |
2216 OHCI1394_LinkControl_rcvPhyPkt);
2217
2218 ar_context_run(&ohci->ar_request_ctx);
2219 ar_context_run(&ohci->ar_response_ctx);
2220
2221 flush_writes(ohci);
2222
2223 /* We are ready to go, reset bus to finish initialization. */
2224 fw_schedule_bus_reset(&ohci->card, false, true);
2225
2226 return 0;
2227}
2228
2229static int ohci_set_config_rom(struct fw_card *card,
2230 const __be32 *config_rom, size_t length)
2231{
2232 struct fw_ohci *ohci;
2233 unsigned long flags;
2234 __be32 *next_config_rom;
2235 dma_addr_t uninitialized_var(next_config_rom_bus);
2236
2237 ohci = fw_ohci(card);
2238
2239 /*
2240 * When the OHCI controller is enabled, the config rom update
2241 * mechanism is a bit tricky, but easy enough to use. See
2242 * section 5.5.6 in the OHCI specification.
2243 *
2244 * The OHCI controller caches the new config rom address in a
2245 * shadow register (ConfigROMmapNext) and needs a bus reset
2246 * for the changes to take place. When the bus reset is
2247 * detected, the controller loads the new values for the
2248 * ConfigRomHeader and BusOptions registers from the specified
2249 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2250 * shadow register. All automatically and atomically.
2251 *
2252 * Now, there's a twist to this story. The automatic load of
2253 * ConfigRomHeader and BusOptions doesn't honor the
2254 * noByteSwapData bit, so with a be32 config rom, the
2255 * controller will load be32 values in to these registers
2256 * during the atomic update, even on litte endian
2257 * architectures. The workaround we use is to put a 0 in the
2258 * header quadlet; 0 is endian agnostic and means that the
2259 * config rom isn't ready yet. In the bus reset tasklet we
2260 * then set up the real values for the two registers.
2261 *
2262 * We use ohci->lock to avoid racing with the code that sets
2263 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2264 */
2265
2266 next_config_rom =
2267 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2268 &next_config_rom_bus, GFP_KERNEL);
2269 if (next_config_rom == NULL)
2270 return -ENOMEM;
2271
2272 spin_lock_irqsave(&ohci->lock, flags);
2273
2274 /*
2275 * If there is not an already pending config_rom update,
2276 * push our new allocation into the ohci->next_config_rom
2277 * and then mark the local variable as null so that we
2278 * won't deallocate the new buffer.
2279 *
2280 * OTOH, if there is a pending config_rom update, just
2281 * use that buffer with the new config_rom data, and
2282 * let this routine free the unused DMA allocation.
2283 */
2284
2285 if (ohci->next_config_rom == NULL) {
2286 ohci->next_config_rom = next_config_rom;
2287 ohci->next_config_rom_bus = next_config_rom_bus;
2288 next_config_rom = NULL;
2289 }
2290
2291 copy_config_rom(ohci->next_config_rom, config_rom, length);
2292
2293 ohci->next_header = config_rom[0];
2294 ohci->next_config_rom[0] = 0;
2295
2296 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2297
2298 spin_unlock_irqrestore(&ohci->lock, flags);
2299
2300 /* If we didn't use the DMA allocation, delete it. */
2301 if (next_config_rom != NULL)
2302 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2303 next_config_rom, next_config_rom_bus);
2304
2305 /*
2306 * Now initiate a bus reset to have the changes take
2307 * effect. We clean up the old config rom memory and DMA
2308 * mappings in the bus reset tasklet, since the OHCI
2309 * controller could need to access it before the bus reset
2310 * takes effect.
2311 */
2312
2313 fw_schedule_bus_reset(&ohci->card, true, true);
2314
2315 return 0;
2316}
2317
2318static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2319{
2320 struct fw_ohci *ohci = fw_ohci(card);
2321
2322 at_context_transmit(&ohci->at_request_ctx, packet);
2323}
2324
2325static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2326{
2327 struct fw_ohci *ohci = fw_ohci(card);
2328
2329 at_context_transmit(&ohci->at_response_ctx, packet);
2330}
2331
2332static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2333{
2334 struct fw_ohci *ohci = fw_ohci(card);
2335 struct context *ctx = &ohci->at_request_ctx;
2336 struct driver_data *driver_data = packet->driver_data;
2337 int ret = -ENOENT;
2338
2339 tasklet_disable(&ctx->tasklet);
2340
2341 if (packet->ack != 0)
2342 goto out;
2343
2344 if (packet->payload_mapped)
2345 dma_unmap_single(ohci->card.device, packet->payload_bus,
2346 packet->payload_length, DMA_TO_DEVICE);
2347
2348 log_ar_at_event('T', packet->speed, packet->header, 0x20);
2349 driver_data->packet = NULL;
2350 packet->ack = RCODE_CANCELLED;
2351 packet->callback(packet, &ohci->card, packet->ack);
2352 ret = 0;
2353 out:
2354 tasklet_enable(&ctx->tasklet);
2355
2356 return ret;
2357}
2358
2359static int ohci_enable_phys_dma(struct fw_card *card,
2360 int node_id, int generation)
2361{
2362#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2363 return 0;
2364#else
2365 struct fw_ohci *ohci = fw_ohci(card);
2366 unsigned long flags;
2367 int n, ret = 0;
2368
2369 /*
2370 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2371 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2372 */
2373
2374 spin_lock_irqsave(&ohci->lock, flags);
2375
2376 if (ohci->generation != generation) {
2377 ret = -ESTALE;
2378 goto out;
2379 }
2380
2381 /*
2382 * Note, if the node ID contains a non-local bus ID, physical DMA is
2383 * enabled for _all_ nodes on remote buses.
2384 */
2385
2386 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2387 if (n < 32)
2388 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2389 else
2390 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2391
2392 flush_writes(ohci);
2393 out:
2394 spin_unlock_irqrestore(&ohci->lock, flags);
2395
2396 return ret;
2397#endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2398}
2399
2400static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2401{
2402 struct fw_ohci *ohci = fw_ohci(card);
2403 unsigned long flags;
2404 u32 value;
2405
2406 switch (csr_offset) {
2407 case CSR_STATE_CLEAR:
2408 case CSR_STATE_SET:
2409 if (ohci->is_root &&
2410 (reg_read(ohci, OHCI1394_LinkControlSet) &
2411 OHCI1394_LinkControl_cycleMaster))
2412 value = CSR_STATE_BIT_CMSTR;
2413 else
2414 value = 0;
2415 if (ohci->csr_state_setclear_abdicate)
2416 value |= CSR_STATE_BIT_ABDICATE;
2417
2418 return value;
2419
2420 case CSR_NODE_IDS:
2421 return reg_read(ohci, OHCI1394_NodeID) << 16;
2422
2423 case CSR_CYCLE_TIME:
2424 return get_cycle_time(ohci);
2425
2426 case CSR_BUS_TIME:
2427 /*
2428 * We might be called just after the cycle timer has wrapped
2429 * around but just before the cycle64Seconds handler, so we
2430 * better check here, too, if the bus time needs to be updated.
2431 */
2432 spin_lock_irqsave(&ohci->lock, flags);
2433 value = update_bus_time(ohci);
2434 spin_unlock_irqrestore(&ohci->lock, flags);
2435 return value;
2436
2437 case CSR_BUSY_TIMEOUT:
2438 value = reg_read(ohci, OHCI1394_ATRetries);
2439 return (value >> 4) & 0x0ffff00f;
2440
2441 case CSR_PRIORITY_BUDGET:
2442 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2443 (ohci->pri_req_max << 8);
2444
2445 default:
2446 WARN_ON(1);
2447 return 0;
2448 }
2449}
2450
2451static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2452{
2453 struct fw_ohci *ohci = fw_ohci(card);
2454 unsigned long flags;
2455
2456 switch (csr_offset) {
2457 case CSR_STATE_CLEAR:
2458 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2459 reg_write(ohci, OHCI1394_LinkControlClear,
2460 OHCI1394_LinkControl_cycleMaster);
2461 flush_writes(ohci);
2462 }
2463 if (value & CSR_STATE_BIT_ABDICATE)
2464 ohci->csr_state_setclear_abdicate = false;
2465 break;
2466
2467 case CSR_STATE_SET:
2468 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2469 reg_write(ohci, OHCI1394_LinkControlSet,
2470 OHCI1394_LinkControl_cycleMaster);
2471 flush_writes(ohci);
2472 }
2473 if (value & CSR_STATE_BIT_ABDICATE)
2474 ohci->csr_state_setclear_abdicate = true;
2475 break;
2476
2477 case CSR_NODE_IDS:
2478 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2479 flush_writes(ohci);
2480 break;
2481
2482 case CSR_CYCLE_TIME:
2483 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2484 reg_write(ohci, OHCI1394_IntEventSet,
2485 OHCI1394_cycleInconsistent);
2486 flush_writes(ohci);
2487 break;
2488
2489 case CSR_BUS_TIME:
2490 spin_lock_irqsave(&ohci->lock, flags);
2491 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2492 spin_unlock_irqrestore(&ohci->lock, flags);
2493 break;
2494
2495 case CSR_BUSY_TIMEOUT:
2496 value = (value & 0xf) | ((value & 0xf) << 4) |
2497 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2498 reg_write(ohci, OHCI1394_ATRetries, value);
2499 flush_writes(ohci);
2500 break;
2501
2502 case CSR_PRIORITY_BUDGET:
2503 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2504 flush_writes(ohci);
2505 break;
2506
2507 default:
2508 WARN_ON(1);
2509 break;
2510 }
2511}
2512
2513static void copy_iso_headers(struct iso_context *ctx, void *p)
2514{
2515 int i = ctx->header_length;
2516
2517 if (i + ctx->base.header_size > PAGE_SIZE)
2518 return;
2519
2520 /*
2521 * The iso header is byteswapped to little endian by
2522 * the controller, but the remaining header quadlets
2523 * are big endian. We want to present all the headers
2524 * as big endian, so we have to swap the first quadlet.
2525 */
2526 if (ctx->base.header_size > 0)
2527 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2528 if (ctx->base.header_size > 4)
2529 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2530 if (ctx->base.header_size > 8)
2531 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2532 ctx->header_length += ctx->base.header_size;
2533}
2534
2535static int handle_ir_packet_per_buffer(struct context *context,
2536 struct descriptor *d,
2537 struct descriptor *last)
2538{
2539 struct iso_context *ctx =
2540 container_of(context, struct iso_context, context);
2541 struct descriptor *pd;
2542 __le32 *ir_header;
2543 void *p;
2544
2545 for (pd = d; pd <= last; pd++)
2546 if (pd->transfer_status)
2547 break;
2548 if (pd > last)
2549 /* Descriptor(s) not done yet, stop iteration */
2550 return 0;
2551
2552 p = last + 1;
2553 copy_iso_headers(ctx, p);
2554
2555 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2556 ir_header = (__le32 *) p;
2557 ctx->base.callback.sc(&ctx->base,
2558 le32_to_cpu(ir_header[0]) & 0xffff,
2559 ctx->header_length, ctx->header,
2560 ctx->base.callback_data);
2561 ctx->header_length = 0;
2562 }
2563
2564 return 1;
2565}
2566
2567/* d == last because each descriptor block is only a single descriptor. */
2568static int handle_ir_buffer_fill(struct context *context,
2569 struct descriptor *d,
2570 struct descriptor *last)
2571{
2572 struct iso_context *ctx =
2573 container_of(context, struct iso_context, context);
2574
2575 if (!last->transfer_status)
2576 /* Descriptor(s) not done yet, stop iteration */
2577 return 0;
2578
2579 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2580 ctx->base.callback.mc(&ctx->base,
2581 le32_to_cpu(last->data_address) +
2582 le16_to_cpu(last->req_count) -
2583 le16_to_cpu(last->res_count),
2584 ctx->base.callback_data);
2585
2586 return 1;
2587}
2588
2589static int handle_it_packet(struct context *context,
2590 struct descriptor *d,
2591 struct descriptor *last)
2592{
2593 struct iso_context *ctx =
2594 container_of(context, struct iso_context, context);
2595 int i;
2596 struct descriptor *pd;
2597
2598 for (pd = d; pd <= last; pd++)
2599 if (pd->transfer_status)
2600 break;
2601 if (pd > last)
2602 /* Descriptor(s) not done yet, stop iteration */
2603 return 0;
2604
2605 i = ctx->header_length;
2606 if (i + 4 < PAGE_SIZE) {
2607 /* Present this value as big-endian to match the receive code */
2608 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2609 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2610 le16_to_cpu(pd->res_count));
2611 ctx->header_length += 4;
2612 }
2613 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2614 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2615 ctx->header_length, ctx->header,
2616 ctx->base.callback_data);
2617 ctx->header_length = 0;
2618 }
2619 return 1;
2620}
2621
2622static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2623{
2624 u32 hi = channels >> 32, lo = channels;
2625
2626 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2627 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2628 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2629 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2630 mmiowb();
2631 ohci->mc_channels = channels;
2632}
2633
2634static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2635 int type, int channel, size_t header_size)
2636{
2637 struct fw_ohci *ohci = fw_ohci(card);
2638 struct iso_context *uninitialized_var(ctx);
2639 descriptor_callback_t uninitialized_var(callback);
2640 u64 *uninitialized_var(channels);
2641 u32 *uninitialized_var(mask), uninitialized_var(regs);
2642 unsigned long flags;
2643 int index, ret = -EBUSY;
2644
2645 spin_lock_irqsave(&ohci->lock, flags);
2646
2647 switch (type) {
2648 case FW_ISO_CONTEXT_TRANSMIT:
2649 mask = &ohci->it_context_mask;
2650 callback = handle_it_packet;
2651 index = ffs(*mask) - 1;
2652 if (index >= 0) {
2653 *mask &= ~(1 << index);
2654 regs = OHCI1394_IsoXmitContextBase(index);
2655 ctx = &ohci->it_context_list[index];
2656 }
2657 break;
2658
2659 case FW_ISO_CONTEXT_RECEIVE:
2660 channels = &ohci->ir_context_channels;
2661 mask = &ohci->ir_context_mask;
2662 callback = handle_ir_packet_per_buffer;
2663 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2664 if (index >= 0) {
2665 *channels &= ~(1ULL << channel);
2666 *mask &= ~(1 << index);
2667 regs = OHCI1394_IsoRcvContextBase(index);
2668 ctx = &ohci->ir_context_list[index];
2669 }
2670 break;
2671
2672 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2673 mask = &ohci->ir_context_mask;
2674 callback = handle_ir_buffer_fill;
2675 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2676 if (index >= 0) {
2677 ohci->mc_allocated = true;
2678 *mask &= ~(1 << index);
2679 regs = OHCI1394_IsoRcvContextBase(index);
2680 ctx = &ohci->ir_context_list[index];
2681 }
2682 break;
2683
2684 default:
2685 index = -1;
2686 ret = -ENOSYS;
2687 }
2688
2689 spin_unlock_irqrestore(&ohci->lock, flags);
2690
2691 if (index < 0)
2692 return ERR_PTR(ret);
2693
2694 memset(ctx, 0, sizeof(*ctx));
2695 ctx->header_length = 0;
2696 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2697 if (ctx->header == NULL) {
2698 ret = -ENOMEM;
2699 goto out;
2700 }
2701 ret = context_init(&ctx->context, ohci, regs, callback);
2702 if (ret < 0)
2703 goto out_with_header;
2704
2705 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2706 set_multichannel_mask(ohci, 0);
2707
2708 return &ctx->base;
2709
2710 out_with_header:
2711 free_page((unsigned long)ctx->header);
2712 out:
2713 spin_lock_irqsave(&ohci->lock, flags);
2714
2715 switch (type) {
2716 case FW_ISO_CONTEXT_RECEIVE:
2717 *channels |= 1ULL << channel;
2718 break;
2719
2720 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2721 ohci->mc_allocated = false;
2722 break;
2723 }
2724 *mask |= 1 << index;
2725
2726 spin_unlock_irqrestore(&ohci->lock, flags);
2727
2728 return ERR_PTR(ret);
2729}
2730
2731static int ohci_start_iso(struct fw_iso_context *base,
2732 s32 cycle, u32 sync, u32 tags)
2733{
2734 struct iso_context *ctx = container_of(base, struct iso_context, base);
2735 struct fw_ohci *ohci = ctx->context.ohci;
2736 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2737 int index;
2738
2739 /* the controller cannot start without any queued packets */
2740 if (ctx->context.last->branch_address == 0)
2741 return -ENODATA;
2742
2743 switch (ctx->base.type) {
2744 case FW_ISO_CONTEXT_TRANSMIT:
2745 index = ctx - ohci->it_context_list;
2746 match = 0;
2747 if (cycle >= 0)
2748 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2749 (cycle & 0x7fff) << 16;
2750
2751 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2752 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2753 context_run(&ctx->context, match);
2754 break;
2755
2756 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2757 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2758 /* fall through */
2759 case FW_ISO_CONTEXT_RECEIVE:
2760 index = ctx - ohci->ir_context_list;
2761 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2762 if (cycle >= 0) {
2763 match |= (cycle & 0x07fff) << 12;
2764 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2765 }
2766
2767 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2768 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2769 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2770 context_run(&ctx->context, control);
2771
2772 ctx->sync = sync;
2773 ctx->tags = tags;
2774
2775 break;
2776 }
2777
2778 return 0;
2779}
2780
2781static int ohci_stop_iso(struct fw_iso_context *base)
2782{
2783 struct fw_ohci *ohci = fw_ohci(base->card);
2784 struct iso_context *ctx = container_of(base, struct iso_context, base);
2785 int index;
2786
2787 switch (ctx->base.type) {
2788 case FW_ISO_CONTEXT_TRANSMIT:
2789 index = ctx - ohci->it_context_list;
2790 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2791 break;
2792
2793 case FW_ISO_CONTEXT_RECEIVE:
2794 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2795 index = ctx - ohci->ir_context_list;
2796 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2797 break;
2798 }
2799 flush_writes(ohci);
2800 context_stop(&ctx->context);
2801 tasklet_kill(&ctx->context.tasklet);
2802
2803 return 0;
2804}
2805
2806static void ohci_free_iso_context(struct fw_iso_context *base)
2807{
2808 struct fw_ohci *ohci = fw_ohci(base->card);
2809 struct iso_context *ctx = container_of(base, struct iso_context, base);
2810 unsigned long flags;
2811 int index;
2812
2813 ohci_stop_iso(base);
2814 context_release(&ctx->context);
2815 free_page((unsigned long)ctx->header);
2816
2817 spin_lock_irqsave(&ohci->lock, flags);
2818
2819 switch (base->type) {
2820 case FW_ISO_CONTEXT_TRANSMIT:
2821 index = ctx - ohci->it_context_list;
2822 ohci->it_context_mask |= 1 << index;
2823 break;
2824
2825 case FW_ISO_CONTEXT_RECEIVE:
2826 index = ctx - ohci->ir_context_list;
2827 ohci->ir_context_mask |= 1 << index;
2828 ohci->ir_context_channels |= 1ULL << base->channel;
2829 break;
2830
2831 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2832 index = ctx - ohci->ir_context_list;
2833 ohci->ir_context_mask |= 1 << index;
2834 ohci->ir_context_channels |= ohci->mc_channels;
2835 ohci->mc_channels = 0;
2836 ohci->mc_allocated = false;
2837 break;
2838 }
2839
2840 spin_unlock_irqrestore(&ohci->lock, flags);
2841}
2842
2843static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2844{
2845 struct fw_ohci *ohci = fw_ohci(base->card);
2846 unsigned long flags;
2847 int ret;
2848
2849 switch (base->type) {
2850 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2851
2852 spin_lock_irqsave(&ohci->lock, flags);
2853
2854 /* Don't allow multichannel to grab other contexts' channels. */
2855 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2856 *channels = ohci->ir_context_channels;
2857 ret = -EBUSY;
2858 } else {
2859 set_multichannel_mask(ohci, *channels);
2860 ret = 0;
2861 }
2862
2863 spin_unlock_irqrestore(&ohci->lock, flags);
2864
2865 break;
2866 default:
2867 ret = -EINVAL;
2868 }
2869
2870 return ret;
2871}
2872
2873#ifdef CONFIG_PM
2874static void ohci_resume_iso_dma(struct fw_ohci *ohci)
2875{
2876 int i;
2877 struct iso_context *ctx;
2878
2879 for (i = 0 ; i < ohci->n_ir ; i++) {
2880 ctx = &ohci->ir_context_list[i];
2881 if (ctx->context.running)
2882 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2883 }
2884
2885 for (i = 0 ; i < ohci->n_it ; i++) {
2886 ctx = &ohci->it_context_list[i];
2887 if (ctx->context.running)
2888 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2889 }
2890}
2891#endif
2892
2893static int queue_iso_transmit(struct iso_context *ctx,
2894 struct fw_iso_packet *packet,
2895 struct fw_iso_buffer *buffer,
2896 unsigned long payload)
2897{
2898 struct descriptor *d, *last, *pd;
2899 struct fw_iso_packet *p;
2900 __le32 *header;
2901 dma_addr_t d_bus, page_bus;
2902 u32 z, header_z, payload_z, irq;
2903 u32 payload_index, payload_end_index, next_page_index;
2904 int page, end_page, i, length, offset;
2905
2906 p = packet;
2907 payload_index = payload;
2908
2909 if (p->skip)
2910 z = 1;
2911 else
2912 z = 2;
2913 if (p->header_length > 0)
2914 z++;
2915
2916 /* Determine the first page the payload isn't contained in. */
2917 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2918 if (p->payload_length > 0)
2919 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2920 else
2921 payload_z = 0;
2922
2923 z += payload_z;
2924
2925 /* Get header size in number of descriptors. */
2926 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2927
2928 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2929 if (d == NULL)
2930 return -ENOMEM;
2931
2932 if (!p->skip) {
2933 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2934 d[0].req_count = cpu_to_le16(8);
2935 /*
2936 * Link the skip address to this descriptor itself. This causes
2937 * a context to skip a cycle whenever lost cycles or FIFO
2938 * overruns occur, without dropping the data. The application
2939 * should then decide whether this is an error condition or not.
2940 * FIXME: Make the context's cycle-lost behaviour configurable?
2941 */
2942 d[0].branch_address = cpu_to_le32(d_bus | z);
2943
2944 header = (__le32 *) &d[1];
2945 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2946 IT_HEADER_TAG(p->tag) |
2947 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2948 IT_HEADER_CHANNEL(ctx->base.channel) |
2949 IT_HEADER_SPEED(ctx->base.speed));
2950 header[1] =
2951 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2952 p->payload_length));
2953 }
2954
2955 if (p->header_length > 0) {
2956 d[2].req_count = cpu_to_le16(p->header_length);
2957 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2958 memcpy(&d[z], p->header, p->header_length);
2959 }
2960
2961 pd = d + z - payload_z;
2962 payload_end_index = payload_index + p->payload_length;
2963 for (i = 0; i < payload_z; i++) {
2964 page = payload_index >> PAGE_SHIFT;
2965 offset = payload_index & ~PAGE_MASK;
2966 next_page_index = (page + 1) << PAGE_SHIFT;
2967 length =
2968 min(next_page_index, payload_end_index) - payload_index;
2969 pd[i].req_count = cpu_to_le16(length);
2970
2971 page_bus = page_private(buffer->pages[page]);
2972 pd[i].data_address = cpu_to_le32(page_bus + offset);
2973
2974 payload_index += length;
2975 }
2976
2977 if (p->interrupt)
2978 irq = DESCRIPTOR_IRQ_ALWAYS;
2979 else
2980 irq = DESCRIPTOR_NO_IRQ;
2981
2982 last = z == 2 ? d : d + z - 1;
2983 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2984 DESCRIPTOR_STATUS |
2985 DESCRIPTOR_BRANCH_ALWAYS |
2986 irq);
2987
2988 context_append(&ctx->context, d, z, header_z);
2989
2990 return 0;
2991}
2992
2993static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2994 struct fw_iso_packet *packet,
2995 struct fw_iso_buffer *buffer,
2996 unsigned long payload)
2997{
2998 struct descriptor *d, *pd;
2999 dma_addr_t d_bus, page_bus;
3000 u32 z, header_z, rest;
3001 int i, j, length;
3002 int page, offset, packet_count, header_size, payload_per_buffer;
3003
3004 /*
3005 * The OHCI controller puts the isochronous header and trailer in the
3006 * buffer, so we need at least 8 bytes.
3007 */
3008 packet_count = packet->header_length / ctx->base.header_size;
3009 header_size = max(ctx->base.header_size, (size_t)8);
3010
3011 /* Get header size in number of descriptors. */
3012 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3013 page = payload >> PAGE_SHIFT;
3014 offset = payload & ~PAGE_MASK;
3015 payload_per_buffer = packet->payload_length / packet_count;
3016
3017 for (i = 0; i < packet_count; i++) {
3018 /* d points to the header descriptor */
3019 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3020 d = context_get_descriptors(&ctx->context,
3021 z + header_z, &d_bus);
3022 if (d == NULL)
3023 return -ENOMEM;
3024
3025 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3026 DESCRIPTOR_INPUT_MORE);
3027 if (packet->skip && i == 0)
3028 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3029 d->req_count = cpu_to_le16(header_size);
3030 d->res_count = d->req_count;
3031 d->transfer_status = 0;
3032 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3033
3034 rest = payload_per_buffer;
3035 pd = d;
3036 for (j = 1; j < z; j++) {
3037 pd++;
3038 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3039 DESCRIPTOR_INPUT_MORE);
3040
3041 if (offset + rest < PAGE_SIZE)
3042 length = rest;
3043 else
3044 length = PAGE_SIZE - offset;
3045 pd->req_count = cpu_to_le16(length);
3046 pd->res_count = pd->req_count;
3047 pd->transfer_status = 0;
3048
3049 page_bus = page_private(buffer->pages[page]);
3050 pd->data_address = cpu_to_le32(page_bus + offset);
3051
3052 offset = (offset + length) & ~PAGE_MASK;
3053 rest -= length;
3054 if (offset == 0)
3055 page++;
3056 }
3057 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3058 DESCRIPTOR_INPUT_LAST |
3059 DESCRIPTOR_BRANCH_ALWAYS);
3060 if (packet->interrupt && i == packet_count - 1)
3061 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3062
3063 context_append(&ctx->context, d, z, header_z);
3064 }
3065
3066 return 0;
3067}
3068
3069static int queue_iso_buffer_fill(struct iso_context *ctx,
3070 struct fw_iso_packet *packet,
3071 struct fw_iso_buffer *buffer,
3072 unsigned long payload)
3073{
3074 struct descriptor *d;
3075 dma_addr_t d_bus, page_bus;
3076 int page, offset, rest, z, i, length;
3077
3078 page = payload >> PAGE_SHIFT;
3079 offset = payload & ~PAGE_MASK;
3080 rest = packet->payload_length;
3081
3082 /* We need one descriptor for each page in the buffer. */
3083 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3084
3085 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3086 return -EFAULT;
3087
3088 for (i = 0; i < z; i++) {
3089 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3090 if (d == NULL)
3091 return -ENOMEM;
3092
3093 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3094 DESCRIPTOR_BRANCH_ALWAYS);
3095 if (packet->skip && i == 0)
3096 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3097 if (packet->interrupt && i == z - 1)
3098 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3099
3100 if (offset + rest < PAGE_SIZE)
3101 length = rest;
3102 else
3103 length = PAGE_SIZE - offset;
3104 d->req_count = cpu_to_le16(length);
3105 d->res_count = d->req_count;
3106 d->transfer_status = 0;
3107
3108 page_bus = page_private(buffer->pages[page]);
3109 d->data_address = cpu_to_le32(page_bus + offset);
3110
3111 rest -= length;
3112 offset = 0;
3113 page++;
3114
3115 context_append(&ctx->context, d, 1, 0);
3116 }
3117
3118 return 0;
3119}
3120
3121static int ohci_queue_iso(struct fw_iso_context *base,
3122 struct fw_iso_packet *packet,
3123 struct fw_iso_buffer *buffer,
3124 unsigned long payload)
3125{
3126 struct iso_context *ctx = container_of(base, struct iso_context, base);
3127 unsigned long flags;
3128 int ret = -ENOSYS;
3129
3130 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3131 switch (base->type) {
3132 case FW_ISO_CONTEXT_TRANSMIT:
3133 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3134 break;
3135 case FW_ISO_CONTEXT_RECEIVE:
3136 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3137 break;
3138 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3139 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3140 break;
3141 }
3142 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3143
3144 return ret;
3145}
3146
3147static void ohci_flush_queue_iso(struct fw_iso_context *base)
3148{
3149 struct context *ctx =
3150 &container_of(base, struct iso_context, base)->context;
3151
3152 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3153}
3154
3155static const struct fw_card_driver ohci_driver = {
3156 .enable = ohci_enable,
3157 .read_phy_reg = ohci_read_phy_reg,
3158 .update_phy_reg = ohci_update_phy_reg,
3159 .set_config_rom = ohci_set_config_rom,
3160 .send_request = ohci_send_request,
3161 .send_response = ohci_send_response,
3162 .cancel_packet = ohci_cancel_packet,
3163 .enable_phys_dma = ohci_enable_phys_dma,
3164 .read_csr = ohci_read_csr,
3165 .write_csr = ohci_write_csr,
3166
3167 .allocate_iso_context = ohci_allocate_iso_context,
3168 .free_iso_context = ohci_free_iso_context,
3169 .set_iso_channels = ohci_set_iso_channels,
3170 .queue_iso = ohci_queue_iso,
3171 .flush_queue_iso = ohci_flush_queue_iso,
3172 .start_iso = ohci_start_iso,
3173 .stop_iso = ohci_stop_iso,
3174};
3175
3176#ifdef CONFIG_PPC_PMAC
3177static void pmac_ohci_on(struct pci_dev *dev)
3178{
3179 if (machine_is(powermac)) {
3180 struct device_node *ofn = pci_device_to_OF_node(dev);
3181
3182 if (ofn) {
3183 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3184 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3185 }
3186 }
3187}
3188
3189static void pmac_ohci_off(struct pci_dev *dev)
3190{
3191 if (machine_is(powermac)) {
3192 struct device_node *ofn = pci_device_to_OF_node(dev);
3193
3194 if (ofn) {
3195 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3196 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3197 }
3198 }
3199}
3200#else
3201static inline void pmac_ohci_on(struct pci_dev *dev) {}
3202static inline void pmac_ohci_off(struct pci_dev *dev) {}
3203#endif /* CONFIG_PPC_PMAC */
3204
3205static int __devinit pci_probe(struct pci_dev *dev,
3206 const struct pci_device_id *ent)
3207{
3208 struct fw_ohci *ohci;
3209 u32 bus_options, max_receive, link_speed, version;
3210 u64 guid;
3211 int i, err;
3212 size_t size;
3213
3214 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3215 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3216 return -ENOSYS;
3217 }
3218
3219 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3220 if (ohci == NULL) {
3221 err = -ENOMEM;
3222 goto fail;
3223 }
3224
3225 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3226
3227 pmac_ohci_on(dev);
3228
3229 err = pci_enable_device(dev);
3230 if (err) {
3231 fw_error("Failed to enable OHCI hardware\n");
3232 goto fail_free;
3233 }
3234
3235 pci_set_master(dev);
3236 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3237 pci_set_drvdata(dev, ohci);
3238
3239 spin_lock_init(&ohci->lock);
3240 mutex_init(&ohci->phy_reg_mutex);
3241
3242 tasklet_init(&ohci->bus_reset_tasklet,
3243 bus_reset_tasklet, (unsigned long)ohci);
3244
3245 err = pci_request_region(dev, 0, ohci_driver_name);
3246 if (err) {
3247 fw_error("MMIO resource unavailable\n");
3248 goto fail_disable;
3249 }
3250
3251 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3252 if (ohci->registers == NULL) {
3253 fw_error("Failed to remap registers\n");
3254 err = -ENXIO;
3255 goto fail_iomem;
3256 }
3257
3258 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3259 if ((ohci_quirks[i].vendor == dev->vendor) &&
3260 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3261 ohci_quirks[i].device == dev->device) &&
3262 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3263 ohci_quirks[i].revision >= dev->revision)) {
3264 ohci->quirks = ohci_quirks[i].flags;
3265 break;
3266 }
3267 if (param_quirks)
3268 ohci->quirks = param_quirks;
3269
3270 /*
3271 * Because dma_alloc_coherent() allocates at least one page,
3272 * we save space by using a common buffer for the AR request/
3273 * response descriptors and the self IDs buffer.
3274 */
3275 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3276 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3277 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3278 PAGE_SIZE,
3279 &ohci->misc_buffer_bus,
3280 GFP_KERNEL);
3281 if (!ohci->misc_buffer) {
3282 err = -ENOMEM;
3283 goto fail_iounmap;
3284 }
3285
3286 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3287 OHCI1394_AsReqRcvContextControlSet);
3288 if (err < 0)
3289 goto fail_misc_buf;
3290
3291 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3292 OHCI1394_AsRspRcvContextControlSet);
3293 if (err < 0)
3294 goto fail_arreq_ctx;
3295
3296 err = context_init(&ohci->at_request_ctx, ohci,
3297 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3298 if (err < 0)
3299 goto fail_arrsp_ctx;
3300
3301 err = context_init(&ohci->at_response_ctx, ohci,
3302 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3303 if (err < 0)
3304 goto fail_atreq_ctx;
3305
3306 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3307 ohci->ir_context_channels = ~0ULL;
3308 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3309 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3310 ohci->ir_context_mask = ohci->ir_context_support;
3311 ohci->n_ir = hweight32(ohci->ir_context_mask);
3312 size = sizeof(struct iso_context) * ohci->n_ir;
3313 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3314
3315 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3316 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3317 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3318 ohci->it_context_mask = ohci->it_context_support;
3319 ohci->n_it = hweight32(ohci->it_context_mask);
3320 size = sizeof(struct iso_context) * ohci->n_it;
3321 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3322
3323 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3324 err = -ENOMEM;
3325 goto fail_contexts;
3326 }
3327
3328 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2;
3329 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3330
3331 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3332 max_receive = (bus_options >> 12) & 0xf;
3333 link_speed = bus_options & 0x7;
3334 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3335 reg_read(ohci, OHCI1394_GUIDLo);
3336
3337 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3338 if (err)
3339 goto fail_contexts;
3340
3341 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3342 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3343 "%d IR + %d IT contexts, quirks 0x%x\n",
3344 dev_name(&dev->dev), version >> 16, version & 0xff,
3345 ohci->n_ir, ohci->n_it, ohci->quirks);
3346
3347 return 0;
3348
3349 fail_contexts:
3350 kfree(ohci->ir_context_list);
3351 kfree(ohci->it_context_list);
3352 context_release(&ohci->at_response_ctx);
3353 fail_atreq_ctx:
3354 context_release(&ohci->at_request_ctx);
3355 fail_arrsp_ctx:
3356 ar_context_release(&ohci->ar_response_ctx);
3357 fail_arreq_ctx:
3358 ar_context_release(&ohci->ar_request_ctx);
3359 fail_misc_buf:
3360 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3361 ohci->misc_buffer, ohci->misc_buffer_bus);
3362 fail_iounmap:
3363 pci_iounmap(dev, ohci->registers);
3364 fail_iomem:
3365 pci_release_region(dev, 0);
3366 fail_disable:
3367 pci_disable_device(dev);
3368 fail_free:
3369 kfree(ohci);
3370 pmac_ohci_off(dev);
3371 fail:
3372 if (err == -ENOMEM)
3373 fw_error("Out of memory\n");
3374
3375 return err;
3376}
3377
3378static void pci_remove(struct pci_dev *dev)
3379{
3380 struct fw_ohci *ohci;
3381
3382 ohci = pci_get_drvdata(dev);
3383 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3384 flush_writes(ohci);
3385 fw_core_remove_card(&ohci->card);
3386
3387 /*
3388 * FIXME: Fail all pending packets here, now that the upper
3389 * layers can't queue any more.
3390 */
3391
3392 software_reset(ohci);
3393 free_irq(dev->irq, ohci);
3394
3395 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3396 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3397 ohci->next_config_rom, ohci->next_config_rom_bus);
3398 if (ohci->config_rom)
3399 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3400 ohci->config_rom, ohci->config_rom_bus);
3401 ar_context_release(&ohci->ar_request_ctx);
3402 ar_context_release(&ohci->ar_response_ctx);
3403 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3404 ohci->misc_buffer, ohci->misc_buffer_bus);
3405 context_release(&ohci->at_request_ctx);
3406 context_release(&ohci->at_response_ctx);
3407 kfree(ohci->it_context_list);
3408 kfree(ohci->ir_context_list);
3409 pci_disable_msi(dev);
3410 pci_iounmap(dev, ohci->registers);
3411 pci_release_region(dev, 0);
3412 pci_disable_device(dev);
3413 kfree(ohci);
3414 pmac_ohci_off(dev);
3415
3416 fw_notify("Removed fw-ohci device.\n");
3417}
3418
3419#ifdef CONFIG_PM
3420static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3421{
3422 struct fw_ohci *ohci = pci_get_drvdata(dev);
3423 int err;
3424
3425 software_reset(ohci);
3426 free_irq(dev->irq, ohci);
3427 pci_disable_msi(dev);
3428 err = pci_save_state(dev);
3429 if (err) {
3430 fw_error("pci_save_state failed\n");
3431 return err;
3432 }
3433 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3434 if (err)
3435 fw_error("pci_set_power_state failed with %d\n", err);
3436 pmac_ohci_off(dev);
3437
3438 return 0;
3439}
3440
3441static int pci_resume(struct pci_dev *dev)
3442{
3443 struct fw_ohci *ohci = pci_get_drvdata(dev);
3444 int err;
3445
3446 pmac_ohci_on(dev);
3447 pci_set_power_state(dev, PCI_D0);
3448 pci_restore_state(dev);
3449 err = pci_enable_device(dev);
3450 if (err) {
3451 fw_error("pci_enable_device failed\n");
3452 return err;
3453 }
3454
3455 /* Some systems don't setup GUID register on resume from ram */
3456 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3457 !reg_read(ohci, OHCI1394_GUIDHi)) {
3458 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3459 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3460 }
3461
3462 err = ohci_enable(&ohci->card, NULL, 0);
3463 if (err)
3464 return err;
3465
3466 ohci_resume_iso_dma(ohci);
3467
3468 return 0;
3469}
3470#endif
3471
3472static const struct pci_device_id pci_table[] = {
3473 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3474 { }
3475};
3476
3477MODULE_DEVICE_TABLE(pci, pci_table);
3478
3479static struct pci_driver fw_ohci_pci_driver = {
3480 .name = ohci_driver_name,
3481 .id_table = pci_table,
3482 .probe = pci_probe,
3483 .remove = pci_remove,
3484#ifdef CONFIG_PM
3485 .resume = pci_resume,
3486 .suspend = pci_suspend,
3487#endif
3488};
3489
3490MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3491MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3492MODULE_LICENSE("GPL");
3493
3494/* Provide a module alias so root-on-sbp2 initrds don't break. */
3495#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3496MODULE_ALIAS("ohci1394");
3497#endif
3498
3499static int __init fw_ohci_init(void)
3500{
3501 return pci_register_driver(&fw_ohci_pci_driver);
3502}
3503
3504static void __exit fw_ohci_cleanup(void)
3505{
3506 pci_unregister_driver(&fw_ohci_pci_driver);
3507}
3508
3509module_init(fw_ohci_init);
3510module_exit(fw_ohci_cleanup);
1/*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#include <linux/bitops.h>
22#include <linux/bug.h>
23#include <linux/compiler.h>
24#include <linux/delay.h>
25#include <linux/device.h>
26#include <linux/dma-mapping.h>
27#include <linux/firewire.h>
28#include <linux/firewire-constants.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/io.h>
32#include <linux/kernel.h>
33#include <linux/list.h>
34#include <linux/mm.h>
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/mutex.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/slab.h>
41#include <linux/spinlock.h>
42#include <linux/string.h>
43#include <linux/time.h>
44#include <linux/vmalloc.h>
45#include <linux/workqueue.h>
46
47#include <asm/byteorder.h>
48#include <asm/page.h>
49
50#ifdef CONFIG_PPC_PMAC
51#include <asm/pmac_feature.h>
52#endif
53
54#include "core.h"
55#include "ohci.h"
56
57#define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args)
58#define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args)
59#define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args)
60
61#define DESCRIPTOR_OUTPUT_MORE 0
62#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
63#define DESCRIPTOR_INPUT_MORE (2 << 12)
64#define DESCRIPTOR_INPUT_LAST (3 << 12)
65#define DESCRIPTOR_STATUS (1 << 11)
66#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
67#define DESCRIPTOR_PING (1 << 7)
68#define DESCRIPTOR_YY (1 << 6)
69#define DESCRIPTOR_NO_IRQ (0 << 4)
70#define DESCRIPTOR_IRQ_ERROR (1 << 4)
71#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
72#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
73#define DESCRIPTOR_WAIT (3 << 0)
74
75#define DESCRIPTOR_CMD (0xf << 12)
76
77struct descriptor {
78 __le16 req_count;
79 __le16 control;
80 __le32 data_address;
81 __le32 branch_address;
82 __le16 res_count;
83 __le16 transfer_status;
84} __attribute__((aligned(16)));
85
86#define CONTROL_SET(regs) (regs)
87#define CONTROL_CLEAR(regs) ((regs) + 4)
88#define COMMAND_PTR(regs) ((regs) + 12)
89#define CONTEXT_MATCH(regs) ((regs) + 16)
90
91#define AR_BUFFER_SIZE (32*1024)
92#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
93/* we need at least two pages for proper list management */
94#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
95
96#define MAX_ASYNC_PAYLOAD 4096
97#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
98#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
99
100struct ar_context {
101 struct fw_ohci *ohci;
102 struct page *pages[AR_BUFFERS];
103 void *buffer;
104 struct descriptor *descriptors;
105 dma_addr_t descriptors_bus;
106 void *pointer;
107 unsigned int last_buffer_index;
108 u32 regs;
109 struct tasklet_struct tasklet;
110};
111
112struct context;
113
114typedef int (*descriptor_callback_t)(struct context *ctx,
115 struct descriptor *d,
116 struct descriptor *last);
117
118/*
119 * A buffer that contains a block of DMA-able coherent memory used for
120 * storing a portion of a DMA descriptor program.
121 */
122struct descriptor_buffer {
123 struct list_head list;
124 dma_addr_t buffer_bus;
125 size_t buffer_size;
126 size_t used;
127 struct descriptor buffer[0];
128};
129
130struct context {
131 struct fw_ohci *ohci;
132 u32 regs;
133 int total_allocation;
134 u32 current_bus;
135 bool running;
136 bool flushing;
137
138 /*
139 * List of page-sized buffers for storing DMA descriptors.
140 * Head of list contains buffers in use and tail of list contains
141 * free buffers.
142 */
143 struct list_head buffer_list;
144
145 /*
146 * Pointer to a buffer inside buffer_list that contains the tail
147 * end of the current DMA program.
148 */
149 struct descriptor_buffer *buffer_tail;
150
151 /*
152 * The descriptor containing the branch address of the first
153 * descriptor that has not yet been filled by the device.
154 */
155 struct descriptor *last;
156
157 /*
158 * The last descriptor block in the DMA program. It contains the branch
159 * address that must be updated upon appending a new descriptor.
160 */
161 struct descriptor *prev;
162 int prev_z;
163
164 descriptor_callback_t callback;
165
166 struct tasklet_struct tasklet;
167};
168
169#define IT_HEADER_SY(v) ((v) << 0)
170#define IT_HEADER_TCODE(v) ((v) << 4)
171#define IT_HEADER_CHANNEL(v) ((v) << 8)
172#define IT_HEADER_TAG(v) ((v) << 14)
173#define IT_HEADER_SPEED(v) ((v) << 16)
174#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
175
176struct iso_context {
177 struct fw_iso_context base;
178 struct context context;
179 void *header;
180 size_t header_length;
181 unsigned long flushing_completions;
182 u32 mc_buffer_bus;
183 u16 mc_completed;
184 u16 last_timestamp;
185 u8 sync;
186 u8 tags;
187};
188
189#define CONFIG_ROM_SIZE 1024
190
191struct fw_ohci {
192 struct fw_card card;
193
194 __iomem char *registers;
195 int node_id;
196 int generation;
197 int request_generation; /* for timestamping incoming requests */
198 unsigned quirks;
199 unsigned int pri_req_max;
200 u32 bus_time;
201 bool bus_time_running;
202 bool is_root;
203 bool csr_state_setclear_abdicate;
204 int n_ir;
205 int n_it;
206 /*
207 * Spinlock for accessing fw_ohci data. Never call out of
208 * this driver with this lock held.
209 */
210 spinlock_t lock;
211
212 struct mutex phy_reg_mutex;
213
214 void *misc_buffer;
215 dma_addr_t misc_buffer_bus;
216
217 struct ar_context ar_request_ctx;
218 struct ar_context ar_response_ctx;
219 struct context at_request_ctx;
220 struct context at_response_ctx;
221
222 u32 it_context_support;
223 u32 it_context_mask; /* unoccupied IT contexts */
224 struct iso_context *it_context_list;
225 u64 ir_context_channels; /* unoccupied channels */
226 u32 ir_context_support;
227 u32 ir_context_mask; /* unoccupied IR contexts */
228 struct iso_context *ir_context_list;
229 u64 mc_channels; /* channels in use by the multichannel IR context */
230 bool mc_allocated;
231
232 __be32 *config_rom;
233 dma_addr_t config_rom_bus;
234 __be32 *next_config_rom;
235 dma_addr_t next_config_rom_bus;
236 __be32 next_header;
237
238 __le32 *self_id;
239 dma_addr_t self_id_bus;
240 struct work_struct bus_reset_work;
241
242 u32 self_id_buffer[512];
243};
244
245static struct workqueue_struct *selfid_workqueue;
246
247static inline struct fw_ohci *fw_ohci(struct fw_card *card)
248{
249 return container_of(card, struct fw_ohci, card);
250}
251
252#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
253#define IR_CONTEXT_BUFFER_FILL 0x80000000
254#define IR_CONTEXT_ISOCH_HEADER 0x40000000
255#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
256#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
257#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
258
259#define CONTEXT_RUN 0x8000
260#define CONTEXT_WAKE 0x1000
261#define CONTEXT_DEAD 0x0800
262#define CONTEXT_ACTIVE 0x0400
263
264#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
265#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
266#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
267
268#define OHCI1394_REGISTER_SIZE 0x800
269#define OHCI1394_PCI_HCI_Control 0x40
270#define SELF_ID_BUF_SIZE 0x800
271#define OHCI_TCODE_PHY_PACKET 0x0e
272#define OHCI_VERSION_1_1 0x010010
273
274static char ohci_driver_name[] = KBUILD_MODNAME;
275
276#define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
277#define PCI_DEVICE_ID_AGERE_FW643 0x5901
278#define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
279#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
280#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
281#define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
282#define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
283#define PCI_DEVICE_ID_VIA_VT630X 0x3044
284#define PCI_REV_ID_VIA_VT6306 0x46
285#define PCI_DEVICE_ID_VIA_VT6315 0x3403
286
287#define QUIRK_CYCLE_TIMER 0x1
288#define QUIRK_RESET_PACKET 0x2
289#define QUIRK_BE_HEADERS 0x4
290#define QUIRK_NO_1394A 0x8
291#define QUIRK_NO_MSI 0x10
292#define QUIRK_TI_SLLZ059 0x20
293#define QUIRK_IR_WAKE 0x40
294
295/* In case of multiple matches in ohci_quirks[], only the first one is used. */
296static const struct {
297 unsigned short vendor, device, revision, flags;
298} ohci_quirks[] = {
299 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
300 QUIRK_CYCLE_TIMER},
301
302 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
303 QUIRK_BE_HEADERS},
304
305 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
306 QUIRK_NO_MSI},
307
308 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
309 QUIRK_RESET_PACKET},
310
311 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
312 QUIRK_NO_MSI},
313
314 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
315 QUIRK_CYCLE_TIMER},
316
317 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
318 QUIRK_NO_MSI},
319
320 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
321 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
322
323 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
324 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
325
326 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
327 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
328
329 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
330 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
331
332 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
333 QUIRK_RESET_PACKET},
334
335 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
336 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
337
338 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0,
339 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI},
340
341 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID,
342 QUIRK_NO_MSI},
343
344 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
345 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
346};
347
348/* This overrides anything that was found in ohci_quirks[]. */
349static int param_quirks;
350module_param_named(quirks, param_quirks, int, 0644);
351MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
352 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
353 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
354 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS)
355 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
356 ", disable MSI = " __stringify(QUIRK_NO_MSI)
357 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
358 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE)
359 ")");
360
361#define OHCI_PARAM_DEBUG_AT_AR 1
362#define OHCI_PARAM_DEBUG_SELFIDS 2
363#define OHCI_PARAM_DEBUG_IRQS 4
364#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
365
366static int param_debug;
367module_param_named(debug, param_debug, int, 0644);
368MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
369 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
370 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
371 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
372 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
373 ", or a combination, or all = -1)");
374
375static bool param_remote_dma;
376module_param_named(remote_dma, param_remote_dma, bool, 0444);
377MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)");
378
379static void log_irqs(struct fw_ohci *ohci, u32 evt)
380{
381 if (likely(!(param_debug &
382 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
383 return;
384
385 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
386 !(evt & OHCI1394_busReset))
387 return;
388
389 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
390 evt & OHCI1394_selfIDComplete ? " selfID" : "",
391 evt & OHCI1394_RQPkt ? " AR_req" : "",
392 evt & OHCI1394_RSPkt ? " AR_resp" : "",
393 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
394 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
395 evt & OHCI1394_isochRx ? " IR" : "",
396 evt & OHCI1394_isochTx ? " IT" : "",
397 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
398 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
399 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
400 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
401 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
402 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
403 evt & OHCI1394_busReset ? " busReset" : "",
404 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
405 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
406 OHCI1394_respTxComplete | OHCI1394_isochRx |
407 OHCI1394_isochTx | OHCI1394_postedWriteErr |
408 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
409 OHCI1394_cycleInconsistent |
410 OHCI1394_regAccessFail | OHCI1394_busReset)
411 ? " ?" : "");
412}
413
414static const char *speed[] = {
415 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
416};
417static const char *power[] = {
418 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
419 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
420};
421static const char port[] = { '.', '-', 'p', 'c', };
422
423static char _p(u32 *s, int shift)
424{
425 return port[*s >> shift & 3];
426}
427
428static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
429{
430 u32 *s;
431
432 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
433 return;
434
435 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
436 self_id_count, generation, ohci->node_id);
437
438 for (s = ohci->self_id_buffer; self_id_count--; ++s)
439 if ((*s & 1 << 23) == 0)
440 ohci_notice(ohci,
441 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
442 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
443 speed[*s >> 14 & 3], *s >> 16 & 63,
444 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
445 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
446 else
447 ohci_notice(ohci,
448 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
449 *s, *s >> 24 & 63,
450 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
451 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
452}
453
454static const char *evts[] = {
455 [0x00] = "evt_no_status", [0x01] = "-reserved-",
456 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
457 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
458 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
459 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
460 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
461 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
462 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
463 [0x10] = "-reserved-", [0x11] = "ack_complete",
464 [0x12] = "ack_pending ", [0x13] = "-reserved-",
465 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
466 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
467 [0x18] = "-reserved-", [0x19] = "-reserved-",
468 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
469 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
470 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
471 [0x20] = "pending/cancelled",
472};
473static const char *tcodes[] = {
474 [0x0] = "QW req", [0x1] = "BW req",
475 [0x2] = "W resp", [0x3] = "-reserved-",
476 [0x4] = "QR req", [0x5] = "BR req",
477 [0x6] = "QR resp", [0x7] = "BR resp",
478 [0x8] = "cycle start", [0x9] = "Lk req",
479 [0xa] = "async stream packet", [0xb] = "Lk resp",
480 [0xc] = "-reserved-", [0xd] = "-reserved-",
481 [0xe] = "link internal", [0xf] = "-reserved-",
482};
483
484static void log_ar_at_event(struct fw_ohci *ohci,
485 char dir, int speed, u32 *header, int evt)
486{
487 int tcode = header[0] >> 4 & 0xf;
488 char specific[12];
489
490 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
491 return;
492
493 if (unlikely(evt >= ARRAY_SIZE(evts)))
494 evt = 0x1f;
495
496 if (evt == OHCI1394_evt_bus_reset) {
497 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
498 dir, (header[2] >> 16) & 0xff);
499 return;
500 }
501
502 switch (tcode) {
503 case 0x0: case 0x6: case 0x8:
504 snprintf(specific, sizeof(specific), " = %08x",
505 be32_to_cpu((__force __be32)header[3]));
506 break;
507 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
508 snprintf(specific, sizeof(specific), " %x,%x",
509 header[3] >> 16, header[3] & 0xffff);
510 break;
511 default:
512 specific[0] = '\0';
513 }
514
515 switch (tcode) {
516 case 0xa:
517 ohci_notice(ohci, "A%c %s, %s\n",
518 dir, evts[evt], tcodes[tcode]);
519 break;
520 case 0xe:
521 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
522 dir, evts[evt], header[1], header[2]);
523 break;
524 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
525 ohci_notice(ohci,
526 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
527 dir, speed, header[0] >> 10 & 0x3f,
528 header[1] >> 16, header[0] >> 16, evts[evt],
529 tcodes[tcode], header[1] & 0xffff, header[2], specific);
530 break;
531 default:
532 ohci_notice(ohci,
533 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
534 dir, speed, header[0] >> 10 & 0x3f,
535 header[1] >> 16, header[0] >> 16, evts[evt],
536 tcodes[tcode], specific);
537 }
538}
539
540static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
541{
542 writel(data, ohci->registers + offset);
543}
544
545static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
546{
547 return readl(ohci->registers + offset);
548}
549
550static inline void flush_writes(const struct fw_ohci *ohci)
551{
552 /* Do a dummy read to flush writes. */
553 reg_read(ohci, OHCI1394_Version);
554}
555
556/*
557 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
558 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
559 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
560 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
561 */
562static int read_phy_reg(struct fw_ohci *ohci, int addr)
563{
564 u32 val;
565 int i;
566
567 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
568 for (i = 0; i < 3 + 100; i++) {
569 val = reg_read(ohci, OHCI1394_PhyControl);
570 if (!~val)
571 return -ENODEV; /* Card was ejected. */
572
573 if (val & OHCI1394_PhyControl_ReadDone)
574 return OHCI1394_PhyControl_ReadData(val);
575
576 /*
577 * Try a few times without waiting. Sleeping is necessary
578 * only when the link/PHY interface is busy.
579 */
580 if (i >= 3)
581 msleep(1);
582 }
583 ohci_err(ohci, "failed to read phy reg %d\n", addr);
584 dump_stack();
585
586 return -EBUSY;
587}
588
589static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
590{
591 int i;
592
593 reg_write(ohci, OHCI1394_PhyControl,
594 OHCI1394_PhyControl_Write(addr, val));
595 for (i = 0; i < 3 + 100; i++) {
596 val = reg_read(ohci, OHCI1394_PhyControl);
597 if (!~val)
598 return -ENODEV; /* Card was ejected. */
599
600 if (!(val & OHCI1394_PhyControl_WritePending))
601 return 0;
602
603 if (i >= 3)
604 msleep(1);
605 }
606 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
607 dump_stack();
608
609 return -EBUSY;
610}
611
612static int update_phy_reg(struct fw_ohci *ohci, int addr,
613 int clear_bits, int set_bits)
614{
615 int ret = read_phy_reg(ohci, addr);
616 if (ret < 0)
617 return ret;
618
619 /*
620 * The interrupt status bits are cleared by writing a one bit.
621 * Avoid clearing them unless explicitly requested in set_bits.
622 */
623 if (addr == 5)
624 clear_bits |= PHY_INT_STATUS_BITS;
625
626 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
627}
628
629static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
630{
631 int ret;
632
633 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
634 if (ret < 0)
635 return ret;
636
637 return read_phy_reg(ohci, addr);
638}
639
640static int ohci_read_phy_reg(struct fw_card *card, int addr)
641{
642 struct fw_ohci *ohci = fw_ohci(card);
643 int ret;
644
645 mutex_lock(&ohci->phy_reg_mutex);
646 ret = read_phy_reg(ohci, addr);
647 mutex_unlock(&ohci->phy_reg_mutex);
648
649 return ret;
650}
651
652static int ohci_update_phy_reg(struct fw_card *card, int addr,
653 int clear_bits, int set_bits)
654{
655 struct fw_ohci *ohci = fw_ohci(card);
656 int ret;
657
658 mutex_lock(&ohci->phy_reg_mutex);
659 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
660 mutex_unlock(&ohci->phy_reg_mutex);
661
662 return ret;
663}
664
665static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
666{
667 return page_private(ctx->pages[i]);
668}
669
670static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
671{
672 struct descriptor *d;
673
674 d = &ctx->descriptors[index];
675 d->branch_address &= cpu_to_le32(~0xf);
676 d->res_count = cpu_to_le16(PAGE_SIZE);
677 d->transfer_status = 0;
678
679 wmb(); /* finish init of new descriptors before branch_address update */
680 d = &ctx->descriptors[ctx->last_buffer_index];
681 d->branch_address |= cpu_to_le32(1);
682
683 ctx->last_buffer_index = index;
684
685 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
686}
687
688static void ar_context_release(struct ar_context *ctx)
689{
690 unsigned int i;
691
692 vunmap(ctx->buffer);
693
694 for (i = 0; i < AR_BUFFERS; i++)
695 if (ctx->pages[i]) {
696 dma_unmap_page(ctx->ohci->card.device,
697 ar_buffer_bus(ctx, i),
698 PAGE_SIZE, DMA_FROM_DEVICE);
699 __free_page(ctx->pages[i]);
700 }
701}
702
703static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
704{
705 struct fw_ohci *ohci = ctx->ohci;
706
707 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
708 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
709 flush_writes(ohci);
710
711 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
712 }
713 /* FIXME: restart? */
714}
715
716static inline unsigned int ar_next_buffer_index(unsigned int index)
717{
718 return (index + 1) % AR_BUFFERS;
719}
720
721static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
722{
723 return ar_next_buffer_index(ctx->last_buffer_index);
724}
725
726/*
727 * We search for the buffer that contains the last AR packet DMA data written
728 * by the controller.
729 */
730static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
731 unsigned int *buffer_offset)
732{
733 unsigned int i, next_i, last = ctx->last_buffer_index;
734 __le16 res_count, next_res_count;
735
736 i = ar_first_buffer_index(ctx);
737 res_count = READ_ONCE(ctx->descriptors[i].res_count);
738
739 /* A buffer that is not yet completely filled must be the last one. */
740 while (i != last && res_count == 0) {
741
742 /* Peek at the next descriptor. */
743 next_i = ar_next_buffer_index(i);
744 rmb(); /* read descriptors in order */
745 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
746 /*
747 * If the next descriptor is still empty, we must stop at this
748 * descriptor.
749 */
750 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
751 /*
752 * The exception is when the DMA data for one packet is
753 * split over three buffers; in this case, the middle
754 * buffer's descriptor might be never updated by the
755 * controller and look still empty, and we have to peek
756 * at the third one.
757 */
758 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
759 next_i = ar_next_buffer_index(next_i);
760 rmb();
761 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
762 if (next_res_count != cpu_to_le16(PAGE_SIZE))
763 goto next_buffer_is_active;
764 }
765
766 break;
767 }
768
769next_buffer_is_active:
770 i = next_i;
771 res_count = next_res_count;
772 }
773
774 rmb(); /* read res_count before the DMA data */
775
776 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
777 if (*buffer_offset > PAGE_SIZE) {
778 *buffer_offset = 0;
779 ar_context_abort(ctx, "corrupted descriptor");
780 }
781
782 return i;
783}
784
785static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
786 unsigned int end_buffer_index,
787 unsigned int end_buffer_offset)
788{
789 unsigned int i;
790
791 i = ar_first_buffer_index(ctx);
792 while (i != end_buffer_index) {
793 dma_sync_single_for_cpu(ctx->ohci->card.device,
794 ar_buffer_bus(ctx, i),
795 PAGE_SIZE, DMA_FROM_DEVICE);
796 i = ar_next_buffer_index(i);
797 }
798 if (end_buffer_offset > 0)
799 dma_sync_single_for_cpu(ctx->ohci->card.device,
800 ar_buffer_bus(ctx, i),
801 end_buffer_offset, DMA_FROM_DEVICE);
802}
803
804#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
805#define cond_le32_to_cpu(v) \
806 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
807#else
808#define cond_le32_to_cpu(v) le32_to_cpu(v)
809#endif
810
811static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
812{
813 struct fw_ohci *ohci = ctx->ohci;
814 struct fw_packet p;
815 u32 status, length, tcode;
816 int evt;
817
818 p.header[0] = cond_le32_to_cpu(buffer[0]);
819 p.header[1] = cond_le32_to_cpu(buffer[1]);
820 p.header[2] = cond_le32_to_cpu(buffer[2]);
821
822 tcode = (p.header[0] >> 4) & 0x0f;
823 switch (tcode) {
824 case TCODE_WRITE_QUADLET_REQUEST:
825 case TCODE_READ_QUADLET_RESPONSE:
826 p.header[3] = (__force __u32) buffer[3];
827 p.header_length = 16;
828 p.payload_length = 0;
829 break;
830
831 case TCODE_READ_BLOCK_REQUEST :
832 p.header[3] = cond_le32_to_cpu(buffer[3]);
833 p.header_length = 16;
834 p.payload_length = 0;
835 break;
836
837 case TCODE_WRITE_BLOCK_REQUEST:
838 case TCODE_READ_BLOCK_RESPONSE:
839 case TCODE_LOCK_REQUEST:
840 case TCODE_LOCK_RESPONSE:
841 p.header[3] = cond_le32_to_cpu(buffer[3]);
842 p.header_length = 16;
843 p.payload_length = p.header[3] >> 16;
844 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
845 ar_context_abort(ctx, "invalid packet length");
846 return NULL;
847 }
848 break;
849
850 case TCODE_WRITE_RESPONSE:
851 case TCODE_READ_QUADLET_REQUEST:
852 case OHCI_TCODE_PHY_PACKET:
853 p.header_length = 12;
854 p.payload_length = 0;
855 break;
856
857 default:
858 ar_context_abort(ctx, "invalid tcode");
859 return NULL;
860 }
861
862 p.payload = (void *) buffer + p.header_length;
863
864 /* FIXME: What to do about evt_* errors? */
865 length = (p.header_length + p.payload_length + 3) / 4;
866 status = cond_le32_to_cpu(buffer[length]);
867 evt = (status >> 16) & 0x1f;
868
869 p.ack = evt - 16;
870 p.speed = (status >> 21) & 0x7;
871 p.timestamp = status & 0xffff;
872 p.generation = ohci->request_generation;
873
874 log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
875
876 /*
877 * Several controllers, notably from NEC and VIA, forget to
878 * write ack_complete status at PHY packet reception.
879 */
880 if (evt == OHCI1394_evt_no_status &&
881 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
882 p.ack = ACK_COMPLETE;
883
884 /*
885 * The OHCI bus reset handler synthesizes a PHY packet with
886 * the new generation number when a bus reset happens (see
887 * section 8.4.2.3). This helps us determine when a request
888 * was received and make sure we send the response in the same
889 * generation. We only need this for requests; for responses
890 * we use the unique tlabel for finding the matching
891 * request.
892 *
893 * Alas some chips sometimes emit bus reset packets with a
894 * wrong generation. We set the correct generation for these
895 * at a slightly incorrect time (in bus_reset_work).
896 */
897 if (evt == OHCI1394_evt_bus_reset) {
898 if (!(ohci->quirks & QUIRK_RESET_PACKET))
899 ohci->request_generation = (p.header[2] >> 16) & 0xff;
900 } else if (ctx == &ohci->ar_request_ctx) {
901 fw_core_handle_request(&ohci->card, &p);
902 } else {
903 fw_core_handle_response(&ohci->card, &p);
904 }
905
906 return buffer + length + 1;
907}
908
909static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
910{
911 void *next;
912
913 while (p < end) {
914 next = handle_ar_packet(ctx, p);
915 if (!next)
916 return p;
917 p = next;
918 }
919
920 return p;
921}
922
923static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
924{
925 unsigned int i;
926
927 i = ar_first_buffer_index(ctx);
928 while (i != end_buffer) {
929 dma_sync_single_for_device(ctx->ohci->card.device,
930 ar_buffer_bus(ctx, i),
931 PAGE_SIZE, DMA_FROM_DEVICE);
932 ar_context_link_page(ctx, i);
933 i = ar_next_buffer_index(i);
934 }
935}
936
937static void ar_context_tasklet(unsigned long data)
938{
939 struct ar_context *ctx = (struct ar_context *)data;
940 unsigned int end_buffer_index, end_buffer_offset;
941 void *p, *end;
942
943 p = ctx->pointer;
944 if (!p)
945 return;
946
947 end_buffer_index = ar_search_last_active_buffer(ctx,
948 &end_buffer_offset);
949 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
950 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
951
952 if (end_buffer_index < ar_first_buffer_index(ctx)) {
953 /*
954 * The filled part of the overall buffer wraps around; handle
955 * all packets up to the buffer end here. If the last packet
956 * wraps around, its tail will be visible after the buffer end
957 * because the buffer start pages are mapped there again.
958 */
959 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
960 p = handle_ar_packets(ctx, p, buffer_end);
961 if (p < buffer_end)
962 goto error;
963 /* adjust p to point back into the actual buffer */
964 p -= AR_BUFFERS * PAGE_SIZE;
965 }
966
967 p = handle_ar_packets(ctx, p, end);
968 if (p != end) {
969 if (p > end)
970 ar_context_abort(ctx, "inconsistent descriptor");
971 goto error;
972 }
973
974 ctx->pointer = p;
975 ar_recycle_buffers(ctx, end_buffer_index);
976
977 return;
978
979error:
980 ctx->pointer = NULL;
981}
982
983static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
984 unsigned int descriptors_offset, u32 regs)
985{
986 unsigned int i;
987 dma_addr_t dma_addr;
988 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
989 struct descriptor *d;
990
991 ctx->regs = regs;
992 ctx->ohci = ohci;
993 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
994
995 for (i = 0; i < AR_BUFFERS; i++) {
996 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
997 if (!ctx->pages[i])
998 goto out_of_memory;
999 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
1000 0, PAGE_SIZE, DMA_FROM_DEVICE);
1001 if (dma_mapping_error(ohci->card.device, dma_addr)) {
1002 __free_page(ctx->pages[i]);
1003 ctx->pages[i] = NULL;
1004 goto out_of_memory;
1005 }
1006 set_page_private(ctx->pages[i], dma_addr);
1007 }
1008
1009 for (i = 0; i < AR_BUFFERS; i++)
1010 pages[i] = ctx->pages[i];
1011 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1012 pages[AR_BUFFERS + i] = ctx->pages[i];
1013 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL);
1014 if (!ctx->buffer)
1015 goto out_of_memory;
1016
1017 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
1018 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1019
1020 for (i = 0; i < AR_BUFFERS; i++) {
1021 d = &ctx->descriptors[i];
1022 d->req_count = cpu_to_le16(PAGE_SIZE);
1023 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1024 DESCRIPTOR_STATUS |
1025 DESCRIPTOR_BRANCH_ALWAYS);
1026 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
1027 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1028 ar_next_buffer_index(i) * sizeof(struct descriptor));
1029 }
1030
1031 return 0;
1032
1033out_of_memory:
1034 ar_context_release(ctx);
1035
1036 return -ENOMEM;
1037}
1038
1039static void ar_context_run(struct ar_context *ctx)
1040{
1041 unsigned int i;
1042
1043 for (i = 0; i < AR_BUFFERS; i++)
1044 ar_context_link_page(ctx, i);
1045
1046 ctx->pointer = ctx->buffer;
1047
1048 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1049 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1050}
1051
1052static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1053{
1054 __le16 branch;
1055
1056 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1057
1058 /* figure out which descriptor the branch address goes in */
1059 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1060 return d;
1061 else
1062 return d + z - 1;
1063}
1064
1065static void context_tasklet(unsigned long data)
1066{
1067 struct context *ctx = (struct context *) data;
1068 struct descriptor *d, *last;
1069 u32 address;
1070 int z;
1071 struct descriptor_buffer *desc;
1072
1073 desc = list_entry(ctx->buffer_list.next,
1074 struct descriptor_buffer, list);
1075 last = ctx->last;
1076 while (last->branch_address != 0) {
1077 struct descriptor_buffer *old_desc = desc;
1078 address = le32_to_cpu(last->branch_address);
1079 z = address & 0xf;
1080 address &= ~0xf;
1081 ctx->current_bus = address;
1082
1083 /* If the branch address points to a buffer outside of the
1084 * current buffer, advance to the next buffer. */
1085 if (address < desc->buffer_bus ||
1086 address >= desc->buffer_bus + desc->used)
1087 desc = list_entry(desc->list.next,
1088 struct descriptor_buffer, list);
1089 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1090 last = find_branch_descriptor(d, z);
1091
1092 if (!ctx->callback(ctx, d, last))
1093 break;
1094
1095 if (old_desc != desc) {
1096 /* If we've advanced to the next buffer, move the
1097 * previous buffer to the free list. */
1098 unsigned long flags;
1099 old_desc->used = 0;
1100 spin_lock_irqsave(&ctx->ohci->lock, flags);
1101 list_move_tail(&old_desc->list, &ctx->buffer_list);
1102 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1103 }
1104 ctx->last = last;
1105 }
1106}
1107
1108/*
1109 * Allocate a new buffer and add it to the list of free buffers for this
1110 * context. Must be called with ohci->lock held.
1111 */
1112static int context_add_buffer(struct context *ctx)
1113{
1114 struct descriptor_buffer *desc;
1115 dma_addr_t uninitialized_var(bus_addr);
1116 int offset;
1117
1118 /*
1119 * 16MB of descriptors should be far more than enough for any DMA
1120 * program. This will catch run-away userspace or DoS attacks.
1121 */
1122 if (ctx->total_allocation >= 16*1024*1024)
1123 return -ENOMEM;
1124
1125 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1126 &bus_addr, GFP_ATOMIC);
1127 if (!desc)
1128 return -ENOMEM;
1129
1130 offset = (void *)&desc->buffer - (void *)desc;
1131 /*
1132 * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads
1133 * for descriptors, even 0x10-byte ones. This can cause page faults when
1134 * an IOMMU is in use and the oversized read crosses a page boundary.
1135 * Work around this by always leaving at least 0x10 bytes of padding.
1136 */
1137 desc->buffer_size = PAGE_SIZE - offset - 0x10;
1138 desc->buffer_bus = bus_addr + offset;
1139 desc->used = 0;
1140
1141 list_add_tail(&desc->list, &ctx->buffer_list);
1142 ctx->total_allocation += PAGE_SIZE;
1143
1144 return 0;
1145}
1146
1147static int context_init(struct context *ctx, struct fw_ohci *ohci,
1148 u32 regs, descriptor_callback_t callback)
1149{
1150 ctx->ohci = ohci;
1151 ctx->regs = regs;
1152 ctx->total_allocation = 0;
1153
1154 INIT_LIST_HEAD(&ctx->buffer_list);
1155 if (context_add_buffer(ctx) < 0)
1156 return -ENOMEM;
1157
1158 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1159 struct descriptor_buffer, list);
1160
1161 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1162 ctx->callback = callback;
1163
1164 /*
1165 * We put a dummy descriptor in the buffer that has a NULL
1166 * branch address and looks like it's been sent. That way we
1167 * have a descriptor to append DMA programs to.
1168 */
1169 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1170 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1171 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1172 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1173 ctx->last = ctx->buffer_tail->buffer;
1174 ctx->prev = ctx->buffer_tail->buffer;
1175 ctx->prev_z = 1;
1176
1177 return 0;
1178}
1179
1180static void context_release(struct context *ctx)
1181{
1182 struct fw_card *card = &ctx->ohci->card;
1183 struct descriptor_buffer *desc, *tmp;
1184
1185 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1186 dma_free_coherent(card->device, PAGE_SIZE, desc,
1187 desc->buffer_bus -
1188 ((void *)&desc->buffer - (void *)desc));
1189}
1190
1191/* Must be called with ohci->lock held */
1192static struct descriptor *context_get_descriptors(struct context *ctx,
1193 int z, dma_addr_t *d_bus)
1194{
1195 struct descriptor *d = NULL;
1196 struct descriptor_buffer *desc = ctx->buffer_tail;
1197
1198 if (z * sizeof(*d) > desc->buffer_size)
1199 return NULL;
1200
1201 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1202 /* No room for the descriptor in this buffer, so advance to the
1203 * next one. */
1204
1205 if (desc->list.next == &ctx->buffer_list) {
1206 /* If there is no free buffer next in the list,
1207 * allocate one. */
1208 if (context_add_buffer(ctx) < 0)
1209 return NULL;
1210 }
1211 desc = list_entry(desc->list.next,
1212 struct descriptor_buffer, list);
1213 ctx->buffer_tail = desc;
1214 }
1215
1216 d = desc->buffer + desc->used / sizeof(*d);
1217 memset(d, 0, z * sizeof(*d));
1218 *d_bus = desc->buffer_bus + desc->used;
1219
1220 return d;
1221}
1222
1223static void context_run(struct context *ctx, u32 extra)
1224{
1225 struct fw_ohci *ohci = ctx->ohci;
1226
1227 reg_write(ohci, COMMAND_PTR(ctx->regs),
1228 le32_to_cpu(ctx->last->branch_address));
1229 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1230 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1231 ctx->running = true;
1232 flush_writes(ohci);
1233}
1234
1235static void context_append(struct context *ctx,
1236 struct descriptor *d, int z, int extra)
1237{
1238 dma_addr_t d_bus;
1239 struct descriptor_buffer *desc = ctx->buffer_tail;
1240 struct descriptor *d_branch;
1241
1242 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1243
1244 desc->used += (z + extra) * sizeof(*d);
1245
1246 wmb(); /* finish init of new descriptors before branch_address update */
1247
1248 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1249 d_branch->branch_address = cpu_to_le32(d_bus | z);
1250
1251 /*
1252 * VT6306 incorrectly checks only the single descriptor at the
1253 * CommandPtr when the wake bit is written, so if it's a
1254 * multi-descriptor block starting with an INPUT_MORE, put a copy of
1255 * the branch address in the first descriptor.
1256 *
1257 * Not doing this for transmit contexts since not sure how it interacts
1258 * with skip addresses.
1259 */
1260 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1261 d_branch != ctx->prev &&
1262 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1263 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1264 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1265 }
1266
1267 ctx->prev = d;
1268 ctx->prev_z = z;
1269}
1270
1271static void context_stop(struct context *ctx)
1272{
1273 struct fw_ohci *ohci = ctx->ohci;
1274 u32 reg;
1275 int i;
1276
1277 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1278 ctx->running = false;
1279
1280 for (i = 0; i < 1000; i++) {
1281 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1282 if ((reg & CONTEXT_ACTIVE) == 0)
1283 return;
1284
1285 if (i)
1286 udelay(10);
1287 }
1288 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
1289}
1290
1291struct driver_data {
1292 u8 inline_data[8];
1293 struct fw_packet *packet;
1294};
1295
1296/*
1297 * This function apppends a packet to the DMA queue for transmission.
1298 * Must always be called with the ochi->lock held to ensure proper
1299 * generation handling and locking around packet queue manipulation.
1300 */
1301static int at_context_queue_packet(struct context *ctx,
1302 struct fw_packet *packet)
1303{
1304 struct fw_ohci *ohci = ctx->ohci;
1305 dma_addr_t d_bus, uninitialized_var(payload_bus);
1306 struct driver_data *driver_data;
1307 struct descriptor *d, *last;
1308 __le32 *header;
1309 int z, tcode;
1310
1311 d = context_get_descriptors(ctx, 4, &d_bus);
1312 if (d == NULL) {
1313 packet->ack = RCODE_SEND_ERROR;
1314 return -1;
1315 }
1316
1317 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1318 d[0].res_count = cpu_to_le16(packet->timestamp);
1319
1320 /*
1321 * The DMA format for asynchronous link packets is different
1322 * from the IEEE1394 layout, so shift the fields around
1323 * accordingly.
1324 */
1325
1326 tcode = (packet->header[0] >> 4) & 0x0f;
1327 header = (__le32 *) &d[1];
1328 switch (tcode) {
1329 case TCODE_WRITE_QUADLET_REQUEST:
1330 case TCODE_WRITE_BLOCK_REQUEST:
1331 case TCODE_WRITE_RESPONSE:
1332 case TCODE_READ_QUADLET_REQUEST:
1333 case TCODE_READ_BLOCK_REQUEST:
1334 case TCODE_READ_QUADLET_RESPONSE:
1335 case TCODE_READ_BLOCK_RESPONSE:
1336 case TCODE_LOCK_REQUEST:
1337 case TCODE_LOCK_RESPONSE:
1338 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1339 (packet->speed << 16));
1340 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1341 (packet->header[0] & 0xffff0000));
1342 header[2] = cpu_to_le32(packet->header[2]);
1343
1344 if (TCODE_IS_BLOCK_PACKET(tcode))
1345 header[3] = cpu_to_le32(packet->header[3]);
1346 else
1347 header[3] = (__force __le32) packet->header[3];
1348
1349 d[0].req_count = cpu_to_le16(packet->header_length);
1350 break;
1351
1352 case TCODE_LINK_INTERNAL:
1353 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1354 (packet->speed << 16));
1355 header[1] = cpu_to_le32(packet->header[1]);
1356 header[2] = cpu_to_le32(packet->header[2]);
1357 d[0].req_count = cpu_to_le16(12);
1358
1359 if (is_ping_packet(&packet->header[1]))
1360 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1361 break;
1362
1363 case TCODE_STREAM_DATA:
1364 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1365 (packet->speed << 16));
1366 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1367 d[0].req_count = cpu_to_le16(8);
1368 break;
1369
1370 default:
1371 /* BUG(); */
1372 packet->ack = RCODE_SEND_ERROR;
1373 return -1;
1374 }
1375
1376 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1377 driver_data = (struct driver_data *) &d[3];
1378 driver_data->packet = packet;
1379 packet->driver_data = driver_data;
1380
1381 if (packet->payload_length > 0) {
1382 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1383 payload_bus = dma_map_single(ohci->card.device,
1384 packet->payload,
1385 packet->payload_length,
1386 DMA_TO_DEVICE);
1387 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1388 packet->ack = RCODE_SEND_ERROR;
1389 return -1;
1390 }
1391 packet->payload_bus = payload_bus;
1392 packet->payload_mapped = true;
1393 } else {
1394 memcpy(driver_data->inline_data, packet->payload,
1395 packet->payload_length);
1396 payload_bus = d_bus + 3 * sizeof(*d);
1397 }
1398
1399 d[2].req_count = cpu_to_le16(packet->payload_length);
1400 d[2].data_address = cpu_to_le32(payload_bus);
1401 last = &d[2];
1402 z = 3;
1403 } else {
1404 last = &d[0];
1405 z = 2;
1406 }
1407
1408 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1409 DESCRIPTOR_IRQ_ALWAYS |
1410 DESCRIPTOR_BRANCH_ALWAYS);
1411
1412 /* FIXME: Document how the locking works. */
1413 if (ohci->generation != packet->generation) {
1414 if (packet->payload_mapped)
1415 dma_unmap_single(ohci->card.device, payload_bus,
1416 packet->payload_length, DMA_TO_DEVICE);
1417 packet->ack = RCODE_GENERATION;
1418 return -1;
1419 }
1420
1421 context_append(ctx, d, z, 4 - z);
1422
1423 if (ctx->running)
1424 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1425 else
1426 context_run(ctx, 0);
1427
1428 return 0;
1429}
1430
1431static void at_context_flush(struct context *ctx)
1432{
1433 tasklet_disable(&ctx->tasklet);
1434
1435 ctx->flushing = true;
1436 context_tasklet((unsigned long)ctx);
1437 ctx->flushing = false;
1438
1439 tasklet_enable(&ctx->tasklet);
1440}
1441
1442static int handle_at_packet(struct context *context,
1443 struct descriptor *d,
1444 struct descriptor *last)
1445{
1446 struct driver_data *driver_data;
1447 struct fw_packet *packet;
1448 struct fw_ohci *ohci = context->ohci;
1449 int evt;
1450
1451 if (last->transfer_status == 0 && !context->flushing)
1452 /* This descriptor isn't done yet, stop iteration. */
1453 return 0;
1454
1455 driver_data = (struct driver_data *) &d[3];
1456 packet = driver_data->packet;
1457 if (packet == NULL)
1458 /* This packet was cancelled, just continue. */
1459 return 1;
1460
1461 if (packet->payload_mapped)
1462 dma_unmap_single(ohci->card.device, packet->payload_bus,
1463 packet->payload_length, DMA_TO_DEVICE);
1464
1465 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1466 packet->timestamp = le16_to_cpu(last->res_count);
1467
1468 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1469
1470 switch (evt) {
1471 case OHCI1394_evt_timeout:
1472 /* Async response transmit timed out. */
1473 packet->ack = RCODE_CANCELLED;
1474 break;
1475
1476 case OHCI1394_evt_flushed:
1477 /*
1478 * The packet was flushed should give same error as
1479 * when we try to use a stale generation count.
1480 */
1481 packet->ack = RCODE_GENERATION;
1482 break;
1483
1484 case OHCI1394_evt_missing_ack:
1485 if (context->flushing)
1486 packet->ack = RCODE_GENERATION;
1487 else {
1488 /*
1489 * Using a valid (current) generation count, but the
1490 * node is not on the bus or not sending acks.
1491 */
1492 packet->ack = RCODE_NO_ACK;
1493 }
1494 break;
1495
1496 case ACK_COMPLETE + 0x10:
1497 case ACK_PENDING + 0x10:
1498 case ACK_BUSY_X + 0x10:
1499 case ACK_BUSY_A + 0x10:
1500 case ACK_BUSY_B + 0x10:
1501 case ACK_DATA_ERROR + 0x10:
1502 case ACK_TYPE_ERROR + 0x10:
1503 packet->ack = evt - 0x10;
1504 break;
1505
1506 case OHCI1394_evt_no_status:
1507 if (context->flushing) {
1508 packet->ack = RCODE_GENERATION;
1509 break;
1510 }
1511 /* fall through */
1512
1513 default:
1514 packet->ack = RCODE_SEND_ERROR;
1515 break;
1516 }
1517
1518 packet->callback(packet, &ohci->card, packet->ack);
1519
1520 return 1;
1521}
1522
1523#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1524#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1525#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1526#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1527#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1528
1529static void handle_local_rom(struct fw_ohci *ohci,
1530 struct fw_packet *packet, u32 csr)
1531{
1532 struct fw_packet response;
1533 int tcode, length, i;
1534
1535 tcode = HEADER_GET_TCODE(packet->header[0]);
1536 if (TCODE_IS_BLOCK_PACKET(tcode))
1537 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1538 else
1539 length = 4;
1540
1541 i = csr - CSR_CONFIG_ROM;
1542 if (i + length > CONFIG_ROM_SIZE) {
1543 fw_fill_response(&response, packet->header,
1544 RCODE_ADDRESS_ERROR, NULL, 0);
1545 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1546 fw_fill_response(&response, packet->header,
1547 RCODE_TYPE_ERROR, NULL, 0);
1548 } else {
1549 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1550 (void *) ohci->config_rom + i, length);
1551 }
1552
1553 fw_core_handle_response(&ohci->card, &response);
1554}
1555
1556static void handle_local_lock(struct fw_ohci *ohci,
1557 struct fw_packet *packet, u32 csr)
1558{
1559 struct fw_packet response;
1560 int tcode, length, ext_tcode, sel, try;
1561 __be32 *payload, lock_old;
1562 u32 lock_arg, lock_data;
1563
1564 tcode = HEADER_GET_TCODE(packet->header[0]);
1565 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1566 payload = packet->payload;
1567 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1568
1569 if (tcode == TCODE_LOCK_REQUEST &&
1570 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1571 lock_arg = be32_to_cpu(payload[0]);
1572 lock_data = be32_to_cpu(payload[1]);
1573 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1574 lock_arg = 0;
1575 lock_data = 0;
1576 } else {
1577 fw_fill_response(&response, packet->header,
1578 RCODE_TYPE_ERROR, NULL, 0);
1579 goto out;
1580 }
1581
1582 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1583 reg_write(ohci, OHCI1394_CSRData, lock_data);
1584 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1585 reg_write(ohci, OHCI1394_CSRControl, sel);
1586
1587 for (try = 0; try < 20; try++)
1588 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1589 lock_old = cpu_to_be32(reg_read(ohci,
1590 OHCI1394_CSRData));
1591 fw_fill_response(&response, packet->header,
1592 RCODE_COMPLETE,
1593 &lock_old, sizeof(lock_old));
1594 goto out;
1595 }
1596
1597 ohci_err(ohci, "swap not done (CSR lock timeout)\n");
1598 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1599
1600 out:
1601 fw_core_handle_response(&ohci->card, &response);
1602}
1603
1604static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1605{
1606 u64 offset, csr;
1607
1608 if (ctx == &ctx->ohci->at_request_ctx) {
1609 packet->ack = ACK_PENDING;
1610 packet->callback(packet, &ctx->ohci->card, packet->ack);
1611 }
1612
1613 offset =
1614 ((unsigned long long)
1615 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1616 packet->header[2];
1617 csr = offset - CSR_REGISTER_BASE;
1618
1619 /* Handle config rom reads. */
1620 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1621 handle_local_rom(ctx->ohci, packet, csr);
1622 else switch (csr) {
1623 case CSR_BUS_MANAGER_ID:
1624 case CSR_BANDWIDTH_AVAILABLE:
1625 case CSR_CHANNELS_AVAILABLE_HI:
1626 case CSR_CHANNELS_AVAILABLE_LO:
1627 handle_local_lock(ctx->ohci, packet, csr);
1628 break;
1629 default:
1630 if (ctx == &ctx->ohci->at_request_ctx)
1631 fw_core_handle_request(&ctx->ohci->card, packet);
1632 else
1633 fw_core_handle_response(&ctx->ohci->card, packet);
1634 break;
1635 }
1636
1637 if (ctx == &ctx->ohci->at_response_ctx) {
1638 packet->ack = ACK_COMPLETE;
1639 packet->callback(packet, &ctx->ohci->card, packet->ack);
1640 }
1641}
1642
1643static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1644{
1645 unsigned long flags;
1646 int ret;
1647
1648 spin_lock_irqsave(&ctx->ohci->lock, flags);
1649
1650 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1651 ctx->ohci->generation == packet->generation) {
1652 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1653 handle_local_request(ctx, packet);
1654 return;
1655 }
1656
1657 ret = at_context_queue_packet(ctx, packet);
1658 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1659
1660 if (ret < 0)
1661 packet->callback(packet, &ctx->ohci->card, packet->ack);
1662
1663}
1664
1665static void detect_dead_context(struct fw_ohci *ohci,
1666 const char *name, unsigned int regs)
1667{
1668 u32 ctl;
1669
1670 ctl = reg_read(ohci, CONTROL_SET(regs));
1671 if (ctl & CONTEXT_DEAD)
1672 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
1673 name, evts[ctl & 0x1f]);
1674}
1675
1676static void handle_dead_contexts(struct fw_ohci *ohci)
1677{
1678 unsigned int i;
1679 char name[8];
1680
1681 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1682 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1683 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1684 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1685 for (i = 0; i < 32; ++i) {
1686 if (!(ohci->it_context_support & (1 << i)))
1687 continue;
1688 sprintf(name, "IT%u", i);
1689 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1690 }
1691 for (i = 0; i < 32; ++i) {
1692 if (!(ohci->ir_context_support & (1 << i)))
1693 continue;
1694 sprintf(name, "IR%u", i);
1695 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1696 }
1697 /* TODO: maybe try to flush and restart the dead contexts */
1698}
1699
1700static u32 cycle_timer_ticks(u32 cycle_timer)
1701{
1702 u32 ticks;
1703
1704 ticks = cycle_timer & 0xfff;
1705 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1706 ticks += (3072 * 8000) * (cycle_timer >> 25);
1707
1708 return ticks;
1709}
1710
1711/*
1712 * Some controllers exhibit one or more of the following bugs when updating the
1713 * iso cycle timer register:
1714 * - When the lowest six bits are wrapping around to zero, a read that happens
1715 * at the same time will return garbage in the lowest ten bits.
1716 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1717 * not incremented for about 60 ns.
1718 * - Occasionally, the entire register reads zero.
1719 *
1720 * To catch these, we read the register three times and ensure that the
1721 * difference between each two consecutive reads is approximately the same, i.e.
1722 * less than twice the other. Furthermore, any negative difference indicates an
1723 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1724 * execute, so we have enough precision to compute the ratio of the differences.)
1725 */
1726static u32 get_cycle_time(struct fw_ohci *ohci)
1727{
1728 u32 c0, c1, c2;
1729 u32 t0, t1, t2;
1730 s32 diff01, diff12;
1731 int i;
1732
1733 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1734
1735 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1736 i = 0;
1737 c1 = c2;
1738 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1739 do {
1740 c0 = c1;
1741 c1 = c2;
1742 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1743 t0 = cycle_timer_ticks(c0);
1744 t1 = cycle_timer_ticks(c1);
1745 t2 = cycle_timer_ticks(c2);
1746 diff01 = t1 - t0;
1747 diff12 = t2 - t1;
1748 } while ((diff01 <= 0 || diff12 <= 0 ||
1749 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1750 && i++ < 20);
1751 }
1752
1753 return c2;
1754}
1755
1756/*
1757 * This function has to be called at least every 64 seconds. The bus_time
1758 * field stores not only the upper 25 bits of the BUS_TIME register but also
1759 * the most significant bit of the cycle timer in bit 6 so that we can detect
1760 * changes in this bit.
1761 */
1762static u32 update_bus_time(struct fw_ohci *ohci)
1763{
1764 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1765
1766 if (unlikely(!ohci->bus_time_running)) {
1767 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1768 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1769 (cycle_time_seconds & 0x40);
1770 ohci->bus_time_running = true;
1771 }
1772
1773 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1774 ohci->bus_time += 0x40;
1775
1776 return ohci->bus_time | cycle_time_seconds;
1777}
1778
1779static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1780{
1781 int reg;
1782
1783 mutex_lock(&ohci->phy_reg_mutex);
1784 reg = write_phy_reg(ohci, 7, port_index);
1785 if (reg >= 0)
1786 reg = read_phy_reg(ohci, 8);
1787 mutex_unlock(&ohci->phy_reg_mutex);
1788 if (reg < 0)
1789 return reg;
1790
1791 switch (reg & 0x0f) {
1792 case 0x06:
1793 return 2; /* is child node (connected to parent node) */
1794 case 0x0e:
1795 return 3; /* is parent node (connected to child node) */
1796 }
1797 return 1; /* not connected */
1798}
1799
1800static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1801 int self_id_count)
1802{
1803 int i;
1804 u32 entry;
1805
1806 for (i = 0; i < self_id_count; i++) {
1807 entry = ohci->self_id_buffer[i];
1808 if ((self_id & 0xff000000) == (entry & 0xff000000))
1809 return -1;
1810 if ((self_id & 0xff000000) < (entry & 0xff000000))
1811 return i;
1812 }
1813 return i;
1814}
1815
1816static int initiated_reset(struct fw_ohci *ohci)
1817{
1818 int reg;
1819 int ret = 0;
1820
1821 mutex_lock(&ohci->phy_reg_mutex);
1822 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1823 if (reg >= 0) {
1824 reg = read_phy_reg(ohci, 8);
1825 reg |= 0x40;
1826 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1827 if (reg >= 0) {
1828 reg = read_phy_reg(ohci, 12); /* read register 12 */
1829 if (reg >= 0) {
1830 if ((reg & 0x08) == 0x08) {
1831 /* bit 3 indicates "initiated reset" */
1832 ret = 0x2;
1833 }
1834 }
1835 }
1836 }
1837 mutex_unlock(&ohci->phy_reg_mutex);
1838 return ret;
1839}
1840
1841/*
1842 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1843 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1844 * Construct the selfID from phy register contents.
1845 */
1846static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1847{
1848 int reg, i, pos, status;
1849 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1850 u32 self_id = 0x8040c800;
1851
1852 reg = reg_read(ohci, OHCI1394_NodeID);
1853 if (!(reg & OHCI1394_NodeID_idValid)) {
1854 ohci_notice(ohci,
1855 "node ID not valid, new bus reset in progress\n");
1856 return -EBUSY;
1857 }
1858 self_id |= ((reg & 0x3f) << 24); /* phy ID */
1859
1860 reg = ohci_read_phy_reg(&ohci->card, 4);
1861 if (reg < 0)
1862 return reg;
1863 self_id |= ((reg & 0x07) << 8); /* power class */
1864
1865 reg = ohci_read_phy_reg(&ohci->card, 1);
1866 if (reg < 0)
1867 return reg;
1868 self_id |= ((reg & 0x3f) << 16); /* gap count */
1869
1870 for (i = 0; i < 3; i++) {
1871 status = get_status_for_port(ohci, i);
1872 if (status < 0)
1873 return status;
1874 self_id |= ((status & 0x3) << (6 - (i * 2)));
1875 }
1876
1877 self_id |= initiated_reset(ohci);
1878
1879 pos = get_self_id_pos(ohci, self_id, self_id_count);
1880 if (pos >= 0) {
1881 memmove(&(ohci->self_id_buffer[pos+1]),
1882 &(ohci->self_id_buffer[pos]),
1883 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1884 ohci->self_id_buffer[pos] = self_id;
1885 self_id_count++;
1886 }
1887 return self_id_count;
1888}
1889
1890static void bus_reset_work(struct work_struct *work)
1891{
1892 struct fw_ohci *ohci =
1893 container_of(work, struct fw_ohci, bus_reset_work);
1894 int self_id_count, generation, new_generation, i, j;
1895 u32 reg;
1896 void *free_rom = NULL;
1897 dma_addr_t free_rom_bus = 0;
1898 bool is_new_root;
1899
1900 reg = reg_read(ohci, OHCI1394_NodeID);
1901 if (!(reg & OHCI1394_NodeID_idValid)) {
1902 ohci_notice(ohci,
1903 "node ID not valid, new bus reset in progress\n");
1904 return;
1905 }
1906 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1907 ohci_notice(ohci, "malconfigured bus\n");
1908 return;
1909 }
1910 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1911 OHCI1394_NodeID_nodeNumber);
1912
1913 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1914 if (!(ohci->is_root && is_new_root))
1915 reg_write(ohci, OHCI1394_LinkControlSet,
1916 OHCI1394_LinkControl_cycleMaster);
1917 ohci->is_root = is_new_root;
1918
1919 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1920 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1921 ohci_notice(ohci, "self ID receive error\n");
1922 return;
1923 }
1924 /*
1925 * The count in the SelfIDCount register is the number of
1926 * bytes in the self ID receive buffer. Since we also receive
1927 * the inverted quadlets and a header quadlet, we shift one
1928 * bit extra to get the actual number of self IDs.
1929 */
1930 self_id_count = (reg >> 3) & 0xff;
1931
1932 if (self_id_count > 252) {
1933 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
1934 return;
1935 }
1936
1937 generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
1938 rmb();
1939
1940 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1941 u32 id = cond_le32_to_cpu(ohci->self_id[i]);
1942 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
1943
1944 if (id != ~id2) {
1945 /*
1946 * If the invalid data looks like a cycle start packet,
1947 * it's likely to be the result of the cycle master
1948 * having a wrong gap count. In this case, the self IDs
1949 * so far are valid and should be processed so that the
1950 * bus manager can then correct the gap count.
1951 */
1952 if (id == 0xffff008f) {
1953 ohci_notice(ohci, "ignoring spurious self IDs\n");
1954 self_id_count = j;
1955 break;
1956 }
1957
1958 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
1959 j, self_id_count, id, id2);
1960 return;
1961 }
1962 ohci->self_id_buffer[j] = id;
1963 }
1964
1965 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1966 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1967 if (self_id_count < 0) {
1968 ohci_notice(ohci,
1969 "could not construct local self ID\n");
1970 return;
1971 }
1972 }
1973
1974 if (self_id_count == 0) {
1975 ohci_notice(ohci, "no self IDs\n");
1976 return;
1977 }
1978 rmb();
1979
1980 /*
1981 * Check the consistency of the self IDs we just read. The
1982 * problem we face is that a new bus reset can start while we
1983 * read out the self IDs from the DMA buffer. If this happens,
1984 * the DMA buffer will be overwritten with new self IDs and we
1985 * will read out inconsistent data. The OHCI specification
1986 * (section 11.2) recommends a technique similar to
1987 * linux/seqlock.h, where we remember the generation of the
1988 * self IDs in the buffer before reading them out and compare
1989 * it to the current generation after reading them out. If
1990 * the two generations match we know we have a consistent set
1991 * of self IDs.
1992 */
1993
1994 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1995 if (new_generation != generation) {
1996 ohci_notice(ohci, "new bus reset, discarding self ids\n");
1997 return;
1998 }
1999
2000 /* FIXME: Document how the locking works. */
2001 spin_lock_irq(&ohci->lock);
2002
2003 ohci->generation = -1; /* prevent AT packet queueing */
2004 context_stop(&ohci->at_request_ctx);
2005 context_stop(&ohci->at_response_ctx);
2006
2007 spin_unlock_irq(&ohci->lock);
2008
2009 /*
2010 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2011 * packets in the AT queues and software needs to drain them.
2012 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2013 */
2014 at_context_flush(&ohci->at_request_ctx);
2015 at_context_flush(&ohci->at_response_ctx);
2016
2017 spin_lock_irq(&ohci->lock);
2018
2019 ohci->generation = generation;
2020 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2021
2022 if (ohci->quirks & QUIRK_RESET_PACKET)
2023 ohci->request_generation = generation;
2024
2025 /*
2026 * This next bit is unrelated to the AT context stuff but we
2027 * have to do it under the spinlock also. If a new config rom
2028 * was set up before this reset, the old one is now no longer
2029 * in use and we can free it. Update the config rom pointers
2030 * to point to the current config rom and clear the
2031 * next_config_rom pointer so a new update can take place.
2032 */
2033
2034 if (ohci->next_config_rom != NULL) {
2035 if (ohci->next_config_rom != ohci->config_rom) {
2036 free_rom = ohci->config_rom;
2037 free_rom_bus = ohci->config_rom_bus;
2038 }
2039 ohci->config_rom = ohci->next_config_rom;
2040 ohci->config_rom_bus = ohci->next_config_rom_bus;
2041 ohci->next_config_rom = NULL;
2042
2043 /*
2044 * Restore config_rom image and manually update
2045 * config_rom registers. Writing the header quadlet
2046 * will indicate that the config rom is ready, so we
2047 * do that last.
2048 */
2049 reg_write(ohci, OHCI1394_BusOptions,
2050 be32_to_cpu(ohci->config_rom[2]));
2051 ohci->config_rom[0] = ohci->next_header;
2052 reg_write(ohci, OHCI1394_ConfigROMhdr,
2053 be32_to_cpu(ohci->next_header));
2054 }
2055
2056 if (param_remote_dma) {
2057 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2058 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2059 }
2060
2061 spin_unlock_irq(&ohci->lock);
2062
2063 if (free_rom)
2064 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2065 free_rom, free_rom_bus);
2066
2067 log_selfids(ohci, generation, self_id_count);
2068
2069 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2070 self_id_count, ohci->self_id_buffer,
2071 ohci->csr_state_setclear_abdicate);
2072 ohci->csr_state_setclear_abdicate = false;
2073}
2074
2075static irqreturn_t irq_handler(int irq, void *data)
2076{
2077 struct fw_ohci *ohci = data;
2078 u32 event, iso_event;
2079 int i;
2080
2081 event = reg_read(ohci, OHCI1394_IntEventClear);
2082
2083 if (!event || !~event)
2084 return IRQ_NONE;
2085
2086 /*
2087 * busReset and postedWriteErr must not be cleared yet
2088 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2089 */
2090 reg_write(ohci, OHCI1394_IntEventClear,
2091 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2092 log_irqs(ohci, event);
2093
2094 if (event & OHCI1394_selfIDComplete)
2095 queue_work(selfid_workqueue, &ohci->bus_reset_work);
2096
2097 if (event & OHCI1394_RQPkt)
2098 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2099
2100 if (event & OHCI1394_RSPkt)
2101 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2102
2103 if (event & OHCI1394_reqTxComplete)
2104 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2105
2106 if (event & OHCI1394_respTxComplete)
2107 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2108
2109 if (event & OHCI1394_isochRx) {
2110 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2111 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2112
2113 while (iso_event) {
2114 i = ffs(iso_event) - 1;
2115 tasklet_schedule(
2116 &ohci->ir_context_list[i].context.tasklet);
2117 iso_event &= ~(1 << i);
2118 }
2119 }
2120
2121 if (event & OHCI1394_isochTx) {
2122 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2123 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2124
2125 while (iso_event) {
2126 i = ffs(iso_event) - 1;
2127 tasklet_schedule(
2128 &ohci->it_context_list[i].context.tasklet);
2129 iso_event &= ~(1 << i);
2130 }
2131 }
2132
2133 if (unlikely(event & OHCI1394_regAccessFail))
2134 ohci_err(ohci, "register access failure\n");
2135
2136 if (unlikely(event & OHCI1394_postedWriteErr)) {
2137 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2138 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2139 reg_write(ohci, OHCI1394_IntEventClear,
2140 OHCI1394_postedWriteErr);
2141 if (printk_ratelimit())
2142 ohci_err(ohci, "PCI posted write error\n");
2143 }
2144
2145 if (unlikely(event & OHCI1394_cycleTooLong)) {
2146 if (printk_ratelimit())
2147 ohci_notice(ohci, "isochronous cycle too long\n");
2148 reg_write(ohci, OHCI1394_LinkControlSet,
2149 OHCI1394_LinkControl_cycleMaster);
2150 }
2151
2152 if (unlikely(event & OHCI1394_cycleInconsistent)) {
2153 /*
2154 * We need to clear this event bit in order to make
2155 * cycleMatch isochronous I/O work. In theory we should
2156 * stop active cycleMatch iso contexts now and restart
2157 * them at least two cycles later. (FIXME?)
2158 */
2159 if (printk_ratelimit())
2160 ohci_notice(ohci, "isochronous cycle inconsistent\n");
2161 }
2162
2163 if (unlikely(event & OHCI1394_unrecoverableError))
2164 handle_dead_contexts(ohci);
2165
2166 if (event & OHCI1394_cycle64Seconds) {
2167 spin_lock(&ohci->lock);
2168 update_bus_time(ohci);
2169 spin_unlock(&ohci->lock);
2170 } else
2171 flush_writes(ohci);
2172
2173 return IRQ_HANDLED;
2174}
2175
2176static int software_reset(struct fw_ohci *ohci)
2177{
2178 u32 val;
2179 int i;
2180
2181 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2182 for (i = 0; i < 500; i++) {
2183 val = reg_read(ohci, OHCI1394_HCControlSet);
2184 if (!~val)
2185 return -ENODEV; /* Card was ejected. */
2186
2187 if (!(val & OHCI1394_HCControl_softReset))
2188 return 0;
2189
2190 msleep(1);
2191 }
2192
2193 return -EBUSY;
2194}
2195
2196static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2197{
2198 size_t size = length * 4;
2199
2200 memcpy(dest, src, size);
2201 if (size < CONFIG_ROM_SIZE)
2202 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2203}
2204
2205static int configure_1394a_enhancements(struct fw_ohci *ohci)
2206{
2207 bool enable_1394a;
2208 int ret, clear, set, offset;
2209
2210 /* Check if the driver should configure link and PHY. */
2211 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2212 OHCI1394_HCControl_programPhyEnable))
2213 return 0;
2214
2215 /* Paranoia: check whether the PHY supports 1394a, too. */
2216 enable_1394a = false;
2217 ret = read_phy_reg(ohci, 2);
2218 if (ret < 0)
2219 return ret;
2220 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2221 ret = read_paged_phy_reg(ohci, 1, 8);
2222 if (ret < 0)
2223 return ret;
2224 if (ret >= 1)
2225 enable_1394a = true;
2226 }
2227
2228 if (ohci->quirks & QUIRK_NO_1394A)
2229 enable_1394a = false;
2230
2231 /* Configure PHY and link consistently. */
2232 if (enable_1394a) {
2233 clear = 0;
2234 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2235 } else {
2236 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2237 set = 0;
2238 }
2239 ret = update_phy_reg(ohci, 5, clear, set);
2240 if (ret < 0)
2241 return ret;
2242
2243 if (enable_1394a)
2244 offset = OHCI1394_HCControlSet;
2245 else
2246 offset = OHCI1394_HCControlClear;
2247 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2248
2249 /* Clean up: configuration has been taken care of. */
2250 reg_write(ohci, OHCI1394_HCControlClear,
2251 OHCI1394_HCControl_programPhyEnable);
2252
2253 return 0;
2254}
2255
2256static int probe_tsb41ba3d(struct fw_ohci *ohci)
2257{
2258 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2259 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2260 int reg, i;
2261
2262 reg = read_phy_reg(ohci, 2);
2263 if (reg < 0)
2264 return reg;
2265 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2266 return 0;
2267
2268 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2269 reg = read_paged_phy_reg(ohci, 1, i + 10);
2270 if (reg < 0)
2271 return reg;
2272 if (reg != id[i])
2273 return 0;
2274 }
2275 return 1;
2276}
2277
2278static int ohci_enable(struct fw_card *card,
2279 const __be32 *config_rom, size_t length)
2280{
2281 struct fw_ohci *ohci = fw_ohci(card);
2282 u32 lps, version, irqs;
2283 int i, ret;
2284
2285 ret = software_reset(ohci);
2286 if (ret < 0) {
2287 ohci_err(ohci, "failed to reset ohci card\n");
2288 return ret;
2289 }
2290
2291 /*
2292 * Now enable LPS, which we need in order to start accessing
2293 * most of the registers. In fact, on some cards (ALI M5251),
2294 * accessing registers in the SClk domain without LPS enabled
2295 * will lock up the machine. Wait 50msec to make sure we have
2296 * full link enabled. However, with some cards (well, at least
2297 * a JMicron PCIe card), we have to try again sometimes.
2298 *
2299 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2300 * cannot actually use the phy at that time. These need tens of
2301 * millisecods pause between LPS write and first phy access too.
2302 */
2303
2304 reg_write(ohci, OHCI1394_HCControlSet,
2305 OHCI1394_HCControl_LPS |
2306 OHCI1394_HCControl_postedWriteEnable);
2307 flush_writes(ohci);
2308
2309 for (lps = 0, i = 0; !lps && i < 3; i++) {
2310 msleep(50);
2311 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2312 OHCI1394_HCControl_LPS;
2313 }
2314
2315 if (!lps) {
2316 ohci_err(ohci, "failed to set Link Power Status\n");
2317 return -EIO;
2318 }
2319
2320 if (ohci->quirks & QUIRK_TI_SLLZ059) {
2321 ret = probe_tsb41ba3d(ohci);
2322 if (ret < 0)
2323 return ret;
2324 if (ret)
2325 ohci_notice(ohci, "local TSB41BA3D phy\n");
2326 else
2327 ohci->quirks &= ~QUIRK_TI_SLLZ059;
2328 }
2329
2330 reg_write(ohci, OHCI1394_HCControlClear,
2331 OHCI1394_HCControl_noByteSwapData);
2332
2333 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2334 reg_write(ohci, OHCI1394_LinkControlSet,
2335 OHCI1394_LinkControl_cycleTimerEnable |
2336 OHCI1394_LinkControl_cycleMaster);
2337
2338 reg_write(ohci, OHCI1394_ATRetries,
2339 OHCI1394_MAX_AT_REQ_RETRIES |
2340 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2341 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2342 (200 << 16));
2343
2344 ohci->bus_time_running = false;
2345
2346 for (i = 0; i < 32; i++)
2347 if (ohci->ir_context_support & (1 << i))
2348 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2349 IR_CONTEXT_MULTI_CHANNEL_MODE);
2350
2351 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2352 if (version >= OHCI_VERSION_1_1) {
2353 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2354 0xfffffffe);
2355 card->broadcast_channel_auto_allocated = true;
2356 }
2357
2358 /* Get implemented bits of the priority arbitration request counter. */
2359 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2360 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2361 reg_write(ohci, OHCI1394_FairnessControl, 0);
2362 card->priority_budget_implemented = ohci->pri_req_max != 0;
2363
2364 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
2365 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2366 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2367
2368 ret = configure_1394a_enhancements(ohci);
2369 if (ret < 0)
2370 return ret;
2371
2372 /* Activate link_on bit and contender bit in our self ID packets.*/
2373 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2374 if (ret < 0)
2375 return ret;
2376
2377 /*
2378 * When the link is not yet enabled, the atomic config rom
2379 * update mechanism described below in ohci_set_config_rom()
2380 * is not active. We have to update ConfigRomHeader and
2381 * BusOptions manually, and the write to ConfigROMmap takes
2382 * effect immediately. We tie this to the enabling of the
2383 * link, so we have a valid config rom before enabling - the
2384 * OHCI requires that ConfigROMhdr and BusOptions have valid
2385 * values before enabling.
2386 *
2387 * However, when the ConfigROMmap is written, some controllers
2388 * always read back quadlets 0 and 2 from the config rom to
2389 * the ConfigRomHeader and BusOptions registers on bus reset.
2390 * They shouldn't do that in this initial case where the link
2391 * isn't enabled. This means we have to use the same
2392 * workaround here, setting the bus header to 0 and then write
2393 * the right values in the bus reset tasklet.
2394 */
2395
2396 if (config_rom) {
2397 ohci->next_config_rom =
2398 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2399 &ohci->next_config_rom_bus,
2400 GFP_KERNEL);
2401 if (ohci->next_config_rom == NULL)
2402 return -ENOMEM;
2403
2404 copy_config_rom(ohci->next_config_rom, config_rom, length);
2405 } else {
2406 /*
2407 * In the suspend case, config_rom is NULL, which
2408 * means that we just reuse the old config rom.
2409 */
2410 ohci->next_config_rom = ohci->config_rom;
2411 ohci->next_config_rom_bus = ohci->config_rom_bus;
2412 }
2413
2414 ohci->next_header = ohci->next_config_rom[0];
2415 ohci->next_config_rom[0] = 0;
2416 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2417 reg_write(ohci, OHCI1394_BusOptions,
2418 be32_to_cpu(ohci->next_config_rom[2]));
2419 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2420
2421 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2422
2423 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2424 OHCI1394_RQPkt | OHCI1394_RSPkt |
2425 OHCI1394_isochTx | OHCI1394_isochRx |
2426 OHCI1394_postedWriteErr |
2427 OHCI1394_selfIDComplete |
2428 OHCI1394_regAccessFail |
2429 OHCI1394_cycleInconsistent |
2430 OHCI1394_unrecoverableError |
2431 OHCI1394_cycleTooLong |
2432 OHCI1394_masterIntEnable;
2433 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2434 irqs |= OHCI1394_busReset;
2435 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2436
2437 reg_write(ohci, OHCI1394_HCControlSet,
2438 OHCI1394_HCControl_linkEnable |
2439 OHCI1394_HCControl_BIBimageValid);
2440
2441 reg_write(ohci, OHCI1394_LinkControlSet,
2442 OHCI1394_LinkControl_rcvSelfID |
2443 OHCI1394_LinkControl_rcvPhyPkt);
2444
2445 ar_context_run(&ohci->ar_request_ctx);
2446 ar_context_run(&ohci->ar_response_ctx);
2447
2448 flush_writes(ohci);
2449
2450 /* We are ready to go, reset bus to finish initialization. */
2451 fw_schedule_bus_reset(&ohci->card, false, true);
2452
2453 return 0;
2454}
2455
2456static int ohci_set_config_rom(struct fw_card *card,
2457 const __be32 *config_rom, size_t length)
2458{
2459 struct fw_ohci *ohci;
2460 __be32 *next_config_rom;
2461 dma_addr_t uninitialized_var(next_config_rom_bus);
2462
2463 ohci = fw_ohci(card);
2464
2465 /*
2466 * When the OHCI controller is enabled, the config rom update
2467 * mechanism is a bit tricky, but easy enough to use. See
2468 * section 5.5.6 in the OHCI specification.
2469 *
2470 * The OHCI controller caches the new config rom address in a
2471 * shadow register (ConfigROMmapNext) and needs a bus reset
2472 * for the changes to take place. When the bus reset is
2473 * detected, the controller loads the new values for the
2474 * ConfigRomHeader and BusOptions registers from the specified
2475 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2476 * shadow register. All automatically and atomically.
2477 *
2478 * Now, there's a twist to this story. The automatic load of
2479 * ConfigRomHeader and BusOptions doesn't honor the
2480 * noByteSwapData bit, so with a be32 config rom, the
2481 * controller will load be32 values in to these registers
2482 * during the atomic update, even on litte endian
2483 * architectures. The workaround we use is to put a 0 in the
2484 * header quadlet; 0 is endian agnostic and means that the
2485 * config rom isn't ready yet. In the bus reset tasklet we
2486 * then set up the real values for the two registers.
2487 *
2488 * We use ohci->lock to avoid racing with the code that sets
2489 * ohci->next_config_rom to NULL (see bus_reset_work).
2490 */
2491
2492 next_config_rom =
2493 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2494 &next_config_rom_bus, GFP_KERNEL);
2495 if (next_config_rom == NULL)
2496 return -ENOMEM;
2497
2498 spin_lock_irq(&ohci->lock);
2499
2500 /*
2501 * If there is not an already pending config_rom update,
2502 * push our new allocation into the ohci->next_config_rom
2503 * and then mark the local variable as null so that we
2504 * won't deallocate the new buffer.
2505 *
2506 * OTOH, if there is a pending config_rom update, just
2507 * use that buffer with the new config_rom data, and
2508 * let this routine free the unused DMA allocation.
2509 */
2510
2511 if (ohci->next_config_rom == NULL) {
2512 ohci->next_config_rom = next_config_rom;
2513 ohci->next_config_rom_bus = next_config_rom_bus;
2514 next_config_rom = NULL;
2515 }
2516
2517 copy_config_rom(ohci->next_config_rom, config_rom, length);
2518
2519 ohci->next_header = config_rom[0];
2520 ohci->next_config_rom[0] = 0;
2521
2522 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2523
2524 spin_unlock_irq(&ohci->lock);
2525
2526 /* If we didn't use the DMA allocation, delete it. */
2527 if (next_config_rom != NULL)
2528 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2529 next_config_rom, next_config_rom_bus);
2530
2531 /*
2532 * Now initiate a bus reset to have the changes take
2533 * effect. We clean up the old config rom memory and DMA
2534 * mappings in the bus reset tasklet, since the OHCI
2535 * controller could need to access it before the bus reset
2536 * takes effect.
2537 */
2538
2539 fw_schedule_bus_reset(&ohci->card, true, true);
2540
2541 return 0;
2542}
2543
2544static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2545{
2546 struct fw_ohci *ohci = fw_ohci(card);
2547
2548 at_context_transmit(&ohci->at_request_ctx, packet);
2549}
2550
2551static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2552{
2553 struct fw_ohci *ohci = fw_ohci(card);
2554
2555 at_context_transmit(&ohci->at_response_ctx, packet);
2556}
2557
2558static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2559{
2560 struct fw_ohci *ohci = fw_ohci(card);
2561 struct context *ctx = &ohci->at_request_ctx;
2562 struct driver_data *driver_data = packet->driver_data;
2563 int ret = -ENOENT;
2564
2565 tasklet_disable(&ctx->tasklet);
2566
2567 if (packet->ack != 0)
2568 goto out;
2569
2570 if (packet->payload_mapped)
2571 dma_unmap_single(ohci->card.device, packet->payload_bus,
2572 packet->payload_length, DMA_TO_DEVICE);
2573
2574 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2575 driver_data->packet = NULL;
2576 packet->ack = RCODE_CANCELLED;
2577 packet->callback(packet, &ohci->card, packet->ack);
2578 ret = 0;
2579 out:
2580 tasklet_enable(&ctx->tasklet);
2581
2582 return ret;
2583}
2584
2585static int ohci_enable_phys_dma(struct fw_card *card,
2586 int node_id, int generation)
2587{
2588 struct fw_ohci *ohci = fw_ohci(card);
2589 unsigned long flags;
2590 int n, ret = 0;
2591
2592 if (param_remote_dma)
2593 return 0;
2594
2595 /*
2596 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2597 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2598 */
2599
2600 spin_lock_irqsave(&ohci->lock, flags);
2601
2602 if (ohci->generation != generation) {
2603 ret = -ESTALE;
2604 goto out;
2605 }
2606
2607 /*
2608 * Note, if the node ID contains a non-local bus ID, physical DMA is
2609 * enabled for _all_ nodes on remote buses.
2610 */
2611
2612 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2613 if (n < 32)
2614 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2615 else
2616 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2617
2618 flush_writes(ohci);
2619 out:
2620 spin_unlock_irqrestore(&ohci->lock, flags);
2621
2622 return ret;
2623}
2624
2625static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2626{
2627 struct fw_ohci *ohci = fw_ohci(card);
2628 unsigned long flags;
2629 u32 value;
2630
2631 switch (csr_offset) {
2632 case CSR_STATE_CLEAR:
2633 case CSR_STATE_SET:
2634 if (ohci->is_root &&
2635 (reg_read(ohci, OHCI1394_LinkControlSet) &
2636 OHCI1394_LinkControl_cycleMaster))
2637 value = CSR_STATE_BIT_CMSTR;
2638 else
2639 value = 0;
2640 if (ohci->csr_state_setclear_abdicate)
2641 value |= CSR_STATE_BIT_ABDICATE;
2642
2643 return value;
2644
2645 case CSR_NODE_IDS:
2646 return reg_read(ohci, OHCI1394_NodeID) << 16;
2647
2648 case CSR_CYCLE_TIME:
2649 return get_cycle_time(ohci);
2650
2651 case CSR_BUS_TIME:
2652 /*
2653 * We might be called just after the cycle timer has wrapped
2654 * around but just before the cycle64Seconds handler, so we
2655 * better check here, too, if the bus time needs to be updated.
2656 */
2657 spin_lock_irqsave(&ohci->lock, flags);
2658 value = update_bus_time(ohci);
2659 spin_unlock_irqrestore(&ohci->lock, flags);
2660 return value;
2661
2662 case CSR_BUSY_TIMEOUT:
2663 value = reg_read(ohci, OHCI1394_ATRetries);
2664 return (value >> 4) & 0x0ffff00f;
2665
2666 case CSR_PRIORITY_BUDGET:
2667 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2668 (ohci->pri_req_max << 8);
2669
2670 default:
2671 WARN_ON(1);
2672 return 0;
2673 }
2674}
2675
2676static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2677{
2678 struct fw_ohci *ohci = fw_ohci(card);
2679 unsigned long flags;
2680
2681 switch (csr_offset) {
2682 case CSR_STATE_CLEAR:
2683 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2684 reg_write(ohci, OHCI1394_LinkControlClear,
2685 OHCI1394_LinkControl_cycleMaster);
2686 flush_writes(ohci);
2687 }
2688 if (value & CSR_STATE_BIT_ABDICATE)
2689 ohci->csr_state_setclear_abdicate = false;
2690 break;
2691
2692 case CSR_STATE_SET:
2693 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2694 reg_write(ohci, OHCI1394_LinkControlSet,
2695 OHCI1394_LinkControl_cycleMaster);
2696 flush_writes(ohci);
2697 }
2698 if (value & CSR_STATE_BIT_ABDICATE)
2699 ohci->csr_state_setclear_abdicate = true;
2700 break;
2701
2702 case CSR_NODE_IDS:
2703 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2704 flush_writes(ohci);
2705 break;
2706
2707 case CSR_CYCLE_TIME:
2708 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2709 reg_write(ohci, OHCI1394_IntEventSet,
2710 OHCI1394_cycleInconsistent);
2711 flush_writes(ohci);
2712 break;
2713
2714 case CSR_BUS_TIME:
2715 spin_lock_irqsave(&ohci->lock, flags);
2716 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2717 (value & ~0x7f);
2718 spin_unlock_irqrestore(&ohci->lock, flags);
2719 break;
2720
2721 case CSR_BUSY_TIMEOUT:
2722 value = (value & 0xf) | ((value & 0xf) << 4) |
2723 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2724 reg_write(ohci, OHCI1394_ATRetries, value);
2725 flush_writes(ohci);
2726 break;
2727
2728 case CSR_PRIORITY_BUDGET:
2729 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2730 flush_writes(ohci);
2731 break;
2732
2733 default:
2734 WARN_ON(1);
2735 break;
2736 }
2737}
2738
2739static void flush_iso_completions(struct iso_context *ctx)
2740{
2741 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2742 ctx->header_length, ctx->header,
2743 ctx->base.callback_data);
2744 ctx->header_length = 0;
2745}
2746
2747static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2748{
2749 u32 *ctx_hdr;
2750
2751 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
2752 if (ctx->base.drop_overflow_headers)
2753 return;
2754 flush_iso_completions(ctx);
2755 }
2756
2757 ctx_hdr = ctx->header + ctx->header_length;
2758 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2759
2760 /*
2761 * The two iso header quadlets are byteswapped to little
2762 * endian by the controller, but we want to present them
2763 * as big endian for consistency with the bus endianness.
2764 */
2765 if (ctx->base.header_size > 0)
2766 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2767 if (ctx->base.header_size > 4)
2768 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2769 if (ctx->base.header_size > 8)
2770 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2771 ctx->header_length += ctx->base.header_size;
2772}
2773
2774static int handle_ir_packet_per_buffer(struct context *context,
2775 struct descriptor *d,
2776 struct descriptor *last)
2777{
2778 struct iso_context *ctx =
2779 container_of(context, struct iso_context, context);
2780 struct descriptor *pd;
2781 u32 buffer_dma;
2782
2783 for (pd = d; pd <= last; pd++)
2784 if (pd->transfer_status)
2785 break;
2786 if (pd > last)
2787 /* Descriptor(s) not done yet, stop iteration */
2788 return 0;
2789
2790 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2791 d++;
2792 buffer_dma = le32_to_cpu(d->data_address);
2793 dma_sync_single_range_for_cpu(context->ohci->card.device,
2794 buffer_dma & PAGE_MASK,
2795 buffer_dma & ~PAGE_MASK,
2796 le16_to_cpu(d->req_count),
2797 DMA_FROM_DEVICE);
2798 }
2799
2800 copy_iso_headers(ctx, (u32 *) (last + 1));
2801
2802 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2803 flush_iso_completions(ctx);
2804
2805 return 1;
2806}
2807
2808/* d == last because each descriptor block is only a single descriptor. */
2809static int handle_ir_buffer_fill(struct context *context,
2810 struct descriptor *d,
2811 struct descriptor *last)
2812{
2813 struct iso_context *ctx =
2814 container_of(context, struct iso_context, context);
2815 unsigned int req_count, res_count, completed;
2816 u32 buffer_dma;
2817
2818 req_count = le16_to_cpu(last->req_count);
2819 res_count = le16_to_cpu(READ_ONCE(last->res_count));
2820 completed = req_count - res_count;
2821 buffer_dma = le32_to_cpu(last->data_address);
2822
2823 if (completed > 0) {
2824 ctx->mc_buffer_bus = buffer_dma;
2825 ctx->mc_completed = completed;
2826 }
2827
2828 if (res_count != 0)
2829 /* Descriptor(s) not done yet, stop iteration */
2830 return 0;
2831
2832 dma_sync_single_range_for_cpu(context->ohci->card.device,
2833 buffer_dma & PAGE_MASK,
2834 buffer_dma & ~PAGE_MASK,
2835 completed, DMA_FROM_DEVICE);
2836
2837 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2838 ctx->base.callback.mc(&ctx->base,
2839 buffer_dma + completed,
2840 ctx->base.callback_data);
2841 ctx->mc_completed = 0;
2842 }
2843
2844 return 1;
2845}
2846
2847static void flush_ir_buffer_fill(struct iso_context *ctx)
2848{
2849 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2850 ctx->mc_buffer_bus & PAGE_MASK,
2851 ctx->mc_buffer_bus & ~PAGE_MASK,
2852 ctx->mc_completed, DMA_FROM_DEVICE);
2853
2854 ctx->base.callback.mc(&ctx->base,
2855 ctx->mc_buffer_bus + ctx->mc_completed,
2856 ctx->base.callback_data);
2857 ctx->mc_completed = 0;
2858}
2859
2860static inline void sync_it_packet_for_cpu(struct context *context,
2861 struct descriptor *pd)
2862{
2863 __le16 control;
2864 u32 buffer_dma;
2865
2866 /* only packets beginning with OUTPUT_MORE* have data buffers */
2867 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2868 return;
2869
2870 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2871 pd += 2;
2872
2873 /*
2874 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2875 * data buffer is in the context program's coherent page and must not
2876 * be synced.
2877 */
2878 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2879 (context->current_bus & PAGE_MASK)) {
2880 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2881 return;
2882 pd++;
2883 }
2884
2885 do {
2886 buffer_dma = le32_to_cpu(pd->data_address);
2887 dma_sync_single_range_for_cpu(context->ohci->card.device,
2888 buffer_dma & PAGE_MASK,
2889 buffer_dma & ~PAGE_MASK,
2890 le16_to_cpu(pd->req_count),
2891 DMA_TO_DEVICE);
2892 control = pd->control;
2893 pd++;
2894 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2895}
2896
2897static int handle_it_packet(struct context *context,
2898 struct descriptor *d,
2899 struct descriptor *last)
2900{
2901 struct iso_context *ctx =
2902 container_of(context, struct iso_context, context);
2903 struct descriptor *pd;
2904 __be32 *ctx_hdr;
2905
2906 for (pd = d; pd <= last; pd++)
2907 if (pd->transfer_status)
2908 break;
2909 if (pd > last)
2910 /* Descriptor(s) not done yet, stop iteration */
2911 return 0;
2912
2913 sync_it_packet_for_cpu(context, d);
2914
2915 if (ctx->header_length + 4 > PAGE_SIZE) {
2916 if (ctx->base.drop_overflow_headers)
2917 return 1;
2918 flush_iso_completions(ctx);
2919 }
2920
2921 ctx_hdr = ctx->header + ctx->header_length;
2922 ctx->last_timestamp = le16_to_cpu(last->res_count);
2923 /* Present this value as big-endian to match the receive code */
2924 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2925 le16_to_cpu(pd->res_count));
2926 ctx->header_length += 4;
2927
2928 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2929 flush_iso_completions(ctx);
2930
2931 return 1;
2932}
2933
2934static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2935{
2936 u32 hi = channels >> 32, lo = channels;
2937
2938 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2939 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2940 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2941 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2942 mmiowb();
2943 ohci->mc_channels = channels;
2944}
2945
2946static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2947 int type, int channel, size_t header_size)
2948{
2949 struct fw_ohci *ohci = fw_ohci(card);
2950 struct iso_context *uninitialized_var(ctx);
2951 descriptor_callback_t uninitialized_var(callback);
2952 u64 *uninitialized_var(channels);
2953 u32 *uninitialized_var(mask), uninitialized_var(regs);
2954 int index, ret = -EBUSY;
2955
2956 spin_lock_irq(&ohci->lock);
2957
2958 switch (type) {
2959 case FW_ISO_CONTEXT_TRANSMIT:
2960 mask = &ohci->it_context_mask;
2961 callback = handle_it_packet;
2962 index = ffs(*mask) - 1;
2963 if (index >= 0) {
2964 *mask &= ~(1 << index);
2965 regs = OHCI1394_IsoXmitContextBase(index);
2966 ctx = &ohci->it_context_list[index];
2967 }
2968 break;
2969
2970 case FW_ISO_CONTEXT_RECEIVE:
2971 channels = &ohci->ir_context_channels;
2972 mask = &ohci->ir_context_mask;
2973 callback = handle_ir_packet_per_buffer;
2974 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2975 if (index >= 0) {
2976 *channels &= ~(1ULL << channel);
2977 *mask &= ~(1 << index);
2978 regs = OHCI1394_IsoRcvContextBase(index);
2979 ctx = &ohci->ir_context_list[index];
2980 }
2981 break;
2982
2983 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2984 mask = &ohci->ir_context_mask;
2985 callback = handle_ir_buffer_fill;
2986 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2987 if (index >= 0) {
2988 ohci->mc_allocated = true;
2989 *mask &= ~(1 << index);
2990 regs = OHCI1394_IsoRcvContextBase(index);
2991 ctx = &ohci->ir_context_list[index];
2992 }
2993 break;
2994
2995 default:
2996 index = -1;
2997 ret = -ENOSYS;
2998 }
2999
3000 spin_unlock_irq(&ohci->lock);
3001
3002 if (index < 0)
3003 return ERR_PTR(ret);
3004
3005 memset(ctx, 0, sizeof(*ctx));
3006 ctx->header_length = 0;
3007 ctx->header = (void *) __get_free_page(GFP_KERNEL);
3008 if (ctx->header == NULL) {
3009 ret = -ENOMEM;
3010 goto out;
3011 }
3012 ret = context_init(&ctx->context, ohci, regs, callback);
3013 if (ret < 0)
3014 goto out_with_header;
3015
3016 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
3017 set_multichannel_mask(ohci, 0);
3018 ctx->mc_completed = 0;
3019 }
3020
3021 return &ctx->base;
3022
3023 out_with_header:
3024 free_page((unsigned long)ctx->header);
3025 out:
3026 spin_lock_irq(&ohci->lock);
3027
3028 switch (type) {
3029 case FW_ISO_CONTEXT_RECEIVE:
3030 *channels |= 1ULL << channel;
3031 break;
3032
3033 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3034 ohci->mc_allocated = false;
3035 break;
3036 }
3037 *mask |= 1 << index;
3038
3039 spin_unlock_irq(&ohci->lock);
3040
3041 return ERR_PTR(ret);
3042}
3043
3044static int ohci_start_iso(struct fw_iso_context *base,
3045 s32 cycle, u32 sync, u32 tags)
3046{
3047 struct iso_context *ctx = container_of(base, struct iso_context, base);
3048 struct fw_ohci *ohci = ctx->context.ohci;
3049 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
3050 int index;
3051
3052 /* the controller cannot start without any queued packets */
3053 if (ctx->context.last->branch_address == 0)
3054 return -ENODATA;
3055
3056 switch (ctx->base.type) {
3057 case FW_ISO_CONTEXT_TRANSMIT:
3058 index = ctx - ohci->it_context_list;
3059 match = 0;
3060 if (cycle >= 0)
3061 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3062 (cycle & 0x7fff) << 16;
3063
3064 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3065 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3066 context_run(&ctx->context, match);
3067 break;
3068
3069 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3070 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3071 /* fall through */
3072 case FW_ISO_CONTEXT_RECEIVE:
3073 index = ctx - ohci->ir_context_list;
3074 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3075 if (cycle >= 0) {
3076 match |= (cycle & 0x07fff) << 12;
3077 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3078 }
3079
3080 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3081 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3082 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3083 context_run(&ctx->context, control);
3084
3085 ctx->sync = sync;
3086 ctx->tags = tags;
3087
3088 break;
3089 }
3090
3091 return 0;
3092}
3093
3094static int ohci_stop_iso(struct fw_iso_context *base)
3095{
3096 struct fw_ohci *ohci = fw_ohci(base->card);
3097 struct iso_context *ctx = container_of(base, struct iso_context, base);
3098 int index;
3099
3100 switch (ctx->base.type) {
3101 case FW_ISO_CONTEXT_TRANSMIT:
3102 index = ctx - ohci->it_context_list;
3103 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3104 break;
3105
3106 case FW_ISO_CONTEXT_RECEIVE:
3107 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3108 index = ctx - ohci->ir_context_list;
3109 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3110 break;
3111 }
3112 flush_writes(ohci);
3113 context_stop(&ctx->context);
3114 tasklet_kill(&ctx->context.tasklet);
3115
3116 return 0;
3117}
3118
3119static void ohci_free_iso_context(struct fw_iso_context *base)
3120{
3121 struct fw_ohci *ohci = fw_ohci(base->card);
3122 struct iso_context *ctx = container_of(base, struct iso_context, base);
3123 unsigned long flags;
3124 int index;
3125
3126 ohci_stop_iso(base);
3127 context_release(&ctx->context);
3128 free_page((unsigned long)ctx->header);
3129
3130 spin_lock_irqsave(&ohci->lock, flags);
3131
3132 switch (base->type) {
3133 case FW_ISO_CONTEXT_TRANSMIT:
3134 index = ctx - ohci->it_context_list;
3135 ohci->it_context_mask |= 1 << index;
3136 break;
3137
3138 case FW_ISO_CONTEXT_RECEIVE:
3139 index = ctx - ohci->ir_context_list;
3140 ohci->ir_context_mask |= 1 << index;
3141 ohci->ir_context_channels |= 1ULL << base->channel;
3142 break;
3143
3144 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3145 index = ctx - ohci->ir_context_list;
3146 ohci->ir_context_mask |= 1 << index;
3147 ohci->ir_context_channels |= ohci->mc_channels;
3148 ohci->mc_channels = 0;
3149 ohci->mc_allocated = false;
3150 break;
3151 }
3152
3153 spin_unlock_irqrestore(&ohci->lock, flags);
3154}
3155
3156static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3157{
3158 struct fw_ohci *ohci = fw_ohci(base->card);
3159 unsigned long flags;
3160 int ret;
3161
3162 switch (base->type) {
3163 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3164
3165 spin_lock_irqsave(&ohci->lock, flags);
3166
3167 /* Don't allow multichannel to grab other contexts' channels. */
3168 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3169 *channels = ohci->ir_context_channels;
3170 ret = -EBUSY;
3171 } else {
3172 set_multichannel_mask(ohci, *channels);
3173 ret = 0;
3174 }
3175
3176 spin_unlock_irqrestore(&ohci->lock, flags);
3177
3178 break;
3179 default:
3180 ret = -EINVAL;
3181 }
3182
3183 return ret;
3184}
3185
3186#ifdef CONFIG_PM
3187static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3188{
3189 int i;
3190 struct iso_context *ctx;
3191
3192 for (i = 0 ; i < ohci->n_ir ; i++) {
3193 ctx = &ohci->ir_context_list[i];
3194 if (ctx->context.running)
3195 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3196 }
3197
3198 for (i = 0 ; i < ohci->n_it ; i++) {
3199 ctx = &ohci->it_context_list[i];
3200 if (ctx->context.running)
3201 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3202 }
3203}
3204#endif
3205
3206static int queue_iso_transmit(struct iso_context *ctx,
3207 struct fw_iso_packet *packet,
3208 struct fw_iso_buffer *buffer,
3209 unsigned long payload)
3210{
3211 struct descriptor *d, *last, *pd;
3212 struct fw_iso_packet *p;
3213 __le32 *header;
3214 dma_addr_t d_bus, page_bus;
3215 u32 z, header_z, payload_z, irq;
3216 u32 payload_index, payload_end_index, next_page_index;
3217 int page, end_page, i, length, offset;
3218
3219 p = packet;
3220 payload_index = payload;
3221
3222 if (p->skip)
3223 z = 1;
3224 else
3225 z = 2;
3226 if (p->header_length > 0)
3227 z++;
3228
3229 /* Determine the first page the payload isn't contained in. */
3230 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3231 if (p->payload_length > 0)
3232 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3233 else
3234 payload_z = 0;
3235
3236 z += payload_z;
3237
3238 /* Get header size in number of descriptors. */
3239 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3240
3241 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3242 if (d == NULL)
3243 return -ENOMEM;
3244
3245 if (!p->skip) {
3246 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3247 d[0].req_count = cpu_to_le16(8);
3248 /*
3249 * Link the skip address to this descriptor itself. This causes
3250 * a context to skip a cycle whenever lost cycles or FIFO
3251 * overruns occur, without dropping the data. The application
3252 * should then decide whether this is an error condition or not.
3253 * FIXME: Make the context's cycle-lost behaviour configurable?
3254 */
3255 d[0].branch_address = cpu_to_le32(d_bus | z);
3256
3257 header = (__le32 *) &d[1];
3258 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3259 IT_HEADER_TAG(p->tag) |
3260 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3261 IT_HEADER_CHANNEL(ctx->base.channel) |
3262 IT_HEADER_SPEED(ctx->base.speed));
3263 header[1] =
3264 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3265 p->payload_length));
3266 }
3267
3268 if (p->header_length > 0) {
3269 d[2].req_count = cpu_to_le16(p->header_length);
3270 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3271 memcpy(&d[z], p->header, p->header_length);
3272 }
3273
3274 pd = d + z - payload_z;
3275 payload_end_index = payload_index + p->payload_length;
3276 for (i = 0; i < payload_z; i++) {
3277 page = payload_index >> PAGE_SHIFT;
3278 offset = payload_index & ~PAGE_MASK;
3279 next_page_index = (page + 1) << PAGE_SHIFT;
3280 length =
3281 min(next_page_index, payload_end_index) - payload_index;
3282 pd[i].req_count = cpu_to_le16(length);
3283
3284 page_bus = page_private(buffer->pages[page]);
3285 pd[i].data_address = cpu_to_le32(page_bus + offset);
3286
3287 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3288 page_bus, offset, length,
3289 DMA_TO_DEVICE);
3290
3291 payload_index += length;
3292 }
3293
3294 if (p->interrupt)
3295 irq = DESCRIPTOR_IRQ_ALWAYS;
3296 else
3297 irq = DESCRIPTOR_NO_IRQ;
3298
3299 last = z == 2 ? d : d + z - 1;
3300 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3301 DESCRIPTOR_STATUS |
3302 DESCRIPTOR_BRANCH_ALWAYS |
3303 irq);
3304
3305 context_append(&ctx->context, d, z, header_z);
3306
3307 return 0;
3308}
3309
3310static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3311 struct fw_iso_packet *packet,
3312 struct fw_iso_buffer *buffer,
3313 unsigned long payload)
3314{
3315 struct device *device = ctx->context.ohci->card.device;
3316 struct descriptor *d, *pd;
3317 dma_addr_t d_bus, page_bus;
3318 u32 z, header_z, rest;
3319 int i, j, length;
3320 int page, offset, packet_count, header_size, payload_per_buffer;
3321
3322 /*
3323 * The OHCI controller puts the isochronous header and trailer in the
3324 * buffer, so we need at least 8 bytes.
3325 */
3326 packet_count = packet->header_length / ctx->base.header_size;
3327 header_size = max(ctx->base.header_size, (size_t)8);
3328
3329 /* Get header size in number of descriptors. */
3330 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3331 page = payload >> PAGE_SHIFT;
3332 offset = payload & ~PAGE_MASK;
3333 payload_per_buffer = packet->payload_length / packet_count;
3334
3335 for (i = 0; i < packet_count; i++) {
3336 /* d points to the header descriptor */
3337 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3338 d = context_get_descriptors(&ctx->context,
3339 z + header_z, &d_bus);
3340 if (d == NULL)
3341 return -ENOMEM;
3342
3343 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3344 DESCRIPTOR_INPUT_MORE);
3345 if (packet->skip && i == 0)
3346 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3347 d->req_count = cpu_to_le16(header_size);
3348 d->res_count = d->req_count;
3349 d->transfer_status = 0;
3350 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3351
3352 rest = payload_per_buffer;
3353 pd = d;
3354 for (j = 1; j < z; j++) {
3355 pd++;
3356 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3357 DESCRIPTOR_INPUT_MORE);
3358
3359 if (offset + rest < PAGE_SIZE)
3360 length = rest;
3361 else
3362 length = PAGE_SIZE - offset;
3363 pd->req_count = cpu_to_le16(length);
3364 pd->res_count = pd->req_count;
3365 pd->transfer_status = 0;
3366
3367 page_bus = page_private(buffer->pages[page]);
3368 pd->data_address = cpu_to_le32(page_bus + offset);
3369
3370 dma_sync_single_range_for_device(device, page_bus,
3371 offset, length,
3372 DMA_FROM_DEVICE);
3373
3374 offset = (offset + length) & ~PAGE_MASK;
3375 rest -= length;
3376 if (offset == 0)
3377 page++;
3378 }
3379 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3380 DESCRIPTOR_INPUT_LAST |
3381 DESCRIPTOR_BRANCH_ALWAYS);
3382 if (packet->interrupt && i == packet_count - 1)
3383 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3384
3385 context_append(&ctx->context, d, z, header_z);
3386 }
3387
3388 return 0;
3389}
3390
3391static int queue_iso_buffer_fill(struct iso_context *ctx,
3392 struct fw_iso_packet *packet,
3393 struct fw_iso_buffer *buffer,
3394 unsigned long payload)
3395{
3396 struct descriptor *d;
3397 dma_addr_t d_bus, page_bus;
3398 int page, offset, rest, z, i, length;
3399
3400 page = payload >> PAGE_SHIFT;
3401 offset = payload & ~PAGE_MASK;
3402 rest = packet->payload_length;
3403
3404 /* We need one descriptor for each page in the buffer. */
3405 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3406
3407 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3408 return -EFAULT;
3409
3410 for (i = 0; i < z; i++) {
3411 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3412 if (d == NULL)
3413 return -ENOMEM;
3414
3415 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3416 DESCRIPTOR_BRANCH_ALWAYS);
3417 if (packet->skip && i == 0)
3418 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3419 if (packet->interrupt && i == z - 1)
3420 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3421
3422 if (offset + rest < PAGE_SIZE)
3423 length = rest;
3424 else
3425 length = PAGE_SIZE - offset;
3426 d->req_count = cpu_to_le16(length);
3427 d->res_count = d->req_count;
3428 d->transfer_status = 0;
3429
3430 page_bus = page_private(buffer->pages[page]);
3431 d->data_address = cpu_to_le32(page_bus + offset);
3432
3433 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3434 page_bus, offset, length,
3435 DMA_FROM_DEVICE);
3436
3437 rest -= length;
3438 offset = 0;
3439 page++;
3440
3441 context_append(&ctx->context, d, 1, 0);
3442 }
3443
3444 return 0;
3445}
3446
3447static int ohci_queue_iso(struct fw_iso_context *base,
3448 struct fw_iso_packet *packet,
3449 struct fw_iso_buffer *buffer,
3450 unsigned long payload)
3451{
3452 struct iso_context *ctx = container_of(base, struct iso_context, base);
3453 unsigned long flags;
3454 int ret = -ENOSYS;
3455
3456 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3457 switch (base->type) {
3458 case FW_ISO_CONTEXT_TRANSMIT:
3459 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3460 break;
3461 case FW_ISO_CONTEXT_RECEIVE:
3462 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3463 break;
3464 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3465 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3466 break;
3467 }
3468 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3469
3470 return ret;
3471}
3472
3473static void ohci_flush_queue_iso(struct fw_iso_context *base)
3474{
3475 struct context *ctx =
3476 &container_of(base, struct iso_context, base)->context;
3477
3478 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3479}
3480
3481static int ohci_flush_iso_completions(struct fw_iso_context *base)
3482{
3483 struct iso_context *ctx = container_of(base, struct iso_context, base);
3484 int ret = 0;
3485
3486 tasklet_disable(&ctx->context.tasklet);
3487
3488 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3489 context_tasklet((unsigned long)&ctx->context);
3490
3491 switch (base->type) {
3492 case FW_ISO_CONTEXT_TRANSMIT:
3493 case FW_ISO_CONTEXT_RECEIVE:
3494 if (ctx->header_length != 0)
3495 flush_iso_completions(ctx);
3496 break;
3497 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3498 if (ctx->mc_completed != 0)
3499 flush_ir_buffer_fill(ctx);
3500 break;
3501 default:
3502 ret = -ENOSYS;
3503 }
3504
3505 clear_bit_unlock(0, &ctx->flushing_completions);
3506 smp_mb__after_atomic();
3507 }
3508
3509 tasklet_enable(&ctx->context.tasklet);
3510
3511 return ret;
3512}
3513
3514static const struct fw_card_driver ohci_driver = {
3515 .enable = ohci_enable,
3516 .read_phy_reg = ohci_read_phy_reg,
3517 .update_phy_reg = ohci_update_phy_reg,
3518 .set_config_rom = ohci_set_config_rom,
3519 .send_request = ohci_send_request,
3520 .send_response = ohci_send_response,
3521 .cancel_packet = ohci_cancel_packet,
3522 .enable_phys_dma = ohci_enable_phys_dma,
3523 .read_csr = ohci_read_csr,
3524 .write_csr = ohci_write_csr,
3525
3526 .allocate_iso_context = ohci_allocate_iso_context,
3527 .free_iso_context = ohci_free_iso_context,
3528 .set_iso_channels = ohci_set_iso_channels,
3529 .queue_iso = ohci_queue_iso,
3530 .flush_queue_iso = ohci_flush_queue_iso,
3531 .flush_iso_completions = ohci_flush_iso_completions,
3532 .start_iso = ohci_start_iso,
3533 .stop_iso = ohci_stop_iso,
3534};
3535
3536#ifdef CONFIG_PPC_PMAC
3537static void pmac_ohci_on(struct pci_dev *dev)
3538{
3539 if (machine_is(powermac)) {
3540 struct device_node *ofn = pci_device_to_OF_node(dev);
3541
3542 if (ofn) {
3543 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3544 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3545 }
3546 }
3547}
3548
3549static void pmac_ohci_off(struct pci_dev *dev)
3550{
3551 if (machine_is(powermac)) {
3552 struct device_node *ofn = pci_device_to_OF_node(dev);
3553
3554 if (ofn) {
3555 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3556 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3557 }
3558 }
3559}
3560#else
3561static inline void pmac_ohci_on(struct pci_dev *dev) {}
3562static inline void pmac_ohci_off(struct pci_dev *dev) {}
3563#endif /* CONFIG_PPC_PMAC */
3564
3565static int pci_probe(struct pci_dev *dev,
3566 const struct pci_device_id *ent)
3567{
3568 struct fw_ohci *ohci;
3569 u32 bus_options, max_receive, link_speed, version;
3570 u64 guid;
3571 int i, err;
3572 size_t size;
3573
3574 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3575 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3576 return -ENOSYS;
3577 }
3578
3579 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3580 if (ohci == NULL) {
3581 err = -ENOMEM;
3582 goto fail;
3583 }
3584
3585 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3586
3587 pmac_ohci_on(dev);
3588
3589 err = pci_enable_device(dev);
3590 if (err) {
3591 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3592 goto fail_free;
3593 }
3594
3595 pci_set_master(dev);
3596 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3597 pci_set_drvdata(dev, ohci);
3598
3599 spin_lock_init(&ohci->lock);
3600 mutex_init(&ohci->phy_reg_mutex);
3601
3602 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3603
3604 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3605 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3606 ohci_err(ohci, "invalid MMIO resource\n");
3607 err = -ENXIO;
3608 goto fail_disable;
3609 }
3610
3611 err = pci_request_region(dev, 0, ohci_driver_name);
3612 if (err) {
3613 ohci_err(ohci, "MMIO resource unavailable\n");
3614 goto fail_disable;
3615 }
3616
3617 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3618 if (ohci->registers == NULL) {
3619 ohci_err(ohci, "failed to remap registers\n");
3620 err = -ENXIO;
3621 goto fail_iomem;
3622 }
3623
3624 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3625 if ((ohci_quirks[i].vendor == dev->vendor) &&
3626 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3627 ohci_quirks[i].device == dev->device) &&
3628 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3629 ohci_quirks[i].revision >= dev->revision)) {
3630 ohci->quirks = ohci_quirks[i].flags;
3631 break;
3632 }
3633 if (param_quirks)
3634 ohci->quirks = param_quirks;
3635
3636 /*
3637 * Because dma_alloc_coherent() allocates at least one page,
3638 * we save space by using a common buffer for the AR request/
3639 * response descriptors and the self IDs buffer.
3640 */
3641 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3642 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3643 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3644 PAGE_SIZE,
3645 &ohci->misc_buffer_bus,
3646 GFP_KERNEL);
3647 if (!ohci->misc_buffer) {
3648 err = -ENOMEM;
3649 goto fail_iounmap;
3650 }
3651
3652 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3653 OHCI1394_AsReqRcvContextControlSet);
3654 if (err < 0)
3655 goto fail_misc_buf;
3656
3657 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3658 OHCI1394_AsRspRcvContextControlSet);
3659 if (err < 0)
3660 goto fail_arreq_ctx;
3661
3662 err = context_init(&ohci->at_request_ctx, ohci,
3663 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3664 if (err < 0)
3665 goto fail_arrsp_ctx;
3666
3667 err = context_init(&ohci->at_response_ctx, ohci,
3668 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3669 if (err < 0)
3670 goto fail_atreq_ctx;
3671
3672 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3673 ohci->ir_context_channels = ~0ULL;
3674 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3675 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3676 ohci->ir_context_mask = ohci->ir_context_support;
3677 ohci->n_ir = hweight32(ohci->ir_context_mask);
3678 size = sizeof(struct iso_context) * ohci->n_ir;
3679 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3680
3681 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3682 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3683 /* JMicron JMB38x often shows 0 at first read, just ignore it */
3684 if (!ohci->it_context_support) {
3685 ohci_notice(ohci, "overriding IsoXmitIntMask\n");
3686 ohci->it_context_support = 0xf;
3687 }
3688 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3689 ohci->it_context_mask = ohci->it_context_support;
3690 ohci->n_it = hweight32(ohci->it_context_mask);
3691 size = sizeof(struct iso_context) * ohci->n_it;
3692 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3693
3694 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3695 err = -ENOMEM;
3696 goto fail_contexts;
3697 }
3698
3699 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2;
3700 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3701
3702 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3703 max_receive = (bus_options >> 12) & 0xf;
3704 link_speed = bus_options & 0x7;
3705 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3706 reg_read(ohci, OHCI1394_GUIDLo);
3707
3708 if (!(ohci->quirks & QUIRK_NO_MSI))
3709 pci_enable_msi(dev);
3710 if (request_irq(dev->irq, irq_handler,
3711 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
3712 ohci_driver_name, ohci)) {
3713 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
3714 err = -EIO;
3715 goto fail_msi;
3716 }
3717
3718 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3719 if (err)
3720 goto fail_irq;
3721
3722 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3723 ohci_notice(ohci,
3724 "added OHCI v%x.%x device as card %d, "
3725 "%d IR + %d IT contexts, quirks 0x%x%s\n",
3726 version >> 16, version & 0xff, ohci->card.index,
3727 ohci->n_ir, ohci->n_it, ohci->quirks,
3728 reg_read(ohci, OHCI1394_PhyUpperBound) ?
3729 ", physUB" : "");
3730
3731 return 0;
3732
3733 fail_irq:
3734 free_irq(dev->irq, ohci);
3735 fail_msi:
3736 pci_disable_msi(dev);
3737 fail_contexts:
3738 kfree(ohci->ir_context_list);
3739 kfree(ohci->it_context_list);
3740 context_release(&ohci->at_response_ctx);
3741 fail_atreq_ctx:
3742 context_release(&ohci->at_request_ctx);
3743 fail_arrsp_ctx:
3744 ar_context_release(&ohci->ar_response_ctx);
3745 fail_arreq_ctx:
3746 ar_context_release(&ohci->ar_request_ctx);
3747 fail_misc_buf:
3748 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3749 ohci->misc_buffer, ohci->misc_buffer_bus);
3750 fail_iounmap:
3751 pci_iounmap(dev, ohci->registers);
3752 fail_iomem:
3753 pci_release_region(dev, 0);
3754 fail_disable:
3755 pci_disable_device(dev);
3756 fail_free:
3757 kfree(ohci);
3758 pmac_ohci_off(dev);
3759 fail:
3760 return err;
3761}
3762
3763static void pci_remove(struct pci_dev *dev)
3764{
3765 struct fw_ohci *ohci = pci_get_drvdata(dev);
3766
3767 /*
3768 * If the removal is happening from the suspend state, LPS won't be
3769 * enabled and host registers (eg., IntMaskClear) won't be accessible.
3770 */
3771 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3772 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3773 flush_writes(ohci);
3774 }
3775 cancel_work_sync(&ohci->bus_reset_work);
3776 fw_core_remove_card(&ohci->card);
3777
3778 /*
3779 * FIXME: Fail all pending packets here, now that the upper
3780 * layers can't queue any more.
3781 */
3782
3783 software_reset(ohci);
3784 free_irq(dev->irq, ohci);
3785
3786 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3787 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3788 ohci->next_config_rom, ohci->next_config_rom_bus);
3789 if (ohci->config_rom)
3790 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3791 ohci->config_rom, ohci->config_rom_bus);
3792 ar_context_release(&ohci->ar_request_ctx);
3793 ar_context_release(&ohci->ar_response_ctx);
3794 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3795 ohci->misc_buffer, ohci->misc_buffer_bus);
3796 context_release(&ohci->at_request_ctx);
3797 context_release(&ohci->at_response_ctx);
3798 kfree(ohci->it_context_list);
3799 kfree(ohci->ir_context_list);
3800 pci_disable_msi(dev);
3801 pci_iounmap(dev, ohci->registers);
3802 pci_release_region(dev, 0);
3803 pci_disable_device(dev);
3804 kfree(ohci);
3805 pmac_ohci_off(dev);
3806
3807 dev_notice(&dev->dev, "removed fw-ohci device\n");
3808}
3809
3810#ifdef CONFIG_PM
3811static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3812{
3813 struct fw_ohci *ohci = pci_get_drvdata(dev);
3814 int err;
3815
3816 software_reset(ohci);
3817 err = pci_save_state(dev);
3818 if (err) {
3819 ohci_err(ohci, "pci_save_state failed\n");
3820 return err;
3821 }
3822 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3823 if (err)
3824 ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
3825 pmac_ohci_off(dev);
3826
3827 return 0;
3828}
3829
3830static int pci_resume(struct pci_dev *dev)
3831{
3832 struct fw_ohci *ohci = pci_get_drvdata(dev);
3833 int err;
3834
3835 pmac_ohci_on(dev);
3836 pci_set_power_state(dev, PCI_D0);
3837 pci_restore_state(dev);
3838 err = pci_enable_device(dev);
3839 if (err) {
3840 ohci_err(ohci, "pci_enable_device failed\n");
3841 return err;
3842 }
3843
3844 /* Some systems don't setup GUID register on resume from ram */
3845 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3846 !reg_read(ohci, OHCI1394_GUIDHi)) {
3847 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3848 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3849 }
3850
3851 err = ohci_enable(&ohci->card, NULL, 0);
3852 if (err)
3853 return err;
3854
3855 ohci_resume_iso_dma(ohci);
3856
3857 return 0;
3858}
3859#endif
3860
3861static const struct pci_device_id pci_table[] = {
3862 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3863 { }
3864};
3865
3866MODULE_DEVICE_TABLE(pci, pci_table);
3867
3868static struct pci_driver fw_ohci_pci_driver = {
3869 .name = ohci_driver_name,
3870 .id_table = pci_table,
3871 .probe = pci_probe,
3872 .remove = pci_remove,
3873#ifdef CONFIG_PM
3874 .resume = pci_resume,
3875 .suspend = pci_suspend,
3876#endif
3877};
3878
3879static int __init fw_ohci_init(void)
3880{
3881 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
3882 if (!selfid_workqueue)
3883 return -ENOMEM;
3884
3885 return pci_register_driver(&fw_ohci_pci_driver);
3886}
3887
3888static void __exit fw_ohci_cleanup(void)
3889{
3890 pci_unregister_driver(&fw_ohci_pci_driver);
3891 destroy_workqueue(selfid_workqueue);
3892}
3893
3894module_init(fw_ohci_init);
3895module_exit(fw_ohci_cleanup);
3896
3897MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3898MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3899MODULE_LICENSE("GPL");
3900
3901/* Provide a module alias so root-on-sbp2 initrds don't break. */
3902MODULE_ALIAS("ohci1394");