1/*
 2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License version 2 and
 6 * only version 2 as published by the Free Software Foundation.
 7 *
 8 * This program is distributed in the hope that it will be useful,
 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __DSI_PHY_H__
15#define __DSI_PHY_H__
16
17#include <linux/regulator/consumer.h>
18
19#include "dsi.h"
20
21#define dsi_phy_read(offset) msm_readl((offset))
22#define dsi_phy_write(offset, data) msm_writel((data), (offset))
23
24struct msm_dsi_phy_ops {
25	int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
26		const unsigned long bit_rate, const unsigned long esc_rate);
27	void (*disable)(struct msm_dsi_phy *phy);
28};
29
30struct msm_dsi_phy_cfg {
31	enum msm_dsi_phy_type type;
32	struct dsi_reg_config reg_cfg;
33	struct msm_dsi_phy_ops ops;
34
35	/*
36	 * Each cell {phy_id, pll_id} of the truth table indicates
37	 * if the source PLL selection bit should be set for each PHY.
38	 * Fill default H/W values in illegal cells, eg. cell {0, 1}.
39	 */
40	bool src_pll_truthtable[DSI_MAX][DSI_MAX];
41	const resource_size_t io_start[DSI_MAX];
42	const int num_dsi_phy;
43};
44
45extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
46extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
47extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
48extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
49
50struct msm_dsi_dphy_timing {
51	u32 clk_pre;
52	u32 clk_post;
53	u32 clk_zero;
54	u32 clk_trail;
55	u32 clk_prepare;
56	u32 hs_exit;
57	u32 hs_zero;
58	u32 hs_prepare;
59	u32 hs_trail;
60	u32 hs_rqst;
61	u32 ta_go;
62	u32 ta_sure;
63	u32 ta_get;
64};
65
66struct msm_dsi_phy {
67	struct platform_device *pdev;
68	void __iomem *base;
69	void __iomem *reg_base;
70	int id;
71
72	struct clk *ahb_clk;
73	struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
74
75	struct msm_dsi_dphy_timing timing;
76	const struct msm_dsi_phy_cfg *cfg;
77
78	bool regulator_ldo_mode;
79
80	struct msm_dsi_pll *pll;
81};
82
83/*
84 * PHY internal functions
85 */
86int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
87	const unsigned long bit_rate, const unsigned long esc_rate);
88void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
89				u32 bit_mask);
90
91#endif /* __DSI_PHY_H__ */
92