1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  4 */
  5
  6#ifndef __DSI_PHY_H__
  7#define __DSI_PHY_H__
  8
  9#include <linux/clk-provider.h>
 10#include <linux/delay.h>
 11#include <linux/regulator/consumer.h>
 12
 13#include "dsi.h"
 14
 15#define dsi_phy_read(offset) msm_readl((offset))
 16#define dsi_phy_write(offset, data) msm_writel((data), (offset))
 17#define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
 18#define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
 19
 20struct msm_dsi_phy_ops {
 21	int (*pll_init)(struct msm_dsi_phy *phy);
 22	int (*enable)(struct msm_dsi_phy *phy,
 23			struct msm_dsi_phy_clk_request *clk_req);
 24	void (*disable)(struct msm_dsi_phy *phy);
 25	void (*save_pll_state)(struct msm_dsi_phy *phy);
 26	int (*restore_pll_state)(struct msm_dsi_phy *phy);
 27};
 28
 29struct msm_dsi_phy_cfg {
 30	struct dsi_reg_config reg_cfg;
 31	struct msm_dsi_phy_ops ops;
 32
 33	unsigned long	min_pll_rate;
 34	unsigned long	max_pll_rate;
 35
 36	const resource_size_t io_start[DSI_MAX];
 37	const int num_dsi_phy;
 38	const int quirks;
 39	bool has_phy_regulator;
 40	bool has_phy_lane;
 41};
 42
 43extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
 44extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs;
 45extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
 46extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
 47extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
 48extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
 49extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
 50extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
 51extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
 52extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
 53extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
 54
 55struct msm_dsi_dphy_timing {
 56	u32 clk_zero;
 57	u32 clk_trail;
 58	u32 clk_prepare;
 59	u32 hs_exit;
 60	u32 hs_zero;
 61	u32 hs_prepare;
 62	u32 hs_trail;
 63	u32 hs_rqst;
 64	u32 ta_go;
 65	u32 ta_sure;
 66	u32 ta_get;
 67
 68	struct msm_dsi_phy_shared_timings shared_timings;
 69
 70	/* For PHY v2 only */
 71	u32 hs_rqst_ckln;
 72	u32 hs_prep_dly;
 73	u32 hs_prep_dly_ckln;
 74	u8 hs_halfbyte_en;
 75	u8 hs_halfbyte_en_ckln;
 76};
 77
 78#define DSI_BYTE_PLL_CLK		0
 79#define DSI_PIXEL_PLL_CLK		1
 80#define NUM_PROVIDED_CLKS		2
 81
 82struct msm_dsi_phy {
 83	struct platform_device *pdev;
 84	void __iomem *base;
 85	void __iomem *pll_base;
 86	void __iomem *reg_base;
 87	void __iomem *lane_base;
 88	phys_addr_t base_size;
 89	phys_addr_t pll_size;
 90	phys_addr_t reg_size;
 91	phys_addr_t lane_size;
 92	int id;
 93
 94	struct clk *ahb_clk;
 95	struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
 96
 97	struct msm_dsi_dphy_timing timing;
 98	const struct msm_dsi_phy_cfg *cfg;
 99
100	enum msm_dsi_phy_usecase usecase;
101	bool regulator_ldo_mode;
102
103	struct clk_hw *vco_hw;
104	bool pll_on;
105
106	struct clk_hw_onecell_data *provided_clocks;
107
108	bool state_saved;
109};
110
111/*
112 * PHY internal functions
113 */
114int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
115			     struct msm_dsi_phy_clk_request *clk_req);
116int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
117				struct msm_dsi_phy_clk_request *clk_req);
118int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
119				struct msm_dsi_phy_clk_request *clk_req);
120int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
121				struct msm_dsi_phy_clk_request *clk_req);
122
123#endif /* __DSI_PHY_H__ */