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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "linux/string.h"
29#include "linux/bitops.h"
30#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
34
35/** @file i915_gem_tiling.c
36 *
37 * Support for managing tiling state of buffer objects.
38 *
39 * The idea behind tiling is to increase cache hit rates by rearranging
40 * pixel data so that a group of pixel accesses are in the same cacheline.
41 * Performance improvement from doing this on the back/depth buffer are on
42 * the order of 30%.
43 *
44 * Intel architectures make this somewhat more complicated, though, by
45 * adjustments made to addressing of data when the memory is in interleaved
46 * mode (matched pairs of DIMMS) to improve memory bandwidth.
47 * For interleaved memory, the CPU sends every sequential 64 bytes
48 * to an alternate memory channel so it can get the bandwidth from both.
49 *
50 * The GPU also rearranges its accesses for increased bandwidth to interleaved
51 * memory, and it matches what the CPU does for non-tiled. However, when tiled
52 * it does it a little differently, since one walks addresses not just in the
53 * X direction but also Y. So, along with alternating channels when bit
54 * 6 of the address flips, it also alternates when other bits flip -- Bits 9
55 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
56 * are common to both the 915 and 965-class hardware.
57 *
58 * The CPU also sometimes XORs in higher bits as well, to improve
59 * bandwidth doing strided access like we do so frequently in graphics. This
60 * is called "Channel XOR Randomization" in the MCH documentation. The result
61 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
62 * decode.
63 *
64 * All of this bit 6 XORing has an effect on our memory management,
65 * as we need to make sure that the 3d driver can correctly address object
66 * contents.
67 *
68 * If we don't have interleaved memory, all tiling is safe and no swizzling is
69 * required.
70 *
71 * When bit 17 is XORed in, we simply refuse to tile at all. Bit
72 * 17 is not just a page offset, so as we page an objet out and back in,
73 * individual pages in it will have different bit 17 addresses, resulting in
74 * each 64 bytes being swapped with its neighbor!
75 *
76 * Otherwise, if interleaved, we have to tell the 3d driver what the address
77 * swizzling it needs to do is, since it's writing with the CPU to the pages
78 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
79 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
80 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
81 * to match what the GPU expects.
82 */
83
84/**
85 * Detects bit 6 swizzling of address lookup between IGD access and CPU
86 * access through main memory.
87 */
88void
89i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
90{
91 drm_i915_private_t *dev_priv = dev->dev_private;
92 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
93 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
94
95 if (INTEL_INFO(dev)->gen >= 5) {
96 /* On Ironlake whatever DRAM config, GPU always do
97 * same swizzling setup.
98 */
99 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
100 swizzle_y = I915_BIT_6_SWIZZLE_9;
101 } else if (IS_GEN2(dev)) {
102 /* As far as we know, the 865 doesn't have these bit 6
103 * swizzling issues.
104 */
105 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
106 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
107 } else if (IS_MOBILE(dev)) {
108 uint32_t dcc;
109
110 /* On mobile 9xx chipsets, channel interleave by the CPU is
111 * determined by DCC. For single-channel, neither the CPU
112 * nor the GPU do swizzling. For dual channel interleaved,
113 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
114 * 9 for Y tiled. The CPU's interleave is independent, and
115 * can be based on either bit 11 (haven't seen this yet) or
116 * bit 17 (common).
117 */
118 dcc = I915_READ(DCC);
119 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
120 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
121 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
122 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
123 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
124 break;
125 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
126 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
127 /* This is the base swizzling by the GPU for
128 * tiled buffers.
129 */
130 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
131 swizzle_y = I915_BIT_6_SWIZZLE_9;
132 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
133 /* Bit 11 swizzling by the CPU in addition. */
134 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
135 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
136 } else {
137 /* Bit 17 swizzling by the CPU in addition. */
138 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
139 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
140 }
141 break;
142 }
143 if (dcc == 0xffffffff) {
144 DRM_ERROR("Couldn't read from MCHBAR. "
145 "Disabling tiling.\n");
146 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
147 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
148 }
149 } else {
150 /* The 965, G33, and newer, have a very flexible memory
151 * configuration. It will enable dual-channel mode
152 * (interleaving) on as much memory as it can, and the GPU
153 * will additionally sometimes enable different bit 6
154 * swizzling for tiled objects from the CPU.
155 *
156 * Here's what I found on the G965:
157 * slot fill memory size swizzling
158 * 0A 0B 1A 1B 1-ch 2-ch
159 * 512 0 0 0 512 0 O
160 * 512 0 512 0 16 1008 X
161 * 512 0 0 512 16 1008 X
162 * 0 512 0 512 16 1008 X
163 * 1024 1024 1024 0 2048 1024 O
164 *
165 * We could probably detect this based on either the DRB
166 * matching, which was the case for the swizzling required in
167 * the table above, or from the 1-ch value being less than
168 * the minimum size of a rank.
169 */
170 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
171 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
172 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
173 } else {
174 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
175 swizzle_y = I915_BIT_6_SWIZZLE_9;
176 }
177 }
178
179 dev_priv->mm.bit_6_swizzle_x = swizzle_x;
180 dev_priv->mm.bit_6_swizzle_y = swizzle_y;
181}
182
183/* Check pitch constriants for all chips & tiling formats */
184static bool
185i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
186{
187 int tile_width;
188
189 /* Linear is always fine */
190 if (tiling_mode == I915_TILING_NONE)
191 return true;
192
193 if (IS_GEN2(dev) ||
194 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
195 tile_width = 128;
196 else
197 tile_width = 512;
198
199 /* check maximum stride & object size */
200 if (INTEL_INFO(dev)->gen >= 4) {
201 /* i965 stores the end address of the gtt mapping in the fence
202 * reg, so dont bother to check the size */
203 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
204 return false;
205 } else {
206 if (stride > 8192)
207 return false;
208
209 if (IS_GEN3(dev)) {
210 if (size > I830_FENCE_MAX_SIZE_VAL << 20)
211 return false;
212 } else {
213 if (size > I830_FENCE_MAX_SIZE_VAL << 19)
214 return false;
215 }
216 }
217
218 /* 965+ just needs multiples of tile width */
219 if (INTEL_INFO(dev)->gen >= 4) {
220 if (stride & (tile_width - 1))
221 return false;
222 return true;
223 }
224
225 /* Pre-965 needs power of two tile widths */
226 if (stride < tile_width)
227 return false;
228
229 if (stride & (stride - 1))
230 return false;
231
232 return true;
233}
234
235/* Is the current GTT allocation valid for the change in tiling? */
236static bool
237i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
238{
239 u32 size;
240
241 if (tiling_mode == I915_TILING_NONE)
242 return true;
243
244 if (INTEL_INFO(obj->base.dev)->gen >= 4)
245 return true;
246
247 if (INTEL_INFO(obj->base.dev)->gen == 3) {
248 if (obj->gtt_offset & ~I915_FENCE_START_MASK)
249 return false;
250 } else {
251 if (obj->gtt_offset & ~I830_FENCE_START_MASK)
252 return false;
253 }
254
255 /*
256 * Previous chips need to be aligned to the size of the smallest
257 * fence register that can contain the object.
258 */
259 if (INTEL_INFO(obj->base.dev)->gen == 3)
260 size = 1024*1024;
261 else
262 size = 512*1024;
263
264 while (size < obj->base.size)
265 size <<= 1;
266
267 if (obj->gtt_space->size != size)
268 return false;
269
270 if (obj->gtt_offset & (size - 1))
271 return false;
272
273 return true;
274}
275
276/**
277 * Sets the tiling mode of an object, returning the required swizzling of
278 * bit 6 of addresses in the object.
279 */
280int
281i915_gem_set_tiling(struct drm_device *dev, void *data,
282 struct drm_file *file)
283{
284 struct drm_i915_gem_set_tiling *args = data;
285 drm_i915_private_t *dev_priv = dev->dev_private;
286 struct drm_i915_gem_object *obj;
287 int ret = 0;
288
289 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
290 if (&obj->base == NULL)
291 return -ENOENT;
292
293 if (!i915_tiling_ok(dev,
294 args->stride, obj->base.size, args->tiling_mode)) {
295 drm_gem_object_unreference_unlocked(&obj->base);
296 return -EINVAL;
297 }
298
299 if (obj->pin_count) {
300 drm_gem_object_unreference_unlocked(&obj->base);
301 return -EBUSY;
302 }
303
304 if (args->tiling_mode == I915_TILING_NONE) {
305 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
306 args->stride = 0;
307 } else {
308 if (args->tiling_mode == I915_TILING_X)
309 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
310 else
311 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
312
313 /* Hide bit 17 swizzling from the user. This prevents old Mesa
314 * from aborting the application on sw fallbacks to bit 17,
315 * and we use the pread/pwrite bit17 paths to swizzle for it.
316 * If there was a user that was relying on the swizzle
317 * information for drm_intel_bo_map()ed reads/writes this would
318 * break it, but we don't have any of those.
319 */
320 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
321 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
322 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
323 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
324
325 /* If we can't handle the swizzling, make it untiled. */
326 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
327 args->tiling_mode = I915_TILING_NONE;
328 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
329 args->stride = 0;
330 }
331 }
332
333 mutex_lock(&dev->struct_mutex);
334 if (args->tiling_mode != obj->tiling_mode ||
335 args->stride != obj->stride) {
336 /* We need to rebind the object if its current allocation
337 * no longer meets the alignment restrictions for its new
338 * tiling mode. Otherwise we can just leave it alone, but
339 * need to ensure that any fence register is cleared.
340 */
341 i915_gem_release_mmap(obj);
342
343 obj->map_and_fenceable =
344 obj->gtt_space == NULL ||
345 (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end &&
346 i915_gem_object_fence_ok(obj, args->tiling_mode));
347
348 /* Rebind if we need a change of alignment */
349 if (!obj->map_and_fenceable) {
350 u32 unfenced_alignment =
351 i915_gem_get_unfenced_gtt_alignment(dev,
352 obj->base.size,
353 args->tiling_mode);
354 if (obj->gtt_offset & (unfenced_alignment - 1))
355 ret = i915_gem_object_unbind(obj);
356 }
357
358 if (ret == 0) {
359 obj->tiling_changed = true;
360 obj->tiling_mode = args->tiling_mode;
361 obj->stride = args->stride;
362 }
363 }
364 /* we have to maintain this existing ABI... */
365 args->stride = obj->stride;
366 args->tiling_mode = obj->tiling_mode;
367 drm_gem_object_unreference(&obj->base);
368 mutex_unlock(&dev->struct_mutex);
369
370 return ret;
371}
372
373/**
374 * Returns the current tiling mode and required bit 6 swizzling for the object.
375 */
376int
377i915_gem_get_tiling(struct drm_device *dev, void *data,
378 struct drm_file *file)
379{
380 struct drm_i915_gem_get_tiling *args = data;
381 drm_i915_private_t *dev_priv = dev->dev_private;
382 struct drm_i915_gem_object *obj;
383
384 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
385 if (&obj->base == NULL)
386 return -ENOENT;
387
388 mutex_lock(&dev->struct_mutex);
389
390 args->tiling_mode = obj->tiling_mode;
391 switch (obj->tiling_mode) {
392 case I915_TILING_X:
393 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
394 break;
395 case I915_TILING_Y:
396 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
397 break;
398 case I915_TILING_NONE:
399 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
400 break;
401 default:
402 DRM_ERROR("unknown tiling mode\n");
403 }
404
405 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
406 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
407 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
408 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
409 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
410
411 drm_gem_object_unreference(&obj->base);
412 mutex_unlock(&dev->struct_mutex);
413
414 return 0;
415}
416
417/**
418 * Swap every 64 bytes of this page around, to account for it having a new
419 * bit 17 of its physical address and therefore being interpreted differently
420 * by the GPU.
421 */
422static void
423i915_gem_swizzle_page(struct page *page)
424{
425 char temp[64];
426 char *vaddr;
427 int i;
428
429 vaddr = kmap(page);
430
431 for (i = 0; i < PAGE_SIZE; i += 128) {
432 memcpy(temp, &vaddr[i], 64);
433 memcpy(&vaddr[i], &vaddr[i + 64], 64);
434 memcpy(&vaddr[i + 64], temp, 64);
435 }
436
437 kunmap(page);
438}
439
440void
441i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
442{
443 struct drm_device *dev = obj->base.dev;
444 drm_i915_private_t *dev_priv = dev->dev_private;
445 int page_count = obj->base.size >> PAGE_SHIFT;
446 int i;
447
448 if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
449 return;
450
451 if (obj->bit_17 == NULL)
452 return;
453
454 for (i = 0; i < page_count; i++) {
455 char new_bit_17 = page_to_phys(obj->pages[i]) >> 17;
456 if ((new_bit_17 & 0x1) !=
457 (test_bit(i, obj->bit_17) != 0)) {
458 i915_gem_swizzle_page(obj->pages[i]);
459 set_page_dirty(obj->pages[i]);
460 }
461 }
462}
463
464void
465i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
466{
467 struct drm_device *dev = obj->base.dev;
468 drm_i915_private_t *dev_priv = dev->dev_private;
469 int page_count = obj->base.size >> PAGE_SHIFT;
470 int i;
471
472 if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
473 return;
474
475 if (obj->bit_17 == NULL) {
476 obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
477 sizeof(long), GFP_KERNEL);
478 if (obj->bit_17 == NULL) {
479 DRM_ERROR("Failed to allocate memory for bit 17 "
480 "record\n");
481 return;
482 }
483 }
484
485 for (i = 0; i < page_count; i++) {
486 if (page_to_phys(obj->pages[i]) & (1 << 17))
487 __set_bit(i, obj->bit_17);
488 else
489 __clear_bit(i, obj->bit_17);
490 }
491}
1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include <linux/string.h>
29#include <linux/bitops.h>
30#include <drm/drmP.h>
31#include <drm/i915_drm.h>
32#include "i915_drv.h"
33
34/**
35 * DOC: buffer object tiling
36 *
37 * i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
38 * declare fence register requirements.
39 *
40 * In principle GEM doesn't care at all about the internal data layout of an
41 * object, and hence it also doesn't care about tiling or swizzling. There's two
42 * exceptions:
43 *
44 * - For X and Y tiling the hardware provides detilers for CPU access, so called
45 * fences. Since there's only a limited amount of them the kernel must manage
46 * these, and therefore userspace must tell the kernel the object tiling if it
47 * wants to use fences for detiling.
48 * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
49 * depends upon the physical page frame number. When swapping such objects the
50 * page frame number might change and the kernel must be able to fix this up
51 * and hence now the tiling. Note that on a subset of platforms with
52 * asymmetric memory channel population the swizzling pattern changes in an
53 * unknown way, and for those the kernel simply forbids swapping completely.
54 *
55 * Since neither of this applies for new tiling layouts on modern platforms like
56 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
57 * Anything else can be handled in userspace entirely without the kernel's
58 * invovlement.
59 */
60
61/* Check pitch constriants for all chips & tiling formats */
62static bool
63i915_tiling_ok(struct drm_i915_private *dev_priv,
64 int stride, int size, int tiling_mode)
65{
66 int tile_width;
67
68 /* Linear is always fine */
69 if (tiling_mode == I915_TILING_NONE)
70 return true;
71
72 if (tiling_mode > I915_TILING_LAST)
73 return false;
74
75 if (IS_GEN2(dev_priv) ||
76 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
77 tile_width = 128;
78 else
79 tile_width = 512;
80
81 /* check maximum stride & object size */
82 /* i965+ stores the end address of the gtt mapping in the fence
83 * reg, so dont bother to check the size */
84 if (INTEL_GEN(dev_priv) >= 7) {
85 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
86 return false;
87 } else if (INTEL_GEN(dev_priv) >= 4) {
88 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
89 return false;
90 } else {
91 if (stride > 8192)
92 return false;
93
94 if (IS_GEN3(dev_priv)) {
95 if (size > I830_FENCE_MAX_SIZE_VAL << 20)
96 return false;
97 } else {
98 if (size > I830_FENCE_MAX_SIZE_VAL << 19)
99 return false;
100 }
101 }
102
103 if (stride < tile_width)
104 return false;
105
106 /* 965+ just needs multiples of tile width */
107 if (INTEL_GEN(dev_priv) >= 4) {
108 if (stride & (tile_width - 1))
109 return false;
110 return true;
111 }
112
113 /* Pre-965 needs power of two tile widths */
114 if (stride & (stride - 1))
115 return false;
116
117 return true;
118}
119
120static bool i915_vma_fence_prepare(struct i915_vma *vma, int tiling_mode)
121{
122 struct drm_i915_private *dev_priv = to_i915(vma->vm->dev);
123 u32 size;
124
125 if (!i915_vma_is_map_and_fenceable(vma))
126 return true;
127
128 if (INTEL_GEN(dev_priv) == 3) {
129 if (vma->node.start & ~I915_FENCE_START_MASK)
130 return false;
131 } else {
132 if (vma->node.start & ~I830_FENCE_START_MASK)
133 return false;
134 }
135
136 size = i915_gem_get_ggtt_size(dev_priv, vma->size, tiling_mode);
137 if (vma->node.size < size)
138 return false;
139
140 if (vma->node.start & (size - 1))
141 return false;
142
143 return true;
144}
145
146/* Make the current GTT allocation valid for the change in tiling. */
147static int
148i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj, int tiling_mode)
149{
150 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
151 struct i915_vma *vma;
152 int ret;
153
154 if (tiling_mode == I915_TILING_NONE)
155 return 0;
156
157 if (INTEL_GEN(dev_priv) >= 4)
158 return 0;
159
160 list_for_each_entry(vma, &obj->vma_list, obj_link) {
161 if (i915_vma_fence_prepare(vma, tiling_mode))
162 continue;
163
164 ret = i915_vma_unbind(vma);
165 if (ret)
166 return ret;
167 }
168
169 return 0;
170}
171
172/**
173 * i915_gem_set_tiling - IOCTL handler to set tiling mode
174 * @dev: DRM device
175 * @data: data pointer for the ioctl
176 * @file: DRM file for the ioctl call
177 *
178 * Sets the tiling mode of an object, returning the required swizzling of
179 * bit 6 of addresses in the object.
180 *
181 * Called by the user via ioctl.
182 *
183 * Returns:
184 * Zero on success, negative errno on failure.
185 */
186int
187i915_gem_set_tiling(struct drm_device *dev, void *data,
188 struct drm_file *file)
189{
190 struct drm_i915_gem_set_tiling *args = data;
191 struct drm_i915_private *dev_priv = to_i915(dev);
192 struct drm_i915_gem_object *obj;
193 int err = 0;
194
195 /* Make sure we don't cross-contaminate obj->tiling_and_stride */
196 BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
197
198 obj = i915_gem_object_lookup(file, args->handle);
199 if (!obj)
200 return -ENOENT;
201
202 if (!i915_tiling_ok(dev_priv,
203 args->stride, obj->base.size, args->tiling_mode)) {
204 i915_gem_object_put(obj);
205 return -EINVAL;
206 }
207
208 mutex_lock(&dev->struct_mutex);
209 if (obj->pin_display || obj->framebuffer_references) {
210 err = -EBUSY;
211 goto err;
212 }
213
214 if (args->tiling_mode == I915_TILING_NONE) {
215 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
216 args->stride = 0;
217 } else {
218 if (args->tiling_mode == I915_TILING_X)
219 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
220 else
221 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
222
223 /* Hide bit 17 swizzling from the user. This prevents old Mesa
224 * from aborting the application on sw fallbacks to bit 17,
225 * and we use the pread/pwrite bit17 paths to swizzle for it.
226 * If there was a user that was relying on the swizzle
227 * information for drm_intel_bo_map()ed reads/writes this would
228 * break it, but we don't have any of those.
229 */
230 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
231 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
232 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
233 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
234
235 /* If we can't handle the swizzling, make it untiled. */
236 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
237 args->tiling_mode = I915_TILING_NONE;
238 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
239 args->stride = 0;
240 }
241 }
242
243 if (args->tiling_mode != i915_gem_object_get_tiling(obj) ||
244 args->stride != i915_gem_object_get_stride(obj)) {
245 /* We need to rebind the object if its current allocation
246 * no longer meets the alignment restrictions for its new
247 * tiling mode. Otherwise we can just leave it alone, but
248 * need to ensure that any fence register is updated before
249 * the next fenced (either through the GTT or by the BLT unit
250 * on older GPUs) access.
251 *
252 * After updating the tiling parameters, we then flag whether
253 * we need to update an associated fence register. Note this
254 * has to also include the unfenced register the GPU uses
255 * whilst executing a fenced command for an untiled object.
256 */
257
258 err = i915_gem_object_fence_prepare(obj, args->tiling_mode);
259 if (!err) {
260 struct i915_vma *vma;
261
262 mutex_lock(&obj->mm.lock);
263 if (obj->mm.pages &&
264 obj->mm.madv == I915_MADV_WILLNEED &&
265 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
266 if (args->tiling_mode == I915_TILING_NONE) {
267 GEM_BUG_ON(!obj->mm.quirked);
268 __i915_gem_object_unpin_pages(obj);
269 obj->mm.quirked = false;
270 }
271 if (!i915_gem_object_is_tiled(obj)) {
272 GEM_BUG_ON(!obj->mm.quirked);
273 __i915_gem_object_pin_pages(obj);
274 obj->mm.quirked = true;
275 }
276 }
277 mutex_unlock(&obj->mm.lock);
278
279 list_for_each_entry(vma, &obj->vma_list, obj_link) {
280 if (!vma->fence)
281 continue;
282
283 vma->fence->dirty = true;
284 }
285 obj->tiling_and_stride =
286 args->stride | args->tiling_mode;
287
288 /* Force the fence to be reacquired for GTT access */
289 i915_gem_release_mmap(obj);
290 }
291 }
292 /* we have to maintain this existing ABI... */
293 args->stride = i915_gem_object_get_stride(obj);
294 args->tiling_mode = i915_gem_object_get_tiling(obj);
295
296 /* Try to preallocate memory required to save swizzling on put-pages */
297 if (i915_gem_object_needs_bit17_swizzle(obj)) {
298 if (obj->bit_17 == NULL) {
299 obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
300 sizeof(long), GFP_KERNEL);
301 }
302 } else {
303 kfree(obj->bit_17);
304 obj->bit_17 = NULL;
305 }
306
307err:
308 i915_gem_object_put(obj);
309 mutex_unlock(&dev->struct_mutex);
310
311 return err;
312}
313
314/**
315 * i915_gem_get_tiling - IOCTL handler to get tiling mode
316 * @dev: DRM device
317 * @data: data pointer for the ioctl
318 * @file: DRM file for the ioctl call
319 *
320 * Returns the current tiling mode and required bit 6 swizzling for the object.
321 *
322 * Called by the user via ioctl.
323 *
324 * Returns:
325 * Zero on success, negative errno on failure.
326 */
327int
328i915_gem_get_tiling(struct drm_device *dev, void *data,
329 struct drm_file *file)
330{
331 struct drm_i915_gem_get_tiling *args = data;
332 struct drm_i915_private *dev_priv = to_i915(dev);
333 struct drm_i915_gem_object *obj;
334 int err = -ENOENT;
335
336 rcu_read_lock();
337 obj = i915_gem_object_lookup_rcu(file, args->handle);
338 if (obj) {
339 args->tiling_mode =
340 READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
341 err = 0;
342 }
343 rcu_read_unlock();
344 if (unlikely(err))
345 return err;
346
347 switch (args->tiling_mode) {
348 case I915_TILING_X:
349 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
350 break;
351 case I915_TILING_Y:
352 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
353 break;
354 default:
355 case I915_TILING_NONE:
356 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
357 break;
358 }
359
360 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
361 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
362 args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
363 else
364 args->phys_swizzle_mode = args->swizzle_mode;
365 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
366 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
367 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
368 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
369
370 return 0;
371}