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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "linux/string.h"
29#include "linux/bitops.h"
30#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
34
35/** @file i915_gem_tiling.c
36 *
37 * Support for managing tiling state of buffer objects.
38 *
39 * The idea behind tiling is to increase cache hit rates by rearranging
40 * pixel data so that a group of pixel accesses are in the same cacheline.
41 * Performance improvement from doing this on the back/depth buffer are on
42 * the order of 30%.
43 *
44 * Intel architectures make this somewhat more complicated, though, by
45 * adjustments made to addressing of data when the memory is in interleaved
46 * mode (matched pairs of DIMMS) to improve memory bandwidth.
47 * For interleaved memory, the CPU sends every sequential 64 bytes
48 * to an alternate memory channel so it can get the bandwidth from both.
49 *
50 * The GPU also rearranges its accesses for increased bandwidth to interleaved
51 * memory, and it matches what the CPU does for non-tiled. However, when tiled
52 * it does it a little differently, since one walks addresses not just in the
53 * X direction but also Y. So, along with alternating channels when bit
54 * 6 of the address flips, it also alternates when other bits flip -- Bits 9
55 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
56 * are common to both the 915 and 965-class hardware.
57 *
58 * The CPU also sometimes XORs in higher bits as well, to improve
59 * bandwidth doing strided access like we do so frequently in graphics. This
60 * is called "Channel XOR Randomization" in the MCH documentation. The result
61 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
62 * decode.
63 *
64 * All of this bit 6 XORing has an effect on our memory management,
65 * as we need to make sure that the 3d driver can correctly address object
66 * contents.
67 *
68 * If we don't have interleaved memory, all tiling is safe and no swizzling is
69 * required.
70 *
71 * When bit 17 is XORed in, we simply refuse to tile at all. Bit
72 * 17 is not just a page offset, so as we page an objet out and back in,
73 * individual pages in it will have different bit 17 addresses, resulting in
74 * each 64 bytes being swapped with its neighbor!
75 *
76 * Otherwise, if interleaved, we have to tell the 3d driver what the address
77 * swizzling it needs to do is, since it's writing with the CPU to the pages
78 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
79 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
80 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
81 * to match what the GPU expects.
82 */
83
84/**
85 * Detects bit 6 swizzling of address lookup between IGD access and CPU
86 * access through main memory.
87 */
88void
89i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
90{
91 drm_i915_private_t *dev_priv = dev->dev_private;
92 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
93 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
94
95 if (INTEL_INFO(dev)->gen >= 5) {
96 /* On Ironlake whatever DRAM config, GPU always do
97 * same swizzling setup.
98 */
99 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
100 swizzle_y = I915_BIT_6_SWIZZLE_9;
101 } else if (IS_GEN2(dev)) {
102 /* As far as we know, the 865 doesn't have these bit 6
103 * swizzling issues.
104 */
105 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
106 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
107 } else if (IS_MOBILE(dev)) {
108 uint32_t dcc;
109
110 /* On mobile 9xx chipsets, channel interleave by the CPU is
111 * determined by DCC. For single-channel, neither the CPU
112 * nor the GPU do swizzling. For dual channel interleaved,
113 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
114 * 9 for Y tiled. The CPU's interleave is independent, and
115 * can be based on either bit 11 (haven't seen this yet) or
116 * bit 17 (common).
117 */
118 dcc = I915_READ(DCC);
119 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
120 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
121 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
122 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
123 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
124 break;
125 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
126 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
127 /* This is the base swizzling by the GPU for
128 * tiled buffers.
129 */
130 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
131 swizzle_y = I915_BIT_6_SWIZZLE_9;
132 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
133 /* Bit 11 swizzling by the CPU in addition. */
134 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
135 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
136 } else {
137 /* Bit 17 swizzling by the CPU in addition. */
138 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
139 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
140 }
141 break;
142 }
143 if (dcc == 0xffffffff) {
144 DRM_ERROR("Couldn't read from MCHBAR. "
145 "Disabling tiling.\n");
146 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
147 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
148 }
149 } else {
150 /* The 965, G33, and newer, have a very flexible memory
151 * configuration. It will enable dual-channel mode
152 * (interleaving) on as much memory as it can, and the GPU
153 * will additionally sometimes enable different bit 6
154 * swizzling for tiled objects from the CPU.
155 *
156 * Here's what I found on the G965:
157 * slot fill memory size swizzling
158 * 0A 0B 1A 1B 1-ch 2-ch
159 * 512 0 0 0 512 0 O
160 * 512 0 512 0 16 1008 X
161 * 512 0 0 512 16 1008 X
162 * 0 512 0 512 16 1008 X
163 * 1024 1024 1024 0 2048 1024 O
164 *
165 * We could probably detect this based on either the DRB
166 * matching, which was the case for the swizzling required in
167 * the table above, or from the 1-ch value being less than
168 * the minimum size of a rank.
169 */
170 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
171 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
172 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
173 } else {
174 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
175 swizzle_y = I915_BIT_6_SWIZZLE_9;
176 }
177 }
178
179 dev_priv->mm.bit_6_swizzle_x = swizzle_x;
180 dev_priv->mm.bit_6_swizzle_y = swizzle_y;
181}
182
183/* Check pitch constriants for all chips & tiling formats */
184static bool
185i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
186{
187 int tile_width;
188
189 /* Linear is always fine */
190 if (tiling_mode == I915_TILING_NONE)
191 return true;
192
193 if (IS_GEN2(dev) ||
194 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
195 tile_width = 128;
196 else
197 tile_width = 512;
198
199 /* check maximum stride & object size */
200 if (INTEL_INFO(dev)->gen >= 4) {
201 /* i965 stores the end address of the gtt mapping in the fence
202 * reg, so dont bother to check the size */
203 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
204 return false;
205 } else {
206 if (stride > 8192)
207 return false;
208
209 if (IS_GEN3(dev)) {
210 if (size > I830_FENCE_MAX_SIZE_VAL << 20)
211 return false;
212 } else {
213 if (size > I830_FENCE_MAX_SIZE_VAL << 19)
214 return false;
215 }
216 }
217
218 /* 965+ just needs multiples of tile width */
219 if (INTEL_INFO(dev)->gen >= 4) {
220 if (stride & (tile_width - 1))
221 return false;
222 return true;
223 }
224
225 /* Pre-965 needs power of two tile widths */
226 if (stride < tile_width)
227 return false;
228
229 if (stride & (stride - 1))
230 return false;
231
232 return true;
233}
234
235/* Is the current GTT allocation valid for the change in tiling? */
236static bool
237i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
238{
239 u32 size;
240
241 if (tiling_mode == I915_TILING_NONE)
242 return true;
243
244 if (INTEL_INFO(obj->base.dev)->gen >= 4)
245 return true;
246
247 if (INTEL_INFO(obj->base.dev)->gen == 3) {
248 if (obj->gtt_offset & ~I915_FENCE_START_MASK)
249 return false;
250 } else {
251 if (obj->gtt_offset & ~I830_FENCE_START_MASK)
252 return false;
253 }
254
255 /*
256 * Previous chips need to be aligned to the size of the smallest
257 * fence register that can contain the object.
258 */
259 if (INTEL_INFO(obj->base.dev)->gen == 3)
260 size = 1024*1024;
261 else
262 size = 512*1024;
263
264 while (size < obj->base.size)
265 size <<= 1;
266
267 if (obj->gtt_space->size != size)
268 return false;
269
270 if (obj->gtt_offset & (size - 1))
271 return false;
272
273 return true;
274}
275
276/**
277 * Sets the tiling mode of an object, returning the required swizzling of
278 * bit 6 of addresses in the object.
279 */
280int
281i915_gem_set_tiling(struct drm_device *dev, void *data,
282 struct drm_file *file)
283{
284 struct drm_i915_gem_set_tiling *args = data;
285 drm_i915_private_t *dev_priv = dev->dev_private;
286 struct drm_i915_gem_object *obj;
287 int ret = 0;
288
289 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
290 if (&obj->base == NULL)
291 return -ENOENT;
292
293 if (!i915_tiling_ok(dev,
294 args->stride, obj->base.size, args->tiling_mode)) {
295 drm_gem_object_unreference_unlocked(&obj->base);
296 return -EINVAL;
297 }
298
299 if (obj->pin_count) {
300 drm_gem_object_unreference_unlocked(&obj->base);
301 return -EBUSY;
302 }
303
304 if (args->tiling_mode == I915_TILING_NONE) {
305 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
306 args->stride = 0;
307 } else {
308 if (args->tiling_mode == I915_TILING_X)
309 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
310 else
311 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
312
313 /* Hide bit 17 swizzling from the user. This prevents old Mesa
314 * from aborting the application on sw fallbacks to bit 17,
315 * and we use the pread/pwrite bit17 paths to swizzle for it.
316 * If there was a user that was relying on the swizzle
317 * information for drm_intel_bo_map()ed reads/writes this would
318 * break it, but we don't have any of those.
319 */
320 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
321 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
322 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
323 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
324
325 /* If we can't handle the swizzling, make it untiled. */
326 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
327 args->tiling_mode = I915_TILING_NONE;
328 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
329 args->stride = 0;
330 }
331 }
332
333 mutex_lock(&dev->struct_mutex);
334 if (args->tiling_mode != obj->tiling_mode ||
335 args->stride != obj->stride) {
336 /* We need to rebind the object if its current allocation
337 * no longer meets the alignment restrictions for its new
338 * tiling mode. Otherwise we can just leave it alone, but
339 * need to ensure that any fence register is cleared.
340 */
341 i915_gem_release_mmap(obj);
342
343 obj->map_and_fenceable =
344 obj->gtt_space == NULL ||
345 (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end &&
346 i915_gem_object_fence_ok(obj, args->tiling_mode));
347
348 /* Rebind if we need a change of alignment */
349 if (!obj->map_and_fenceable) {
350 u32 unfenced_alignment =
351 i915_gem_get_unfenced_gtt_alignment(dev,
352 obj->base.size,
353 args->tiling_mode);
354 if (obj->gtt_offset & (unfenced_alignment - 1))
355 ret = i915_gem_object_unbind(obj);
356 }
357
358 if (ret == 0) {
359 obj->tiling_changed = true;
360 obj->tiling_mode = args->tiling_mode;
361 obj->stride = args->stride;
362 }
363 }
364 /* we have to maintain this existing ABI... */
365 args->stride = obj->stride;
366 args->tiling_mode = obj->tiling_mode;
367 drm_gem_object_unreference(&obj->base);
368 mutex_unlock(&dev->struct_mutex);
369
370 return ret;
371}
372
373/**
374 * Returns the current tiling mode and required bit 6 swizzling for the object.
375 */
376int
377i915_gem_get_tiling(struct drm_device *dev, void *data,
378 struct drm_file *file)
379{
380 struct drm_i915_gem_get_tiling *args = data;
381 drm_i915_private_t *dev_priv = dev->dev_private;
382 struct drm_i915_gem_object *obj;
383
384 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
385 if (&obj->base == NULL)
386 return -ENOENT;
387
388 mutex_lock(&dev->struct_mutex);
389
390 args->tiling_mode = obj->tiling_mode;
391 switch (obj->tiling_mode) {
392 case I915_TILING_X:
393 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
394 break;
395 case I915_TILING_Y:
396 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
397 break;
398 case I915_TILING_NONE:
399 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
400 break;
401 default:
402 DRM_ERROR("unknown tiling mode\n");
403 }
404
405 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
406 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
407 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
408 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
409 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
410
411 drm_gem_object_unreference(&obj->base);
412 mutex_unlock(&dev->struct_mutex);
413
414 return 0;
415}
416
417/**
418 * Swap every 64 bytes of this page around, to account for it having a new
419 * bit 17 of its physical address and therefore being interpreted differently
420 * by the GPU.
421 */
422static void
423i915_gem_swizzle_page(struct page *page)
424{
425 char temp[64];
426 char *vaddr;
427 int i;
428
429 vaddr = kmap(page);
430
431 for (i = 0; i < PAGE_SIZE; i += 128) {
432 memcpy(temp, &vaddr[i], 64);
433 memcpy(&vaddr[i], &vaddr[i + 64], 64);
434 memcpy(&vaddr[i + 64], temp, 64);
435 }
436
437 kunmap(page);
438}
439
440void
441i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
442{
443 struct drm_device *dev = obj->base.dev;
444 drm_i915_private_t *dev_priv = dev->dev_private;
445 int page_count = obj->base.size >> PAGE_SHIFT;
446 int i;
447
448 if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
449 return;
450
451 if (obj->bit_17 == NULL)
452 return;
453
454 for (i = 0; i < page_count; i++) {
455 char new_bit_17 = page_to_phys(obj->pages[i]) >> 17;
456 if ((new_bit_17 & 0x1) !=
457 (test_bit(i, obj->bit_17) != 0)) {
458 i915_gem_swizzle_page(obj->pages[i]);
459 set_page_dirty(obj->pages[i]);
460 }
461 }
462}
463
464void
465i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
466{
467 struct drm_device *dev = obj->base.dev;
468 drm_i915_private_t *dev_priv = dev->dev_private;
469 int page_count = obj->base.size >> PAGE_SHIFT;
470 int i;
471
472 if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
473 return;
474
475 if (obj->bit_17 == NULL) {
476 obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
477 sizeof(long), GFP_KERNEL);
478 if (obj->bit_17 == NULL) {
479 DRM_ERROR("Failed to allocate memory for bit 17 "
480 "record\n");
481 return;
482 }
483 }
484
485 for (i = 0; i < page_count; i++) {
486 if (page_to_phys(obj->pages[i]) & (1 << 17))
487 __set_bit(i, obj->bit_17);
488 else
489 __clear_bit(i, obj->bit_17);
490 }
491}
1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include <linux/string.h>
29#include <linux/bitops.h>
30#include <drm/drmP.h>
31#include <drm/i915_drm.h>
32#include "i915_drv.h"
33
34/**
35 * DOC: buffer object tiling
36 *
37 * i915_gem_set_tiling_ioctl() and i915_gem_get_tiling_ioctl() is the userspace
38 * interface to declare fence register requirements.
39 *
40 * In principle GEM doesn't care at all about the internal data layout of an
41 * object, and hence it also doesn't care about tiling or swizzling. There's two
42 * exceptions:
43 *
44 * - For X and Y tiling the hardware provides detilers for CPU access, so called
45 * fences. Since there's only a limited amount of them the kernel must manage
46 * these, and therefore userspace must tell the kernel the object tiling if it
47 * wants to use fences for detiling.
48 * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
49 * depends upon the physical page frame number. When swapping such objects the
50 * page frame number might change and the kernel must be able to fix this up
51 * and hence now the tiling. Note that on a subset of platforms with
52 * asymmetric memory channel population the swizzling pattern changes in an
53 * unknown way, and for those the kernel simply forbids swapping completely.
54 *
55 * Since neither of this applies for new tiling layouts on modern platforms like
56 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
57 * Anything else can be handled in userspace entirely without the kernel's
58 * invovlement.
59 */
60
61/**
62 * i915_gem_fence_size - required global GTT size for a fence
63 * @i915: i915 device
64 * @size: object size
65 * @tiling: tiling mode
66 * @stride: tiling stride
67 *
68 * Return the required global GTT size for a fence (view of a tiled object),
69 * taking into account potential fence register mapping.
70 */
71u32 i915_gem_fence_size(struct drm_i915_private *i915,
72 u32 size, unsigned int tiling, unsigned int stride)
73{
74 u32 ggtt_size;
75
76 GEM_BUG_ON(!size);
77
78 if (tiling == I915_TILING_NONE)
79 return size;
80
81 GEM_BUG_ON(!stride);
82
83 if (INTEL_GEN(i915) >= 4) {
84 stride *= i915_gem_tile_height(tiling);
85 GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE));
86 return roundup(size, stride);
87 }
88
89 /* Previous chips need a power-of-two fence region when tiling */
90 if (IS_GEN3(i915))
91 ggtt_size = 1024*1024;
92 else
93 ggtt_size = 512*1024;
94
95 while (ggtt_size < size)
96 ggtt_size <<= 1;
97
98 return ggtt_size;
99}
100
101/**
102 * i915_gem_fence_alignment - required global GTT alignment for a fence
103 * @i915: i915 device
104 * @size: object size
105 * @tiling: tiling mode
106 * @stride: tiling stride
107 *
108 * Return the required global GTT alignment for a fence (a view of a tiled
109 * object), taking into account potential fence register mapping.
110 */
111u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
112 unsigned int tiling, unsigned int stride)
113{
114 GEM_BUG_ON(!size);
115
116 /*
117 * Minimum alignment is 4k (GTT page size), but might be greater
118 * if a fence register is needed for the object.
119 */
120 if (tiling == I915_TILING_NONE)
121 return I915_GTT_MIN_ALIGNMENT;
122
123 if (INTEL_GEN(i915) >= 4)
124 return I965_FENCE_PAGE;
125
126 /*
127 * Previous chips need to be aligned to the size of the smallest
128 * fence register that can contain the object.
129 */
130 return i915_gem_fence_size(i915, size, tiling, stride);
131}
132
133/* Check pitch constriants for all chips & tiling formats */
134static bool
135i915_tiling_ok(struct drm_i915_gem_object *obj,
136 unsigned int tiling, unsigned int stride)
137{
138 struct drm_i915_private *i915 = to_i915(obj->base.dev);
139 unsigned int tile_width;
140
141 /* Linear is always fine */
142 if (tiling == I915_TILING_NONE)
143 return true;
144
145 if (tiling > I915_TILING_LAST)
146 return false;
147
148 /* check maximum stride & object size */
149 /* i965+ stores the end address of the gtt mapping in the fence
150 * reg, so dont bother to check the size */
151 if (INTEL_GEN(i915) >= 7) {
152 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
153 return false;
154 } else if (INTEL_GEN(i915) >= 4) {
155 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
156 return false;
157 } else {
158 if (stride > 8192)
159 return false;
160
161 if (!is_power_of_2(stride))
162 return false;
163 }
164
165 if (IS_GEN2(i915) ||
166 (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
167 tile_width = 128;
168 else
169 tile_width = 512;
170
171 if (!stride || !IS_ALIGNED(stride, tile_width))
172 return false;
173
174 return true;
175}
176
177static bool i915_vma_fence_prepare(struct i915_vma *vma,
178 int tiling_mode, unsigned int stride)
179{
180 struct drm_i915_private *i915 = vma->vm->i915;
181 u32 size, alignment;
182
183 if (!i915_vma_is_map_and_fenceable(vma))
184 return true;
185
186 size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
187 if (vma->node.size < size)
188 return false;
189
190 alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
191 if (!IS_ALIGNED(vma->node.start, alignment))
192 return false;
193
194 return true;
195}
196
197/* Make the current GTT allocation valid for the change in tiling. */
198static int
199i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
200 int tiling_mode, unsigned int stride)
201{
202 struct i915_vma *vma;
203 int ret;
204
205 if (tiling_mode == I915_TILING_NONE)
206 return 0;
207
208 for_each_ggtt_vma(vma, obj) {
209 if (i915_vma_fence_prepare(vma, tiling_mode, stride))
210 continue;
211
212 ret = i915_vma_unbind(vma);
213 if (ret)
214 return ret;
215 }
216
217 return 0;
218}
219
220int
221i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
222 unsigned int tiling, unsigned int stride)
223{
224 struct drm_i915_private *i915 = to_i915(obj->base.dev);
225 struct i915_vma *vma;
226 int err;
227
228 /* Make sure we don't cross-contaminate obj->tiling_and_stride */
229 BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
230
231 GEM_BUG_ON(!i915_tiling_ok(obj, tiling, stride));
232 GEM_BUG_ON(!stride ^ (tiling == I915_TILING_NONE));
233 lockdep_assert_held(&i915->drm.struct_mutex);
234
235 if ((tiling | stride) == obj->tiling_and_stride)
236 return 0;
237
238 if (i915_gem_object_is_framebuffer(obj))
239 return -EBUSY;
240
241 /* We need to rebind the object if its current allocation
242 * no longer meets the alignment restrictions for its new
243 * tiling mode. Otherwise we can just leave it alone, but
244 * need to ensure that any fence register is updated before
245 * the next fenced (either through the GTT or by the BLT unit
246 * on older GPUs) access.
247 *
248 * After updating the tiling parameters, we then flag whether
249 * we need to update an associated fence register. Note this
250 * has to also include the unfenced register the GPU uses
251 * whilst executing a fenced command for an untiled object.
252 */
253
254 err = i915_gem_object_fence_prepare(obj, tiling, stride);
255 if (err)
256 return err;
257
258 i915_gem_object_lock(obj);
259 if (i915_gem_object_is_framebuffer(obj)) {
260 i915_gem_object_unlock(obj);
261 return -EBUSY;
262 }
263
264 /* If the memory has unknown (i.e. varying) swizzling, we pin the
265 * pages to prevent them being swapped out and causing corruption
266 * due to the change in swizzling.
267 */
268 mutex_lock(&obj->mm.lock);
269 if (i915_gem_object_has_pages(obj) &&
270 obj->mm.madv == I915_MADV_WILLNEED &&
271 i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
272 if (tiling == I915_TILING_NONE) {
273 GEM_BUG_ON(!obj->mm.quirked);
274 __i915_gem_object_unpin_pages(obj);
275 obj->mm.quirked = false;
276 }
277 if (!i915_gem_object_is_tiled(obj)) {
278 GEM_BUG_ON(obj->mm.quirked);
279 __i915_gem_object_pin_pages(obj);
280 obj->mm.quirked = true;
281 }
282 }
283 mutex_unlock(&obj->mm.lock);
284
285 for_each_ggtt_vma(vma, obj) {
286 vma->fence_size =
287 i915_gem_fence_size(i915, vma->size, tiling, stride);
288 vma->fence_alignment =
289 i915_gem_fence_alignment(i915,
290 vma->size, tiling, stride);
291
292 if (vma->fence)
293 vma->fence->dirty = true;
294 }
295
296 obj->tiling_and_stride = tiling | stride;
297 i915_gem_object_unlock(obj);
298
299 /* Force the fence to be reacquired for GTT access */
300 i915_gem_release_mmap(obj);
301
302 /* Try to preallocate memory required to save swizzling on put-pages */
303 if (i915_gem_object_needs_bit17_swizzle(obj)) {
304 if (!obj->bit_17) {
305 obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
306 sizeof(long), GFP_KERNEL);
307 }
308 } else {
309 kfree(obj->bit_17);
310 obj->bit_17 = NULL;
311 }
312
313 return 0;
314}
315
316/**
317 * i915_gem_set_tiling_ioctl - IOCTL handler to set tiling mode
318 * @dev: DRM device
319 * @data: data pointer for the ioctl
320 * @file: DRM file for the ioctl call
321 *
322 * Sets the tiling mode of an object, returning the required swizzling of
323 * bit 6 of addresses in the object.
324 *
325 * Called by the user via ioctl.
326 *
327 * Returns:
328 * Zero on success, negative errno on failure.
329 */
330int
331i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
332 struct drm_file *file)
333{
334 struct drm_i915_gem_set_tiling *args = data;
335 struct drm_i915_gem_object *obj;
336 int err;
337
338 obj = i915_gem_object_lookup(file, args->handle);
339 if (!obj)
340 return -ENOENT;
341
342 /*
343 * The tiling mode of proxy objects is handled by its generator, and
344 * not allowed to be changed by userspace.
345 */
346 if (i915_gem_object_is_proxy(obj)) {
347 err = -ENXIO;
348 goto err;
349 }
350
351 if (!i915_tiling_ok(obj, args->tiling_mode, args->stride)) {
352 err = -EINVAL;
353 goto err;
354 }
355
356 if (args->tiling_mode == I915_TILING_NONE) {
357 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
358 args->stride = 0;
359 } else {
360 if (args->tiling_mode == I915_TILING_X)
361 args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_x;
362 else
363 args->swizzle_mode = to_i915(dev)->mm.bit_6_swizzle_y;
364
365 /* Hide bit 17 swizzling from the user. This prevents old Mesa
366 * from aborting the application on sw fallbacks to bit 17,
367 * and we use the pread/pwrite bit17 paths to swizzle for it.
368 * If there was a user that was relying on the swizzle
369 * information for drm_intel_bo_map()ed reads/writes this would
370 * break it, but we don't have any of those.
371 */
372 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
373 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
374 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
375 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
376
377 /* If we can't handle the swizzling, make it untiled. */
378 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
379 args->tiling_mode = I915_TILING_NONE;
380 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
381 args->stride = 0;
382 }
383 }
384
385 err = mutex_lock_interruptible(&dev->struct_mutex);
386 if (err)
387 goto err;
388
389 err = i915_gem_object_set_tiling(obj, args->tiling_mode, args->stride);
390 mutex_unlock(&dev->struct_mutex);
391
392 /* We have to maintain this existing ABI... */
393 args->stride = i915_gem_object_get_stride(obj);
394 args->tiling_mode = i915_gem_object_get_tiling(obj);
395
396err:
397 i915_gem_object_put(obj);
398 return err;
399}
400
401/**
402 * i915_gem_get_tiling_ioctl - IOCTL handler to get tiling mode
403 * @dev: DRM device
404 * @data: data pointer for the ioctl
405 * @file: DRM file for the ioctl call
406 *
407 * Returns the current tiling mode and required bit 6 swizzling for the object.
408 *
409 * Called by the user via ioctl.
410 *
411 * Returns:
412 * Zero on success, negative errno on failure.
413 */
414int
415i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
416 struct drm_file *file)
417{
418 struct drm_i915_gem_get_tiling *args = data;
419 struct drm_i915_private *dev_priv = to_i915(dev);
420 struct drm_i915_gem_object *obj;
421 int err = -ENOENT;
422
423 rcu_read_lock();
424 obj = i915_gem_object_lookup_rcu(file, args->handle);
425 if (obj) {
426 args->tiling_mode =
427 READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
428 err = 0;
429 }
430 rcu_read_unlock();
431 if (unlikely(err))
432 return err;
433
434 switch (args->tiling_mode) {
435 case I915_TILING_X:
436 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
437 break;
438 case I915_TILING_Y:
439 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
440 break;
441 default:
442 case I915_TILING_NONE:
443 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
444 break;
445 }
446
447 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
448 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
449 args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
450 else
451 args->phys_swizzle_mode = args->swizzle_mode;
452 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
453 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
454 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
455 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
456
457 return 0;
458}