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1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
28#include "reg.h"
29#include "phy.h"
30#include "btcoex.h"
31
32#include "../regd.h"
33
34#define ATHEROS_VENDOR_ID 0x168c
35
36#define AR5416_DEVID_PCI 0x0023
37#define AR5416_DEVID_PCIE 0x0024
38#define AR9160_DEVID_PCI 0x0027
39#define AR9280_DEVID_PCI 0x0029
40#define AR9280_DEVID_PCIE 0x002a
41#define AR9285_DEVID_PCIE 0x002b
42#define AR2427_DEVID_PCIE 0x002c
43#define AR9287_DEVID_PCI 0x002d
44#define AR9287_DEVID_PCIE 0x002e
45#define AR9300_DEVID_PCIE 0x0030
46#define AR9300_DEVID_AR9340 0x0031
47#define AR9300_DEVID_AR9485_PCIE 0x0032
48#define AR9300_DEVID_AR9330 0x0035
49
50#define AR5416_AR9100_DEVID 0x000b
51
52#define AR_SUBVENDOR_ID_NOG 0x0e11
53#define AR_SUBVENDOR_ID_NEW_A 0x7065
54#define AR5416_MAGIC 0x19641014
55
56#define AR9280_COEX2WIRE_SUBSYSID 0x309b
57#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
58#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
59
60#define AR9300_NUM_BT_WEIGHTS 4
61#define AR9300_NUM_WLAN_WEIGHTS 4
62
63#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
64
65#define ATH_DEFAULT_NOISE_FLOOR -95
66
67#define ATH9K_RSSI_BAD -128
68
69#define ATH9K_NUM_CHANNELS 38
70
71/* Register read/write primitives */
72#define REG_WRITE(_ah, _reg, _val) \
73 (_ah)->reg_ops.write((_ah), (_val), (_reg))
74
75#define REG_READ(_ah, _reg) \
76 (_ah)->reg_ops.read((_ah), (_reg))
77
78#define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
79 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
80
81#define REG_RMW(_ah, _reg, _set, _clr) \
82 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
83
84#define ENABLE_REGWRITE_BUFFER(_ah) \
85 do { \
86 if ((_ah)->reg_ops.enable_write_buffer) \
87 (_ah)->reg_ops.enable_write_buffer((_ah)); \
88 } while (0)
89
90#define REGWRITE_BUFFER_FLUSH(_ah) \
91 do { \
92 if ((_ah)->reg_ops.write_flush) \
93 (_ah)->reg_ops.write_flush((_ah)); \
94 } while (0)
95
96#define SM(_v, _f) (((_v) << _f##_S) & _f)
97#define MS(_v, _f) (((_v) & _f) >> _f##_S)
98#define REG_RMW_FIELD(_a, _r, _f, _v) \
99 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
100#define REG_READ_FIELD(_a, _r, _f) \
101 (((REG_READ(_a, _r) & _f) >> _f##_S))
102#define REG_SET_BIT(_a, _r, _f) \
103 REG_RMW(_a, _r, (_f), 0)
104#define REG_CLR_BIT(_a, _r, _f) \
105 REG_RMW(_a, _r, 0, (_f))
106
107#define DO_DELAY(x) do { \
108 if (((++(x) % 64) == 0) && \
109 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
110 != ATH_USB)) \
111 udelay(1); \
112 } while (0)
113
114#define REG_WRITE_ARRAY(iniarray, column, regWr) \
115 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
116
117#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
118#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
119#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
120#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
121#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
122#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
123#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
124
125#define AR_GPIOD_MASK 0x00001FFF
126#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
127
128#define BASE_ACTIVATE_DELAY 100
129#define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
130#define COEF_SCALE_S 24
131#define HT40_CHANNEL_CENTER_SHIFT 10
132
133#define ATH9K_ANTENNA0_CHAINMASK 0x1
134#define ATH9K_ANTENNA1_CHAINMASK 0x2
135
136#define ATH9K_NUM_DMA_DEBUG_REGS 8
137#define ATH9K_NUM_QUEUES 10
138
139#define MAX_RATE_POWER 63
140#define AH_WAIT_TIMEOUT 100000 /* (us) */
141#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
142#define AH_TIME_QUANTUM 10
143#define AR_KEYTABLE_SIZE 128
144#define POWER_UP_TIME 10000
145#define SPUR_RSSI_THRESH 40
146#define UPPER_5G_SUB_BAND_START 5700
147#define MID_5G_SUB_BAND_START 5400
148
149#define CAB_TIMEOUT_VAL 10
150#define BEACON_TIMEOUT_VAL 10
151#define MIN_BEACON_TIMEOUT_VAL 1
152#define SLEEP_SLOP 3
153
154#define INIT_CONFIG_STATUS 0x00000000
155#define INIT_RSSI_THR 0x00000700
156#define INIT_BCON_CNTRL_REG 0x00000000
157
158#define TU_TO_USEC(_tu) ((_tu) << 10)
159
160#define ATH9K_HW_RX_HP_QDEPTH 16
161#define ATH9K_HW_RX_LP_QDEPTH 128
162
163#define PAPRD_GAIN_TABLE_ENTRIES 32
164#define PAPRD_TABLE_SZ 24
165#define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
166
167enum ath_hw_txq_subtype {
168 ATH_TXQ_AC_BE = 0,
169 ATH_TXQ_AC_BK = 1,
170 ATH_TXQ_AC_VI = 2,
171 ATH_TXQ_AC_VO = 3,
172};
173
174enum ath_ini_subsys {
175 ATH_INI_PRE = 0,
176 ATH_INI_CORE,
177 ATH_INI_POST,
178 ATH_INI_NUM_SPLIT,
179};
180
181enum ath9k_hw_caps {
182 ATH9K_HW_CAP_HT = BIT(0),
183 ATH9K_HW_CAP_RFSILENT = BIT(1),
184 ATH9K_HW_CAP_CST = BIT(2),
185 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
186 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
187 ATH9K_HW_CAP_EDMA = BIT(6),
188 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
189 ATH9K_HW_CAP_LDPC = BIT(8),
190 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
191 ATH9K_HW_CAP_SGI_20 = BIT(10),
192 ATH9K_HW_CAP_PAPRD = BIT(11),
193 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
194 ATH9K_HW_CAP_2GHZ = BIT(13),
195 ATH9K_HW_CAP_5GHZ = BIT(14),
196 ATH9K_HW_CAP_APM = BIT(15),
197};
198
199struct ath9k_hw_capabilities {
200 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
201 u16 rts_aggr_limit;
202 u8 tx_chainmask;
203 u8 rx_chainmask;
204 u8 max_txchains;
205 u8 max_rxchains;
206 u8 num_gpio_pins;
207 u8 rx_hp_qdepth;
208 u8 rx_lp_qdepth;
209 u8 rx_status_len;
210 u8 tx_desc_len;
211 u8 txs_len;
212 u16 pcie_lcr_offset;
213 bool pcie_lcr_extsync_en;
214};
215
216struct ath9k_ops_config {
217 int dma_beacon_response_time;
218 int sw_beacon_response_time;
219 int additional_swba_backoff;
220 int ack_6mb;
221 u32 cwm_ignore_extcca;
222 bool pcieSerDesWrite;
223 u8 pcie_clock_req;
224 u32 pcie_waen;
225 u8 analog_shiftreg;
226 u8 paprd_disable;
227 u32 ofdm_trig_low;
228 u32 ofdm_trig_high;
229 u32 cck_trig_high;
230 u32 cck_trig_low;
231 u32 enable_ani;
232 int serialize_regmode;
233 bool rx_intr_mitigation;
234 bool tx_intr_mitigation;
235#define SPUR_DISABLE 0
236#define SPUR_ENABLE_IOCTL 1
237#define SPUR_ENABLE_EEPROM 2
238#define AR_SPUR_5413_1 1640
239#define AR_SPUR_5413_2 1200
240#define AR_NO_SPUR 0x8000
241#define AR_BASE_FREQ_2GHZ 2300
242#define AR_BASE_FREQ_5GHZ 4900
243#define AR_SPUR_FEEQ_BOUND_HT40 19
244#define AR_SPUR_FEEQ_BOUND_HT20 10
245 int spurmode;
246 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
247 u8 max_txtrig_level;
248 u16 ani_poll_interval; /* ANI poll interval in ms */
249};
250
251enum ath9k_int {
252 ATH9K_INT_RX = 0x00000001,
253 ATH9K_INT_RXDESC = 0x00000002,
254 ATH9K_INT_RXHP = 0x00000001,
255 ATH9K_INT_RXLP = 0x00000002,
256 ATH9K_INT_RXNOFRM = 0x00000008,
257 ATH9K_INT_RXEOL = 0x00000010,
258 ATH9K_INT_RXORN = 0x00000020,
259 ATH9K_INT_TX = 0x00000040,
260 ATH9K_INT_TXDESC = 0x00000080,
261 ATH9K_INT_TIM_TIMER = 0x00000100,
262 ATH9K_INT_BB_WATCHDOG = 0x00000400,
263 ATH9K_INT_TXURN = 0x00000800,
264 ATH9K_INT_MIB = 0x00001000,
265 ATH9K_INT_RXPHY = 0x00004000,
266 ATH9K_INT_RXKCM = 0x00008000,
267 ATH9K_INT_SWBA = 0x00010000,
268 ATH9K_INT_BMISS = 0x00040000,
269 ATH9K_INT_BNR = 0x00100000,
270 ATH9K_INT_TIM = 0x00200000,
271 ATH9K_INT_DTIM = 0x00400000,
272 ATH9K_INT_DTIMSYNC = 0x00800000,
273 ATH9K_INT_GPIO = 0x01000000,
274 ATH9K_INT_CABEND = 0x02000000,
275 ATH9K_INT_TSFOOR = 0x04000000,
276 ATH9K_INT_GENTIMER = 0x08000000,
277 ATH9K_INT_CST = 0x10000000,
278 ATH9K_INT_GTT = 0x20000000,
279 ATH9K_INT_FATAL = 0x40000000,
280 ATH9K_INT_GLOBAL = 0x80000000,
281 ATH9K_INT_BMISC = ATH9K_INT_TIM |
282 ATH9K_INT_DTIM |
283 ATH9K_INT_DTIMSYNC |
284 ATH9K_INT_TSFOOR |
285 ATH9K_INT_CABEND,
286 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
287 ATH9K_INT_RXDESC |
288 ATH9K_INT_RXEOL |
289 ATH9K_INT_RXORN |
290 ATH9K_INT_TXURN |
291 ATH9K_INT_TXDESC |
292 ATH9K_INT_MIB |
293 ATH9K_INT_RXPHY |
294 ATH9K_INT_RXKCM |
295 ATH9K_INT_SWBA |
296 ATH9K_INT_BMISS |
297 ATH9K_INT_GPIO,
298 ATH9K_INT_NOCARD = 0xffffffff
299};
300
301#define CHANNEL_CW_INT 0x00002
302#define CHANNEL_CCK 0x00020
303#define CHANNEL_OFDM 0x00040
304#define CHANNEL_2GHZ 0x00080
305#define CHANNEL_5GHZ 0x00100
306#define CHANNEL_PASSIVE 0x00200
307#define CHANNEL_DYN 0x00400
308#define CHANNEL_HALF 0x04000
309#define CHANNEL_QUARTER 0x08000
310#define CHANNEL_HT20 0x10000
311#define CHANNEL_HT40PLUS 0x20000
312#define CHANNEL_HT40MINUS 0x40000
313
314#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
315#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
316#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
317#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
318#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
319#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
320#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
321#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
322#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
323#define CHANNEL_ALL \
324 (CHANNEL_OFDM| \
325 CHANNEL_CCK| \
326 CHANNEL_2GHZ | \
327 CHANNEL_5GHZ | \
328 CHANNEL_HT20 | \
329 CHANNEL_HT40PLUS | \
330 CHANNEL_HT40MINUS)
331
332struct ath9k_hw_cal_data {
333 u16 channel;
334 u32 channelFlags;
335 int32_t CalValid;
336 int8_t iCoff;
337 int8_t qCoff;
338 bool paprd_done;
339 bool nfcal_pending;
340 bool nfcal_interference;
341 u16 small_signal_gain[AR9300_MAX_CHAINS];
342 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
343 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
344};
345
346struct ath9k_channel {
347 struct ieee80211_channel *chan;
348 struct ar5416AniState ani;
349 u16 channel;
350 u32 channelFlags;
351 u32 chanmode;
352 s16 noisefloor;
353};
354
355#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
356 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
357 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
358 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
359#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
360#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
361#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
362#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
363#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
364#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
365 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
366 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
367
368/* These macros check chanmode and not channelFlags */
369#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
370#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
371 ((_c)->chanmode == CHANNEL_G_HT20))
372#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
373 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
374 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
375 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
376#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
377
378enum ath9k_power_mode {
379 ATH9K_PM_AWAKE = 0,
380 ATH9K_PM_FULL_SLEEP,
381 ATH9K_PM_NETWORK_SLEEP,
382 ATH9K_PM_UNDEFINED
383};
384
385enum ath9k_tp_scale {
386 ATH9K_TP_SCALE_MAX = 0,
387 ATH9K_TP_SCALE_50,
388 ATH9K_TP_SCALE_25,
389 ATH9K_TP_SCALE_12,
390 ATH9K_TP_SCALE_MIN
391};
392
393enum ser_reg_mode {
394 SER_REG_MODE_OFF = 0,
395 SER_REG_MODE_ON = 1,
396 SER_REG_MODE_AUTO = 2,
397};
398
399enum ath9k_rx_qtype {
400 ATH9K_RX_QUEUE_HP,
401 ATH9K_RX_QUEUE_LP,
402 ATH9K_RX_QUEUE_MAX,
403};
404
405struct ath9k_beacon_state {
406 u32 bs_nexttbtt;
407 u32 bs_nextdtim;
408 u32 bs_intval;
409#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
410 u32 bs_dtimperiod;
411 u16 bs_cfpperiod;
412 u16 bs_cfpmaxduration;
413 u32 bs_cfpnext;
414 u16 bs_timoffset;
415 u16 bs_bmissthreshold;
416 u32 bs_sleepduration;
417 u32 bs_tsfoor_threshold;
418};
419
420struct chan_centers {
421 u16 synth_center;
422 u16 ctl_center;
423 u16 ext_center;
424};
425
426enum {
427 ATH9K_RESET_POWER_ON,
428 ATH9K_RESET_WARM,
429 ATH9K_RESET_COLD,
430};
431
432struct ath9k_hw_version {
433 u32 magic;
434 u16 devid;
435 u16 subvendorid;
436 u32 macVersion;
437 u16 macRev;
438 u16 phyRev;
439 u16 analog5GhzRev;
440 u16 analog2GhzRev;
441 u16 subsysid;
442 enum ath_usb_dev usbdev;
443};
444
445/* Generic TSF timer definitions */
446
447#define ATH_MAX_GEN_TIMER 16
448
449#define AR_GENTMR_BIT(_index) (1 << (_index))
450
451/*
452 * Using de Bruijin sequence to look up 1's index in a 32 bit number
453 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
454 */
455#define debruijn32 0x077CB531U
456
457struct ath_gen_timer_configuration {
458 u32 next_addr;
459 u32 period_addr;
460 u32 mode_addr;
461 u32 mode_mask;
462};
463
464struct ath_gen_timer {
465 void (*trigger)(void *arg);
466 void (*overflow)(void *arg);
467 void *arg;
468 u8 index;
469};
470
471struct ath_gen_timer_table {
472 u32 gen_timer_index[32];
473 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
474 union {
475 unsigned long timer_bits;
476 u16 val;
477 } timer_mask;
478};
479
480struct ath_hw_antcomb_conf {
481 u8 main_lna_conf;
482 u8 alt_lna_conf;
483 u8 fast_div_bias;
484 u8 main_gaintb;
485 u8 alt_gaintb;
486 int lna1_lna2_delta;
487 u8 div_group;
488};
489
490/**
491 * struct ath_hw_radar_conf - radar detection initialization parameters
492 *
493 * @pulse_inband: threshold for checking the ratio of in-band power
494 * to total power for short radar pulses (half dB steps)
495 * @pulse_inband_step: threshold for checking an in-band power to total
496 * power ratio increase for short radar pulses (half dB steps)
497 * @pulse_height: threshold for detecting the beginning of a short
498 * radar pulse (dB step)
499 * @pulse_rssi: threshold for detecting if a short radar pulse is
500 * gone (dB step)
501 * @pulse_maxlen: maximum pulse length (0.8 us steps)
502 *
503 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
504 * @radar_inband: threshold for checking the ratio of in-band power
505 * to total power for long radar pulses (half dB steps)
506 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
507 *
508 * @ext_channel: enable extension channel radar detection
509 */
510struct ath_hw_radar_conf {
511 unsigned int pulse_inband;
512 unsigned int pulse_inband_step;
513 unsigned int pulse_height;
514 unsigned int pulse_rssi;
515 unsigned int pulse_maxlen;
516
517 unsigned int radar_rssi;
518 unsigned int radar_inband;
519 int fir_power;
520
521 bool ext_channel;
522};
523
524/**
525 * struct ath_hw_private_ops - callbacks used internally by hardware code
526 *
527 * This structure contains private callbacks designed to only be used internally
528 * by the hardware core.
529 *
530 * @init_cal_settings: setup types of calibrations supported
531 * @init_cal: starts actual calibration
532 *
533 * @init_mode_regs: Initializes mode registers
534 * @init_mode_gain_regs: Initialize TX/RX gain registers
535 *
536 * @rf_set_freq: change frequency
537 * @spur_mitigate_freq: spur mitigation
538 * @rf_alloc_ext_banks:
539 * @rf_free_ext_banks:
540 * @set_rf_regs:
541 * @compute_pll_control: compute the PLL control value to use for
542 * AR_RTC_PLL_CONTROL for a given channel
543 * @setup_calibration: set up calibration
544 * @iscal_supported: used to query if a type of calibration is supported
545 *
546 * @ani_cache_ini_regs: cache the values for ANI from the initial
547 * register settings through the register initialization.
548 */
549struct ath_hw_private_ops {
550 /* Calibration ops */
551 void (*init_cal_settings)(struct ath_hw *ah);
552 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
553
554 void (*init_mode_regs)(struct ath_hw *ah);
555 void (*init_mode_gain_regs)(struct ath_hw *ah);
556 void (*setup_calibration)(struct ath_hw *ah,
557 struct ath9k_cal_list *currCal);
558
559 /* PHY ops */
560 int (*rf_set_freq)(struct ath_hw *ah,
561 struct ath9k_channel *chan);
562 void (*spur_mitigate_freq)(struct ath_hw *ah,
563 struct ath9k_channel *chan);
564 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
565 void (*rf_free_ext_banks)(struct ath_hw *ah);
566 bool (*set_rf_regs)(struct ath_hw *ah,
567 struct ath9k_channel *chan,
568 u16 modesIndex);
569 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
570 void (*init_bb)(struct ath_hw *ah,
571 struct ath9k_channel *chan);
572 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
573 void (*olc_init)(struct ath_hw *ah);
574 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
575 void (*mark_phy_inactive)(struct ath_hw *ah);
576 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
577 bool (*rfbus_req)(struct ath_hw *ah);
578 void (*rfbus_done)(struct ath_hw *ah);
579 void (*restore_chainmask)(struct ath_hw *ah);
580 void (*set_diversity)(struct ath_hw *ah, bool value);
581 u32 (*compute_pll_control)(struct ath_hw *ah,
582 struct ath9k_channel *chan);
583 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
584 int param);
585 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
586 void (*set_radar_params)(struct ath_hw *ah,
587 struct ath_hw_radar_conf *conf);
588
589 /* ANI */
590 void (*ani_cache_ini_regs)(struct ath_hw *ah);
591};
592
593/**
594 * struct ath_hw_ops - callbacks used by hardware code and driver code
595 *
596 * This structure contains callbacks designed to to be used internally by
597 * hardware code and also by the lower level driver.
598 *
599 * @config_pci_powersave:
600 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
601 */
602struct ath_hw_ops {
603 void (*config_pci_powersave)(struct ath_hw *ah,
604 int restore,
605 int power_off);
606 void (*rx_enable)(struct ath_hw *ah);
607 void (*set_desc_link)(void *ds, u32 link);
608 bool (*calibrate)(struct ath_hw *ah,
609 struct ath9k_channel *chan,
610 u8 rxchainmask,
611 bool longcal);
612 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
613 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
614 bool is_firstseg, bool is_is_lastseg,
615 const void *ds0, dma_addr_t buf_addr,
616 unsigned int qcu);
617 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
618 struct ath_tx_status *ts);
619 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
620 u32 pktLen, enum ath9k_pkt_type type,
621 u32 txPower, u32 keyIx,
622 enum ath9k_key_type keyType,
623 u32 flags);
624 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
625 void *lastds,
626 u32 durUpdateEn, u32 rtsctsRate,
627 u32 rtsctsDuration,
628 struct ath9k_11n_rate_series series[],
629 u32 nseries, u32 flags);
630 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
631 u32 aggrLen);
632 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
633 u32 numDelims);
634 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
635 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
636 void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
637 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
638 struct ath_hw_antcomb_conf *antconf);
639 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
640 struct ath_hw_antcomb_conf *antconf);
641
642};
643
644struct ath_nf_limits {
645 s16 max;
646 s16 min;
647 s16 nominal;
648};
649
650/* ah_flags */
651#define AH_USE_EEPROM 0x1
652#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
653
654struct ath_hw {
655 struct ath_ops reg_ops;
656
657 struct ieee80211_hw *hw;
658 struct ath_common common;
659 struct ath9k_hw_version hw_version;
660 struct ath9k_ops_config config;
661 struct ath9k_hw_capabilities caps;
662 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
663 struct ath9k_channel *curchan;
664
665 union {
666 struct ar5416_eeprom_def def;
667 struct ar5416_eeprom_4k map4k;
668 struct ar9287_eeprom map9287;
669 struct ar9300_eeprom ar9300_eep;
670 } eeprom;
671 const struct eeprom_ops *eep_ops;
672
673 bool sw_mgmt_crypto;
674 bool is_pciexpress;
675 bool aspm_enabled;
676 bool is_monitoring;
677 bool need_an_top2_fixup;
678 u16 tx_trig_level;
679
680 u32 nf_regs[6];
681 struct ath_nf_limits nf_2g;
682 struct ath_nf_limits nf_5g;
683 u16 rfsilent;
684 u32 rfkill_gpio;
685 u32 rfkill_polarity;
686 u32 ah_flags;
687
688 bool htc_reset_init;
689
690 enum nl80211_iftype opmode;
691 enum ath9k_power_mode power_mode;
692
693 struct ath9k_hw_cal_data *caldata;
694 struct ath9k_pacal_info pacal_info;
695 struct ar5416Stats stats;
696 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
697
698 int16_t curchan_rad_index;
699 enum ath9k_int imask;
700 u32 imrs2_reg;
701 u32 txok_interrupt_mask;
702 u32 txerr_interrupt_mask;
703 u32 txdesc_interrupt_mask;
704 u32 txeol_interrupt_mask;
705 u32 txurn_interrupt_mask;
706 bool chip_fullsleep;
707 u32 atim_window;
708
709 /* Calibration */
710 u32 supp_cals;
711 struct ath9k_cal_list iq_caldata;
712 struct ath9k_cal_list adcgain_caldata;
713 struct ath9k_cal_list adcdc_caldata;
714 struct ath9k_cal_list tempCompCalData;
715 struct ath9k_cal_list *cal_list;
716 struct ath9k_cal_list *cal_list_last;
717 struct ath9k_cal_list *cal_list_curr;
718#define totalPowerMeasI meas0.unsign
719#define totalPowerMeasQ meas1.unsign
720#define totalIqCorrMeas meas2.sign
721#define totalAdcIOddPhase meas0.unsign
722#define totalAdcIEvenPhase meas1.unsign
723#define totalAdcQOddPhase meas2.unsign
724#define totalAdcQEvenPhase meas3.unsign
725#define totalAdcDcOffsetIOddPhase meas0.sign
726#define totalAdcDcOffsetIEvenPhase meas1.sign
727#define totalAdcDcOffsetQOddPhase meas2.sign
728#define totalAdcDcOffsetQEvenPhase meas3.sign
729 union {
730 u32 unsign[AR5416_MAX_CHAINS];
731 int32_t sign[AR5416_MAX_CHAINS];
732 } meas0;
733 union {
734 u32 unsign[AR5416_MAX_CHAINS];
735 int32_t sign[AR5416_MAX_CHAINS];
736 } meas1;
737 union {
738 u32 unsign[AR5416_MAX_CHAINS];
739 int32_t sign[AR5416_MAX_CHAINS];
740 } meas2;
741 union {
742 u32 unsign[AR5416_MAX_CHAINS];
743 int32_t sign[AR5416_MAX_CHAINS];
744 } meas3;
745 u16 cal_samples;
746
747 u32 sta_id1_defaults;
748 u32 misc_mode;
749 enum {
750 AUTO_32KHZ,
751 USE_32KHZ,
752 DONT_USE_32KHZ,
753 } enable_32kHz_clock;
754
755 /* Private to hardware code */
756 struct ath_hw_private_ops private_ops;
757 /* Accessed by the lower level driver */
758 struct ath_hw_ops ops;
759
760 /* Used to program the radio on non single-chip devices */
761 u32 *analogBank0Data;
762 u32 *analogBank1Data;
763 u32 *analogBank2Data;
764 u32 *analogBank3Data;
765 u32 *analogBank6Data;
766 u32 *analogBank6TPCData;
767 u32 *analogBank7Data;
768 u32 *addac5416_21;
769 u32 *bank6Temp;
770
771 u8 txpower_limit;
772 int coverage_class;
773 u32 slottime;
774 u32 globaltxtimeout;
775
776 /* ANI */
777 u32 proc_phyerr;
778 u32 aniperiod;
779 int totalSizeDesired[5];
780 int coarse_high[5];
781 int coarse_low[5];
782 int firpwr[5];
783 enum ath9k_ani_cmd ani_function;
784
785 /* Bluetooth coexistance */
786 struct ath_btcoex_hw btcoex_hw;
787 u32 bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS];
788 u32 bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS];
789
790 u32 intr_txqs;
791 u8 txchainmask;
792 u8 rxchainmask;
793
794 struct ath_hw_radar_conf radar_conf;
795
796 u32 originalGain[22];
797 int initPDADC;
798 int PDADCdelta;
799 int led_pin;
800 u32 gpio_mask;
801 u32 gpio_val;
802
803 struct ar5416IniArray iniModes;
804 struct ar5416IniArray iniCommon;
805 struct ar5416IniArray iniBank0;
806 struct ar5416IniArray iniBB_RfGain;
807 struct ar5416IniArray iniBank1;
808 struct ar5416IniArray iniBank2;
809 struct ar5416IniArray iniBank3;
810 struct ar5416IniArray iniBank6;
811 struct ar5416IniArray iniBank6TPC;
812 struct ar5416IniArray iniBank7;
813 struct ar5416IniArray iniAddac;
814 struct ar5416IniArray iniPcieSerdes;
815 struct ar5416IniArray iniPcieSerdesLowPower;
816 struct ar5416IniArray iniModesAdditional;
817 struct ar5416IniArray iniModesAdditional_40M;
818 struct ar5416IniArray iniModesRxGain;
819 struct ar5416IniArray iniModesTxGain;
820 struct ar5416IniArray iniModes_9271_1_0_only;
821 struct ar5416IniArray iniCckfirNormal;
822 struct ar5416IniArray iniCckfirJapan2484;
823 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
824 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
825 struct ar5416IniArray iniModes_9271_ANI_reg;
826 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
827 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
828
829 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
830 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
831 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
832 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
833
834 u32 intr_gen_timer_trigger;
835 u32 intr_gen_timer_thresh;
836 struct ath_gen_timer_table hw_gen_timers;
837
838 struct ar9003_txs *ts_ring;
839 void *ts_start;
840 u32 ts_paddr_start;
841 u32 ts_paddr_end;
842 u16 ts_tail;
843 u8 ts_size;
844
845 u32 bb_watchdog_last_status;
846 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
847 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
848
849 unsigned int paprd_target_power;
850 unsigned int paprd_training_power;
851 unsigned int paprd_ratemask;
852 unsigned int paprd_ratemask_ht40;
853 bool paprd_table_write_done;
854 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
855 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
856 /*
857 * Store the permanent value of Reg 0x4004in WARegVal
858 * so we dont have to R/M/W. We should not be reading
859 * this register when in sleep states.
860 */
861 u32 WARegVal;
862
863 /* Enterprise mode cap */
864 u32 ent_mode;
865
866 bool is_clk_25mhz;
867 int (*get_mac_revision)(void);
868 int (*external_reset)(void);
869};
870
871struct ath_bus_ops {
872 enum ath_bus_type ath_bus_type;
873 void (*read_cachesize)(struct ath_common *common, int *csz);
874 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
875 void (*bt_coex_prep)(struct ath_common *common);
876 void (*extn_synch_en)(struct ath_common *common);
877 void (*aspm_init)(struct ath_common *common);
878};
879
880static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
881{
882 return &ah->common;
883}
884
885static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
886{
887 return &(ath9k_hw_common(ah)->regulatory);
888}
889
890static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
891{
892 return &ah->private_ops;
893}
894
895static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
896{
897 return &ah->ops;
898}
899
900static inline u8 get_streams(int mask)
901{
902 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
903}
904
905/* Initialization, Detach, Reset */
906const char *ath9k_hw_probe(u16 vendorid, u16 devid);
907void ath9k_hw_deinit(struct ath_hw *ah);
908int ath9k_hw_init(struct ath_hw *ah);
909int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
910 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
911int ath9k_hw_fill_cap_info(struct ath_hw *ah);
912u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
913
914/* GPIO / RFKILL / Antennae */
915void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
916u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
917void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
918 u32 ah_signal_type);
919void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
920u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
921void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
922
923/* General Operation */
924bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
925void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
926 int column, unsigned int *writecnt);
927u32 ath9k_hw_reverse_bits(u32 val, u32 n);
928u16 ath9k_hw_computetxtime(struct ath_hw *ah,
929 u8 phy, int kbps,
930 u32 frameLen, u16 rateix, bool shortPreamble);
931void ath9k_hw_get_channel_centers(struct ath_hw *ah,
932 struct ath9k_channel *chan,
933 struct chan_centers *centers);
934u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
935void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
936bool ath9k_hw_phy_disable(struct ath_hw *ah);
937bool ath9k_hw_disable(struct ath_hw *ah);
938void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
939void ath9k_hw_setopmode(struct ath_hw *ah);
940void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
941void ath9k_hw_setbssidmask(struct ath_hw *ah);
942void ath9k_hw_write_associd(struct ath_hw *ah);
943u32 ath9k_hw_gettsf32(struct ath_hw *ah);
944u64 ath9k_hw_gettsf64(struct ath_hw *ah);
945void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
946void ath9k_hw_reset_tsf(struct ath_hw *ah);
947void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
948void ath9k_hw_init_global_settings(struct ath_hw *ah);
949u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
950void ath9k_hw_set11nmac2040(struct ath_hw *ah);
951void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
952void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
953 const struct ath9k_beacon_state *bs);
954bool ath9k_hw_check_alive(struct ath_hw *ah);
955
956bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
957
958/* Generic hw timer primitives */
959struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
960 void (*trigger)(void *),
961 void (*overflow)(void *),
962 void *arg,
963 u8 timer_index);
964void ath9k_hw_gen_timer_start(struct ath_hw *ah,
965 struct ath_gen_timer *timer,
966 u32 timer_next,
967 u32 timer_period);
968void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
969
970void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
971void ath_gen_timer_isr(struct ath_hw *hw);
972
973void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
974
975/* HTC */
976void ath9k_hw_htc_resetinit(struct ath_hw *ah);
977
978/* PHY */
979void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
980 u32 *coef_mantissa, u32 *coef_exponent);
981
982/*
983 * Code Specific to AR5008, AR9001 or AR9002,
984 * we stuff these here to avoid callbacks for AR9003.
985 */
986void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
987int ar9002_hw_rf_claim(struct ath_hw *ah);
988void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
989
990/*
991 * Code specific to AR9003, we stuff these here to avoid callbacks
992 * for older families
993 */
994void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
995void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
996void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
997void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
998void ar9003_paprd_enable(struct ath_hw *ah, bool val);
999void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1000 struct ath9k_hw_cal_data *caldata,
1001 int chain);
1002int ar9003_paprd_create_curve(struct ath_hw *ah,
1003 struct ath9k_hw_cal_data *caldata, int chain);
1004int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1005int ar9003_paprd_init_table(struct ath_hw *ah);
1006bool ar9003_paprd_is_done(struct ath_hw *ah);
1007void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
1008
1009/* Hardware family op attach helpers */
1010void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1011void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1012void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1013
1014void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1015void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1016
1017void ar9002_hw_attach_ops(struct ath_hw *ah);
1018void ar9003_hw_attach_ops(struct ath_hw *ah);
1019
1020void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1021/*
1022 * ANI work can be shared between all families but a next
1023 * generation implementation of ANI will be used only for AR9003 only
1024 * for now as the other families still need to be tested with the same
1025 * next generation ANI. Feel free to start testing it though for the
1026 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1027 */
1028extern int modparam_force_new_ani;
1029void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1030void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1031void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1032
1033#define ATH_PCIE_CAP_LINK_CTRL 0x70
1034#define ATH_PCIE_CAP_LINK_L0S 1
1035#define ATH_PCIE_CAP_LINK_L1 2
1036
1037#define ATH9K_CLOCK_RATE_CCK 22
1038#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1039#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1040#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1041
1042#endif
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/firmware.h>
24
25#include "mac.h"
26#include "ani.h"
27#include "eeprom.h"
28#include "calib.h"
29#include "reg.h"
30#include "reg_mci.h"
31#include "phy.h"
32#include "btcoex.h"
33#include "dynack.h"
34
35#include "../regd.h"
36
37#define ATHEROS_VENDOR_ID 0x168c
38
39#define AR5416_DEVID_PCI 0x0023
40#define AR5416_DEVID_PCIE 0x0024
41#define AR9160_DEVID_PCI 0x0027
42#define AR9280_DEVID_PCI 0x0029
43#define AR9280_DEVID_PCIE 0x002a
44#define AR9285_DEVID_PCIE 0x002b
45#define AR2427_DEVID_PCIE 0x002c
46#define AR9287_DEVID_PCI 0x002d
47#define AR9287_DEVID_PCIE 0x002e
48#define AR9300_DEVID_PCIE 0x0030
49#define AR9300_DEVID_AR9340 0x0031
50#define AR9300_DEVID_AR9485_PCIE 0x0032
51#define AR9300_DEVID_AR9580 0x0033
52#define AR9300_DEVID_AR9462 0x0034
53#define AR9300_DEVID_AR9330 0x0035
54#define AR9300_DEVID_QCA955X 0x0038
55#define AR9485_DEVID_AR1111 0x0037
56#define AR9300_DEVID_AR9565 0x0036
57#define AR9300_DEVID_AR953X 0x003d
58#define AR9300_DEVID_QCA956X 0x003f
59
60#define AR5416_AR9100_DEVID 0x000b
61
62#define AR_SUBVENDOR_ID_NOG 0x0e11
63#define AR_SUBVENDOR_ID_NEW_A 0x7065
64#define AR5416_MAGIC 0x19641014
65
66#define AR9280_COEX2WIRE_SUBSYSID 0x309b
67#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
68#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
69
70#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
71
72#define ATH_DEFAULT_NOISE_FLOOR -95
73
74#define ATH9K_RSSI_BAD -128
75
76#define ATH9K_NUM_CHANNELS 38
77
78/* Register read/write primitives */
79#define REG_WRITE(_ah, _reg, _val) \
80 (_ah)->reg_ops.write((_ah), (_val), (_reg))
81
82#define REG_READ(_ah, _reg) \
83 (_ah)->reg_ops.read((_ah), (_reg))
84
85#define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
86 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
87
88#define REG_RMW(_ah, _reg, _set, _clr) \
89 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
90
91#define ENABLE_REGWRITE_BUFFER(_ah) \
92 do { \
93 if ((_ah)->reg_ops.enable_write_buffer) \
94 (_ah)->reg_ops.enable_write_buffer((_ah)); \
95 } while (0)
96
97#define REGWRITE_BUFFER_FLUSH(_ah) \
98 do { \
99 if ((_ah)->reg_ops.write_flush) \
100 (_ah)->reg_ops.write_flush((_ah)); \
101 } while (0)
102
103#define ENABLE_REG_RMW_BUFFER(_ah) \
104 do { \
105 if ((_ah)->reg_ops.enable_rmw_buffer) \
106 (_ah)->reg_ops.enable_rmw_buffer((_ah)); \
107 } while (0)
108
109#define REG_RMW_BUFFER_FLUSH(_ah) \
110 do { \
111 if ((_ah)->reg_ops.rmw_flush) \
112 (_ah)->reg_ops.rmw_flush((_ah)); \
113 } while (0)
114
115#define PR_EEP(_s, _val) \
116 do { \
117 len += scnprintf(buf + len, size - len, "%20s : %10d\n",\
118 _s, (_val)); \
119 } while (0)
120
121#define SM(_v, _f) (((_v) << _f##_S) & _f)
122#define MS(_v, _f) (((_v) & _f) >> _f##_S)
123#define REG_RMW_FIELD(_a, _r, _f, _v) \
124 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
125#define REG_READ_FIELD(_a, _r, _f) \
126 (((REG_READ(_a, _r) & _f) >> _f##_S))
127#define REG_SET_BIT(_a, _r, _f) \
128 REG_RMW(_a, _r, (_f), 0)
129#define REG_CLR_BIT(_a, _r, _f) \
130 REG_RMW(_a, _r, 0, (_f))
131
132#define DO_DELAY(x) do { \
133 if (((++(x) % 64) == 0) && \
134 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
135 != ATH_USB)) \
136 udelay(1); \
137 } while (0)
138
139#define REG_WRITE_ARRAY(iniarray, column, regWr) \
140 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
141#define REG_READ_ARRAY(ah, array, size) \
142 ath9k_hw_read_array(ah, array, size)
143
144#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
145#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
146#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
147#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
148#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
149#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
150#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
151#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
152#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
153#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
154#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
155#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
156#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
157#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
158#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
159#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
160#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
161
162#define AR_GPIOD_MASK 0x00001FFF
163
164#define BASE_ACTIVATE_DELAY 100
165#define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
166#define COEF_SCALE_S 24
167#define HT40_CHANNEL_CENTER_SHIFT 10
168
169#define ATH9K_ANTENNA0_CHAINMASK 0x1
170#define ATH9K_ANTENNA1_CHAINMASK 0x2
171
172#define ATH9K_NUM_DMA_DEBUG_REGS 8
173#define ATH9K_NUM_QUEUES 10
174
175#define MAX_RATE_POWER 63
176#define AH_WAIT_TIMEOUT 100000 /* (us) */
177#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
178#define AH_TIME_QUANTUM 10
179#define AR_KEYTABLE_SIZE 128
180#define POWER_UP_TIME 10000
181#define SPUR_RSSI_THRESH 40
182#define UPPER_5G_SUB_BAND_START 5700
183#define MID_5G_SUB_BAND_START 5400
184
185#define CAB_TIMEOUT_VAL 10
186#define BEACON_TIMEOUT_VAL 10
187#define MIN_BEACON_TIMEOUT_VAL 1
188#define SLEEP_SLOP TU_TO_USEC(3)
189
190#define INIT_CONFIG_STATUS 0x00000000
191#define INIT_RSSI_THR 0x00000700
192#define INIT_BCON_CNTRL_REG 0x00000000
193
194#define TU_TO_USEC(_tu) ((_tu) << 10)
195
196#define ATH9K_HW_RX_HP_QDEPTH 16
197#define ATH9K_HW_RX_LP_QDEPTH 128
198
199#define PAPRD_GAIN_TABLE_ENTRIES 32
200#define PAPRD_TABLE_SZ 24
201#define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
202
203/*
204 * Wake on Wireless
205 */
206
207/* Keep Alive Frame */
208#define KAL_FRAME_LEN 28
209#define KAL_FRAME_TYPE 0x2 /* data frame */
210#define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */
211#define KAL_DURATION_ID 0x3d
212#define KAL_NUM_DATA_WORDS 6
213#define KAL_NUM_DESC_WORDS 12
214#define KAL_ANTENNA_MODE 1
215#define KAL_TO_DS 1
216#define KAL_DELAY 4 /* delay of 4ms between 2 KAL frames */
217#define KAL_TIMEOUT 900
218
219#define MAX_PATTERN_SIZE 256
220#define MAX_PATTERN_MASK_SIZE 32
221#define MAX_NUM_PATTERN 16
222#define MAX_NUM_PATTERN_LEGACY 8
223#define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and
224 deauthenticate packets */
225
226/*
227 * WoW trigger mapping to hardware code
228 */
229
230#define AH_WOW_USER_PATTERN_EN BIT(0)
231#define AH_WOW_MAGIC_PATTERN_EN BIT(1)
232#define AH_WOW_LINK_CHANGE BIT(2)
233#define AH_WOW_BEACON_MISS BIT(3)
234
235enum ath_hw_txq_subtype {
236 ATH_TXQ_AC_BK = 0,
237 ATH_TXQ_AC_BE = 1,
238 ATH_TXQ_AC_VI = 2,
239 ATH_TXQ_AC_VO = 3,
240};
241
242enum ath_ini_subsys {
243 ATH_INI_PRE = 0,
244 ATH_INI_CORE,
245 ATH_INI_POST,
246 ATH_INI_NUM_SPLIT,
247};
248
249enum ath9k_hw_caps {
250 ATH9K_HW_CAP_HT = BIT(0),
251 ATH9K_HW_CAP_RFSILENT = BIT(1),
252 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
253 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
254 ATH9K_HW_CAP_EDMA = BIT(4),
255 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
256 ATH9K_HW_CAP_LDPC = BIT(6),
257 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
258 ATH9K_HW_CAP_SGI_20 = BIT(8),
259 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
260 ATH9K_HW_CAP_2GHZ = BIT(11),
261 ATH9K_HW_CAP_5GHZ = BIT(12),
262 ATH9K_HW_CAP_APM = BIT(13),
263#ifdef CONFIG_ATH9K_PCOEM
264 ATH9K_HW_CAP_RTT = BIT(14),
265 ATH9K_HW_CAP_MCI = BIT(15),
266 ATH9K_HW_CAP_BT_ANT_DIV = BIT(17),
267#else
268 ATH9K_HW_CAP_RTT = 0,
269 ATH9K_HW_CAP_MCI = 0,
270 ATH9K_HW_CAP_BT_ANT_DIV = 0,
271#endif
272 ATH9K_HW_CAP_DFS = BIT(18),
273 ATH9K_HW_CAP_PAPRD = BIT(19),
274 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(20),
275};
276
277/*
278 * WoW device capabilities
279 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
280 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
281 * an exact user defined pattern or de-authentication/disassoc pattern.
282 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
283 * bytes of the pattern for user defined pattern, de-authentication and
284 * disassociation patterns for all types of possible frames recieved
285 * of those types.
286 */
287
288struct ath9k_hw_wow {
289 u32 wow_event_mask;
290 u32 wow_event_mask2;
291 u8 max_patterns;
292};
293
294struct ath9k_hw_capabilities {
295 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
296 u16 rts_aggr_limit;
297 u8 tx_chainmask;
298 u8 rx_chainmask;
299 u8 chip_chainmask;
300 u8 max_txchains;
301 u8 max_rxchains;
302 u8 num_gpio_pins;
303 u32 gpio_mask;
304 u32 gpio_requested;
305 u8 rx_hp_qdepth;
306 u8 rx_lp_qdepth;
307 u8 rx_status_len;
308 u8 tx_desc_len;
309 u8 txs_len;
310};
311
312#define AR_NO_SPUR 0x8000
313#define AR_BASE_FREQ_2GHZ 2300
314#define AR_BASE_FREQ_5GHZ 4900
315#define AR_SPUR_FEEQ_BOUND_HT40 19
316#define AR_SPUR_FEEQ_BOUND_HT20 10
317
318enum ath9k_hw_hang_checks {
319 HW_BB_WATCHDOG = BIT(0),
320 HW_PHYRESTART_CLC_WAR = BIT(1),
321 HW_BB_RIFS_HANG = BIT(2),
322 HW_BB_DFS_HANG = BIT(3),
323 HW_BB_RX_CLEAR_STUCK_HANG = BIT(4),
324 HW_MAC_HANG = BIT(5),
325};
326
327#define AR_PCIE_PLL_PWRSAVE_CONTROL BIT(0)
328#define AR_PCIE_PLL_PWRSAVE_ON_D3 BIT(1)
329#define AR_PCIE_PLL_PWRSAVE_ON_D0 BIT(2)
330#define AR_PCIE_CDR_PWRSAVE_ON_D3 BIT(3)
331#define AR_PCIE_CDR_PWRSAVE_ON_D0 BIT(4)
332
333struct ath9k_ops_config {
334 int dma_beacon_response_time;
335 int sw_beacon_response_time;
336 bool cwm_ignore_extcca;
337 u32 pcie_waen;
338 u8 analog_shiftreg;
339 u32 ofdm_trig_low;
340 u32 ofdm_trig_high;
341 u32 cck_trig_high;
342 u32 cck_trig_low;
343 bool enable_paprd;
344 int serialize_regmode;
345 bool rx_intr_mitigation;
346 bool tx_intr_mitigation;
347 u8 max_txtrig_level;
348 u16 ani_poll_interval; /* ANI poll interval in ms */
349 u16 hw_hang_checks;
350 u16 rimt_first;
351 u16 rimt_last;
352
353 /* Platform specific config */
354 u32 aspm_l1_fix;
355 u32 xlna_gpio;
356 u32 ant_ctrl_comm2g_switch_enable;
357 bool xatten_margin_cfg;
358 bool alt_mingainidx;
359 u8 pll_pwrsave;
360 bool tx_gain_buffalo;
361 bool led_active_high;
362};
363
364enum ath9k_int {
365 ATH9K_INT_RX = 0x00000001,
366 ATH9K_INT_RXDESC = 0x00000002,
367 ATH9K_INT_RXHP = 0x00000001,
368 ATH9K_INT_RXLP = 0x00000002,
369 ATH9K_INT_RXNOFRM = 0x00000008,
370 ATH9K_INT_RXEOL = 0x00000010,
371 ATH9K_INT_RXORN = 0x00000020,
372 ATH9K_INT_TX = 0x00000040,
373 ATH9K_INT_TXDESC = 0x00000080,
374 ATH9K_INT_TIM_TIMER = 0x00000100,
375 ATH9K_INT_MCI = 0x00000200,
376 ATH9K_INT_BB_WATCHDOG = 0x00000400,
377 ATH9K_INT_TXURN = 0x00000800,
378 ATH9K_INT_MIB = 0x00001000,
379 ATH9K_INT_RXPHY = 0x00004000,
380 ATH9K_INT_RXKCM = 0x00008000,
381 ATH9K_INT_SWBA = 0x00010000,
382 ATH9K_INT_BMISS = 0x00040000,
383 ATH9K_INT_BNR = 0x00100000,
384 ATH9K_INT_TIM = 0x00200000,
385 ATH9K_INT_DTIM = 0x00400000,
386 ATH9K_INT_DTIMSYNC = 0x00800000,
387 ATH9K_INT_GPIO = 0x01000000,
388 ATH9K_INT_CABEND = 0x02000000,
389 ATH9K_INT_TSFOOR = 0x04000000,
390 ATH9K_INT_GENTIMER = 0x08000000,
391 ATH9K_INT_CST = 0x10000000,
392 ATH9K_INT_GTT = 0x20000000,
393 ATH9K_INT_FATAL = 0x40000000,
394 ATH9K_INT_GLOBAL = 0x80000000,
395 ATH9K_INT_BMISC = ATH9K_INT_TIM |
396 ATH9K_INT_DTIM |
397 ATH9K_INT_DTIMSYNC |
398 ATH9K_INT_TSFOOR |
399 ATH9K_INT_CABEND,
400 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
401 ATH9K_INT_RXDESC |
402 ATH9K_INT_RXEOL |
403 ATH9K_INT_RXORN |
404 ATH9K_INT_TXURN |
405 ATH9K_INT_TXDESC |
406 ATH9K_INT_MIB |
407 ATH9K_INT_RXPHY |
408 ATH9K_INT_RXKCM |
409 ATH9K_INT_SWBA |
410 ATH9K_INT_BMISS |
411 ATH9K_INT_GPIO,
412 ATH9K_INT_NOCARD = 0xffffffff
413};
414
415#define MAX_RTT_TABLE_ENTRY 6
416#define MAX_IQCAL_MEASUREMENT 8
417#define MAX_CL_TAB_ENTRY 16
418#define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
419
420enum ath9k_cal_flags {
421 RTT_DONE,
422 PAPRD_PACKET_SENT,
423 PAPRD_DONE,
424 NFCAL_PENDING,
425 NFCAL_INTF,
426 TXIQCAL_DONE,
427 TXCLCAL_DONE,
428 SW_PKDET_DONE,
429};
430
431struct ath9k_hw_cal_data {
432 u16 channel;
433 u16 channelFlags;
434 unsigned long cal_flags;
435 int32_t CalValid;
436 int8_t iCoff;
437 int8_t qCoff;
438 u8 caldac[2];
439 u16 small_signal_gain[AR9300_MAX_CHAINS];
440 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
441 u32 num_measures[AR9300_MAX_CHAINS];
442 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
443 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
444 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY];
445 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
446};
447
448struct ath9k_channel {
449 struct ieee80211_channel *chan;
450 u16 channel;
451 u16 channelFlags;
452 s16 noisefloor;
453};
454
455#define CHANNEL_5GHZ BIT(0)
456#define CHANNEL_HALF BIT(1)
457#define CHANNEL_QUARTER BIT(2)
458#define CHANNEL_HT BIT(3)
459#define CHANNEL_HT40PLUS BIT(4)
460#define CHANNEL_HT40MINUS BIT(5)
461
462#define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ))
463#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
464
465#define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF))
466#define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER))
467#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
468 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
469
470#define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT)
471
472#define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c))
473
474#define IS_CHAN_HT40(_c) \
475 (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)))
476
477#define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS)
478#define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS)
479
480enum ath9k_power_mode {
481 ATH9K_PM_AWAKE = 0,
482 ATH9K_PM_FULL_SLEEP,
483 ATH9K_PM_NETWORK_SLEEP,
484 ATH9K_PM_UNDEFINED
485};
486
487enum ser_reg_mode {
488 SER_REG_MODE_OFF = 0,
489 SER_REG_MODE_ON = 1,
490 SER_REG_MODE_AUTO = 2,
491};
492
493enum ath9k_rx_qtype {
494 ATH9K_RX_QUEUE_HP,
495 ATH9K_RX_QUEUE_LP,
496 ATH9K_RX_QUEUE_MAX,
497};
498
499struct ath9k_beacon_state {
500 u32 bs_nexttbtt;
501 u32 bs_nextdtim;
502 u32 bs_intval;
503#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
504 u32 bs_dtimperiod;
505 u16 bs_bmissthreshold;
506 u32 bs_sleepduration;
507 u32 bs_tsfoor_threshold;
508};
509
510struct chan_centers {
511 u16 synth_center;
512 u16 ctl_center;
513 u16 ext_center;
514};
515
516enum {
517 ATH9K_RESET_POWER_ON,
518 ATH9K_RESET_WARM,
519 ATH9K_RESET_COLD,
520};
521
522struct ath9k_hw_version {
523 u32 magic;
524 u16 devid;
525 u16 subvendorid;
526 u32 macVersion;
527 u16 macRev;
528 u16 phyRev;
529 u16 analog5GhzRev;
530 u16 analog2GhzRev;
531 enum ath_usb_dev usbdev;
532};
533
534/* Generic TSF timer definitions */
535
536#define ATH_MAX_GEN_TIMER 16
537
538#define AR_GENTMR_BIT(_index) (1 << (_index))
539
540struct ath_gen_timer_configuration {
541 u32 next_addr;
542 u32 period_addr;
543 u32 mode_addr;
544 u32 mode_mask;
545};
546
547struct ath_gen_timer {
548 void (*trigger)(void *arg);
549 void (*overflow)(void *arg);
550 void *arg;
551 u8 index;
552};
553
554struct ath_gen_timer_table {
555 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
556 u16 timer_mask;
557 bool tsf2_enabled;
558};
559
560struct ath_hw_antcomb_conf {
561 u8 main_lna_conf;
562 u8 alt_lna_conf;
563 u8 fast_div_bias;
564 u8 main_gaintb;
565 u8 alt_gaintb;
566 int lna1_lna2_delta;
567 int lna1_lna2_switch_delta;
568 u8 div_group;
569};
570
571/**
572 * struct ath_hw_radar_conf - radar detection initialization parameters
573 *
574 * @pulse_inband: threshold for checking the ratio of in-band power
575 * to total power for short radar pulses (half dB steps)
576 * @pulse_inband_step: threshold for checking an in-band power to total
577 * power ratio increase for short radar pulses (half dB steps)
578 * @pulse_height: threshold for detecting the beginning of a short
579 * radar pulse (dB step)
580 * @pulse_rssi: threshold for detecting if a short radar pulse is
581 * gone (dB step)
582 * @pulse_maxlen: maximum pulse length (0.8 us steps)
583 *
584 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
585 * @radar_inband: threshold for checking the ratio of in-band power
586 * to total power for long radar pulses (half dB steps)
587 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
588 *
589 * @ext_channel: enable extension channel radar detection
590 */
591struct ath_hw_radar_conf {
592 unsigned int pulse_inband;
593 unsigned int pulse_inband_step;
594 unsigned int pulse_height;
595 unsigned int pulse_rssi;
596 unsigned int pulse_maxlen;
597
598 unsigned int radar_rssi;
599 unsigned int radar_inband;
600 int fir_power;
601
602 bool ext_channel;
603};
604
605/**
606 * struct ath_hw_private_ops - callbacks used internally by hardware code
607 *
608 * This structure contains private callbacks designed to only be used internally
609 * by the hardware core.
610 *
611 * @init_cal_settings: setup types of calibrations supported
612 * @init_cal: starts actual calibration
613 *
614 * @init_mode_gain_regs: Initialize TX/RX gain registers
615 *
616 * @rf_set_freq: change frequency
617 * @spur_mitigate_freq: spur mitigation
618 * @set_rf_regs:
619 * @compute_pll_control: compute the PLL control value to use for
620 * AR_RTC_PLL_CONTROL for a given channel
621 * @setup_calibration: set up calibration
622 * @iscal_supported: used to query if a type of calibration is supported
623 *
624 * @ani_cache_ini_regs: cache the values for ANI from the initial
625 * register settings through the register initialization.
626 */
627struct ath_hw_private_ops {
628 void (*init_hang_checks)(struct ath_hw *ah);
629 bool (*detect_mac_hang)(struct ath_hw *ah);
630 bool (*detect_bb_hang)(struct ath_hw *ah);
631
632 /* Calibration ops */
633 void (*init_cal_settings)(struct ath_hw *ah);
634 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
635
636 void (*init_mode_gain_regs)(struct ath_hw *ah);
637 void (*setup_calibration)(struct ath_hw *ah,
638 struct ath9k_cal_list *currCal);
639
640 /* PHY ops */
641 int (*rf_set_freq)(struct ath_hw *ah,
642 struct ath9k_channel *chan);
643 void (*spur_mitigate_freq)(struct ath_hw *ah,
644 struct ath9k_channel *chan);
645 bool (*set_rf_regs)(struct ath_hw *ah,
646 struct ath9k_channel *chan,
647 u16 modesIndex);
648 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
649 void (*init_bb)(struct ath_hw *ah,
650 struct ath9k_channel *chan);
651 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
652 void (*olc_init)(struct ath_hw *ah);
653 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
654 void (*mark_phy_inactive)(struct ath_hw *ah);
655 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
656 bool (*rfbus_req)(struct ath_hw *ah);
657 void (*rfbus_done)(struct ath_hw *ah);
658 void (*restore_chainmask)(struct ath_hw *ah);
659 u32 (*compute_pll_control)(struct ath_hw *ah,
660 struct ath9k_channel *chan);
661 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
662 int param);
663 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
664 void (*set_radar_params)(struct ath_hw *ah,
665 struct ath_hw_radar_conf *conf);
666 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
667 u8 *ini_reloaded);
668
669 /* ANI */
670 void (*ani_cache_ini_regs)(struct ath_hw *ah);
671
672#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
673 bool (*is_aic_enabled)(struct ath_hw *ah);
674#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
675};
676
677/**
678 * struct ath_spec_scan - parameters for Atheros spectral scan
679 *
680 * @enabled: enable/disable spectral scan
681 * @short_repeat: controls whether the chip is in spectral scan mode
682 * for 4 usec (enabled) or 204 usec (disabled)
683 * @count: number of scan results requested. There are special meanings
684 * in some chip revisions:
685 * AR92xx: highest bit set (>=128) for endless mode
686 * (spectral scan won't stopped until explicitly disabled)
687 * AR9300 and newer: 0 for endless mode
688 * @endless: true if endless mode is intended. Otherwise, count value is
689 * corrected to the next possible value.
690 * @period: time duration between successive spectral scan entry points
691 * (period*256*Tclk). Tclk = ath_common->clockrate
692 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS
693 *
694 * Note: Tclk = 40MHz or 44MHz depending upon operating mode.
695 * Typically it's 44MHz in 2/5GHz on later chips, but there's
696 * a "fast clock" check for this in 5GHz.
697 *
698 */
699struct ath_spec_scan {
700 bool enabled;
701 bool short_repeat;
702 bool endless;
703 u8 count;
704 u8 period;
705 u8 fft_period;
706};
707
708/**
709 * struct ath_hw_ops - callbacks used by hardware code and driver code
710 *
711 * This structure contains callbacks designed to to be used internally by
712 * hardware code and also by the lower level driver.
713 *
714 * @config_pci_powersave:
715 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
716 *
717 * @spectral_scan_config: set parameters for spectral scan and enable/disable it
718 * @spectral_scan_trigger: trigger a spectral scan run
719 * @spectral_scan_wait: wait for a spectral scan run to finish
720 */
721struct ath_hw_ops {
722 void (*config_pci_powersave)(struct ath_hw *ah,
723 bool power_off);
724 void (*rx_enable)(struct ath_hw *ah);
725 void (*set_desc_link)(void *ds, u32 link);
726 int (*calibrate)(struct ath_hw *ah, struct ath9k_channel *chan,
727 u8 rxchainmask, bool longcal);
728 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked,
729 u32 *sync_cause_p);
730 void (*set_txdesc)(struct ath_hw *ah, void *ds,
731 struct ath_tx_info *i);
732 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
733 struct ath_tx_status *ts);
734 int (*get_duration)(struct ath_hw *ah, const void *ds, int index);
735 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
736 struct ath_hw_antcomb_conf *antconf);
737 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
738 struct ath_hw_antcomb_conf *antconf);
739 void (*spectral_scan_config)(struct ath_hw *ah,
740 struct ath_spec_scan *param);
741 void (*spectral_scan_trigger)(struct ath_hw *ah);
742 void (*spectral_scan_wait)(struct ath_hw *ah);
743
744 void (*tx99_start)(struct ath_hw *ah, u32 qnum);
745 void (*tx99_stop)(struct ath_hw *ah);
746 void (*tx99_set_txpower)(struct ath_hw *ah, u8 power);
747
748#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
749 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable);
750#endif
751};
752
753struct ath_nf_limits {
754 s16 max;
755 s16 min;
756 s16 nominal;
757};
758
759enum ath_cal_list {
760 TX_IQ_CAL = BIT(0),
761 TX_IQ_ON_AGC_CAL = BIT(1),
762 TX_CL_CAL = BIT(2),
763};
764
765/* ah_flags */
766#define AH_USE_EEPROM 0x1
767#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
768#define AH_FASTCC 0x4
769#define AH_NO_EEP_SWAP 0x8 /* Do not swap EEPROM data */
770
771struct ath_hw {
772 struct ath_ops reg_ops;
773
774 struct device *dev;
775 struct ieee80211_hw *hw;
776 struct ath_common common;
777 struct ath9k_hw_version hw_version;
778 struct ath9k_ops_config config;
779 struct ath9k_hw_capabilities caps;
780 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
781 struct ath9k_channel *curchan;
782
783 union {
784 struct ar5416_eeprom_def def;
785 struct ar5416_eeprom_4k map4k;
786 struct ar9287_eeprom map9287;
787 struct ar9300_eeprom ar9300_eep;
788 } eeprom;
789 const struct eeprom_ops *eep_ops;
790
791 bool sw_mgmt_crypto_tx;
792 bool sw_mgmt_crypto_rx;
793 bool is_pciexpress;
794 bool aspm_enabled;
795 bool is_monitoring;
796 bool need_an_top2_fixup;
797 u16 tx_trig_level;
798
799 u32 nf_regs[6];
800 struct ath_nf_limits nf_2g;
801 struct ath_nf_limits nf_5g;
802 u16 rfsilent;
803 u32 rfkill_gpio;
804 u32 rfkill_polarity;
805 u32 ah_flags;
806
807 bool reset_power_on;
808 bool htc_reset_init;
809
810 enum nl80211_iftype opmode;
811 enum ath9k_power_mode power_mode;
812
813 s8 noise;
814 struct ath9k_hw_cal_data *caldata;
815 struct ath9k_pacal_info pacal_info;
816 struct ar5416Stats stats;
817 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
818
819 enum ath9k_int imask;
820 u32 imrs2_reg;
821 u32 txok_interrupt_mask;
822 u32 txerr_interrupt_mask;
823 u32 txdesc_interrupt_mask;
824 u32 txeol_interrupt_mask;
825 u32 txurn_interrupt_mask;
826 atomic_t intr_ref_cnt;
827 bool chip_fullsleep;
828 u32 modes_index;
829
830 /* Calibration */
831 u32 supp_cals;
832 struct ath9k_cal_list iq_caldata;
833 struct ath9k_cal_list adcgain_caldata;
834 struct ath9k_cal_list adcdc_caldata;
835 struct ath9k_cal_list *cal_list;
836 struct ath9k_cal_list *cal_list_last;
837 struct ath9k_cal_list *cal_list_curr;
838#define totalPowerMeasI meas0.unsign
839#define totalPowerMeasQ meas1.unsign
840#define totalIqCorrMeas meas2.sign
841#define totalAdcIOddPhase meas0.unsign
842#define totalAdcIEvenPhase meas1.unsign
843#define totalAdcQOddPhase meas2.unsign
844#define totalAdcQEvenPhase meas3.unsign
845#define totalAdcDcOffsetIOddPhase meas0.sign
846#define totalAdcDcOffsetIEvenPhase meas1.sign
847#define totalAdcDcOffsetQOddPhase meas2.sign
848#define totalAdcDcOffsetQEvenPhase meas3.sign
849 union {
850 u32 unsign[AR5416_MAX_CHAINS];
851 int32_t sign[AR5416_MAX_CHAINS];
852 } meas0;
853 union {
854 u32 unsign[AR5416_MAX_CHAINS];
855 int32_t sign[AR5416_MAX_CHAINS];
856 } meas1;
857 union {
858 u32 unsign[AR5416_MAX_CHAINS];
859 int32_t sign[AR5416_MAX_CHAINS];
860 } meas2;
861 union {
862 u32 unsign[AR5416_MAX_CHAINS];
863 int32_t sign[AR5416_MAX_CHAINS];
864 } meas3;
865 u16 cal_samples;
866 u8 enabled_cals;
867
868 u32 sta_id1_defaults;
869 u32 misc_mode;
870
871 /* Private to hardware code */
872 struct ath_hw_private_ops private_ops;
873 /* Accessed by the lower level driver */
874 struct ath_hw_ops ops;
875
876 /* Used to program the radio on non single-chip devices */
877 u32 *analogBank6Data;
878
879 int coverage_class;
880 u32 slottime;
881 u32 globaltxtimeout;
882
883 /* ANI */
884 u32 aniperiod;
885 enum ath9k_ani_cmd ani_function;
886 u32 ani_skip_count;
887 struct ar5416AniState ani;
888
889#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
890 struct ath_btcoex_hw btcoex_hw;
891#endif
892
893 u32 intr_txqs;
894 u8 txchainmask;
895 u8 rxchainmask;
896
897 struct ath_hw_radar_conf radar_conf;
898
899 u32 originalGain[22];
900 int initPDADC;
901 int PDADCdelta;
902 int led_pin;
903 u32 gpio_mask;
904 u32 gpio_val;
905
906 struct ar5416IniArray ini_dfs;
907 struct ar5416IniArray iniModes;
908 struct ar5416IniArray iniCommon;
909 struct ar5416IniArray iniBB_RfGain;
910 struct ar5416IniArray iniBank6;
911 struct ar5416IniArray iniAddac;
912 struct ar5416IniArray iniPcieSerdes;
913 struct ar5416IniArray iniPcieSerdesLowPower;
914 struct ar5416IniArray iniModesFastClock;
915 struct ar5416IniArray iniAdditional;
916 struct ar5416IniArray iniModesRxGain;
917 struct ar5416IniArray ini_modes_rx_gain_bounds;
918 struct ar5416IniArray iniModesTxGain;
919 struct ar5416IniArray iniCckfirNormal;
920 struct ar5416IniArray iniCckfirJapan2484;
921 struct ar5416IniArray iniModes_9271_ANI_reg;
922 struct ar5416IniArray ini_radio_post_sys2ant;
923 struct ar5416IniArray ini_modes_rxgain_xlna;
924 struct ar5416IniArray ini_modes_rxgain_bb_core;
925 struct ar5416IniArray ini_modes_rxgain_bb_postamble;
926
927 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
928 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
929 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
930 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
931
932 u32 intr_gen_timer_trigger;
933 u32 intr_gen_timer_thresh;
934 struct ath_gen_timer_table hw_gen_timers;
935
936 struct ar9003_txs *ts_ring;
937 u32 ts_paddr_start;
938 u32 ts_paddr_end;
939 u16 ts_tail;
940 u16 ts_size;
941
942 u32 bb_watchdog_last_status;
943 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
944 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
945
946 unsigned int paprd_target_power;
947 unsigned int paprd_training_power;
948 unsigned int paprd_ratemask;
949 unsigned int paprd_ratemask_ht40;
950 bool paprd_table_write_done;
951 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
952 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
953 /*
954 * Store the permanent value of Reg 0x4004in WARegVal
955 * so we dont have to R/M/W. We should not be reading
956 * this register when in sleep states.
957 */
958 u32 WARegVal;
959
960 /* Enterprise mode cap */
961 u32 ent_mode;
962
963#ifdef CONFIG_ATH9K_WOW
964 struct ath9k_hw_wow wow;
965#endif
966 bool is_clk_25mhz;
967 int (*get_mac_revision)(void);
968 int (*external_reset)(void);
969 bool disable_2ghz;
970 bool disable_5ghz;
971
972 const struct firmware *eeprom_blob;
973
974 struct ath_dynack dynack;
975
976 bool tpc_enabled;
977 u8 tx_power[Ar5416RateSize];
978 u8 tx_power_stbc[Ar5416RateSize];
979};
980
981struct ath_bus_ops {
982 enum ath_bus_type ath_bus_type;
983 void (*read_cachesize)(struct ath_common *common, int *csz);
984 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
985 void (*bt_coex_prep)(struct ath_common *common);
986 void (*aspm_init)(struct ath_common *common);
987};
988
989static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
990{
991 return &ah->common;
992}
993
994static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
995{
996 return &(ath9k_hw_common(ah)->regulatory);
997}
998
999static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
1000{
1001 return &ah->private_ops;
1002}
1003
1004static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
1005{
1006 return &ah->ops;
1007}
1008
1009static inline u8 get_streams(int mask)
1010{
1011 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
1012}
1013
1014/* Initialization, Detach, Reset */
1015void ath9k_hw_deinit(struct ath_hw *ah);
1016int ath9k_hw_init(struct ath_hw *ah);
1017int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1018 struct ath9k_hw_cal_data *caldata, bool fastcc);
1019int ath9k_hw_fill_cap_info(struct ath_hw *ah);
1020u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
1021
1022/* GPIO / RFKILL / Antennae */
1023void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label);
1024void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
1025 u32 ah_signal_type);
1026void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio);
1027u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
1028void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
1029void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
1030
1031/* General Operation */
1032void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
1033 int hw_delay);
1034bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
1035void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
1036 int column, unsigned int *writecnt);
1037void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size);
1038u32 ath9k_hw_reverse_bits(u32 val, u32 n);
1039u16 ath9k_hw_computetxtime(struct ath_hw *ah,
1040 u8 phy, int kbps,
1041 u32 frameLen, u16 rateix, bool shortPreamble);
1042void ath9k_hw_get_channel_centers(struct ath_hw *ah,
1043 struct ath9k_channel *chan,
1044 struct chan_centers *centers);
1045u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
1046void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
1047bool ath9k_hw_phy_disable(struct ath_hw *ah);
1048bool ath9k_hw_disable(struct ath_hw *ah);
1049void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
1050void ath9k_hw_setopmode(struct ath_hw *ah);
1051void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
1052void ath9k_hw_write_associd(struct ath_hw *ah);
1053u32 ath9k_hw_gettsf32(struct ath_hw *ah);
1054u64 ath9k_hw_gettsf64(struct ath_hw *ah);
1055void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
1056void ath9k_hw_reset_tsf(struct ath_hw *ah);
1057u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur);
1058void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
1059void ath9k_hw_init_global_settings(struct ath_hw *ah);
1060u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
1061void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan);
1062void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
1063void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1064 const struct ath9k_beacon_state *bs);
1065void ath9k_hw_check_nav(struct ath_hw *ah);
1066bool ath9k_hw_check_alive(struct ath_hw *ah);
1067
1068bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
1069
1070/* Generic hw timer primitives */
1071struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
1072 void (*trigger)(void *),
1073 void (*overflow)(void *),
1074 void *arg,
1075 u8 timer_index);
1076void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1077 struct ath_gen_timer *timer,
1078 u32 timer_next,
1079 u32 timer_period);
1080void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah);
1081void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
1082
1083void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
1084void ath_gen_timer_isr(struct ath_hw *hw);
1085
1086void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
1087
1088/* PHY */
1089void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1090 u32 *coef_mantissa, u32 *coef_exponent);
1091void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
1092 bool test);
1093
1094/*
1095 * Code Specific to AR5008, AR9001 or AR9002,
1096 * we stuff these here to avoid callbacks for AR9003.
1097 */
1098int ar9002_hw_rf_claim(struct ath_hw *ah);
1099void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1100
1101/*
1102 * Code specific to AR9003, we stuff these here to avoid callbacks
1103 * for older families
1104 */
1105bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah);
1106void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1107void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1108void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1109void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1110void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1111void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1112 struct ath9k_hw_cal_data *caldata,
1113 int chain);
1114int ar9003_paprd_create_curve(struct ath_hw *ah,
1115 struct ath9k_hw_cal_data *caldata, int chain);
1116void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1117int ar9003_paprd_init_table(struct ath_hw *ah);
1118bool ar9003_paprd_is_done(struct ath_hw *ah);
1119bool ar9003_is_paprd_enabled(struct ath_hw *ah);
1120void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1121void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
1122 struct ath9k_channel *chan);
1123void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah,
1124 struct ath9k_channel *chan, int bin);
1125void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array,
1126 struct ath9k_channel *chan, int ht40_delta);
1127
1128/* Hardware family op attach helpers */
1129int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1130void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1131void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1132
1133void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1134void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1135
1136int ar9002_hw_attach_ops(struct ath_hw *ah);
1137void ar9003_hw_attach_ops(struct ath_hw *ah);
1138
1139void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1140
1141void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1142void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1143
1144void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us);
1145void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us);
1146void ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
1147
1148#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1149void ar9003_hw_attach_aic_ops(struct ath_hw *ah);
1150static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1151{
1152 return ah->btcoex_hw.enabled;
1153}
1154static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1155{
1156 return ah->common.btcoex_enabled &&
1157 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1158
1159}
1160void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1161static inline enum ath_btcoex_scheme
1162ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1163{
1164 return ah->btcoex_hw.scheme;
1165}
1166#else
1167static inline void ar9003_hw_attach_aic_ops(struct ath_hw *ah)
1168{
1169}
1170static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1171{
1172 return false;
1173}
1174static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1175{
1176 return false;
1177}
1178static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1179{
1180}
1181static inline enum ath_btcoex_scheme
1182ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1183{
1184 return ATH_BTCOEX_CFG_NONE;
1185}
1186#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1187
1188
1189#ifdef CONFIG_ATH9K_WOW
1190int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1191 u8 *user_mask, int pattern_count,
1192 int pattern_len);
1193u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
1194void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
1195#else
1196static inline int ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
1197 u8 *user_pattern,
1198 u8 *user_mask,
1199 int pattern_count,
1200 int pattern_len)
1201{
1202 return 0;
1203}
1204static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1205{
1206 return 0;
1207}
1208static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1209{
1210}
1211#endif
1212
1213#define ATH9K_CLOCK_RATE_CCK 22
1214#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1215#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1216#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1217
1218#endif