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1/*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29#include "drmP.h"
30#include "drm.h"
31#include "i915_drm.h"
32#include "i915_drv.h"
33#include "i915_trace.h"
34#include "intel_drv.h"
35
36struct change_domains {
37 uint32_t invalidate_domains;
38 uint32_t flush_domains;
39 uint32_t flush_rings;
40 uint32_t flips;
41};
42
43/*
44 * Set the next domain for the specified object. This
45 * may not actually perform the necessary flushing/invaliding though,
46 * as that may want to be batched with other set_domain operations
47 *
48 * This is (we hope) the only really tricky part of gem. The goal
49 * is fairly simple -- track which caches hold bits of the object
50 * and make sure they remain coherent. A few concrete examples may
51 * help to explain how it works. For shorthand, we use the notation
52 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
53 * a pair of read and write domain masks.
54 *
55 * Case 1: the batch buffer
56 *
57 * 1. Allocated
58 * 2. Written by CPU
59 * 3. Mapped to GTT
60 * 4. Read by GPU
61 * 5. Unmapped from GTT
62 * 6. Freed
63 *
64 * Let's take these a step at a time
65 *
66 * 1. Allocated
67 * Pages allocated from the kernel may still have
68 * cache contents, so we set them to (CPU, CPU) always.
69 * 2. Written by CPU (using pwrite)
70 * The pwrite function calls set_domain (CPU, CPU) and
71 * this function does nothing (as nothing changes)
72 * 3. Mapped by GTT
73 * This function asserts that the object is not
74 * currently in any GPU-based read or write domains
75 * 4. Read by GPU
76 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
77 * As write_domain is zero, this function adds in the
78 * current read domains (CPU+COMMAND, 0).
79 * flush_domains is set to CPU.
80 * invalidate_domains is set to COMMAND
81 * clflush is run to get data out of the CPU caches
82 * then i915_dev_set_domain calls i915_gem_flush to
83 * emit an MI_FLUSH and drm_agp_chipset_flush
84 * 5. Unmapped from GTT
85 * i915_gem_object_unbind calls set_domain (CPU, CPU)
86 * flush_domains and invalidate_domains end up both zero
87 * so no flushing/invalidating happens
88 * 6. Freed
89 * yay, done
90 *
91 * Case 2: The shared render buffer
92 *
93 * 1. Allocated
94 * 2. Mapped to GTT
95 * 3. Read/written by GPU
96 * 4. set_domain to (CPU,CPU)
97 * 5. Read/written by CPU
98 * 6. Read/written by GPU
99 *
100 * 1. Allocated
101 * Same as last example, (CPU, CPU)
102 * 2. Mapped to GTT
103 * Nothing changes (assertions find that it is not in the GPU)
104 * 3. Read/written by GPU
105 * execbuffer calls set_domain (RENDER, RENDER)
106 * flush_domains gets CPU
107 * invalidate_domains gets GPU
108 * clflush (obj)
109 * MI_FLUSH and drm_agp_chipset_flush
110 * 4. set_domain (CPU, CPU)
111 * flush_domains gets GPU
112 * invalidate_domains gets CPU
113 * wait_rendering (obj) to make sure all drawing is complete.
114 * This will include an MI_FLUSH to get the data from GPU
115 * to memory
116 * clflush (obj) to invalidate the CPU cache
117 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
118 * 5. Read/written by CPU
119 * cache lines are loaded and dirtied
120 * 6. Read written by GPU
121 * Same as last GPU access
122 *
123 * Case 3: The constant buffer
124 *
125 * 1. Allocated
126 * 2. Written by CPU
127 * 3. Read by GPU
128 * 4. Updated (written) by CPU again
129 * 5. Read by GPU
130 *
131 * 1. Allocated
132 * (CPU, CPU)
133 * 2. Written by CPU
134 * (CPU, CPU)
135 * 3. Read by GPU
136 * (CPU+RENDER, 0)
137 * flush_domains = CPU
138 * invalidate_domains = RENDER
139 * clflush (obj)
140 * MI_FLUSH
141 * drm_agp_chipset_flush
142 * 4. Updated (written) by CPU again
143 * (CPU, CPU)
144 * flush_domains = 0 (no previous write domain)
145 * invalidate_domains = 0 (no new read domains)
146 * 5. Read by GPU
147 * (CPU+RENDER, 0)
148 * flush_domains = CPU
149 * invalidate_domains = RENDER
150 * clflush (obj)
151 * MI_FLUSH
152 * drm_agp_chipset_flush
153 */
154static void
155i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj,
156 struct intel_ring_buffer *ring,
157 struct change_domains *cd)
158{
159 uint32_t invalidate_domains = 0, flush_domains = 0;
160
161 /*
162 * If the object isn't moving to a new write domain,
163 * let the object stay in multiple read domains
164 */
165 if (obj->base.pending_write_domain == 0)
166 obj->base.pending_read_domains |= obj->base.read_domains;
167
168 /*
169 * Flush the current write domain if
170 * the new read domains don't match. Invalidate
171 * any read domains which differ from the old
172 * write domain
173 */
174 if (obj->base.write_domain &&
175 (((obj->base.write_domain != obj->base.pending_read_domains ||
176 obj->ring != ring)) ||
177 (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) {
178 flush_domains |= obj->base.write_domain;
179 invalidate_domains |=
180 obj->base.pending_read_domains & ~obj->base.write_domain;
181 }
182 /*
183 * Invalidate any read caches which may have
184 * stale data. That is, any new read domains.
185 */
186 invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains;
187 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
188 i915_gem_clflush_object(obj);
189
190 if (obj->base.pending_write_domain)
191 cd->flips |= atomic_read(&obj->pending_flip);
192
193 /* The actual obj->write_domain will be updated with
194 * pending_write_domain after we emit the accumulated flush for all
195 * of our domain changes in execbuffers (which clears objects'
196 * write_domains). So if we have a current write domain that we
197 * aren't changing, set pending_write_domain to that.
198 */
199 if (flush_domains == 0 && obj->base.pending_write_domain == 0)
200 obj->base.pending_write_domain = obj->base.write_domain;
201
202 cd->invalidate_domains |= invalidate_domains;
203 cd->flush_domains |= flush_domains;
204 if (flush_domains & I915_GEM_GPU_DOMAINS)
205 cd->flush_rings |= obj->ring->id;
206 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
207 cd->flush_rings |= ring->id;
208}
209
210struct eb_objects {
211 int and;
212 struct hlist_head buckets[0];
213};
214
215static struct eb_objects *
216eb_create(int size)
217{
218 struct eb_objects *eb;
219 int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
220 while (count > size)
221 count >>= 1;
222 eb = kzalloc(count*sizeof(struct hlist_head) +
223 sizeof(struct eb_objects),
224 GFP_KERNEL);
225 if (eb == NULL)
226 return eb;
227
228 eb->and = count - 1;
229 return eb;
230}
231
232static void
233eb_reset(struct eb_objects *eb)
234{
235 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
236}
237
238static void
239eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
240{
241 hlist_add_head(&obj->exec_node,
242 &eb->buckets[obj->exec_handle & eb->and]);
243}
244
245static struct drm_i915_gem_object *
246eb_get_object(struct eb_objects *eb, unsigned long handle)
247{
248 struct hlist_head *head;
249 struct hlist_node *node;
250 struct drm_i915_gem_object *obj;
251
252 head = &eb->buckets[handle & eb->and];
253 hlist_for_each(node, head) {
254 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
255 if (obj->exec_handle == handle)
256 return obj;
257 }
258
259 return NULL;
260}
261
262static void
263eb_destroy(struct eb_objects *eb)
264{
265 kfree(eb);
266}
267
268static int
269i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
270 struct eb_objects *eb,
271 struct drm_i915_gem_relocation_entry *reloc)
272{
273 struct drm_device *dev = obj->base.dev;
274 struct drm_gem_object *target_obj;
275 uint32_t target_offset;
276 int ret = -EINVAL;
277
278 /* we've already hold a reference to all valid objects */
279 target_obj = &eb_get_object(eb, reloc->target_handle)->base;
280 if (unlikely(target_obj == NULL))
281 return -ENOENT;
282
283 target_offset = to_intel_bo(target_obj)->gtt_offset;
284
285 /* The target buffer should have appeared before us in the
286 * exec_object list, so it should have a GTT space bound by now.
287 */
288 if (unlikely(target_offset == 0)) {
289 DRM_ERROR("No GTT space found for object %d\n",
290 reloc->target_handle);
291 return ret;
292 }
293
294 /* Validate that the target is in a valid r/w GPU domain */
295 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
296 DRM_ERROR("reloc with multiple write domains: "
297 "obj %p target %d offset %d "
298 "read %08x write %08x",
299 obj, reloc->target_handle,
300 (int) reloc->offset,
301 reloc->read_domains,
302 reloc->write_domain);
303 return ret;
304 }
305 if (unlikely((reloc->write_domain | reloc->read_domains) & I915_GEM_DOMAIN_CPU)) {
306 DRM_ERROR("reloc with read/write CPU domains: "
307 "obj %p target %d offset %d "
308 "read %08x write %08x",
309 obj, reloc->target_handle,
310 (int) reloc->offset,
311 reloc->read_domains,
312 reloc->write_domain);
313 return ret;
314 }
315 if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
316 reloc->write_domain != target_obj->pending_write_domain)) {
317 DRM_ERROR("Write domain conflict: "
318 "obj %p target %d offset %d "
319 "new %08x old %08x\n",
320 obj, reloc->target_handle,
321 (int) reloc->offset,
322 reloc->write_domain,
323 target_obj->pending_write_domain);
324 return ret;
325 }
326
327 target_obj->pending_read_domains |= reloc->read_domains;
328 target_obj->pending_write_domain |= reloc->write_domain;
329
330 /* If the relocation already has the right value in it, no
331 * more work needs to be done.
332 */
333 if (target_offset == reloc->presumed_offset)
334 return 0;
335
336 /* Check that the relocation address is valid... */
337 if (unlikely(reloc->offset > obj->base.size - 4)) {
338 DRM_ERROR("Relocation beyond object bounds: "
339 "obj %p target %d offset %d size %d.\n",
340 obj, reloc->target_handle,
341 (int) reloc->offset,
342 (int) obj->base.size);
343 return ret;
344 }
345 if (unlikely(reloc->offset & 3)) {
346 DRM_ERROR("Relocation not 4-byte aligned: "
347 "obj %p target %d offset %d.\n",
348 obj, reloc->target_handle,
349 (int) reloc->offset);
350 return ret;
351 }
352
353 reloc->delta += target_offset;
354 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
355 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
356 char *vaddr;
357
358 vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]);
359 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
360 kunmap_atomic(vaddr);
361 } else {
362 struct drm_i915_private *dev_priv = dev->dev_private;
363 uint32_t __iomem *reloc_entry;
364 void __iomem *reloc_page;
365
366 /* We can't wait for rendering with pagefaults disabled */
367 if (obj->active && in_atomic())
368 return -EFAULT;
369
370 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
371 if (ret)
372 return ret;
373
374 /* Map the page containing the relocation we're going to perform. */
375 reloc->offset += obj->gtt_offset;
376 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
377 reloc->offset & PAGE_MASK);
378 reloc_entry = (uint32_t __iomem *)
379 (reloc_page + (reloc->offset & ~PAGE_MASK));
380 iowrite32(reloc->delta, reloc_entry);
381 io_mapping_unmap_atomic(reloc_page);
382 }
383
384 /* and update the user's relocation entry */
385 reloc->presumed_offset = target_offset;
386
387 return 0;
388}
389
390static int
391i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
392 struct eb_objects *eb)
393{
394 struct drm_i915_gem_relocation_entry __user *user_relocs;
395 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
396 int i, ret;
397
398 user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
399 for (i = 0; i < entry->relocation_count; i++) {
400 struct drm_i915_gem_relocation_entry reloc;
401
402 if (__copy_from_user_inatomic(&reloc,
403 user_relocs+i,
404 sizeof(reloc)))
405 return -EFAULT;
406
407 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &reloc);
408 if (ret)
409 return ret;
410
411 if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset,
412 &reloc.presumed_offset,
413 sizeof(reloc.presumed_offset)))
414 return -EFAULT;
415 }
416
417 return 0;
418}
419
420static int
421i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
422 struct eb_objects *eb,
423 struct drm_i915_gem_relocation_entry *relocs)
424{
425 const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
426 int i, ret;
427
428 for (i = 0; i < entry->relocation_count; i++) {
429 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
430 if (ret)
431 return ret;
432 }
433
434 return 0;
435}
436
437static int
438i915_gem_execbuffer_relocate(struct drm_device *dev,
439 struct eb_objects *eb,
440 struct list_head *objects)
441{
442 struct drm_i915_gem_object *obj;
443 int ret = 0;
444
445 /* This is the fast path and we cannot handle a pagefault whilst
446 * holding the struct mutex lest the user pass in the relocations
447 * contained within a mmaped bo. For in such a case we, the page
448 * fault handler would call i915_gem_fault() and we would try to
449 * acquire the struct mutex again. Obviously this is bad and so
450 * lockdep complains vehemently.
451 */
452 pagefault_disable();
453 list_for_each_entry(obj, objects, exec_list) {
454 ret = i915_gem_execbuffer_relocate_object(obj, eb);
455 if (ret)
456 break;
457 }
458 pagefault_enable();
459
460 return ret;
461}
462
463static int
464i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
465 struct drm_file *file,
466 struct list_head *objects)
467{
468 struct drm_i915_gem_object *obj;
469 int ret, retry;
470 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
471 struct list_head ordered_objects;
472
473 INIT_LIST_HEAD(&ordered_objects);
474 while (!list_empty(objects)) {
475 struct drm_i915_gem_exec_object2 *entry;
476 bool need_fence, need_mappable;
477
478 obj = list_first_entry(objects,
479 struct drm_i915_gem_object,
480 exec_list);
481 entry = obj->exec_entry;
482
483 need_fence =
484 has_fenced_gpu_access &&
485 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
486 obj->tiling_mode != I915_TILING_NONE;
487 need_mappable =
488 entry->relocation_count ? true : need_fence;
489
490 if (need_mappable)
491 list_move(&obj->exec_list, &ordered_objects);
492 else
493 list_move_tail(&obj->exec_list, &ordered_objects);
494
495 obj->base.pending_read_domains = 0;
496 obj->base.pending_write_domain = 0;
497 }
498 list_splice(&ordered_objects, objects);
499
500 /* Attempt to pin all of the buffers into the GTT.
501 * This is done in 3 phases:
502 *
503 * 1a. Unbind all objects that do not match the GTT constraints for
504 * the execbuffer (fenceable, mappable, alignment etc).
505 * 1b. Increment pin count for already bound objects.
506 * 2. Bind new objects.
507 * 3. Decrement pin count.
508 *
509 * This avoid unnecessary unbinding of later objects in order to makr
510 * room for the earlier objects *unless* we need to defragment.
511 */
512 retry = 0;
513 do {
514 ret = 0;
515
516 /* Unbind any ill-fitting objects or pin. */
517 list_for_each_entry(obj, objects, exec_list) {
518 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
519 bool need_fence, need_mappable;
520 if (!obj->gtt_space)
521 continue;
522
523 need_fence =
524 has_fenced_gpu_access &&
525 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
526 obj->tiling_mode != I915_TILING_NONE;
527 need_mappable =
528 entry->relocation_count ? true : need_fence;
529
530 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
531 (need_mappable && !obj->map_and_fenceable))
532 ret = i915_gem_object_unbind(obj);
533 else
534 ret = i915_gem_object_pin(obj,
535 entry->alignment,
536 need_mappable);
537 if (ret)
538 goto err;
539
540 entry++;
541 }
542
543 /* Bind fresh objects */
544 list_for_each_entry(obj, objects, exec_list) {
545 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
546 bool need_fence;
547
548 need_fence =
549 has_fenced_gpu_access &&
550 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
551 obj->tiling_mode != I915_TILING_NONE;
552
553 if (!obj->gtt_space) {
554 bool need_mappable =
555 entry->relocation_count ? true : need_fence;
556
557 ret = i915_gem_object_pin(obj,
558 entry->alignment,
559 need_mappable);
560 if (ret)
561 break;
562 }
563
564 if (has_fenced_gpu_access) {
565 if (need_fence) {
566 ret = i915_gem_object_get_fence(obj, ring);
567 if (ret)
568 break;
569 } else if (entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
570 obj->tiling_mode == I915_TILING_NONE) {
571 /* XXX pipelined! */
572 ret = i915_gem_object_put_fence(obj);
573 if (ret)
574 break;
575 }
576 obj->pending_fenced_gpu_access = need_fence;
577 }
578
579 entry->offset = obj->gtt_offset;
580 }
581
582 /* Decrement pin count for bound objects */
583 list_for_each_entry(obj, objects, exec_list) {
584 if (obj->gtt_space)
585 i915_gem_object_unpin(obj);
586 }
587
588 if (ret != -ENOSPC || retry > 1)
589 return ret;
590
591 /* First attempt, just clear anything that is purgeable.
592 * Second attempt, clear the entire GTT.
593 */
594 ret = i915_gem_evict_everything(ring->dev, retry == 0);
595 if (ret)
596 return ret;
597
598 retry++;
599 } while (1);
600
601err:
602 obj = list_entry(obj->exec_list.prev,
603 struct drm_i915_gem_object,
604 exec_list);
605 while (objects != &obj->exec_list) {
606 if (obj->gtt_space)
607 i915_gem_object_unpin(obj);
608
609 obj = list_entry(obj->exec_list.prev,
610 struct drm_i915_gem_object,
611 exec_list);
612 }
613
614 return ret;
615}
616
617static int
618i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
619 struct drm_file *file,
620 struct intel_ring_buffer *ring,
621 struct list_head *objects,
622 struct eb_objects *eb,
623 struct drm_i915_gem_exec_object2 *exec,
624 int count)
625{
626 struct drm_i915_gem_relocation_entry *reloc;
627 struct drm_i915_gem_object *obj;
628 int *reloc_offset;
629 int i, total, ret;
630
631 /* We may process another execbuffer during the unlock... */
632 while (!list_empty(objects)) {
633 obj = list_first_entry(objects,
634 struct drm_i915_gem_object,
635 exec_list);
636 list_del_init(&obj->exec_list);
637 drm_gem_object_unreference(&obj->base);
638 }
639
640 mutex_unlock(&dev->struct_mutex);
641
642 total = 0;
643 for (i = 0; i < count; i++)
644 total += exec[i].relocation_count;
645
646 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
647 reloc = drm_malloc_ab(total, sizeof(*reloc));
648 if (reloc == NULL || reloc_offset == NULL) {
649 drm_free_large(reloc);
650 drm_free_large(reloc_offset);
651 mutex_lock(&dev->struct_mutex);
652 return -ENOMEM;
653 }
654
655 total = 0;
656 for (i = 0; i < count; i++) {
657 struct drm_i915_gem_relocation_entry __user *user_relocs;
658
659 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
660
661 if (copy_from_user(reloc+total, user_relocs,
662 exec[i].relocation_count * sizeof(*reloc))) {
663 ret = -EFAULT;
664 mutex_lock(&dev->struct_mutex);
665 goto err;
666 }
667
668 reloc_offset[i] = total;
669 total += exec[i].relocation_count;
670 }
671
672 ret = i915_mutex_lock_interruptible(dev);
673 if (ret) {
674 mutex_lock(&dev->struct_mutex);
675 goto err;
676 }
677
678 /* reacquire the objects */
679 eb_reset(eb);
680 for (i = 0; i < count; i++) {
681 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
682 exec[i].handle));
683 if (&obj->base == NULL) {
684 DRM_ERROR("Invalid object handle %d at index %d\n",
685 exec[i].handle, i);
686 ret = -ENOENT;
687 goto err;
688 }
689
690 list_add_tail(&obj->exec_list, objects);
691 obj->exec_handle = exec[i].handle;
692 obj->exec_entry = &exec[i];
693 eb_add_object(eb, obj);
694 }
695
696 ret = i915_gem_execbuffer_reserve(ring, file, objects);
697 if (ret)
698 goto err;
699
700 list_for_each_entry(obj, objects, exec_list) {
701 int offset = obj->exec_entry - exec;
702 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
703 reloc + reloc_offset[offset]);
704 if (ret)
705 goto err;
706 }
707
708 /* Leave the user relocations as are, this is the painfully slow path,
709 * and we want to avoid the complication of dropping the lock whilst
710 * having buffers reserved in the aperture and so causing spurious
711 * ENOSPC for random operations.
712 */
713
714err:
715 drm_free_large(reloc);
716 drm_free_large(reloc_offset);
717 return ret;
718}
719
720static int
721i915_gem_execbuffer_flush(struct drm_device *dev,
722 uint32_t invalidate_domains,
723 uint32_t flush_domains,
724 uint32_t flush_rings)
725{
726 drm_i915_private_t *dev_priv = dev->dev_private;
727 int i, ret;
728
729 if (flush_domains & I915_GEM_DOMAIN_CPU)
730 intel_gtt_chipset_flush();
731
732 if (flush_domains & I915_GEM_DOMAIN_GTT)
733 wmb();
734
735 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
736 for (i = 0; i < I915_NUM_RINGS; i++)
737 if (flush_rings & (1 << i)) {
738 ret = i915_gem_flush_ring(&dev_priv->ring[i],
739 invalidate_domains,
740 flush_domains);
741 if (ret)
742 return ret;
743 }
744 }
745
746 return 0;
747}
748
749static int
750i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
751 struct intel_ring_buffer *to)
752{
753 struct intel_ring_buffer *from = obj->ring;
754 u32 seqno;
755 int ret, idx;
756
757 if (from == NULL || to == from)
758 return 0;
759
760 /* XXX gpu semaphores are implicated in various hard hangs on SNB */
761 if (INTEL_INFO(obj->base.dev)->gen < 6 || !i915_semaphores)
762 return i915_gem_object_wait_rendering(obj);
763
764 idx = intel_ring_sync_index(from, to);
765
766 seqno = obj->last_rendering_seqno;
767 if (seqno <= from->sync_seqno[idx])
768 return 0;
769
770 if (seqno == from->outstanding_lazy_request) {
771 struct drm_i915_gem_request *request;
772
773 request = kzalloc(sizeof(*request), GFP_KERNEL);
774 if (request == NULL)
775 return -ENOMEM;
776
777 ret = i915_add_request(from, NULL, request);
778 if (ret) {
779 kfree(request);
780 return ret;
781 }
782
783 seqno = request->seqno;
784 }
785
786 from->sync_seqno[idx] = seqno;
787 return intel_ring_sync(to, from, seqno - 1);
788}
789
790static int
791i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips)
792{
793 u32 plane, flip_mask;
794 int ret;
795
796 /* Check for any pending flips. As we only maintain a flip queue depth
797 * of 1, we can simply insert a WAIT for the next display flip prior
798 * to executing the batch and avoid stalling the CPU.
799 */
800
801 for (plane = 0; flips >> plane; plane++) {
802 if (((flips >> plane) & 1) == 0)
803 continue;
804
805 if (plane)
806 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
807 else
808 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
809
810 ret = intel_ring_begin(ring, 2);
811 if (ret)
812 return ret;
813
814 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
815 intel_ring_emit(ring, MI_NOOP);
816 intel_ring_advance(ring);
817 }
818
819 return 0;
820}
821
822
823static int
824i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
825 struct list_head *objects)
826{
827 struct drm_i915_gem_object *obj;
828 struct change_domains cd;
829 int ret;
830
831 memset(&cd, 0, sizeof(cd));
832 list_for_each_entry(obj, objects, exec_list)
833 i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
834
835 if (cd.invalidate_domains | cd.flush_domains) {
836 ret = i915_gem_execbuffer_flush(ring->dev,
837 cd.invalidate_domains,
838 cd.flush_domains,
839 cd.flush_rings);
840 if (ret)
841 return ret;
842 }
843
844 if (cd.flips) {
845 ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips);
846 if (ret)
847 return ret;
848 }
849
850 list_for_each_entry(obj, objects, exec_list) {
851 ret = i915_gem_execbuffer_sync_rings(obj, ring);
852 if (ret)
853 return ret;
854 }
855
856 return 0;
857}
858
859static bool
860i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
861{
862 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
863}
864
865static int
866validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
867 int count)
868{
869 int i;
870
871 for (i = 0; i < count; i++) {
872 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
873 int length; /* limited by fault_in_pages_readable() */
874
875 /* First check for malicious input causing overflow */
876 if (exec[i].relocation_count >
877 INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
878 return -EINVAL;
879
880 length = exec[i].relocation_count *
881 sizeof(struct drm_i915_gem_relocation_entry);
882 if (!access_ok(VERIFY_READ, ptr, length))
883 return -EFAULT;
884
885 /* we may also need to update the presumed offsets */
886 if (!access_ok(VERIFY_WRITE, ptr, length))
887 return -EFAULT;
888
889 if (fault_in_pages_readable(ptr, length))
890 return -EFAULT;
891 }
892
893 return 0;
894}
895
896static void
897i915_gem_execbuffer_move_to_active(struct list_head *objects,
898 struct intel_ring_buffer *ring,
899 u32 seqno)
900{
901 struct drm_i915_gem_object *obj;
902
903 list_for_each_entry(obj, objects, exec_list) {
904 u32 old_read = obj->base.read_domains;
905 u32 old_write = obj->base.write_domain;
906
907
908 obj->base.read_domains = obj->base.pending_read_domains;
909 obj->base.write_domain = obj->base.pending_write_domain;
910 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
911
912 i915_gem_object_move_to_active(obj, ring, seqno);
913 if (obj->base.write_domain) {
914 obj->dirty = 1;
915 obj->pending_gpu_write = true;
916 list_move_tail(&obj->gpu_write_list,
917 &ring->gpu_write_list);
918 intel_mark_busy(ring->dev, obj);
919 }
920
921 trace_i915_gem_object_change_domain(obj, old_read, old_write);
922 }
923}
924
925static void
926i915_gem_execbuffer_retire_commands(struct drm_device *dev,
927 struct drm_file *file,
928 struct intel_ring_buffer *ring)
929{
930 struct drm_i915_gem_request *request;
931 u32 invalidate;
932
933 /*
934 * Ensure that the commands in the batch buffer are
935 * finished before the interrupt fires.
936 *
937 * The sampler always gets flushed on i965 (sigh).
938 */
939 invalidate = I915_GEM_DOMAIN_COMMAND;
940 if (INTEL_INFO(dev)->gen >= 4)
941 invalidate |= I915_GEM_DOMAIN_SAMPLER;
942 if (ring->flush(ring, invalidate, 0)) {
943 i915_gem_next_request_seqno(ring);
944 return;
945 }
946
947 /* Add a breadcrumb for the completion of the batch buffer */
948 request = kzalloc(sizeof(*request), GFP_KERNEL);
949 if (request == NULL || i915_add_request(ring, file, request)) {
950 i915_gem_next_request_seqno(ring);
951 kfree(request);
952 }
953}
954
955static int
956i915_gem_do_execbuffer(struct drm_device *dev, void *data,
957 struct drm_file *file,
958 struct drm_i915_gem_execbuffer2 *args,
959 struct drm_i915_gem_exec_object2 *exec)
960{
961 drm_i915_private_t *dev_priv = dev->dev_private;
962 struct list_head objects;
963 struct eb_objects *eb;
964 struct drm_i915_gem_object *batch_obj;
965 struct drm_clip_rect *cliprects = NULL;
966 struct intel_ring_buffer *ring;
967 u32 exec_start, exec_len;
968 u32 seqno;
969 int ret, mode, i;
970
971 if (!i915_gem_check_execbuffer(args)) {
972 DRM_ERROR("execbuf with invalid offset/length\n");
973 return -EINVAL;
974 }
975
976 ret = validate_exec_list(exec, args->buffer_count);
977 if (ret)
978 return ret;
979
980 switch (args->flags & I915_EXEC_RING_MASK) {
981 case I915_EXEC_DEFAULT:
982 case I915_EXEC_RENDER:
983 ring = &dev_priv->ring[RCS];
984 break;
985 case I915_EXEC_BSD:
986 if (!HAS_BSD(dev)) {
987 DRM_ERROR("execbuf with invalid ring (BSD)\n");
988 return -EINVAL;
989 }
990 ring = &dev_priv->ring[VCS];
991 break;
992 case I915_EXEC_BLT:
993 if (!HAS_BLT(dev)) {
994 DRM_ERROR("execbuf with invalid ring (BLT)\n");
995 return -EINVAL;
996 }
997 ring = &dev_priv->ring[BCS];
998 break;
999 default:
1000 DRM_ERROR("execbuf with unknown ring: %d\n",
1001 (int)(args->flags & I915_EXEC_RING_MASK));
1002 return -EINVAL;
1003 }
1004
1005 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1006 switch (mode) {
1007 case I915_EXEC_CONSTANTS_REL_GENERAL:
1008 case I915_EXEC_CONSTANTS_ABSOLUTE:
1009 case I915_EXEC_CONSTANTS_REL_SURFACE:
1010 if (ring == &dev_priv->ring[RCS] &&
1011 mode != dev_priv->relative_constants_mode) {
1012 if (INTEL_INFO(dev)->gen < 4)
1013 return -EINVAL;
1014
1015 if (INTEL_INFO(dev)->gen > 5 &&
1016 mode == I915_EXEC_CONSTANTS_REL_SURFACE)
1017 return -EINVAL;
1018
1019 ret = intel_ring_begin(ring, 4);
1020 if (ret)
1021 return ret;
1022
1023 intel_ring_emit(ring, MI_NOOP);
1024 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1025 intel_ring_emit(ring, INSTPM);
1026 intel_ring_emit(ring,
1027 I915_EXEC_CONSTANTS_MASK << 16 | mode);
1028 intel_ring_advance(ring);
1029
1030 dev_priv->relative_constants_mode = mode;
1031 }
1032 break;
1033 default:
1034 DRM_ERROR("execbuf with unknown constants: %d\n", mode);
1035 return -EINVAL;
1036 }
1037
1038 if (args->buffer_count < 1) {
1039 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1040 return -EINVAL;
1041 }
1042
1043 if (args->num_cliprects != 0) {
1044 if (ring != &dev_priv->ring[RCS]) {
1045 DRM_ERROR("clip rectangles are only valid with the render ring\n");
1046 return -EINVAL;
1047 }
1048
1049 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
1050 GFP_KERNEL);
1051 if (cliprects == NULL) {
1052 ret = -ENOMEM;
1053 goto pre_mutex_err;
1054 }
1055
1056 if (copy_from_user(cliprects,
1057 (struct drm_clip_rect __user *)(uintptr_t)
1058 args->cliprects_ptr,
1059 sizeof(*cliprects)*args->num_cliprects)) {
1060 ret = -EFAULT;
1061 goto pre_mutex_err;
1062 }
1063 }
1064
1065 ret = i915_mutex_lock_interruptible(dev);
1066 if (ret)
1067 goto pre_mutex_err;
1068
1069 if (dev_priv->mm.suspended) {
1070 mutex_unlock(&dev->struct_mutex);
1071 ret = -EBUSY;
1072 goto pre_mutex_err;
1073 }
1074
1075 eb = eb_create(args->buffer_count);
1076 if (eb == NULL) {
1077 mutex_unlock(&dev->struct_mutex);
1078 ret = -ENOMEM;
1079 goto pre_mutex_err;
1080 }
1081
1082 /* Look up object handles */
1083 INIT_LIST_HEAD(&objects);
1084 for (i = 0; i < args->buffer_count; i++) {
1085 struct drm_i915_gem_object *obj;
1086
1087 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
1088 exec[i].handle));
1089 if (&obj->base == NULL) {
1090 DRM_ERROR("Invalid object handle %d at index %d\n",
1091 exec[i].handle, i);
1092 /* prevent error path from reading uninitialized data */
1093 ret = -ENOENT;
1094 goto err;
1095 }
1096
1097 if (!list_empty(&obj->exec_list)) {
1098 DRM_ERROR("Object %p [handle %d, index %d] appears more than once in object list\n",
1099 obj, exec[i].handle, i);
1100 ret = -EINVAL;
1101 goto err;
1102 }
1103
1104 list_add_tail(&obj->exec_list, &objects);
1105 obj->exec_handle = exec[i].handle;
1106 obj->exec_entry = &exec[i];
1107 eb_add_object(eb, obj);
1108 }
1109
1110 /* take note of the batch buffer before we might reorder the lists */
1111 batch_obj = list_entry(objects.prev,
1112 struct drm_i915_gem_object,
1113 exec_list);
1114
1115 /* Move the objects en-masse into the GTT, evicting if necessary. */
1116 ret = i915_gem_execbuffer_reserve(ring, file, &objects);
1117 if (ret)
1118 goto err;
1119
1120 /* The objects are in their final locations, apply the relocations. */
1121 ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
1122 if (ret) {
1123 if (ret == -EFAULT) {
1124 ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
1125 &objects, eb,
1126 exec,
1127 args->buffer_count);
1128 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1129 }
1130 if (ret)
1131 goto err;
1132 }
1133
1134 /* Set the pending read domains for the batch buffer to COMMAND */
1135 if (batch_obj->base.pending_write_domain) {
1136 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
1137 ret = -EINVAL;
1138 goto err;
1139 }
1140 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1141
1142 ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
1143 if (ret)
1144 goto err;
1145
1146 seqno = i915_gem_next_request_seqno(ring);
1147 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) {
1148 if (seqno < ring->sync_seqno[i]) {
1149 /* The GPU can not handle its semaphore value wrapping,
1150 * so every billion or so execbuffers, we need to stall
1151 * the GPU in order to reset the counters.
1152 */
1153 ret = i915_gpu_idle(dev);
1154 if (ret)
1155 goto err;
1156
1157 BUG_ON(ring->sync_seqno[i]);
1158 }
1159 }
1160
1161 trace_i915_gem_ring_dispatch(ring, seqno);
1162
1163 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1164 exec_len = args->batch_len;
1165 if (cliprects) {
1166 for (i = 0; i < args->num_cliprects; i++) {
1167 ret = i915_emit_box(dev, &cliprects[i],
1168 args->DR1, args->DR4);
1169 if (ret)
1170 goto err;
1171
1172 ret = ring->dispatch_execbuffer(ring,
1173 exec_start, exec_len);
1174 if (ret)
1175 goto err;
1176 }
1177 } else {
1178 ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
1179 if (ret)
1180 goto err;
1181 }
1182
1183 i915_gem_execbuffer_move_to_active(&objects, ring, seqno);
1184 i915_gem_execbuffer_retire_commands(dev, file, ring);
1185
1186err:
1187 eb_destroy(eb);
1188 while (!list_empty(&objects)) {
1189 struct drm_i915_gem_object *obj;
1190
1191 obj = list_first_entry(&objects,
1192 struct drm_i915_gem_object,
1193 exec_list);
1194 list_del_init(&obj->exec_list);
1195 drm_gem_object_unreference(&obj->base);
1196 }
1197
1198 mutex_unlock(&dev->struct_mutex);
1199
1200pre_mutex_err:
1201 kfree(cliprects);
1202 return ret;
1203}
1204
1205/*
1206 * Legacy execbuffer just creates an exec2 list from the original exec object
1207 * list array and passes it to the real function.
1208 */
1209int
1210i915_gem_execbuffer(struct drm_device *dev, void *data,
1211 struct drm_file *file)
1212{
1213 struct drm_i915_gem_execbuffer *args = data;
1214 struct drm_i915_gem_execbuffer2 exec2;
1215 struct drm_i915_gem_exec_object *exec_list = NULL;
1216 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1217 int ret, i;
1218
1219 if (args->buffer_count < 1) {
1220 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1221 return -EINVAL;
1222 }
1223
1224 /* Copy in the exec list from userland */
1225 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1226 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1227 if (exec_list == NULL || exec2_list == NULL) {
1228 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1229 args->buffer_count);
1230 drm_free_large(exec_list);
1231 drm_free_large(exec2_list);
1232 return -ENOMEM;
1233 }
1234 ret = copy_from_user(exec_list,
1235 (struct drm_i915_relocation_entry __user *)
1236 (uintptr_t) args->buffers_ptr,
1237 sizeof(*exec_list) * args->buffer_count);
1238 if (ret != 0) {
1239 DRM_ERROR("copy %d exec entries failed %d\n",
1240 args->buffer_count, ret);
1241 drm_free_large(exec_list);
1242 drm_free_large(exec2_list);
1243 return -EFAULT;
1244 }
1245
1246 for (i = 0; i < args->buffer_count; i++) {
1247 exec2_list[i].handle = exec_list[i].handle;
1248 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1249 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1250 exec2_list[i].alignment = exec_list[i].alignment;
1251 exec2_list[i].offset = exec_list[i].offset;
1252 if (INTEL_INFO(dev)->gen < 4)
1253 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1254 else
1255 exec2_list[i].flags = 0;
1256 }
1257
1258 exec2.buffers_ptr = args->buffers_ptr;
1259 exec2.buffer_count = args->buffer_count;
1260 exec2.batch_start_offset = args->batch_start_offset;
1261 exec2.batch_len = args->batch_len;
1262 exec2.DR1 = args->DR1;
1263 exec2.DR4 = args->DR4;
1264 exec2.num_cliprects = args->num_cliprects;
1265 exec2.cliprects_ptr = args->cliprects_ptr;
1266 exec2.flags = I915_EXEC_RENDER;
1267
1268 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1269 if (!ret) {
1270 /* Copy the new buffer offsets back to the user's exec list. */
1271 for (i = 0; i < args->buffer_count; i++)
1272 exec_list[i].offset = exec2_list[i].offset;
1273 /* ... and back out to userspace */
1274 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1275 (uintptr_t) args->buffers_ptr,
1276 exec_list,
1277 sizeof(*exec_list) * args->buffer_count);
1278 if (ret) {
1279 ret = -EFAULT;
1280 DRM_ERROR("failed to copy %d exec entries "
1281 "back to user (%d)\n",
1282 args->buffer_count, ret);
1283 }
1284 }
1285
1286 drm_free_large(exec_list);
1287 drm_free_large(exec2_list);
1288 return ret;
1289}
1290
1291int
1292i915_gem_execbuffer2(struct drm_device *dev, void *data,
1293 struct drm_file *file)
1294{
1295 struct drm_i915_gem_execbuffer2 *args = data;
1296 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1297 int ret;
1298
1299 if (args->buffer_count < 1) {
1300 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
1301 return -EINVAL;
1302 }
1303
1304 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1305 GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
1306 if (exec2_list == NULL)
1307 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1308 args->buffer_count);
1309 if (exec2_list == NULL) {
1310 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
1311 args->buffer_count);
1312 return -ENOMEM;
1313 }
1314 ret = copy_from_user(exec2_list,
1315 (struct drm_i915_relocation_entry __user *)
1316 (uintptr_t) args->buffers_ptr,
1317 sizeof(*exec2_list) * args->buffer_count);
1318 if (ret != 0) {
1319 DRM_ERROR("copy %d exec entries failed %d\n",
1320 args->buffer_count, ret);
1321 drm_free_large(exec2_list);
1322 return -EFAULT;
1323 }
1324
1325 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1326 if (!ret) {
1327 /* Copy the new buffer offsets back to the user's exec list. */
1328 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1329 (uintptr_t) args->buffers_ptr,
1330 exec2_list,
1331 sizeof(*exec2_list) * args->buffer_count);
1332 if (ret) {
1333 ret = -EFAULT;
1334 DRM_ERROR("failed to copy %d exec entries "
1335 "back to user (%d)\n",
1336 args->buffer_count, ret);
1337 }
1338 }
1339
1340 drm_free_large(exec2_list);
1341 return ret;
1342}
1/*
2 * Copyright © 2008,2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 *
27 */
28
29#include <linux/dma_remapping.h>
30#include <linux/reservation.h>
31#include <linux/uaccess.h>
32
33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
35
36#include "i915_drv.h"
37#include "i915_trace.h"
38#include "intel_drv.h"
39#include "intel_frontbuffer.h"
40
41#define DBG_USE_CPU_RELOC 0 /* -1 force GTT relocs; 1 force CPU relocs */
42
43#define __EXEC_OBJECT_HAS_PIN (1<<31)
44#define __EXEC_OBJECT_HAS_FENCE (1<<30)
45#define __EXEC_OBJECT_NEEDS_MAP (1<<29)
46#define __EXEC_OBJECT_NEEDS_BIAS (1<<28)
47#define __EXEC_OBJECT_INTERNAL_FLAGS (0xf<<28) /* all of the above */
48
49#define BATCH_OFFSET_BIAS (256*1024)
50
51struct i915_execbuffer_params {
52 struct drm_device *dev;
53 struct drm_file *file;
54 struct i915_vma *batch;
55 u32 dispatch_flags;
56 u32 args_batch_start_offset;
57 struct intel_engine_cs *engine;
58 struct i915_gem_context *ctx;
59 struct drm_i915_gem_request *request;
60};
61
62struct eb_vmas {
63 struct drm_i915_private *i915;
64 struct list_head vmas;
65 int and;
66 union {
67 struct i915_vma *lut[0];
68 struct hlist_head buckets[0];
69 };
70};
71
72static struct eb_vmas *
73eb_create(struct drm_i915_private *i915,
74 struct drm_i915_gem_execbuffer2 *args)
75{
76 struct eb_vmas *eb = NULL;
77
78 if (args->flags & I915_EXEC_HANDLE_LUT) {
79 unsigned size = args->buffer_count;
80 size *= sizeof(struct i915_vma *);
81 size += sizeof(struct eb_vmas);
82 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
83 }
84
85 if (eb == NULL) {
86 unsigned size = args->buffer_count;
87 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
88 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
89 while (count > 2*size)
90 count >>= 1;
91 eb = kzalloc(count*sizeof(struct hlist_head) +
92 sizeof(struct eb_vmas),
93 GFP_TEMPORARY);
94 if (eb == NULL)
95 return eb;
96
97 eb->and = count - 1;
98 } else
99 eb->and = -args->buffer_count;
100
101 eb->i915 = i915;
102 INIT_LIST_HEAD(&eb->vmas);
103 return eb;
104}
105
106static void
107eb_reset(struct eb_vmas *eb)
108{
109 if (eb->and >= 0)
110 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
111}
112
113static struct i915_vma *
114eb_get_batch(struct eb_vmas *eb)
115{
116 struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
117
118 /*
119 * SNA is doing fancy tricks with compressing batch buffers, which leads
120 * to negative relocation deltas. Usually that works out ok since the
121 * relocate address is still positive, except when the batch is placed
122 * very low in the GTT. Ensure this doesn't happen.
123 *
124 * Note that actual hangs have only been observed on gen7, but for
125 * paranoia do it everywhere.
126 */
127 if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0)
128 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
129
130 return vma;
131}
132
133static int
134eb_lookup_vmas(struct eb_vmas *eb,
135 struct drm_i915_gem_exec_object2 *exec,
136 const struct drm_i915_gem_execbuffer2 *args,
137 struct i915_address_space *vm,
138 struct drm_file *file)
139{
140 struct drm_i915_gem_object *obj;
141 struct list_head objects;
142 int i, ret;
143
144 INIT_LIST_HEAD(&objects);
145 spin_lock(&file->table_lock);
146 /* Grab a reference to the object and release the lock so we can lookup
147 * or create the VMA without using GFP_ATOMIC */
148 for (i = 0; i < args->buffer_count; i++) {
149 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
150 if (obj == NULL) {
151 spin_unlock(&file->table_lock);
152 DRM_DEBUG("Invalid object handle %d at index %d\n",
153 exec[i].handle, i);
154 ret = -ENOENT;
155 goto err;
156 }
157
158 if (!list_empty(&obj->obj_exec_link)) {
159 spin_unlock(&file->table_lock);
160 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
161 obj, exec[i].handle, i);
162 ret = -EINVAL;
163 goto err;
164 }
165
166 i915_gem_object_get(obj);
167 list_add_tail(&obj->obj_exec_link, &objects);
168 }
169 spin_unlock(&file->table_lock);
170
171 i = 0;
172 while (!list_empty(&objects)) {
173 struct i915_vma *vma;
174
175 obj = list_first_entry(&objects,
176 struct drm_i915_gem_object,
177 obj_exec_link);
178
179 /*
180 * NOTE: We can leak any vmas created here when something fails
181 * later on. But that's no issue since vma_unbind can deal with
182 * vmas which are not actually bound. And since only
183 * lookup_or_create exists as an interface to get at the vma
184 * from the (obj, vm) we don't run the risk of creating
185 * duplicated vmas for the same vm.
186 */
187 vma = i915_gem_obj_lookup_or_create_vma(obj, vm, NULL);
188 if (unlikely(IS_ERR(vma))) {
189 DRM_DEBUG("Failed to lookup VMA\n");
190 ret = PTR_ERR(vma);
191 goto err;
192 }
193
194 /* Transfer ownership from the objects list to the vmas list. */
195 list_add_tail(&vma->exec_list, &eb->vmas);
196 list_del_init(&obj->obj_exec_link);
197
198 vma->exec_entry = &exec[i];
199 if (eb->and < 0) {
200 eb->lut[i] = vma;
201 } else {
202 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
203 vma->exec_handle = handle;
204 hlist_add_head(&vma->exec_node,
205 &eb->buckets[handle & eb->and]);
206 }
207 ++i;
208 }
209
210 return 0;
211
212
213err:
214 while (!list_empty(&objects)) {
215 obj = list_first_entry(&objects,
216 struct drm_i915_gem_object,
217 obj_exec_link);
218 list_del_init(&obj->obj_exec_link);
219 i915_gem_object_put(obj);
220 }
221 /*
222 * Objects already transfered to the vmas list will be unreferenced by
223 * eb_destroy.
224 */
225
226 return ret;
227}
228
229static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
230{
231 if (eb->and < 0) {
232 if (handle >= -eb->and)
233 return NULL;
234 return eb->lut[handle];
235 } else {
236 struct hlist_head *head;
237 struct i915_vma *vma;
238
239 head = &eb->buckets[handle & eb->and];
240 hlist_for_each_entry(vma, head, exec_node) {
241 if (vma->exec_handle == handle)
242 return vma;
243 }
244 return NULL;
245 }
246}
247
248static void
249i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
250{
251 struct drm_i915_gem_exec_object2 *entry;
252
253 if (!drm_mm_node_allocated(&vma->node))
254 return;
255
256 entry = vma->exec_entry;
257
258 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
259 i915_vma_unpin_fence(vma);
260
261 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
262 __i915_vma_unpin(vma);
263
264 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
265}
266
267static void eb_destroy(struct eb_vmas *eb)
268{
269 while (!list_empty(&eb->vmas)) {
270 struct i915_vma *vma;
271
272 vma = list_first_entry(&eb->vmas,
273 struct i915_vma,
274 exec_list);
275 list_del_init(&vma->exec_list);
276 i915_gem_execbuffer_unreserve_vma(vma);
277 i915_vma_put(vma);
278 }
279 kfree(eb);
280}
281
282static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
283{
284 if (!i915_gem_object_has_struct_page(obj))
285 return false;
286
287 if (DBG_USE_CPU_RELOC)
288 return DBG_USE_CPU_RELOC > 0;
289
290 return (HAS_LLC(to_i915(obj->base.dev)) ||
291 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
292 obj->cache_level != I915_CACHE_NONE);
293}
294
295/* Used to convert any address to canonical form.
296 * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
297 * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
298 * addresses to be in a canonical form:
299 * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
300 * canonical form [63:48] == [47]."
301 */
302#define GEN8_HIGH_ADDRESS_BIT 47
303static inline uint64_t gen8_canonical_addr(uint64_t address)
304{
305 return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
306}
307
308static inline uint64_t gen8_noncanonical_addr(uint64_t address)
309{
310 return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1);
311}
312
313static inline uint64_t
314relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
315 uint64_t target_offset)
316{
317 return gen8_canonical_addr((int)reloc->delta + target_offset);
318}
319
320struct reloc_cache {
321 struct drm_i915_private *i915;
322 struct drm_mm_node node;
323 unsigned long vaddr;
324 unsigned int page;
325 bool use_64bit_reloc;
326};
327
328static void reloc_cache_init(struct reloc_cache *cache,
329 struct drm_i915_private *i915)
330{
331 cache->page = -1;
332 cache->vaddr = 0;
333 cache->i915 = i915;
334 /* Must be a variable in the struct to allow GCC to unroll. */
335 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
336 cache->node.allocated = false;
337}
338
339static inline void *unmask_page(unsigned long p)
340{
341 return (void *)(uintptr_t)(p & PAGE_MASK);
342}
343
344static inline unsigned int unmask_flags(unsigned long p)
345{
346 return p & ~PAGE_MASK;
347}
348
349#define KMAP 0x4 /* after CLFLUSH_FLAGS */
350
351static void reloc_cache_fini(struct reloc_cache *cache)
352{
353 void *vaddr;
354
355 if (!cache->vaddr)
356 return;
357
358 vaddr = unmask_page(cache->vaddr);
359 if (cache->vaddr & KMAP) {
360 if (cache->vaddr & CLFLUSH_AFTER)
361 mb();
362
363 kunmap_atomic(vaddr);
364 i915_gem_obj_finish_shmem_access((struct drm_i915_gem_object *)cache->node.mm);
365 } else {
366 wmb();
367 io_mapping_unmap_atomic((void __iomem *)vaddr);
368 if (cache->node.allocated) {
369 struct i915_ggtt *ggtt = &cache->i915->ggtt;
370
371 ggtt->base.clear_range(&ggtt->base,
372 cache->node.start,
373 cache->node.size);
374 drm_mm_remove_node(&cache->node);
375 } else {
376 i915_vma_unpin((struct i915_vma *)cache->node.mm);
377 }
378 }
379}
380
381static void *reloc_kmap(struct drm_i915_gem_object *obj,
382 struct reloc_cache *cache,
383 int page)
384{
385 void *vaddr;
386
387 if (cache->vaddr) {
388 kunmap_atomic(unmask_page(cache->vaddr));
389 } else {
390 unsigned int flushes;
391 int ret;
392
393 ret = i915_gem_obj_prepare_shmem_write(obj, &flushes);
394 if (ret)
395 return ERR_PTR(ret);
396
397 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
398 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
399
400 cache->vaddr = flushes | KMAP;
401 cache->node.mm = (void *)obj;
402 if (flushes)
403 mb();
404 }
405
406 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
407 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
408 cache->page = page;
409
410 return vaddr;
411}
412
413static void *reloc_iomap(struct drm_i915_gem_object *obj,
414 struct reloc_cache *cache,
415 int page)
416{
417 struct i915_ggtt *ggtt = &cache->i915->ggtt;
418 unsigned long offset;
419 void *vaddr;
420
421 if (cache->vaddr) {
422 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
423 } else {
424 struct i915_vma *vma;
425 int ret;
426
427 if (use_cpu_reloc(obj))
428 return NULL;
429
430 ret = i915_gem_object_set_to_gtt_domain(obj, true);
431 if (ret)
432 return ERR_PTR(ret);
433
434 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
435 PIN_MAPPABLE | PIN_NONBLOCK);
436 if (IS_ERR(vma)) {
437 memset(&cache->node, 0, sizeof(cache->node));
438 ret = drm_mm_insert_node_in_range_generic
439 (&ggtt->base.mm, &cache->node,
440 4096, 0, 0,
441 0, ggtt->mappable_end,
442 DRM_MM_SEARCH_DEFAULT,
443 DRM_MM_CREATE_DEFAULT);
444 if (ret) /* no inactive aperture space, use cpu reloc */
445 return NULL;
446 } else {
447 ret = i915_vma_put_fence(vma);
448 if (ret) {
449 i915_vma_unpin(vma);
450 return ERR_PTR(ret);
451 }
452
453 cache->node.start = vma->node.start;
454 cache->node.mm = (void *)vma;
455 }
456 }
457
458 offset = cache->node.start;
459 if (cache->node.allocated) {
460 wmb();
461 ggtt->base.insert_page(&ggtt->base,
462 i915_gem_object_get_dma_address(obj, page),
463 offset, I915_CACHE_NONE, 0);
464 } else {
465 offset += page << PAGE_SHIFT;
466 }
467
468 vaddr = (void __force *) io_mapping_map_atomic_wc(&cache->i915->ggtt.mappable, offset);
469 cache->page = page;
470 cache->vaddr = (unsigned long)vaddr;
471
472 return vaddr;
473}
474
475static void *reloc_vaddr(struct drm_i915_gem_object *obj,
476 struct reloc_cache *cache,
477 int page)
478{
479 void *vaddr;
480
481 if (cache->page == page) {
482 vaddr = unmask_page(cache->vaddr);
483 } else {
484 vaddr = NULL;
485 if ((cache->vaddr & KMAP) == 0)
486 vaddr = reloc_iomap(obj, cache, page);
487 if (!vaddr)
488 vaddr = reloc_kmap(obj, cache, page);
489 }
490
491 return vaddr;
492}
493
494static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
495{
496 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
497 if (flushes & CLFLUSH_BEFORE) {
498 clflushopt(addr);
499 mb();
500 }
501
502 *addr = value;
503
504 /* Writes to the same cacheline are serialised by the CPU
505 * (including clflush). On the write path, we only require
506 * that it hits memory in an orderly fashion and place
507 * mb barriers at the start and end of the relocation phase
508 * to ensure ordering of clflush wrt to the system.
509 */
510 if (flushes & CLFLUSH_AFTER)
511 clflushopt(addr);
512 } else
513 *addr = value;
514}
515
516static int
517relocate_entry(struct drm_i915_gem_object *obj,
518 const struct drm_i915_gem_relocation_entry *reloc,
519 struct reloc_cache *cache,
520 u64 target_offset)
521{
522 u64 offset = reloc->offset;
523 bool wide = cache->use_64bit_reloc;
524 void *vaddr;
525
526 target_offset = relocation_target(reloc, target_offset);
527repeat:
528 vaddr = reloc_vaddr(obj, cache, offset >> PAGE_SHIFT);
529 if (IS_ERR(vaddr))
530 return PTR_ERR(vaddr);
531
532 clflush_write32(vaddr + offset_in_page(offset),
533 lower_32_bits(target_offset),
534 cache->vaddr);
535
536 if (wide) {
537 offset += sizeof(u32);
538 target_offset >>= 32;
539 wide = false;
540 goto repeat;
541 }
542
543 return 0;
544}
545
546static int
547i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
548 struct eb_vmas *eb,
549 struct drm_i915_gem_relocation_entry *reloc,
550 struct reloc_cache *cache)
551{
552 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
553 struct drm_gem_object *target_obj;
554 struct drm_i915_gem_object *target_i915_obj;
555 struct i915_vma *target_vma;
556 uint64_t target_offset;
557 int ret;
558
559 /* we've already hold a reference to all valid objects */
560 target_vma = eb_get_vma(eb, reloc->target_handle);
561 if (unlikely(target_vma == NULL))
562 return -ENOENT;
563 target_i915_obj = target_vma->obj;
564 target_obj = &target_vma->obj->base;
565
566 target_offset = gen8_canonical_addr(target_vma->node.start);
567
568 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
569 * pipe_control writes because the gpu doesn't properly redirect them
570 * through the ppgtt for non_secure batchbuffers. */
571 if (unlikely(IS_GEN6(dev_priv) &&
572 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
573 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
574 PIN_GLOBAL);
575 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
576 return ret;
577 }
578
579 /* Validate that the target is in a valid r/w GPU domain */
580 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
581 DRM_DEBUG("reloc with multiple write domains: "
582 "obj %p target %d offset %d "
583 "read %08x write %08x",
584 obj, reloc->target_handle,
585 (int) reloc->offset,
586 reloc->read_domains,
587 reloc->write_domain);
588 return -EINVAL;
589 }
590 if (unlikely((reloc->write_domain | reloc->read_domains)
591 & ~I915_GEM_GPU_DOMAINS)) {
592 DRM_DEBUG("reloc with read/write non-GPU domains: "
593 "obj %p target %d offset %d "
594 "read %08x write %08x",
595 obj, reloc->target_handle,
596 (int) reloc->offset,
597 reloc->read_domains,
598 reloc->write_domain);
599 return -EINVAL;
600 }
601
602 target_obj->pending_read_domains |= reloc->read_domains;
603 target_obj->pending_write_domain |= reloc->write_domain;
604
605 /* If the relocation already has the right value in it, no
606 * more work needs to be done.
607 */
608 if (target_offset == reloc->presumed_offset)
609 return 0;
610
611 /* Check that the relocation address is valid... */
612 if (unlikely(reloc->offset >
613 obj->base.size - (cache->use_64bit_reloc ? 8 : 4))) {
614 DRM_DEBUG("Relocation beyond object bounds: "
615 "obj %p target %d offset %d size %d.\n",
616 obj, reloc->target_handle,
617 (int) reloc->offset,
618 (int) obj->base.size);
619 return -EINVAL;
620 }
621 if (unlikely(reloc->offset & 3)) {
622 DRM_DEBUG("Relocation not 4-byte aligned: "
623 "obj %p target %d offset %d.\n",
624 obj, reloc->target_handle,
625 (int) reloc->offset);
626 return -EINVAL;
627 }
628
629 ret = relocate_entry(obj, reloc, cache, target_offset);
630 if (ret)
631 return ret;
632
633 /* and update the user's relocation entry */
634 reloc->presumed_offset = target_offset;
635 return 0;
636}
637
638static int
639i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
640 struct eb_vmas *eb)
641{
642#define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
643 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
644 struct drm_i915_gem_relocation_entry __user *user_relocs;
645 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
646 struct reloc_cache cache;
647 int remain, ret = 0;
648
649 user_relocs = u64_to_user_ptr(entry->relocs_ptr);
650 reloc_cache_init(&cache, eb->i915);
651
652 remain = entry->relocation_count;
653 while (remain) {
654 struct drm_i915_gem_relocation_entry *r = stack_reloc;
655 unsigned long unwritten;
656 unsigned int count;
657
658 count = min_t(unsigned int, remain, ARRAY_SIZE(stack_reloc));
659 remain -= count;
660
661 /* This is the fast path and we cannot handle a pagefault
662 * whilst holding the struct mutex lest the user pass in the
663 * relocations contained within a mmaped bo. For in such a case
664 * we, the page fault handler would call i915_gem_fault() and
665 * we would try to acquire the struct mutex again. Obviously
666 * this is bad and so lockdep complains vehemently.
667 */
668 pagefault_disable();
669 unwritten = __copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]));
670 pagefault_enable();
671 if (unlikely(unwritten)) {
672 ret = -EFAULT;
673 goto out;
674 }
675
676 do {
677 u64 offset = r->presumed_offset;
678
679 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r, &cache);
680 if (ret)
681 goto out;
682
683 if (r->presumed_offset != offset) {
684 pagefault_disable();
685 unwritten = __put_user(r->presumed_offset,
686 &user_relocs->presumed_offset);
687 pagefault_enable();
688 if (unlikely(unwritten)) {
689 /* Note that reporting an error now
690 * leaves everything in an inconsistent
691 * state as we have *already* changed
692 * the relocation value inside the
693 * object. As we have not changed the
694 * reloc.presumed_offset or will not
695 * change the execobject.offset, on the
696 * call we may not rewrite the value
697 * inside the object, leaving it
698 * dangling and causing a GPU hang.
699 */
700 ret = -EFAULT;
701 goto out;
702 }
703 }
704
705 user_relocs++;
706 r++;
707 } while (--count);
708 }
709
710out:
711 reloc_cache_fini(&cache);
712 return ret;
713#undef N_RELOC
714}
715
716static int
717i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
718 struct eb_vmas *eb,
719 struct drm_i915_gem_relocation_entry *relocs)
720{
721 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
722 struct reloc_cache cache;
723 int i, ret = 0;
724
725 reloc_cache_init(&cache, eb->i915);
726 for (i = 0; i < entry->relocation_count; i++) {
727 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i], &cache);
728 if (ret)
729 break;
730 }
731 reloc_cache_fini(&cache);
732
733 return ret;
734}
735
736static int
737i915_gem_execbuffer_relocate(struct eb_vmas *eb)
738{
739 struct i915_vma *vma;
740 int ret = 0;
741
742 list_for_each_entry(vma, &eb->vmas, exec_list) {
743 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
744 if (ret)
745 break;
746 }
747
748 return ret;
749}
750
751static bool only_mappable_for_reloc(unsigned int flags)
752{
753 return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
754 __EXEC_OBJECT_NEEDS_MAP;
755}
756
757static int
758i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
759 struct intel_engine_cs *engine,
760 bool *need_reloc)
761{
762 struct drm_i915_gem_object *obj = vma->obj;
763 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
764 uint64_t flags;
765 int ret;
766
767 flags = PIN_USER;
768 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
769 flags |= PIN_GLOBAL;
770
771 if (!drm_mm_node_allocated(&vma->node)) {
772 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
773 * limit address to the first 4GBs for unflagged objects.
774 */
775 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
776 flags |= PIN_ZONE_4G;
777 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
778 flags |= PIN_GLOBAL | PIN_MAPPABLE;
779 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
780 flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
781 if (entry->flags & EXEC_OBJECT_PINNED)
782 flags |= entry->offset | PIN_OFFSET_FIXED;
783 if ((flags & PIN_MAPPABLE) == 0)
784 flags |= PIN_HIGH;
785 }
786
787 ret = i915_vma_pin(vma,
788 entry->pad_to_size,
789 entry->alignment,
790 flags);
791 if ((ret == -ENOSPC || ret == -E2BIG) &&
792 only_mappable_for_reloc(entry->flags))
793 ret = i915_vma_pin(vma,
794 entry->pad_to_size,
795 entry->alignment,
796 flags & ~PIN_MAPPABLE);
797 if (ret)
798 return ret;
799
800 entry->flags |= __EXEC_OBJECT_HAS_PIN;
801
802 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
803 ret = i915_vma_get_fence(vma);
804 if (ret)
805 return ret;
806
807 if (i915_vma_pin_fence(vma))
808 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
809 }
810
811 if (entry->offset != vma->node.start) {
812 entry->offset = vma->node.start;
813 *need_reloc = true;
814 }
815
816 if (entry->flags & EXEC_OBJECT_WRITE) {
817 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
818 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
819 }
820
821 return 0;
822}
823
824static bool
825need_reloc_mappable(struct i915_vma *vma)
826{
827 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
828
829 if (entry->relocation_count == 0)
830 return false;
831
832 if (!i915_vma_is_ggtt(vma))
833 return false;
834
835 /* See also use_cpu_reloc() */
836 if (HAS_LLC(to_i915(vma->obj->base.dev)))
837 return false;
838
839 if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
840 return false;
841
842 return true;
843}
844
845static bool
846eb_vma_misplaced(struct i915_vma *vma)
847{
848 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
849
850 WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
851 !i915_vma_is_ggtt(vma));
852
853 if (entry->alignment &&
854 vma->node.start & (entry->alignment - 1))
855 return true;
856
857 if (vma->node.size < entry->pad_to_size)
858 return true;
859
860 if (entry->flags & EXEC_OBJECT_PINNED &&
861 vma->node.start != entry->offset)
862 return true;
863
864 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
865 vma->node.start < BATCH_OFFSET_BIAS)
866 return true;
867
868 /* avoid costly ping-pong once a batch bo ended up non-mappable */
869 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
870 !i915_vma_is_map_and_fenceable(vma))
871 return !only_mappable_for_reloc(entry->flags);
872
873 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
874 (vma->node.start + vma->node.size - 1) >> 32)
875 return true;
876
877 return false;
878}
879
880static int
881i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
882 struct list_head *vmas,
883 struct i915_gem_context *ctx,
884 bool *need_relocs)
885{
886 struct drm_i915_gem_object *obj;
887 struct i915_vma *vma;
888 struct i915_address_space *vm;
889 struct list_head ordered_vmas;
890 struct list_head pinned_vmas;
891 bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
892 int retry;
893
894 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
895
896 INIT_LIST_HEAD(&ordered_vmas);
897 INIT_LIST_HEAD(&pinned_vmas);
898 while (!list_empty(vmas)) {
899 struct drm_i915_gem_exec_object2 *entry;
900 bool need_fence, need_mappable;
901
902 vma = list_first_entry(vmas, struct i915_vma, exec_list);
903 obj = vma->obj;
904 entry = vma->exec_entry;
905
906 if (ctx->flags & CONTEXT_NO_ZEROMAP)
907 entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
908
909 if (!has_fenced_gpu_access)
910 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
911 need_fence =
912 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
913 i915_gem_object_is_tiled(obj);
914 need_mappable = need_fence || need_reloc_mappable(vma);
915
916 if (entry->flags & EXEC_OBJECT_PINNED)
917 list_move_tail(&vma->exec_list, &pinned_vmas);
918 else if (need_mappable) {
919 entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
920 list_move(&vma->exec_list, &ordered_vmas);
921 } else
922 list_move_tail(&vma->exec_list, &ordered_vmas);
923
924 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
925 obj->base.pending_write_domain = 0;
926 }
927 list_splice(&ordered_vmas, vmas);
928 list_splice(&pinned_vmas, vmas);
929
930 /* Attempt to pin all of the buffers into the GTT.
931 * This is done in 3 phases:
932 *
933 * 1a. Unbind all objects that do not match the GTT constraints for
934 * the execbuffer (fenceable, mappable, alignment etc).
935 * 1b. Increment pin count for already bound objects.
936 * 2. Bind new objects.
937 * 3. Decrement pin count.
938 *
939 * This avoid unnecessary unbinding of later objects in order to make
940 * room for the earlier objects *unless* we need to defragment.
941 */
942 retry = 0;
943 do {
944 int ret = 0;
945
946 /* Unbind any ill-fitting objects or pin. */
947 list_for_each_entry(vma, vmas, exec_list) {
948 if (!drm_mm_node_allocated(&vma->node))
949 continue;
950
951 if (eb_vma_misplaced(vma))
952 ret = i915_vma_unbind(vma);
953 else
954 ret = i915_gem_execbuffer_reserve_vma(vma,
955 engine,
956 need_relocs);
957 if (ret)
958 goto err;
959 }
960
961 /* Bind fresh objects */
962 list_for_each_entry(vma, vmas, exec_list) {
963 if (drm_mm_node_allocated(&vma->node))
964 continue;
965
966 ret = i915_gem_execbuffer_reserve_vma(vma, engine,
967 need_relocs);
968 if (ret)
969 goto err;
970 }
971
972err:
973 if (ret != -ENOSPC || retry++)
974 return ret;
975
976 /* Decrement pin count for bound objects */
977 list_for_each_entry(vma, vmas, exec_list)
978 i915_gem_execbuffer_unreserve_vma(vma);
979
980 ret = i915_gem_evict_vm(vm, true);
981 if (ret)
982 return ret;
983 } while (1);
984}
985
986static int
987i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
988 struct drm_i915_gem_execbuffer2 *args,
989 struct drm_file *file,
990 struct intel_engine_cs *engine,
991 struct eb_vmas *eb,
992 struct drm_i915_gem_exec_object2 *exec,
993 struct i915_gem_context *ctx)
994{
995 struct drm_i915_gem_relocation_entry *reloc;
996 struct i915_address_space *vm;
997 struct i915_vma *vma;
998 bool need_relocs;
999 int *reloc_offset;
1000 int i, total, ret;
1001 unsigned count = args->buffer_count;
1002
1003 vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
1004
1005 /* We may process another execbuffer during the unlock... */
1006 while (!list_empty(&eb->vmas)) {
1007 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
1008 list_del_init(&vma->exec_list);
1009 i915_gem_execbuffer_unreserve_vma(vma);
1010 i915_vma_put(vma);
1011 }
1012
1013 mutex_unlock(&dev->struct_mutex);
1014
1015 total = 0;
1016 for (i = 0; i < count; i++)
1017 total += exec[i].relocation_count;
1018
1019 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
1020 reloc = drm_malloc_ab(total, sizeof(*reloc));
1021 if (reloc == NULL || reloc_offset == NULL) {
1022 drm_free_large(reloc);
1023 drm_free_large(reloc_offset);
1024 mutex_lock(&dev->struct_mutex);
1025 return -ENOMEM;
1026 }
1027
1028 total = 0;
1029 for (i = 0; i < count; i++) {
1030 struct drm_i915_gem_relocation_entry __user *user_relocs;
1031 u64 invalid_offset = (u64)-1;
1032 int j;
1033
1034 user_relocs = u64_to_user_ptr(exec[i].relocs_ptr);
1035
1036 if (copy_from_user(reloc+total, user_relocs,
1037 exec[i].relocation_count * sizeof(*reloc))) {
1038 ret = -EFAULT;
1039 mutex_lock(&dev->struct_mutex);
1040 goto err;
1041 }
1042
1043 /* As we do not update the known relocation offsets after
1044 * relocating (due to the complexities in lock handling),
1045 * we need to mark them as invalid now so that we force the
1046 * relocation processing next time. Just in case the target
1047 * object is evicted and then rebound into its old
1048 * presumed_offset before the next execbuffer - if that
1049 * happened we would make the mistake of assuming that the
1050 * relocations were valid.
1051 */
1052 for (j = 0; j < exec[i].relocation_count; j++) {
1053 if (__copy_to_user(&user_relocs[j].presumed_offset,
1054 &invalid_offset,
1055 sizeof(invalid_offset))) {
1056 ret = -EFAULT;
1057 mutex_lock(&dev->struct_mutex);
1058 goto err;
1059 }
1060 }
1061
1062 reloc_offset[i] = total;
1063 total += exec[i].relocation_count;
1064 }
1065
1066 ret = i915_mutex_lock_interruptible(dev);
1067 if (ret) {
1068 mutex_lock(&dev->struct_mutex);
1069 goto err;
1070 }
1071
1072 /* reacquire the objects */
1073 eb_reset(eb);
1074 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1075 if (ret)
1076 goto err;
1077
1078 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1079 ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
1080 &need_relocs);
1081 if (ret)
1082 goto err;
1083
1084 list_for_each_entry(vma, &eb->vmas, exec_list) {
1085 int offset = vma->exec_entry - exec;
1086 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
1087 reloc + reloc_offset[offset]);
1088 if (ret)
1089 goto err;
1090 }
1091
1092 /* Leave the user relocations as are, this is the painfully slow path,
1093 * and we want to avoid the complication of dropping the lock whilst
1094 * having buffers reserved in the aperture and so causing spurious
1095 * ENOSPC for random operations.
1096 */
1097
1098err:
1099 drm_free_large(reloc);
1100 drm_free_large(reloc_offset);
1101 return ret;
1102}
1103
1104static int
1105i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
1106 struct list_head *vmas)
1107{
1108 struct i915_vma *vma;
1109 int ret;
1110
1111 list_for_each_entry(vma, vmas, exec_list) {
1112 struct drm_i915_gem_object *obj = vma->obj;
1113
1114 ret = i915_gem_request_await_object
1115 (req, obj, obj->base.pending_write_domain);
1116 if (ret)
1117 return ret;
1118
1119 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
1120 i915_gem_clflush_object(obj, false);
1121 }
1122
1123 /* Unconditionally flush any chipset caches (for streaming writes). */
1124 i915_gem_chipset_flush(req->engine->i915);
1125
1126 /* Unconditionally invalidate GPU caches and TLBs. */
1127 return req->engine->emit_flush(req, EMIT_INVALIDATE);
1128}
1129
1130static bool
1131i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1132{
1133 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
1134 return false;
1135
1136 /* Kernel clipping was a DRI1 misfeature */
1137 if (exec->num_cliprects || exec->cliprects_ptr)
1138 return false;
1139
1140 if (exec->DR4 == 0xffffffff) {
1141 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1142 exec->DR4 = 0;
1143 }
1144 if (exec->DR1 || exec->DR4)
1145 return false;
1146
1147 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1148 return false;
1149
1150 return true;
1151}
1152
1153static int
1154validate_exec_list(struct drm_device *dev,
1155 struct drm_i915_gem_exec_object2 *exec,
1156 int count)
1157{
1158 unsigned relocs_total = 0;
1159 unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
1160 unsigned invalid_flags;
1161 int i;
1162
1163 /* INTERNAL flags must not overlap with external ones */
1164 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & ~__EXEC_OBJECT_UNKNOWN_FLAGS);
1165
1166 invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
1167 if (USES_FULL_PPGTT(dev))
1168 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
1169
1170 for (i = 0; i < count; i++) {
1171 char __user *ptr = u64_to_user_ptr(exec[i].relocs_ptr);
1172 int length; /* limited by fault_in_pages_readable() */
1173
1174 if (exec[i].flags & invalid_flags)
1175 return -EINVAL;
1176
1177 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1178 * any non-page-aligned or non-canonical addresses.
1179 */
1180 if (exec[i].flags & EXEC_OBJECT_PINNED) {
1181 if (exec[i].offset !=
1182 gen8_canonical_addr(exec[i].offset & PAGE_MASK))
1183 return -EINVAL;
1184 }
1185
1186 /* From drm_mm perspective address space is continuous,
1187 * so from this point we're always using non-canonical
1188 * form internally.
1189 */
1190 exec[i].offset = gen8_noncanonical_addr(exec[i].offset);
1191
1192 if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
1193 return -EINVAL;
1194
1195 /* pad_to_size was once a reserved field, so sanitize it */
1196 if (exec[i].flags & EXEC_OBJECT_PAD_TO_SIZE) {
1197 if (offset_in_page(exec[i].pad_to_size))
1198 return -EINVAL;
1199 } else {
1200 exec[i].pad_to_size = 0;
1201 }
1202
1203 /* First check for malicious input causing overflow in
1204 * the worst case where we need to allocate the entire
1205 * relocation tree as a single array.
1206 */
1207 if (exec[i].relocation_count > relocs_max - relocs_total)
1208 return -EINVAL;
1209 relocs_total += exec[i].relocation_count;
1210
1211 length = exec[i].relocation_count *
1212 sizeof(struct drm_i915_gem_relocation_entry);
1213 /*
1214 * We must check that the entire relocation array is safe
1215 * to read, but since we may need to update the presumed
1216 * offsets during execution, check for full write access.
1217 */
1218 if (!access_ok(VERIFY_WRITE, ptr, length))
1219 return -EFAULT;
1220
1221 if (likely(!i915.prefault_disable)) {
1222 if (fault_in_pages_readable(ptr, length))
1223 return -EFAULT;
1224 }
1225 }
1226
1227 return 0;
1228}
1229
1230static struct i915_gem_context *
1231i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
1232 struct intel_engine_cs *engine, const u32 ctx_id)
1233{
1234 struct i915_gem_context *ctx;
1235 struct i915_ctx_hang_stats *hs;
1236
1237 ctx = i915_gem_context_lookup(file->driver_priv, ctx_id);
1238 if (IS_ERR(ctx))
1239 return ctx;
1240
1241 hs = &ctx->hang_stats;
1242 if (hs->banned) {
1243 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
1244 return ERR_PTR(-EIO);
1245 }
1246
1247 return ctx;
1248}
1249
1250static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
1251{
1252 return !(obj->cache_level == I915_CACHE_NONE ||
1253 obj->cache_level == I915_CACHE_WT);
1254}
1255
1256void i915_vma_move_to_active(struct i915_vma *vma,
1257 struct drm_i915_gem_request *req,
1258 unsigned int flags)
1259{
1260 struct drm_i915_gem_object *obj = vma->obj;
1261 const unsigned int idx = req->engine->id;
1262
1263 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1264
1265 /* Add a reference if we're newly entering the active list.
1266 * The order in which we add operations to the retirement queue is
1267 * vital here: mark_active adds to the start of the callback list,
1268 * such that subsequent callbacks are called first. Therefore we
1269 * add the active reference first and queue for it to be dropped
1270 * *last*.
1271 */
1272 if (!i915_vma_is_active(vma))
1273 obj->active_count++;
1274 i915_vma_set_active(vma, idx);
1275 i915_gem_active_set(&vma->last_read[idx], req);
1276 list_move_tail(&vma->vm_link, &vma->vm->active_list);
1277
1278 if (flags & EXEC_OBJECT_WRITE) {
1279 if (intel_fb_obj_invalidate(obj, ORIGIN_CS))
1280 i915_gem_active_set(&obj->frontbuffer_write, req);
1281
1282 /* update for the implicit flush after a batch */
1283 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1284 if (!obj->cache_dirty && gpu_write_needs_clflush(obj))
1285 obj->cache_dirty = true;
1286 }
1287
1288 if (flags & EXEC_OBJECT_NEEDS_FENCE)
1289 i915_gem_active_set(&vma->last_fence, req);
1290}
1291
1292static void eb_export_fence(struct drm_i915_gem_object *obj,
1293 struct drm_i915_gem_request *req,
1294 unsigned int flags)
1295{
1296 struct reservation_object *resv = obj->resv;
1297
1298 /* Ignore errors from failing to allocate the new fence, we can't
1299 * handle an error right now. Worst case should be missed
1300 * synchronisation leading to rendering corruption.
1301 */
1302 ww_mutex_lock(&resv->lock, NULL);
1303 if (flags & EXEC_OBJECT_WRITE)
1304 reservation_object_add_excl_fence(resv, &req->fence);
1305 else if (reservation_object_reserve_shared(resv) == 0)
1306 reservation_object_add_shared_fence(resv, &req->fence);
1307 ww_mutex_unlock(&resv->lock);
1308}
1309
1310static void
1311i915_gem_execbuffer_move_to_active(struct list_head *vmas,
1312 struct drm_i915_gem_request *req)
1313{
1314 struct i915_vma *vma;
1315
1316 list_for_each_entry(vma, vmas, exec_list) {
1317 struct drm_i915_gem_object *obj = vma->obj;
1318 u32 old_read = obj->base.read_domains;
1319 u32 old_write = obj->base.write_domain;
1320
1321 obj->base.write_domain = obj->base.pending_write_domain;
1322 if (obj->base.write_domain)
1323 vma->exec_entry->flags |= EXEC_OBJECT_WRITE;
1324 else
1325 obj->base.pending_read_domains |= obj->base.read_domains;
1326 obj->base.read_domains = obj->base.pending_read_domains;
1327
1328 i915_vma_move_to_active(vma, req, vma->exec_entry->flags);
1329 eb_export_fence(obj, req, vma->exec_entry->flags);
1330 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1331 }
1332}
1333
1334static int
1335i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
1336{
1337 struct intel_ring *ring = req->ring;
1338 int ret, i;
1339
1340 if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
1341 DRM_DEBUG("sol reset is gen7/rcs only\n");
1342 return -EINVAL;
1343 }
1344
1345 ret = intel_ring_begin(req, 4 * 3);
1346 if (ret)
1347 return ret;
1348
1349 for (i = 0; i < 4; i++) {
1350 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1351 intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i));
1352 intel_ring_emit(ring, 0);
1353 }
1354
1355 intel_ring_advance(ring);
1356
1357 return 0;
1358}
1359
1360static struct i915_vma *
1361i915_gem_execbuffer_parse(struct intel_engine_cs *engine,
1362 struct drm_i915_gem_exec_object2 *shadow_exec_entry,
1363 struct drm_i915_gem_object *batch_obj,
1364 struct eb_vmas *eb,
1365 u32 batch_start_offset,
1366 u32 batch_len,
1367 bool is_master)
1368{
1369 struct drm_i915_gem_object *shadow_batch_obj;
1370 struct i915_vma *vma;
1371 int ret;
1372
1373 shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool,
1374 PAGE_ALIGN(batch_len));
1375 if (IS_ERR(shadow_batch_obj))
1376 return ERR_CAST(shadow_batch_obj);
1377
1378 ret = intel_engine_cmd_parser(engine,
1379 batch_obj,
1380 shadow_batch_obj,
1381 batch_start_offset,
1382 batch_len,
1383 is_master);
1384 if (ret) {
1385 if (ret == -EACCES) /* unhandled chained batch */
1386 vma = NULL;
1387 else
1388 vma = ERR_PTR(ret);
1389 goto out;
1390 }
1391
1392 vma = i915_gem_object_ggtt_pin(shadow_batch_obj, NULL, 0, 0, 0);
1393 if (IS_ERR(vma))
1394 goto out;
1395
1396 memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
1397
1398 vma->exec_entry = shadow_exec_entry;
1399 vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1400 i915_gem_object_get(shadow_batch_obj);
1401 list_add_tail(&vma->exec_list, &eb->vmas);
1402
1403out:
1404 i915_gem_object_unpin_pages(shadow_batch_obj);
1405 return vma;
1406}
1407
1408static int
1409execbuf_submit(struct i915_execbuffer_params *params,
1410 struct drm_i915_gem_execbuffer2 *args,
1411 struct list_head *vmas)
1412{
1413 u64 exec_start, exec_len;
1414 int ret;
1415
1416 ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
1417 if (ret)
1418 return ret;
1419
1420 ret = i915_switch_context(params->request);
1421 if (ret)
1422 return ret;
1423
1424 if (args->flags & I915_EXEC_CONSTANTS_MASK) {
1425 DRM_DEBUG("I915_EXEC_CONSTANTS_* unsupported\n");
1426 return -EINVAL;
1427 }
1428
1429 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1430 ret = i915_reset_gen7_sol_offsets(params->request);
1431 if (ret)
1432 return ret;
1433 }
1434
1435 exec_len = args->batch_len;
1436 exec_start = params->batch->node.start +
1437 params->args_batch_start_offset;
1438
1439 if (exec_len == 0)
1440 exec_len = params->batch->size - params->args_batch_start_offset;
1441
1442 ret = params->engine->emit_bb_start(params->request,
1443 exec_start, exec_len,
1444 params->dispatch_flags);
1445 if (ret)
1446 return ret;
1447
1448 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1449
1450 i915_gem_execbuffer_move_to_active(vmas, params->request);
1451
1452 return 0;
1453}
1454
1455/**
1456 * Find one BSD ring to dispatch the corresponding BSD command.
1457 * The engine index is returned.
1458 */
1459static unsigned int
1460gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
1461 struct drm_file *file)
1462{
1463 struct drm_i915_file_private *file_priv = file->driver_priv;
1464
1465 /* Check whether the file_priv has already selected one ring. */
1466 if ((int)file_priv->bsd_engine < 0)
1467 file_priv->bsd_engine = atomic_fetch_xor(1,
1468 &dev_priv->mm.bsd_engine_dispatch_index);
1469
1470 return file_priv->bsd_engine;
1471}
1472
1473#define I915_USER_RINGS (4)
1474
1475static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
1476 [I915_EXEC_DEFAULT] = RCS,
1477 [I915_EXEC_RENDER] = RCS,
1478 [I915_EXEC_BLT] = BCS,
1479 [I915_EXEC_BSD] = VCS,
1480 [I915_EXEC_VEBOX] = VECS
1481};
1482
1483static struct intel_engine_cs *
1484eb_select_engine(struct drm_i915_private *dev_priv,
1485 struct drm_file *file,
1486 struct drm_i915_gem_execbuffer2 *args)
1487{
1488 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
1489 struct intel_engine_cs *engine;
1490
1491 if (user_ring_id > I915_USER_RINGS) {
1492 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
1493 return NULL;
1494 }
1495
1496 if ((user_ring_id != I915_EXEC_BSD) &&
1497 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1498 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1499 "bsd dispatch flags: %d\n", (int)(args->flags));
1500 return NULL;
1501 }
1502
1503 if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
1504 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
1505
1506 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
1507 bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
1508 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
1509 bsd_idx <= I915_EXEC_BSD_RING2) {
1510 bsd_idx >>= I915_EXEC_BSD_SHIFT;
1511 bsd_idx--;
1512 } else {
1513 DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
1514 bsd_idx);
1515 return NULL;
1516 }
1517
1518 engine = dev_priv->engine[_VCS(bsd_idx)];
1519 } else {
1520 engine = dev_priv->engine[user_ring_map[user_ring_id]];
1521 }
1522
1523 if (!engine) {
1524 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
1525 return NULL;
1526 }
1527
1528 return engine;
1529}
1530
1531static int
1532i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1533 struct drm_file *file,
1534 struct drm_i915_gem_execbuffer2 *args,
1535 struct drm_i915_gem_exec_object2 *exec)
1536{
1537 struct drm_i915_private *dev_priv = to_i915(dev);
1538 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1539 struct eb_vmas *eb;
1540 struct drm_i915_gem_exec_object2 shadow_exec_entry;
1541 struct intel_engine_cs *engine;
1542 struct i915_gem_context *ctx;
1543 struct i915_address_space *vm;
1544 struct i915_execbuffer_params params_master; /* XXX: will be removed later */
1545 struct i915_execbuffer_params *params = ¶ms_master;
1546 const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1547 u32 dispatch_flags;
1548 int ret;
1549 bool need_relocs;
1550
1551 if (!i915_gem_check_execbuffer(args))
1552 return -EINVAL;
1553
1554 ret = validate_exec_list(dev, exec, args->buffer_count);
1555 if (ret)
1556 return ret;
1557
1558 dispatch_flags = 0;
1559 if (args->flags & I915_EXEC_SECURE) {
1560 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
1561 return -EPERM;
1562
1563 dispatch_flags |= I915_DISPATCH_SECURE;
1564 }
1565 if (args->flags & I915_EXEC_IS_PINNED)
1566 dispatch_flags |= I915_DISPATCH_PINNED;
1567
1568 engine = eb_select_engine(dev_priv, file, args);
1569 if (!engine)
1570 return -EINVAL;
1571
1572 if (args->buffer_count < 1) {
1573 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1574 return -EINVAL;
1575 }
1576
1577 if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
1578 if (!HAS_RESOURCE_STREAMER(dev_priv)) {
1579 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1580 return -EINVAL;
1581 }
1582 if (engine->id != RCS) {
1583 DRM_DEBUG("RS is not available on %s\n",
1584 engine->name);
1585 return -EINVAL;
1586 }
1587
1588 dispatch_flags |= I915_DISPATCH_RS;
1589 }
1590
1591 /* Take a local wakeref for preparing to dispatch the execbuf as
1592 * we expect to access the hardware fairly frequently in the
1593 * process. Upon first dispatch, we acquire another prolonged
1594 * wakeref that we hold until the GPU has been idle for at least
1595 * 100ms.
1596 */
1597 intel_runtime_pm_get(dev_priv);
1598
1599 ret = i915_mutex_lock_interruptible(dev);
1600 if (ret)
1601 goto pre_mutex_err;
1602
1603 ctx = i915_gem_validate_context(dev, file, engine, ctx_id);
1604 if (IS_ERR(ctx)) {
1605 mutex_unlock(&dev->struct_mutex);
1606 ret = PTR_ERR(ctx);
1607 goto pre_mutex_err;
1608 }
1609
1610 i915_gem_context_get(ctx);
1611
1612 if (ctx->ppgtt)
1613 vm = &ctx->ppgtt->base;
1614 else
1615 vm = &ggtt->base;
1616
1617 memset(¶ms_master, 0x00, sizeof(params_master));
1618
1619 eb = eb_create(dev_priv, args);
1620 if (eb == NULL) {
1621 i915_gem_context_put(ctx);
1622 mutex_unlock(&dev->struct_mutex);
1623 ret = -ENOMEM;
1624 goto pre_mutex_err;
1625 }
1626
1627 /* Look up object handles */
1628 ret = eb_lookup_vmas(eb, exec, args, vm, file);
1629 if (ret)
1630 goto err;
1631
1632 /* take note of the batch buffer before we might reorder the lists */
1633 params->batch = eb_get_batch(eb);
1634
1635 /* Move the objects en-masse into the GTT, evicting if necessary. */
1636 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1637 ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
1638 &need_relocs);
1639 if (ret)
1640 goto err;
1641
1642 /* The objects are in their final locations, apply the relocations. */
1643 if (need_relocs)
1644 ret = i915_gem_execbuffer_relocate(eb);
1645 if (ret) {
1646 if (ret == -EFAULT) {
1647 ret = i915_gem_execbuffer_relocate_slow(dev, args, file,
1648 engine,
1649 eb, exec, ctx);
1650 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1651 }
1652 if (ret)
1653 goto err;
1654 }
1655
1656 /* Set the pending read domains for the batch buffer to COMMAND */
1657 if (params->batch->obj->base.pending_write_domain) {
1658 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1659 ret = -EINVAL;
1660 goto err;
1661 }
1662 if (args->batch_start_offset > params->batch->size ||
1663 args->batch_len > params->batch->size - args->batch_start_offset) {
1664 DRM_DEBUG("Attempting to use out-of-bounds batch\n");
1665 ret = -EINVAL;
1666 goto err;
1667 }
1668
1669 params->args_batch_start_offset = args->batch_start_offset;
1670 if (intel_engine_needs_cmd_parser(engine) && args->batch_len) {
1671 struct i915_vma *vma;
1672
1673 vma = i915_gem_execbuffer_parse(engine, &shadow_exec_entry,
1674 params->batch->obj,
1675 eb,
1676 args->batch_start_offset,
1677 args->batch_len,
1678 drm_is_current_master(file));
1679 if (IS_ERR(vma)) {
1680 ret = PTR_ERR(vma);
1681 goto err;
1682 }
1683
1684 if (vma) {
1685 /*
1686 * Batch parsed and accepted:
1687 *
1688 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1689 * bit from MI_BATCH_BUFFER_START commands issued in
1690 * the dispatch_execbuffer implementations. We
1691 * specifically don't want that set on batches the
1692 * command parser has accepted.
1693 */
1694 dispatch_flags |= I915_DISPATCH_SECURE;
1695 params->args_batch_start_offset = 0;
1696 params->batch = vma;
1697 }
1698 }
1699
1700 params->batch->obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1701
1702 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1703 * batch" bit. Hence we need to pin secure batches into the global gtt.
1704 * hsw should have this fixed, but bdw mucks it up again. */
1705 if (dispatch_flags & I915_DISPATCH_SECURE) {
1706 struct drm_i915_gem_object *obj = params->batch->obj;
1707 struct i915_vma *vma;
1708
1709 /*
1710 * So on first glance it looks freaky that we pin the batch here
1711 * outside of the reservation loop. But:
1712 * - The batch is already pinned into the relevant ppgtt, so we
1713 * already have the backing storage fully allocated.
1714 * - No other BO uses the global gtt (well contexts, but meh),
1715 * so we don't really have issues with multiple objects not
1716 * fitting due to fragmentation.
1717 * So this is actually safe.
1718 */
1719 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
1720 if (IS_ERR(vma)) {
1721 ret = PTR_ERR(vma);
1722 goto err;
1723 }
1724
1725 params->batch = vma;
1726 }
1727
1728 /* Allocate a request for this batch buffer nice and early. */
1729 params->request = i915_gem_request_alloc(engine, ctx);
1730 if (IS_ERR(params->request)) {
1731 ret = PTR_ERR(params->request);
1732 goto err_batch_unpin;
1733 }
1734
1735 /* Whilst this request exists, batch_obj will be on the
1736 * active_list, and so will hold the active reference. Only when this
1737 * request is retired will the the batch_obj be moved onto the
1738 * inactive_list and lose its active reference. Hence we do not need
1739 * to explicitly hold another reference here.
1740 */
1741 params->request->batch = params->batch;
1742
1743 ret = i915_gem_request_add_to_client(params->request, file);
1744 if (ret)
1745 goto err_request;
1746
1747 /*
1748 * Save assorted stuff away to pass through to *_submission().
1749 * NB: This data should be 'persistent' and not local as it will
1750 * kept around beyond the duration of the IOCTL once the GPU
1751 * scheduler arrives.
1752 */
1753 params->dev = dev;
1754 params->file = file;
1755 params->engine = engine;
1756 params->dispatch_flags = dispatch_flags;
1757 params->ctx = ctx;
1758
1759 ret = execbuf_submit(params, args, &eb->vmas);
1760err_request:
1761 __i915_add_request(params->request, ret == 0);
1762
1763err_batch_unpin:
1764 /*
1765 * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1766 * batch vma for correctness. For less ugly and less fragility this
1767 * needs to be adjusted to also track the ggtt batch vma properly as
1768 * active.
1769 */
1770 if (dispatch_flags & I915_DISPATCH_SECURE)
1771 i915_vma_unpin(params->batch);
1772err:
1773 /* the request owns the ref now */
1774 i915_gem_context_put(ctx);
1775 eb_destroy(eb);
1776
1777 mutex_unlock(&dev->struct_mutex);
1778
1779pre_mutex_err:
1780 /* intel_gpu_busy should also get a ref, so it will free when the device
1781 * is really idle. */
1782 intel_runtime_pm_put(dev_priv);
1783 return ret;
1784}
1785
1786/*
1787 * Legacy execbuffer just creates an exec2 list from the original exec object
1788 * list array and passes it to the real function.
1789 */
1790int
1791i915_gem_execbuffer(struct drm_device *dev, void *data,
1792 struct drm_file *file)
1793{
1794 struct drm_i915_gem_execbuffer *args = data;
1795 struct drm_i915_gem_execbuffer2 exec2;
1796 struct drm_i915_gem_exec_object *exec_list = NULL;
1797 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1798 int ret, i;
1799
1800 if (args->buffer_count < 1) {
1801 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1802 return -EINVAL;
1803 }
1804
1805 /* Copy in the exec list from userland */
1806 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1807 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1808 if (exec_list == NULL || exec2_list == NULL) {
1809 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1810 args->buffer_count);
1811 drm_free_large(exec_list);
1812 drm_free_large(exec2_list);
1813 return -ENOMEM;
1814 }
1815 ret = copy_from_user(exec_list,
1816 u64_to_user_ptr(args->buffers_ptr),
1817 sizeof(*exec_list) * args->buffer_count);
1818 if (ret != 0) {
1819 DRM_DEBUG("copy %d exec entries failed %d\n",
1820 args->buffer_count, ret);
1821 drm_free_large(exec_list);
1822 drm_free_large(exec2_list);
1823 return -EFAULT;
1824 }
1825
1826 for (i = 0; i < args->buffer_count; i++) {
1827 exec2_list[i].handle = exec_list[i].handle;
1828 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1829 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1830 exec2_list[i].alignment = exec_list[i].alignment;
1831 exec2_list[i].offset = exec_list[i].offset;
1832 if (INTEL_GEN(to_i915(dev)) < 4)
1833 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1834 else
1835 exec2_list[i].flags = 0;
1836 }
1837
1838 exec2.buffers_ptr = args->buffers_ptr;
1839 exec2.buffer_count = args->buffer_count;
1840 exec2.batch_start_offset = args->batch_start_offset;
1841 exec2.batch_len = args->batch_len;
1842 exec2.DR1 = args->DR1;
1843 exec2.DR4 = args->DR4;
1844 exec2.num_cliprects = args->num_cliprects;
1845 exec2.cliprects_ptr = args->cliprects_ptr;
1846 exec2.flags = I915_EXEC_RENDER;
1847 i915_execbuffer2_set_context_id(exec2, 0);
1848
1849 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1850 if (!ret) {
1851 struct drm_i915_gem_exec_object __user *user_exec_list =
1852 u64_to_user_ptr(args->buffers_ptr);
1853
1854 /* Copy the new buffer offsets back to the user's exec list. */
1855 for (i = 0; i < args->buffer_count; i++) {
1856 exec2_list[i].offset =
1857 gen8_canonical_addr(exec2_list[i].offset);
1858 ret = __copy_to_user(&user_exec_list[i].offset,
1859 &exec2_list[i].offset,
1860 sizeof(user_exec_list[i].offset));
1861 if (ret) {
1862 ret = -EFAULT;
1863 DRM_DEBUG("failed to copy %d exec entries "
1864 "back to user (%d)\n",
1865 args->buffer_count, ret);
1866 break;
1867 }
1868 }
1869 }
1870
1871 drm_free_large(exec_list);
1872 drm_free_large(exec2_list);
1873 return ret;
1874}
1875
1876int
1877i915_gem_execbuffer2(struct drm_device *dev, void *data,
1878 struct drm_file *file)
1879{
1880 struct drm_i915_gem_execbuffer2 *args = data;
1881 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1882 int ret;
1883
1884 if (args->buffer_count < 1 ||
1885 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1886 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1887 return -EINVAL;
1888 }
1889
1890 if (args->rsvd2 != 0) {
1891 DRM_DEBUG("dirty rvsd2 field\n");
1892 return -EINVAL;
1893 }
1894
1895 exec2_list = drm_malloc_gfp(args->buffer_count,
1896 sizeof(*exec2_list),
1897 GFP_TEMPORARY);
1898 if (exec2_list == NULL) {
1899 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1900 args->buffer_count);
1901 return -ENOMEM;
1902 }
1903 ret = copy_from_user(exec2_list,
1904 u64_to_user_ptr(args->buffers_ptr),
1905 sizeof(*exec2_list) * args->buffer_count);
1906 if (ret != 0) {
1907 DRM_DEBUG("copy %d exec entries failed %d\n",
1908 args->buffer_count, ret);
1909 drm_free_large(exec2_list);
1910 return -EFAULT;
1911 }
1912
1913 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1914 if (!ret) {
1915 /* Copy the new buffer offsets back to the user's exec list. */
1916 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1917 u64_to_user_ptr(args->buffers_ptr);
1918 int i;
1919
1920 for (i = 0; i < args->buffer_count; i++) {
1921 exec2_list[i].offset =
1922 gen8_canonical_addr(exec2_list[i].offset);
1923 ret = __copy_to_user(&user_exec_list[i].offset,
1924 &exec2_list[i].offset,
1925 sizeof(user_exec_list[i].offset));
1926 if (ret) {
1927 ret = -EFAULT;
1928 DRM_DEBUG("failed to copy %d exec entries "
1929 "back to user\n",
1930 args->buffer_count);
1931 break;
1932 }
1933 }
1934 }
1935
1936 drm_free_large(exec2_list);
1937 return ret;
1938}