Loading...
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Setting up the clock on the MIPS boards.
19 */
20
21#include <linux/types.h>
22#include <linux/i8253.h>
23#include <linux/init.h>
24#include <linux/kernel_stat.h>
25#include <linux/sched.h>
26#include <linux/spinlock.h>
27#include <linux/interrupt.h>
28#include <linux/time.h>
29#include <linux/timex.h>
30#include <linux/mc146818rtc.h>
31
32#include <asm/mipsregs.h>
33#include <asm/mipsmtregs.h>
34#include <asm/hardirq.h>
35#include <asm/irq.h>
36#include <asm/div64.h>
37#include <asm/cpu.h>
38#include <asm/time.h>
39#include <asm/mc146818-time.h>
40#include <asm/msc01_ic.h>
41
42#include <asm/mips-boards/generic.h>
43#include <asm/mips-boards/prom.h>
44
45#include <asm/mips-boards/maltaint.h>
46
47unsigned long cpu_khz;
48
49static int mips_cpu_timer_irq;
50static int mips_cpu_perf_irq;
51extern int cp0_perfcount_irq;
52
53static void mips_timer_dispatch(void)
54{
55 do_IRQ(mips_cpu_timer_irq);
56}
57
58static void mips_perf_dispatch(void)
59{
60 do_IRQ(mips_cpu_perf_irq);
61}
62
63/*
64 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
65 */
66static unsigned int __init estimate_cpu_frequency(void)
67{
68 unsigned int prid = read_c0_prid() & 0xffff00;
69 unsigned int count;
70
71 unsigned long flags;
72 unsigned int start;
73
74 local_irq_save(flags);
75
76 /* Start counter exactly on falling edge of update flag */
77 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
78 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
79
80 /* Start r4k counter. */
81 start = read_c0_count();
82
83 /* Read counter exactly on falling edge of update flag */
84 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
85 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
86
87 count = read_c0_count() - start;
88
89 /* restore interrupts */
90 local_irq_restore(flags);
91
92 mips_hpt_frequency = count;
93 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
94 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
95 count *= 2;
96
97 count += 5000; /* round */
98 count -= count%10000;
99
100 return count;
101}
102
103void read_persistent_clock(struct timespec *ts)
104{
105 ts->tv_sec = mc146818_get_cmos_time();
106 ts->tv_nsec = 0;
107}
108
109static void __init plat_perf_setup(void)
110{
111#ifdef MSC01E_INT_BASE
112 if (cpu_has_veic) {
113 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
114 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
115 } else
116#endif
117 if (cp0_perfcount_irq >= 0) {
118 if (cpu_has_vint)
119 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
120 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
121#ifdef CONFIG_SMP
122 irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
123#endif
124 }
125}
126
127unsigned int __cpuinit get_c0_compare_int(void)
128{
129#ifdef MSC01E_INT_BASE
130 if (cpu_has_veic) {
131 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
132 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
133 } else
134#endif
135 {
136 if (cpu_has_vint)
137 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
138 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
139 }
140
141 return mips_cpu_timer_irq;
142}
143
144void __init plat_time_init(void)
145{
146 unsigned int est_freq;
147
148 /* Set Data mode - binary. */
149 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
150
151 est_freq = estimate_cpu_frequency();
152
153 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
154 (est_freq%1000000)*100/1000000);
155
156 cpu_khz = est_freq / 1000;
157
158 mips_scroll_message();
159#ifdef CONFIG_I8253 /* Only Malta has a PIT */
160 setup_pit_timer();
161#endif
162
163 plat_perf_setup();
164}
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Setting up the clock on the MIPS boards.
19 */
20#include <linux/types.h>
21#include <linux/i8253.h>
22#include <linux/init.h>
23#include <linux/kernel_stat.h>
24#include <linux/math64.h>
25#include <linux/sched.h>
26#include <linux/spinlock.h>
27#include <linux/interrupt.h>
28#include <linux/irqchip/mips-gic.h>
29#include <linux/timex.h>
30#include <linux/mc146818rtc.h>
31
32#include <asm/cpu.h>
33#include <asm/mipsregs.h>
34#include <asm/mipsmtregs.h>
35#include <asm/hardirq.h>
36#include <asm/irq.h>
37#include <asm/div64.h>
38#include <asm/setup.h>
39#include <asm/time.h>
40#include <asm/mc146818-time.h>
41#include <asm/msc01_ic.h>
42
43#include <asm/mips-boards/generic.h>
44#include <asm/mips-boards/maltaint.h>
45
46static int mips_cpu_timer_irq;
47static int mips_cpu_perf_irq;
48extern int cp0_perfcount_irq;
49
50static unsigned int gic_frequency;
51
52static void mips_timer_dispatch(void)
53{
54 do_IRQ(mips_cpu_timer_irq);
55}
56
57static void mips_perf_dispatch(void)
58{
59 do_IRQ(mips_cpu_perf_irq);
60}
61
62static unsigned int freqround(unsigned int freq, unsigned int amount)
63{
64 freq += amount;
65 freq -= freq % (amount*2);
66 return freq;
67}
68
69/*
70 * Estimate CPU and GIC frequencies.
71 */
72static void __init estimate_frequencies(void)
73{
74 unsigned long flags;
75 unsigned int count, start;
76 unsigned char secs1, secs2, ctrl;
77 int secs;
78 u64 giccount = 0, gicstart = 0;
79
80#if defined(CONFIG_KVM_GUEST) && CONFIG_KVM_GUEST_TIMER_FREQ
81 mips_hpt_frequency = CONFIG_KVM_GUEST_TIMER_FREQ * 1000000;
82 return;
83#endif
84
85 local_irq_save(flags);
86
87 if (gic_present)
88 gic_start_count();
89
90 /*
91 * Read counters exactly on rising edge of update flag.
92 * This helps get an accurate reading under virtualisation.
93 */
94 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
95 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
96 start = read_c0_count();
97 if (gic_present)
98 gicstart = gic_read_count();
99
100 /* Wait for falling edge before reading RTC. */
101 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
102 secs1 = CMOS_READ(RTC_SECONDS);
103
104 /* Read counters again exactly on rising edge of update flag. */
105 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
106 count = read_c0_count();
107 if (gic_present)
108 giccount = gic_read_count();
109
110 /* Wait for falling edge before reading RTC again. */
111 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
112 secs2 = CMOS_READ(RTC_SECONDS);
113
114 ctrl = CMOS_READ(RTC_CONTROL);
115
116 local_irq_restore(flags);
117
118 if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
119 secs1 = bcd2bin(secs1);
120 secs2 = bcd2bin(secs2);
121 }
122 secs = secs2 - secs1;
123 if (secs < 1)
124 secs += 60;
125
126 count -= start;
127 count /= secs;
128 mips_hpt_frequency = count;
129
130 if (gic_present) {
131 giccount = div_u64(giccount - gicstart, secs);
132 gic_frequency = giccount;
133 }
134}
135
136void read_persistent_clock(struct timespec *ts)
137{
138 ts->tv_sec = mc146818_get_cmos_time();
139 ts->tv_nsec = 0;
140}
141
142int get_c0_fdc_int(void)
143{
144 /*
145 * Some cores claim the FDC is routable through the GIC, but it doesn't
146 * actually seem to be connected for those Malta bitstreams.
147 */
148 switch (current_cpu_type()) {
149 case CPU_INTERAPTIV:
150 case CPU_PROAPTIV:
151 return -1;
152 };
153
154 if (cpu_has_veic)
155 return -1;
156 else if (gic_present)
157 return gic_get_c0_fdc_int();
158 else if (cp0_fdc_irq >= 0)
159 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
160 else
161 return -1;
162}
163
164int get_c0_perfcount_int(void)
165{
166 if (cpu_has_veic) {
167 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
168 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
169 } else if (gic_present) {
170 mips_cpu_perf_irq = gic_get_c0_perfcount_int();
171 } else if (cp0_perfcount_irq >= 0) {
172 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
173 } else {
174 mips_cpu_perf_irq = -1;
175 }
176
177 return mips_cpu_perf_irq;
178}
179EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
180
181unsigned int get_c0_compare_int(void)
182{
183 if (cpu_has_veic) {
184 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
185 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
186 } else if (gic_present) {
187 mips_cpu_timer_irq = gic_get_c0_compare_int();
188 } else {
189 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
190 }
191
192 return mips_cpu_timer_irq;
193}
194
195static void __init init_rtc(void)
196{
197 unsigned char freq, ctrl;
198
199 /* Set 32KHz time base if not already set */
200 freq = CMOS_READ(RTC_FREQ_SELECT);
201 if ((freq & RTC_DIV_CTL) != RTC_REF_CLCK_32KHZ)
202 CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
203
204 /* Ensure SET bit is clear so RTC can run */
205 ctrl = CMOS_READ(RTC_CONTROL);
206 if (ctrl & RTC_SET)
207 CMOS_WRITE(ctrl & ~RTC_SET, RTC_CONTROL);
208}
209
210void __init plat_time_init(void)
211{
212 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
213 unsigned int freq;
214
215 init_rtc();
216 estimate_frequencies();
217
218 freq = mips_hpt_frequency;
219 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
220 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
221 freq *= 2;
222 freq = freqround(freq, 5000);
223 printk("CPU frequency %d.%02d MHz\n", freq/1000000,
224 (freq%1000000)*100/1000000);
225
226 mips_scroll_message();
227
228#ifdef CONFIG_I8253
229 /* Only Malta has a PIT. */
230 setup_pit_timer();
231#endif
232
233#ifdef CONFIG_MIPS_GIC
234 if (gic_present) {
235 freq = freqround(gic_frequency, 5000);
236 printk("GIC frequency %d.%02d MHz\n", freq/1000000,
237 (freq%1000000)*100/1000000);
238#ifdef CONFIG_CLKSRC_MIPS_GIC
239 gic_clocksource_init(gic_frequency);
240#endif
241 }
242#endif
243}