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1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Setting up the clock on the MIPS boards.
19 */
20
21#include <linux/types.h>
22#include <linux/i8253.h>
23#include <linux/init.h>
24#include <linux/kernel_stat.h>
25#include <linux/sched.h>
26#include <linux/spinlock.h>
27#include <linux/interrupt.h>
28#include <linux/time.h>
29#include <linux/timex.h>
30#include <linux/mc146818rtc.h>
31
32#include <asm/mipsregs.h>
33#include <asm/mipsmtregs.h>
34#include <asm/hardirq.h>
35#include <asm/irq.h>
36#include <asm/div64.h>
37#include <asm/cpu.h>
38#include <asm/time.h>
39#include <asm/mc146818-time.h>
40#include <asm/msc01_ic.h>
41
42#include <asm/mips-boards/generic.h>
43#include <asm/mips-boards/prom.h>
44
45#include <asm/mips-boards/maltaint.h>
46
47unsigned long cpu_khz;
48
49static int mips_cpu_timer_irq;
50static int mips_cpu_perf_irq;
51extern int cp0_perfcount_irq;
52
53static void mips_timer_dispatch(void)
54{
55 do_IRQ(mips_cpu_timer_irq);
56}
57
58static void mips_perf_dispatch(void)
59{
60 do_IRQ(mips_cpu_perf_irq);
61}
62
63/*
64 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
65 */
66static unsigned int __init estimate_cpu_frequency(void)
67{
68 unsigned int prid = read_c0_prid() & 0xffff00;
69 unsigned int count;
70
71 unsigned long flags;
72 unsigned int start;
73
74 local_irq_save(flags);
75
76 /* Start counter exactly on falling edge of update flag */
77 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
78 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
79
80 /* Start r4k counter. */
81 start = read_c0_count();
82
83 /* Read counter exactly on falling edge of update flag */
84 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
85 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
86
87 count = read_c0_count() - start;
88
89 /* restore interrupts */
90 local_irq_restore(flags);
91
92 mips_hpt_frequency = count;
93 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
94 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
95 count *= 2;
96
97 count += 5000; /* round */
98 count -= count%10000;
99
100 return count;
101}
102
103void read_persistent_clock(struct timespec *ts)
104{
105 ts->tv_sec = mc146818_get_cmos_time();
106 ts->tv_nsec = 0;
107}
108
109static void __init plat_perf_setup(void)
110{
111#ifdef MSC01E_INT_BASE
112 if (cpu_has_veic) {
113 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
114 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
115 } else
116#endif
117 if (cp0_perfcount_irq >= 0) {
118 if (cpu_has_vint)
119 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
120 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
121#ifdef CONFIG_SMP
122 irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
123#endif
124 }
125}
126
127unsigned int __cpuinit get_c0_compare_int(void)
128{
129#ifdef MSC01E_INT_BASE
130 if (cpu_has_veic) {
131 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
132 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
133 } else
134#endif
135 {
136 if (cpu_has_vint)
137 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
138 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
139 }
140
141 return mips_cpu_timer_irq;
142}
143
144void __init plat_time_init(void)
145{
146 unsigned int est_freq;
147
148 /* Set Data mode - binary. */
149 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
150
151 est_freq = estimate_cpu_frequency();
152
153 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
154 (est_freq%1000000)*100/1000000);
155
156 cpu_khz = est_freq / 1000;
157
158 mips_scroll_message();
159#ifdef CONFIG_I8253 /* Only Malta has a PIT */
160 setup_pit_timer();
161#endif
162
163 plat_perf_setup();
164}
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Setting up the clock on the MIPS boards.
19 */
20#include <linux/types.h>
21#include <linux/i8253.h>
22#include <linux/init.h>
23#include <linux/kernel_stat.h>
24#include <linux/sched.h>
25#include <linux/spinlock.h>
26#include <linux/interrupt.h>
27#include <linux/timex.h>
28#include <linux/mc146818rtc.h>
29
30#include <asm/cpu.h>
31#include <asm/mipsregs.h>
32#include <asm/mipsmtregs.h>
33#include <asm/hardirq.h>
34#include <asm/irq.h>
35#include <asm/div64.h>
36#include <asm/setup.h>
37#include <asm/time.h>
38#include <asm/mc146818-time.h>
39#include <asm/msc01_ic.h>
40#include <asm/gic.h>
41
42#include <asm/mips-boards/generic.h>
43#include <asm/mips-boards/maltaint.h>
44
45static int mips_cpu_timer_irq;
46static int mips_cpu_perf_irq;
47extern int cp0_perfcount_irq;
48
49static void mips_timer_dispatch(void)
50{
51 do_IRQ(mips_cpu_timer_irq);
52}
53
54static void mips_perf_dispatch(void)
55{
56 do_IRQ(mips_cpu_perf_irq);
57}
58
59static unsigned int freqround(unsigned int freq, unsigned int amount)
60{
61 freq += amount;
62 freq -= freq % (amount*2);
63 return freq;
64}
65
66/*
67 * Estimate CPU and GIC frequencies.
68 */
69static void __init estimate_frequencies(void)
70{
71 unsigned long flags;
72 unsigned int count, start;
73#ifdef CONFIG_IRQ_GIC
74 unsigned int giccount = 0, gicstart = 0;
75#endif
76
77#if defined (CONFIG_KVM_GUEST) && defined (CONFIG_KVM_HOST_FREQ)
78 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
79
80 /*
81 * XXXKYMA: hardwire the CPU frequency to Host Freq/4
82 */
83 count = (CONFIG_KVM_HOST_FREQ * 1000000) >> 3;
84 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
85 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
86 count *= 2;
87
88 mips_hpt_frequency = count;
89 return;
90#endif
91
92 local_irq_save(flags);
93
94 /* Start counter exactly on falling edge of update flag. */
95 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
96 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
97
98 /* Initialize counters. */
99 start = read_c0_count();
100#ifdef CONFIG_IRQ_GIC
101 if (gic_present)
102 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
103#endif
104
105 /* Read counter exactly on falling edge of update flag. */
106 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
107 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
108
109 count = read_c0_count();
110#ifdef CONFIG_IRQ_GIC
111 if (gic_present)
112 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
113#endif
114
115 local_irq_restore(flags);
116
117 count -= start;
118 mips_hpt_frequency = count;
119
120#ifdef CONFIG_IRQ_GIC
121 if (gic_present) {
122 giccount -= gicstart;
123 gic_frequency = giccount;
124 }
125#endif
126}
127
128void read_persistent_clock(struct timespec *ts)
129{
130 ts->tv_sec = mc146818_get_cmos_time();
131 ts->tv_nsec = 0;
132}
133
134static void __init plat_perf_setup(void)
135{
136#ifdef MSC01E_INT_BASE
137 if (cpu_has_veic) {
138 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
139 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
140 } else
141#endif
142 if (cp0_perfcount_irq >= 0) {
143 if (cpu_has_vint)
144 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
145 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
146#ifdef CONFIG_SMP
147 irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
148#endif
149 }
150}
151
152unsigned int get_c0_compare_int(void)
153{
154#ifdef MSC01E_INT_BASE
155 if (cpu_has_veic) {
156 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
157 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
158 } else
159#endif
160 {
161 if (cpu_has_vint)
162 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
163 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
164 }
165
166 return mips_cpu_timer_irq;
167}
168
169static void __init init_rtc(void)
170{
171 /* stop the clock whilst setting it up */
172 CMOS_WRITE(RTC_SET | RTC_24H, RTC_CONTROL);
173
174 /* 32KHz time base */
175 CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);
176
177 /* start the clock */
178 CMOS_WRITE(RTC_24H, RTC_CONTROL);
179}
180
181void __init plat_time_init(void)
182{
183 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
184 unsigned int freq;
185
186 init_rtc();
187 estimate_frequencies();
188
189 freq = mips_hpt_frequency;
190 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
191 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
192 freq *= 2;
193 freq = freqround(freq, 5000);
194 printk("CPU frequency %d.%02d MHz\n", freq/1000000,
195 (freq%1000000)*100/1000000);
196
197 mips_scroll_message();
198
199#ifdef CONFIG_I8253
200 /* Only Malta has a PIT. */
201 setup_pit_timer();
202#endif
203
204#ifdef CONFIG_IRQ_GIC
205 if (gic_present) {
206 freq = freqround(gic_frequency, 5000);
207 printk("GIC frequency %d.%02d MHz\n", freq/1000000,
208 (freq%1000000)*100/1000000);
209#ifdef CONFIG_CSRC_GIC
210 gic_clocksource_init(gic_frequency);
211#endif
212 }
213#endif
214
215 plat_perf_setup();
216}