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1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
29 *
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
41 *
42 * Cycle bit rules:
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
47 *
48 * Producer rules:
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
52 * cycle state).
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
56 *
57 * Consumer rules:
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
65 */
66
67#include <linux/scatterlist.h>
68#include <linux/slab.h>
69#include "xhci.h"
70
71static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
74
75/*
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
77 * address of the TRB.
78 */
79dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
80 union xhci_trb *trb)
81{
82 unsigned long segment_offset;
83
84 if (!seg || !trb || trb < seg->trbs)
85 return 0;
86 /* offset in TRBs */
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
89 return 0;
90 return seg->dma + (segment_offset * sizeof(*trb));
91}
92
93/* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
95 */
96static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
98{
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
102 else
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
104}
105
106/* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
108 * event seg?
109 */
110static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
112{
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
115 else
116 return TRB_TYPE_LINK_LE32(trb->link.control);
117}
118
119static int enqueue_is_link_trb(struct xhci_ring *ring)
120{
121 struct xhci_link_trb *link = &ring->enqueue->link;
122 return TRB_TYPE_LINK_LE32(link->control);
123}
124
125/* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
128 */
129static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
133{
134 if (last_trb(xhci, ring, *seg, *trb)) {
135 *seg = (*seg)->next;
136 *trb = ((*seg)->trbs);
137 } else {
138 (*trb)++;
139 }
140}
141
142/*
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
145 */
146static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
147{
148 union xhci_trb *next = ++(ring->dequeue);
149 unsigned long long addr;
150
151 ring->deq_updates++;
152 /* Update the dequeue pointer further if that was a link TRB or we're at
153 * the end of an event ring segment (which doesn't have link TRBS)
154 */
155 while (last_trb(xhci, ring, ring->deq_seg, next)) {
156 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
157 ring->cycle_state = (ring->cycle_state ? 0 : 1);
158 if (!in_interrupt())
159 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
160 ring,
161 (unsigned int) ring->cycle_state);
162 }
163 ring->deq_seg = ring->deq_seg->next;
164 ring->dequeue = ring->deq_seg->trbs;
165 next = ring->dequeue;
166 }
167 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
168}
169
170/*
171 * See Cycle bit rules. SW is the consumer for the event ring only.
172 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
173 *
174 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
175 * chain bit is set), then set the chain bit in all the following link TRBs.
176 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
177 * have their chain bit cleared (so that each Link TRB is a separate TD).
178 *
179 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
180 * set, but other sections talk about dealing with the chain bit set. This was
181 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
182 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
183 *
184 * @more_trbs_coming: Will you enqueue more TRBs before calling
185 * prepare_transfer()?
186 */
187static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
188 bool consumer, bool more_trbs_coming)
189{
190 u32 chain;
191 union xhci_trb *next;
192 unsigned long long addr;
193
194 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
195 next = ++(ring->enqueue);
196
197 ring->enq_updates++;
198 /* Update the dequeue pointer further if that was a link TRB or we're at
199 * the end of an event ring segment (which doesn't have link TRBS)
200 */
201 while (last_trb(xhci, ring, ring->enq_seg, next)) {
202 if (!consumer) {
203 if (ring != xhci->event_ring) {
204 /*
205 * If the caller doesn't plan on enqueueing more
206 * TDs before ringing the doorbell, then we
207 * don't want to give the link TRB to the
208 * hardware just yet. We'll give the link TRB
209 * back in prepare_ring() just before we enqueue
210 * the TD at the top of the ring.
211 */
212 if (!chain && !more_trbs_coming)
213 break;
214
215 /* If we're not dealing with 0.95 hardware,
216 * carry over the chain bit of the previous TRB
217 * (which may mean the chain bit is cleared).
218 */
219 if (!xhci_link_trb_quirk(xhci)) {
220 next->link.control &=
221 cpu_to_le32(~TRB_CHAIN);
222 next->link.control |=
223 cpu_to_le32(chain);
224 }
225 /* Give this link TRB to the hardware */
226 wmb();
227 next->link.control ^= cpu_to_le32(TRB_CYCLE);
228 }
229 /* Toggle the cycle bit after the last ring segment. */
230 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
231 ring->cycle_state = (ring->cycle_state ? 0 : 1);
232 if (!in_interrupt())
233 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
234 ring,
235 (unsigned int) ring->cycle_state);
236 }
237 }
238 ring->enq_seg = ring->enq_seg->next;
239 ring->enqueue = ring->enq_seg->trbs;
240 next = ring->enqueue;
241 }
242 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
243}
244
245/*
246 * Check to see if there's room to enqueue num_trbs on the ring. See rules
247 * above.
248 * FIXME: this would be simpler and faster if we just kept track of the number
249 * of free TRBs in a ring.
250 */
251static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
252 unsigned int num_trbs)
253{
254 int i;
255 union xhci_trb *enq = ring->enqueue;
256 struct xhci_segment *enq_seg = ring->enq_seg;
257 struct xhci_segment *cur_seg;
258 unsigned int left_on_ring;
259
260 /* If we are currently pointing to a link TRB, advance the
261 * enqueue pointer before checking for space */
262 while (last_trb(xhci, ring, enq_seg, enq)) {
263 enq_seg = enq_seg->next;
264 enq = enq_seg->trbs;
265 }
266
267 /* Check if ring is empty */
268 if (enq == ring->dequeue) {
269 /* Can't use link trbs */
270 left_on_ring = TRBS_PER_SEGMENT - 1;
271 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
272 cur_seg = cur_seg->next)
273 left_on_ring += TRBS_PER_SEGMENT - 1;
274
275 /* Always need one TRB free in the ring. */
276 left_on_ring -= 1;
277 if (num_trbs > left_on_ring) {
278 xhci_warn(xhci, "Not enough room on ring; "
279 "need %u TRBs, %u TRBs left\n",
280 num_trbs, left_on_ring);
281 return 0;
282 }
283 return 1;
284 }
285 /* Make sure there's an extra empty TRB available */
286 for (i = 0; i <= num_trbs; ++i) {
287 if (enq == ring->dequeue)
288 return 0;
289 enq++;
290 while (last_trb(xhci, ring, enq_seg, enq)) {
291 enq_seg = enq_seg->next;
292 enq = enq_seg->trbs;
293 }
294 }
295 return 1;
296}
297
298/* Ring the host controller doorbell after placing a command on the ring */
299void xhci_ring_cmd_db(struct xhci_hcd *xhci)
300{
301 xhci_dbg(xhci, "// Ding dong!\n");
302 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
303 /* Flush PCI posted writes */
304 xhci_readl(xhci, &xhci->dba->doorbell[0]);
305}
306
307void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
308 unsigned int slot_id,
309 unsigned int ep_index,
310 unsigned int stream_id)
311{
312 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
313 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
314 unsigned int ep_state = ep->ep_state;
315
316 /* Don't ring the doorbell for this endpoint if there are pending
317 * cancellations because we don't want to interrupt processing.
318 * We don't want to restart any stream rings if there's a set dequeue
319 * pointer command pending because the device can choose to start any
320 * stream once the endpoint is on the HW schedule.
321 * FIXME - check all the stream rings for pending cancellations.
322 */
323 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
324 (ep_state & EP_HALTED))
325 return;
326 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
327 /* The CPU has better things to do at this point than wait for a
328 * write-posting flush. It'll get there soon enough.
329 */
330}
331
332/* Ring the doorbell for any rings with pending URBs */
333static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
334 unsigned int slot_id,
335 unsigned int ep_index)
336{
337 unsigned int stream_id;
338 struct xhci_virt_ep *ep;
339
340 ep = &xhci->devs[slot_id]->eps[ep_index];
341
342 /* A ring has pending URBs if its TD list is not empty */
343 if (!(ep->ep_state & EP_HAS_STREAMS)) {
344 if (!(list_empty(&ep->ring->td_list)))
345 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
346 return;
347 }
348
349 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
350 stream_id++) {
351 struct xhci_stream_info *stream_info = ep->stream_info;
352 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
353 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
354 stream_id);
355 }
356}
357
358/*
359 * Find the segment that trb is in. Start searching in start_seg.
360 * If we must move past a segment that has a link TRB with a toggle cycle state
361 * bit set, then we will toggle the value pointed at by cycle_state.
362 */
363static struct xhci_segment *find_trb_seg(
364 struct xhci_segment *start_seg,
365 union xhci_trb *trb, int *cycle_state)
366{
367 struct xhci_segment *cur_seg = start_seg;
368 struct xhci_generic_trb *generic_trb;
369
370 while (cur_seg->trbs > trb ||
371 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
372 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
373 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
374 *cycle_state ^= 0x1;
375 cur_seg = cur_seg->next;
376 if (cur_seg == start_seg)
377 /* Looped over the entire list. Oops! */
378 return NULL;
379 }
380 return cur_seg;
381}
382
383
384static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
385 unsigned int slot_id, unsigned int ep_index,
386 unsigned int stream_id)
387{
388 struct xhci_virt_ep *ep;
389
390 ep = &xhci->devs[slot_id]->eps[ep_index];
391 /* Common case: no streams */
392 if (!(ep->ep_state & EP_HAS_STREAMS))
393 return ep->ring;
394
395 if (stream_id == 0) {
396 xhci_warn(xhci,
397 "WARN: Slot ID %u, ep index %u has streams, "
398 "but URB has no stream ID.\n",
399 slot_id, ep_index);
400 return NULL;
401 }
402
403 if (stream_id < ep->stream_info->num_streams)
404 return ep->stream_info->stream_rings[stream_id];
405
406 xhci_warn(xhci,
407 "WARN: Slot ID %u, ep index %u has "
408 "stream IDs 1 to %u allocated, "
409 "but stream ID %u is requested.\n",
410 slot_id, ep_index,
411 ep->stream_info->num_streams - 1,
412 stream_id);
413 return NULL;
414}
415
416/* Get the right ring for the given URB.
417 * If the endpoint supports streams, boundary check the URB's stream ID.
418 * If the endpoint doesn't support streams, return the singular endpoint ring.
419 */
420static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
421 struct urb *urb)
422{
423 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
424 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
425}
426
427/*
428 * Move the xHC's endpoint ring dequeue pointer past cur_td.
429 * Record the new state of the xHC's endpoint ring dequeue segment,
430 * dequeue pointer, and new consumer cycle state in state.
431 * Update our internal representation of the ring's dequeue pointer.
432 *
433 * We do this in three jumps:
434 * - First we update our new ring state to be the same as when the xHC stopped.
435 * - Then we traverse the ring to find the segment that contains
436 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
437 * any link TRBs with the toggle cycle bit set.
438 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
439 * if we've moved it past a link TRB with the toggle cycle bit set.
440 *
441 * Some of the uses of xhci_generic_trb are grotty, but if they're done
442 * with correct __le32 accesses they should work fine. Only users of this are
443 * in here.
444 */
445void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
446 unsigned int slot_id, unsigned int ep_index,
447 unsigned int stream_id, struct xhci_td *cur_td,
448 struct xhci_dequeue_state *state)
449{
450 struct xhci_virt_device *dev = xhci->devs[slot_id];
451 struct xhci_ring *ep_ring;
452 struct xhci_generic_trb *trb;
453 struct xhci_ep_ctx *ep_ctx;
454 dma_addr_t addr;
455
456 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
457 ep_index, stream_id);
458 if (!ep_ring) {
459 xhci_warn(xhci, "WARN can't find new dequeue state "
460 "for invalid stream ID %u.\n",
461 stream_id);
462 return;
463 }
464 state->new_cycle_state = 0;
465 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
466 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
467 dev->eps[ep_index].stopped_trb,
468 &state->new_cycle_state);
469 if (!state->new_deq_seg) {
470 WARN_ON(1);
471 return;
472 }
473
474 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
475 xhci_dbg(xhci, "Finding endpoint context\n");
476 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
477 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
478
479 state->new_deq_ptr = cur_td->last_trb;
480 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
481 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
482 state->new_deq_ptr,
483 &state->new_cycle_state);
484 if (!state->new_deq_seg) {
485 WARN_ON(1);
486 return;
487 }
488
489 trb = &state->new_deq_ptr->generic;
490 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
491 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
492 state->new_cycle_state ^= 0x1;
493 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
494
495 /*
496 * If there is only one segment in a ring, find_trb_seg()'s while loop
497 * will not run, and it will return before it has a chance to see if it
498 * needs to toggle the cycle bit. It can't tell if the stalled transfer
499 * ended just before the link TRB on a one-segment ring, or if the TD
500 * wrapped around the top of the ring, because it doesn't have the TD in
501 * question. Look for the one-segment case where stalled TRB's address
502 * is greater than the new dequeue pointer address.
503 */
504 if (ep_ring->first_seg == ep_ring->first_seg->next &&
505 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
506 state->new_cycle_state ^= 0x1;
507 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
508
509 /* Don't update the ring cycle state for the producer (us). */
510 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
511 state->new_deq_seg);
512 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
513 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
514 (unsigned long long) addr);
515}
516
517/* flip_cycle means flip the cycle bit of all but the first and last TRB.
518 * (The last TRB actually points to the ring enqueue pointer, which is not part
519 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
520 */
521static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
522 struct xhci_td *cur_td, bool flip_cycle)
523{
524 struct xhci_segment *cur_seg;
525 union xhci_trb *cur_trb;
526
527 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
528 true;
529 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
530 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
531 /* Unchain any chained Link TRBs, but
532 * leave the pointers intact.
533 */
534 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
535 /* Flip the cycle bit (link TRBs can't be the first
536 * or last TRB).
537 */
538 if (flip_cycle)
539 cur_trb->generic.field[3] ^=
540 cpu_to_le32(TRB_CYCLE);
541 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
542 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
543 "in seg %p (0x%llx dma)\n",
544 cur_trb,
545 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
546 cur_seg,
547 (unsigned long long)cur_seg->dma);
548 } else {
549 cur_trb->generic.field[0] = 0;
550 cur_trb->generic.field[1] = 0;
551 cur_trb->generic.field[2] = 0;
552 /* Preserve only the cycle bit of this TRB */
553 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
554 /* Flip the cycle bit except on the first or last TRB */
555 if (flip_cycle && cur_trb != cur_td->first_trb &&
556 cur_trb != cur_td->last_trb)
557 cur_trb->generic.field[3] ^=
558 cpu_to_le32(TRB_CYCLE);
559 cur_trb->generic.field[3] |= cpu_to_le32(
560 TRB_TYPE(TRB_TR_NOOP));
561 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
562 "in seg %p (0x%llx dma)\n",
563 cur_trb,
564 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
565 cur_seg,
566 (unsigned long long)cur_seg->dma);
567 }
568 if (cur_trb == cur_td->last_trb)
569 break;
570 }
571}
572
573static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
574 unsigned int ep_index, unsigned int stream_id,
575 struct xhci_segment *deq_seg,
576 union xhci_trb *deq_ptr, u32 cycle_state);
577
578void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
579 unsigned int slot_id, unsigned int ep_index,
580 unsigned int stream_id,
581 struct xhci_dequeue_state *deq_state)
582{
583 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
584
585 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
586 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
587 deq_state->new_deq_seg,
588 (unsigned long long)deq_state->new_deq_seg->dma,
589 deq_state->new_deq_ptr,
590 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
591 deq_state->new_cycle_state);
592 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
593 deq_state->new_deq_seg,
594 deq_state->new_deq_ptr,
595 (u32) deq_state->new_cycle_state);
596 /* Stop the TD queueing code from ringing the doorbell until
597 * this command completes. The HC won't set the dequeue pointer
598 * if the ring is running, and ringing the doorbell starts the
599 * ring running.
600 */
601 ep->ep_state |= SET_DEQ_PENDING;
602}
603
604static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
605 struct xhci_virt_ep *ep)
606{
607 ep->ep_state &= ~EP_HALT_PENDING;
608 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
609 * timer is running on another CPU, we don't decrement stop_cmds_pending
610 * (since we didn't successfully stop the watchdog timer).
611 */
612 if (del_timer(&ep->stop_cmd_timer))
613 ep->stop_cmds_pending--;
614}
615
616/* Must be called with xhci->lock held in interrupt context */
617static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
618 struct xhci_td *cur_td, int status, char *adjective)
619{
620 struct usb_hcd *hcd;
621 struct urb *urb;
622 struct urb_priv *urb_priv;
623
624 urb = cur_td->urb;
625 urb_priv = urb->hcpriv;
626 urb_priv->td_cnt++;
627 hcd = bus_to_hcd(urb->dev->bus);
628
629 /* Only giveback urb when this is the last td in urb */
630 if (urb_priv->td_cnt == urb_priv->length) {
631 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
632 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
633 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
634 if (xhci->quirks & XHCI_AMD_PLL_FIX)
635 usb_amd_quirk_pll_enable();
636 }
637 }
638 usb_hcd_unlink_urb_from_ep(hcd, urb);
639
640 spin_unlock(&xhci->lock);
641 usb_hcd_giveback_urb(hcd, urb, status);
642 xhci_urb_free_priv(xhci, urb_priv);
643 spin_lock(&xhci->lock);
644 }
645}
646
647/*
648 * When we get a command completion for a Stop Endpoint Command, we need to
649 * unlink any cancelled TDs from the ring. There are two ways to do that:
650 *
651 * 1. If the HW was in the middle of processing the TD that needs to be
652 * cancelled, then we must move the ring's dequeue pointer past the last TRB
653 * in the TD with a Set Dequeue Pointer Command.
654 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
655 * bit cleared) so that the HW will skip over them.
656 */
657static void handle_stopped_endpoint(struct xhci_hcd *xhci,
658 union xhci_trb *trb, struct xhci_event_cmd *event)
659{
660 unsigned int slot_id;
661 unsigned int ep_index;
662 struct xhci_virt_device *virt_dev;
663 struct xhci_ring *ep_ring;
664 struct xhci_virt_ep *ep;
665 struct list_head *entry;
666 struct xhci_td *cur_td = NULL;
667 struct xhci_td *last_unlinked_td;
668
669 struct xhci_dequeue_state deq_state;
670
671 if (unlikely(TRB_TO_SUSPEND_PORT(
672 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
673 slot_id = TRB_TO_SLOT_ID(
674 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
675 virt_dev = xhci->devs[slot_id];
676 if (virt_dev)
677 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
678 event);
679 else
680 xhci_warn(xhci, "Stop endpoint command "
681 "completion for disabled slot %u\n",
682 slot_id);
683 return;
684 }
685
686 memset(&deq_state, 0, sizeof(deq_state));
687 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
688 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
689 ep = &xhci->devs[slot_id]->eps[ep_index];
690
691 if (list_empty(&ep->cancelled_td_list)) {
692 xhci_stop_watchdog_timer_in_irq(xhci, ep);
693 ep->stopped_td = NULL;
694 ep->stopped_trb = NULL;
695 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
696 return;
697 }
698
699 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
700 * We have the xHCI lock, so nothing can modify this list until we drop
701 * it. We're also in the event handler, so we can't get re-interrupted
702 * if another Stop Endpoint command completes
703 */
704 list_for_each(entry, &ep->cancelled_td_list) {
705 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
706 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
707 cur_td->first_trb,
708 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
709 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
710 if (!ep_ring) {
711 /* This shouldn't happen unless a driver is mucking
712 * with the stream ID after submission. This will
713 * leave the TD on the hardware ring, and the hardware
714 * will try to execute it, and may access a buffer
715 * that has already been freed. In the best case, the
716 * hardware will execute it, and the event handler will
717 * ignore the completion event for that TD, since it was
718 * removed from the td_list for that endpoint. In
719 * short, don't muck with the stream ID after
720 * submission.
721 */
722 xhci_warn(xhci, "WARN Cancelled URB %p "
723 "has invalid stream ID %u.\n",
724 cur_td->urb,
725 cur_td->urb->stream_id);
726 goto remove_finished_td;
727 }
728 /*
729 * If we stopped on the TD we need to cancel, then we have to
730 * move the xHC endpoint ring dequeue pointer past this TD.
731 */
732 if (cur_td == ep->stopped_td)
733 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
734 cur_td->urb->stream_id,
735 cur_td, &deq_state);
736 else
737 td_to_noop(xhci, ep_ring, cur_td, false);
738remove_finished_td:
739 /*
740 * The event handler won't see a completion for this TD anymore,
741 * so remove it from the endpoint ring's TD list. Keep it in
742 * the cancelled TD list for URB completion later.
743 */
744 list_del_init(&cur_td->td_list);
745 }
746 last_unlinked_td = cur_td;
747 xhci_stop_watchdog_timer_in_irq(xhci, ep);
748
749 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
750 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
751 xhci_queue_new_dequeue_state(xhci,
752 slot_id, ep_index,
753 ep->stopped_td->urb->stream_id,
754 &deq_state);
755 xhci_ring_cmd_db(xhci);
756 } else {
757 /* Otherwise ring the doorbell(s) to restart queued transfers */
758 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
759 }
760 ep->stopped_td = NULL;
761 ep->stopped_trb = NULL;
762
763 /*
764 * Drop the lock and complete the URBs in the cancelled TD list.
765 * New TDs to be cancelled might be added to the end of the list before
766 * we can complete all the URBs for the TDs we already unlinked.
767 * So stop when we've completed the URB for the last TD we unlinked.
768 */
769 do {
770 cur_td = list_entry(ep->cancelled_td_list.next,
771 struct xhci_td, cancelled_td_list);
772 list_del_init(&cur_td->cancelled_td_list);
773
774 /* Clean up the cancelled URB */
775 /* Doesn't matter what we pass for status, since the core will
776 * just overwrite it (because the URB has been unlinked).
777 */
778 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
779
780 /* Stop processing the cancelled list if the watchdog timer is
781 * running.
782 */
783 if (xhci->xhc_state & XHCI_STATE_DYING)
784 return;
785 } while (cur_td != last_unlinked_td);
786
787 /* Return to the event handler with xhci->lock re-acquired */
788}
789
790/* Watchdog timer function for when a stop endpoint command fails to complete.
791 * In this case, we assume the host controller is broken or dying or dead. The
792 * host may still be completing some other events, so we have to be careful to
793 * let the event ring handler and the URB dequeueing/enqueueing functions know
794 * through xhci->state.
795 *
796 * The timer may also fire if the host takes a very long time to respond to the
797 * command, and the stop endpoint command completion handler cannot delete the
798 * timer before the timer function is called. Another endpoint cancellation may
799 * sneak in before the timer function can grab the lock, and that may queue
800 * another stop endpoint command and add the timer back. So we cannot use a
801 * simple flag to say whether there is a pending stop endpoint command for a
802 * particular endpoint.
803 *
804 * Instead we use a combination of that flag and a counter for the number of
805 * pending stop endpoint commands. If the timer is the tail end of the last
806 * stop endpoint command, and the endpoint's command is still pending, we assume
807 * the host is dying.
808 */
809void xhci_stop_endpoint_command_watchdog(unsigned long arg)
810{
811 struct xhci_hcd *xhci;
812 struct xhci_virt_ep *ep;
813 struct xhci_virt_ep *temp_ep;
814 struct xhci_ring *ring;
815 struct xhci_td *cur_td;
816 int ret, i, j;
817
818 ep = (struct xhci_virt_ep *) arg;
819 xhci = ep->xhci;
820
821 spin_lock(&xhci->lock);
822
823 ep->stop_cmds_pending--;
824 if (xhci->xhc_state & XHCI_STATE_DYING) {
825 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
826 "xHCI as DYING, exiting.\n");
827 spin_unlock(&xhci->lock);
828 return;
829 }
830 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
831 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
832 "exiting.\n");
833 spin_unlock(&xhci->lock);
834 return;
835 }
836
837 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
838 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
839 /* Oops, HC is dead or dying or at least not responding to the stop
840 * endpoint command.
841 */
842 xhci->xhc_state |= XHCI_STATE_DYING;
843 /* Disable interrupts from the host controller and start halting it */
844 xhci_quiesce(xhci);
845 spin_unlock(&xhci->lock);
846
847 ret = xhci_halt(xhci);
848
849 spin_lock(&xhci->lock);
850 if (ret < 0) {
851 /* This is bad; the host is not responding to commands and it's
852 * not allowing itself to be halted. At least interrupts are
853 * disabled. If we call usb_hc_died(), it will attempt to
854 * disconnect all device drivers under this host. Those
855 * disconnect() methods will wait for all URBs to be unlinked,
856 * so we must complete them.
857 */
858 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
859 xhci_warn(xhci, "Completing active URBs anyway.\n");
860 /* We could turn all TDs on the rings to no-ops. This won't
861 * help if the host has cached part of the ring, and is slow if
862 * we want to preserve the cycle bit. Skip it and hope the host
863 * doesn't touch the memory.
864 */
865 }
866 for (i = 0; i < MAX_HC_SLOTS; i++) {
867 if (!xhci->devs[i])
868 continue;
869 for (j = 0; j < 31; j++) {
870 temp_ep = &xhci->devs[i]->eps[j];
871 ring = temp_ep->ring;
872 if (!ring)
873 continue;
874 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
875 "ep index %u\n", i, j);
876 while (!list_empty(&ring->td_list)) {
877 cur_td = list_first_entry(&ring->td_list,
878 struct xhci_td,
879 td_list);
880 list_del_init(&cur_td->td_list);
881 if (!list_empty(&cur_td->cancelled_td_list))
882 list_del_init(&cur_td->cancelled_td_list);
883 xhci_giveback_urb_in_irq(xhci, cur_td,
884 -ESHUTDOWN, "killed");
885 }
886 while (!list_empty(&temp_ep->cancelled_td_list)) {
887 cur_td = list_first_entry(
888 &temp_ep->cancelled_td_list,
889 struct xhci_td,
890 cancelled_td_list);
891 list_del_init(&cur_td->cancelled_td_list);
892 xhci_giveback_urb_in_irq(xhci, cur_td,
893 -ESHUTDOWN, "killed");
894 }
895 }
896 }
897 spin_unlock(&xhci->lock);
898 xhci_dbg(xhci, "Calling usb_hc_died()\n");
899 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
900 xhci_dbg(xhci, "xHCI host controller is dead.\n");
901}
902
903/*
904 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
905 * we need to clear the set deq pending flag in the endpoint ring state, so that
906 * the TD queueing code can ring the doorbell again. We also need to ring the
907 * endpoint doorbell to restart the ring, but only if there aren't more
908 * cancellations pending.
909 */
910static void handle_set_deq_completion(struct xhci_hcd *xhci,
911 struct xhci_event_cmd *event,
912 union xhci_trb *trb)
913{
914 unsigned int slot_id;
915 unsigned int ep_index;
916 unsigned int stream_id;
917 struct xhci_ring *ep_ring;
918 struct xhci_virt_device *dev;
919 struct xhci_ep_ctx *ep_ctx;
920 struct xhci_slot_ctx *slot_ctx;
921
922 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
923 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
924 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
925 dev = xhci->devs[slot_id];
926
927 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
928 if (!ep_ring) {
929 xhci_warn(xhci, "WARN Set TR deq ptr command for "
930 "freed stream ID %u\n",
931 stream_id);
932 /* XXX: Harmless??? */
933 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
934 return;
935 }
936
937 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
938 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
939
940 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
941 unsigned int ep_state;
942 unsigned int slot_state;
943
944 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
945 case COMP_TRB_ERR:
946 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
947 "of stream ID configuration\n");
948 break;
949 case COMP_CTX_STATE:
950 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
951 "to incorrect slot or ep state.\n");
952 ep_state = le32_to_cpu(ep_ctx->ep_info);
953 ep_state &= EP_STATE_MASK;
954 slot_state = le32_to_cpu(slot_ctx->dev_state);
955 slot_state = GET_SLOT_STATE(slot_state);
956 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
957 slot_state, ep_state);
958 break;
959 case COMP_EBADSLT:
960 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
961 "slot %u was not enabled.\n", slot_id);
962 break;
963 default:
964 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
965 "completion code of %u.\n",
966 GET_COMP_CODE(le32_to_cpu(event->status)));
967 break;
968 }
969 /* OK what do we do now? The endpoint state is hosed, and we
970 * should never get to this point if the synchronization between
971 * queueing, and endpoint state are correct. This might happen
972 * if the device gets disconnected after we've finished
973 * cancelling URBs, which might not be an error...
974 */
975 } else {
976 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
977 le64_to_cpu(ep_ctx->deq));
978 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
979 dev->eps[ep_index].queued_deq_ptr) ==
980 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
981 /* Update the ring's dequeue segment and dequeue pointer
982 * to reflect the new position.
983 */
984 ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
985 ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
986 } else {
987 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
988 "Ptr command & xHCI internal state.\n");
989 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
990 dev->eps[ep_index].queued_deq_seg,
991 dev->eps[ep_index].queued_deq_ptr);
992 }
993 }
994
995 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
996 dev->eps[ep_index].queued_deq_seg = NULL;
997 dev->eps[ep_index].queued_deq_ptr = NULL;
998 /* Restart any rings with pending URBs */
999 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1000}
1001
1002static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1003 struct xhci_event_cmd *event,
1004 union xhci_trb *trb)
1005{
1006 int slot_id;
1007 unsigned int ep_index;
1008
1009 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1010 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1011 /* This command will only fail if the endpoint wasn't halted,
1012 * but we don't care.
1013 */
1014 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1015 GET_COMP_CODE(le32_to_cpu(event->status)));
1016
1017 /* HW with the reset endpoint quirk needs to have a configure endpoint
1018 * command complete before the endpoint can be used. Queue that here
1019 * because the HW can't handle two commands being queued in a row.
1020 */
1021 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1022 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1023 xhci_queue_configure_endpoint(xhci,
1024 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1025 false);
1026 xhci_ring_cmd_db(xhci);
1027 } else {
1028 /* Clear our internal halted state and restart the ring(s) */
1029 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1030 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1031 }
1032}
1033
1034/* Check to see if a command in the device's command queue matches this one.
1035 * Signal the completion or free the command, and return 1. Return 0 if the
1036 * completed command isn't at the head of the command list.
1037 */
1038static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1039 struct xhci_virt_device *virt_dev,
1040 struct xhci_event_cmd *event)
1041{
1042 struct xhci_command *command;
1043
1044 if (list_empty(&virt_dev->cmd_list))
1045 return 0;
1046
1047 command = list_entry(virt_dev->cmd_list.next,
1048 struct xhci_command, cmd_list);
1049 if (xhci->cmd_ring->dequeue != command->command_trb)
1050 return 0;
1051
1052 command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1053 list_del(&command->cmd_list);
1054 if (command->completion)
1055 complete(command->completion);
1056 else
1057 xhci_free_command(xhci, command);
1058 return 1;
1059}
1060
1061static void handle_cmd_completion(struct xhci_hcd *xhci,
1062 struct xhci_event_cmd *event)
1063{
1064 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1065 u64 cmd_dma;
1066 dma_addr_t cmd_dequeue_dma;
1067 struct xhci_input_control_ctx *ctrl_ctx;
1068 struct xhci_virt_device *virt_dev;
1069 unsigned int ep_index;
1070 struct xhci_ring *ep_ring;
1071 unsigned int ep_state;
1072
1073 cmd_dma = le64_to_cpu(event->cmd_trb);
1074 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1075 xhci->cmd_ring->dequeue);
1076 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1077 if (cmd_dequeue_dma == 0) {
1078 xhci->error_bitmask |= 1 << 4;
1079 return;
1080 }
1081 /* Does the DMA address match our internal dequeue pointer address? */
1082 if (cmd_dma != (u64) cmd_dequeue_dma) {
1083 xhci->error_bitmask |= 1 << 5;
1084 return;
1085 }
1086 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1087 & TRB_TYPE_BITMASK) {
1088 case TRB_TYPE(TRB_ENABLE_SLOT):
1089 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1090 xhci->slot_id = slot_id;
1091 else
1092 xhci->slot_id = 0;
1093 complete(&xhci->addr_dev);
1094 break;
1095 case TRB_TYPE(TRB_DISABLE_SLOT):
1096 if (xhci->devs[slot_id]) {
1097 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1098 /* Delete default control endpoint resources */
1099 xhci_free_device_endpoint_resources(xhci,
1100 xhci->devs[slot_id], true);
1101 xhci_free_virt_device(xhci, slot_id);
1102 }
1103 break;
1104 case TRB_TYPE(TRB_CONFIG_EP):
1105 virt_dev = xhci->devs[slot_id];
1106 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1107 break;
1108 /*
1109 * Configure endpoint commands can come from the USB core
1110 * configuration or alt setting changes, or because the HW
1111 * needed an extra configure endpoint command after a reset
1112 * endpoint command or streams were being configured.
1113 * If the command was for a halted endpoint, the xHCI driver
1114 * is not waiting on the configure endpoint command.
1115 */
1116 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1117 virt_dev->in_ctx);
1118 /* Input ctx add_flags are the endpoint index plus one */
1119 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1120 /* A usb_set_interface() call directly after clearing a halted
1121 * condition may race on this quirky hardware. Not worth
1122 * worrying about, since this is prototype hardware. Not sure
1123 * if this will work for streams, but streams support was
1124 * untested on this prototype.
1125 */
1126 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1127 ep_index != (unsigned int) -1 &&
1128 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1129 le32_to_cpu(ctrl_ctx->drop_flags)) {
1130 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1131 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1132 if (!(ep_state & EP_HALTED))
1133 goto bandwidth_change;
1134 xhci_dbg(xhci, "Completed config ep cmd - "
1135 "last ep index = %d, state = %d\n",
1136 ep_index, ep_state);
1137 /* Clear internal halted state and restart ring(s) */
1138 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1139 ~EP_HALTED;
1140 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1141 break;
1142 }
1143bandwidth_change:
1144 xhci_dbg(xhci, "Completed config ep cmd\n");
1145 xhci->devs[slot_id]->cmd_status =
1146 GET_COMP_CODE(le32_to_cpu(event->status));
1147 complete(&xhci->devs[slot_id]->cmd_completion);
1148 break;
1149 case TRB_TYPE(TRB_EVAL_CONTEXT):
1150 virt_dev = xhci->devs[slot_id];
1151 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1152 break;
1153 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1154 complete(&xhci->devs[slot_id]->cmd_completion);
1155 break;
1156 case TRB_TYPE(TRB_ADDR_DEV):
1157 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1158 complete(&xhci->addr_dev);
1159 break;
1160 case TRB_TYPE(TRB_STOP_RING):
1161 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1162 break;
1163 case TRB_TYPE(TRB_SET_DEQ):
1164 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1165 break;
1166 case TRB_TYPE(TRB_CMD_NOOP):
1167 break;
1168 case TRB_TYPE(TRB_RESET_EP):
1169 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1170 break;
1171 case TRB_TYPE(TRB_RESET_DEV):
1172 xhci_dbg(xhci, "Completed reset device command.\n");
1173 slot_id = TRB_TO_SLOT_ID(
1174 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1175 virt_dev = xhci->devs[slot_id];
1176 if (virt_dev)
1177 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1178 else
1179 xhci_warn(xhci, "Reset device command completion "
1180 "for disabled slot %u\n", slot_id);
1181 break;
1182 case TRB_TYPE(TRB_NEC_GET_FW):
1183 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1184 xhci->error_bitmask |= 1 << 6;
1185 break;
1186 }
1187 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1188 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1189 NEC_FW_MINOR(le32_to_cpu(event->status)));
1190 break;
1191 default:
1192 /* Skip over unknown commands on the event ring */
1193 xhci->error_bitmask |= 1 << 6;
1194 break;
1195 }
1196 inc_deq(xhci, xhci->cmd_ring, false);
1197}
1198
1199static void handle_vendor_event(struct xhci_hcd *xhci,
1200 union xhci_trb *event)
1201{
1202 u32 trb_type;
1203
1204 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1205 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1206 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1207 handle_cmd_completion(xhci, &event->event_cmd);
1208}
1209
1210/* @port_id: the one-based port ID from the hardware (indexed from array of all
1211 * port registers -- USB 3.0 and USB 2.0).
1212 *
1213 * Returns a zero-based port number, which is suitable for indexing into each of
1214 * the split roothubs' port arrays and bus state arrays.
1215 */
1216static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1217 struct xhci_hcd *xhci, u32 port_id)
1218{
1219 unsigned int i;
1220 unsigned int num_similar_speed_ports = 0;
1221
1222 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1223 * and usb2_ports are 0-based indexes. Count the number of similar
1224 * speed ports, up to 1 port before this port.
1225 */
1226 for (i = 0; i < (port_id - 1); i++) {
1227 u8 port_speed = xhci->port_array[i];
1228
1229 /*
1230 * Skip ports that don't have known speeds, or have duplicate
1231 * Extended Capabilities port speed entries.
1232 */
1233 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1234 continue;
1235
1236 /*
1237 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1238 * 1.1 ports are under the USB 2.0 hub. If the port speed
1239 * matches the device speed, it's a similar speed port.
1240 */
1241 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1242 num_similar_speed_ports++;
1243 }
1244 return num_similar_speed_ports;
1245}
1246
1247static void handle_port_status(struct xhci_hcd *xhci,
1248 union xhci_trb *event)
1249{
1250 struct usb_hcd *hcd;
1251 u32 port_id;
1252 u32 temp, temp1;
1253 int max_ports;
1254 int slot_id;
1255 unsigned int faked_port_index;
1256 u8 major_revision;
1257 struct xhci_bus_state *bus_state;
1258 __le32 __iomem **port_array;
1259 bool bogus_port_status = false;
1260
1261 /* Port status change events always have a successful completion code */
1262 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1263 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1264 xhci->error_bitmask |= 1 << 8;
1265 }
1266 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1267 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1268
1269 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1270 if ((port_id <= 0) || (port_id > max_ports)) {
1271 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1272 bogus_port_status = true;
1273 goto cleanup;
1274 }
1275
1276 /* Figure out which usb_hcd this port is attached to:
1277 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1278 */
1279 major_revision = xhci->port_array[port_id - 1];
1280 if (major_revision == 0) {
1281 xhci_warn(xhci, "Event for port %u not in "
1282 "Extended Capabilities, ignoring.\n",
1283 port_id);
1284 bogus_port_status = true;
1285 goto cleanup;
1286 }
1287 if (major_revision == DUPLICATE_ENTRY) {
1288 xhci_warn(xhci, "Event for port %u duplicated in"
1289 "Extended Capabilities, ignoring.\n",
1290 port_id);
1291 bogus_port_status = true;
1292 goto cleanup;
1293 }
1294
1295 /*
1296 * Hardware port IDs reported by a Port Status Change Event include USB
1297 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1298 * resume event, but we first need to translate the hardware port ID
1299 * into the index into the ports on the correct split roothub, and the
1300 * correct bus_state structure.
1301 */
1302 /* Find the right roothub. */
1303 hcd = xhci_to_hcd(xhci);
1304 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1305 hcd = xhci->shared_hcd;
1306 bus_state = &xhci->bus_state[hcd_index(hcd)];
1307 if (hcd->speed == HCD_USB3)
1308 port_array = xhci->usb3_ports;
1309 else
1310 port_array = xhci->usb2_ports;
1311 /* Find the faked port hub number */
1312 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1313 port_id);
1314
1315 temp = xhci_readl(xhci, port_array[faked_port_index]);
1316 if (hcd->state == HC_STATE_SUSPENDED) {
1317 xhci_dbg(xhci, "resume root hub\n");
1318 usb_hcd_resume_root_hub(hcd);
1319 }
1320
1321 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1322 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1323
1324 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1325 if (!(temp1 & CMD_RUN)) {
1326 xhci_warn(xhci, "xHC is not running.\n");
1327 goto cleanup;
1328 }
1329
1330 if (DEV_SUPERSPEED(temp)) {
1331 xhci_dbg(xhci, "resume SS port %d\n", port_id);
1332 temp = xhci_port_state_to_neutral(temp);
1333 temp &= ~PORT_PLS_MASK;
1334 temp |= PORT_LINK_STROBE | XDEV_U0;
1335 xhci_writel(xhci, temp, port_array[faked_port_index]);
1336 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1337 faked_port_index);
1338 if (!slot_id) {
1339 xhci_dbg(xhci, "slot_id is zero\n");
1340 goto cleanup;
1341 }
1342 xhci_ring_device(xhci, slot_id);
1343 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1344 /* Clear PORT_PLC */
1345 temp = xhci_readl(xhci, port_array[faked_port_index]);
1346 temp = xhci_port_state_to_neutral(temp);
1347 temp |= PORT_PLC;
1348 xhci_writel(xhci, temp, port_array[faked_port_index]);
1349 } else {
1350 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1351 bus_state->resume_done[faked_port_index] = jiffies +
1352 msecs_to_jiffies(20);
1353 mod_timer(&hcd->rh_timer,
1354 bus_state->resume_done[faked_port_index]);
1355 /* Do the rest in GetPortStatus */
1356 }
1357 }
1358
1359cleanup:
1360 /* Update event ring dequeue pointer before dropping the lock */
1361 inc_deq(xhci, xhci->event_ring, true);
1362
1363 /* Don't make the USB core poll the roothub if we got a bad port status
1364 * change event. Besides, at that point we can't tell which roothub
1365 * (USB 2.0 or USB 3.0) to kick.
1366 */
1367 if (bogus_port_status)
1368 return;
1369
1370 spin_unlock(&xhci->lock);
1371 /* Pass this up to the core */
1372 usb_hcd_poll_rh_status(hcd);
1373 spin_lock(&xhci->lock);
1374}
1375
1376/*
1377 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1378 * at end_trb, which may be in another segment. If the suspect DMA address is a
1379 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1380 * returns 0.
1381 */
1382struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1383 union xhci_trb *start_trb,
1384 union xhci_trb *end_trb,
1385 dma_addr_t suspect_dma)
1386{
1387 dma_addr_t start_dma;
1388 dma_addr_t end_seg_dma;
1389 dma_addr_t end_trb_dma;
1390 struct xhci_segment *cur_seg;
1391
1392 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1393 cur_seg = start_seg;
1394
1395 do {
1396 if (start_dma == 0)
1397 return NULL;
1398 /* We may get an event for a Link TRB in the middle of a TD */
1399 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1400 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1401 /* If the end TRB isn't in this segment, this is set to 0 */
1402 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1403
1404 if (end_trb_dma > 0) {
1405 /* The end TRB is in this segment, so suspect should be here */
1406 if (start_dma <= end_trb_dma) {
1407 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1408 return cur_seg;
1409 } else {
1410 /* Case for one segment with
1411 * a TD wrapped around to the top
1412 */
1413 if ((suspect_dma >= start_dma &&
1414 suspect_dma <= end_seg_dma) ||
1415 (suspect_dma >= cur_seg->dma &&
1416 suspect_dma <= end_trb_dma))
1417 return cur_seg;
1418 }
1419 return NULL;
1420 } else {
1421 /* Might still be somewhere in this segment */
1422 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1423 return cur_seg;
1424 }
1425 cur_seg = cur_seg->next;
1426 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1427 } while (cur_seg != start_seg);
1428
1429 return NULL;
1430}
1431
1432static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1433 unsigned int slot_id, unsigned int ep_index,
1434 unsigned int stream_id,
1435 struct xhci_td *td, union xhci_trb *event_trb)
1436{
1437 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1438 ep->ep_state |= EP_HALTED;
1439 ep->stopped_td = td;
1440 ep->stopped_trb = event_trb;
1441 ep->stopped_stream = stream_id;
1442
1443 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1444 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1445
1446 ep->stopped_td = NULL;
1447 ep->stopped_trb = NULL;
1448 ep->stopped_stream = 0;
1449
1450 xhci_ring_cmd_db(xhci);
1451}
1452
1453/* Check if an error has halted the endpoint ring. The class driver will
1454 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1455 * However, a babble and other errors also halt the endpoint ring, and the class
1456 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1457 * Ring Dequeue Pointer command manually.
1458 */
1459static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1460 struct xhci_ep_ctx *ep_ctx,
1461 unsigned int trb_comp_code)
1462{
1463 /* TRB completion codes that may require a manual halt cleanup */
1464 if (trb_comp_code == COMP_TX_ERR ||
1465 trb_comp_code == COMP_BABBLE ||
1466 trb_comp_code == COMP_SPLIT_ERR)
1467 /* The 0.96 spec says a babbling control endpoint
1468 * is not halted. The 0.96 spec says it is. Some HW
1469 * claims to be 0.95 compliant, but it halts the control
1470 * endpoint anyway. Check if a babble halted the
1471 * endpoint.
1472 */
1473 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1474 cpu_to_le32(EP_STATE_HALTED))
1475 return 1;
1476
1477 return 0;
1478}
1479
1480int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1481{
1482 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1483 /* Vendor defined "informational" completion code,
1484 * treat as not-an-error.
1485 */
1486 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1487 trb_comp_code);
1488 xhci_dbg(xhci, "Treating code as success.\n");
1489 return 1;
1490 }
1491 return 0;
1492}
1493
1494/*
1495 * Finish the td processing, remove the td from td list;
1496 * Return 1 if the urb can be given back.
1497 */
1498static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1499 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1500 struct xhci_virt_ep *ep, int *status, bool skip)
1501{
1502 struct xhci_virt_device *xdev;
1503 struct xhci_ring *ep_ring;
1504 unsigned int slot_id;
1505 int ep_index;
1506 struct urb *urb = NULL;
1507 struct xhci_ep_ctx *ep_ctx;
1508 int ret = 0;
1509 struct urb_priv *urb_priv;
1510 u32 trb_comp_code;
1511
1512 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1513 xdev = xhci->devs[slot_id];
1514 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1515 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1516 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1517 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1518
1519 if (skip)
1520 goto td_cleanup;
1521
1522 if (trb_comp_code == COMP_STOP_INVAL ||
1523 trb_comp_code == COMP_STOP) {
1524 /* The Endpoint Stop Command completion will take care of any
1525 * stopped TDs. A stopped TD may be restarted, so don't update
1526 * the ring dequeue pointer or take this TD off any lists yet.
1527 */
1528 ep->stopped_td = td;
1529 ep->stopped_trb = event_trb;
1530 return 0;
1531 } else {
1532 if (trb_comp_code == COMP_STALL) {
1533 /* The transfer is completed from the driver's
1534 * perspective, but we need to issue a set dequeue
1535 * command for this stalled endpoint to move the dequeue
1536 * pointer past the TD. We can't do that here because
1537 * the halt condition must be cleared first. Let the
1538 * USB class driver clear the stall later.
1539 */
1540 ep->stopped_td = td;
1541 ep->stopped_trb = event_trb;
1542 ep->stopped_stream = ep_ring->stream_id;
1543 } else if (xhci_requires_manual_halt_cleanup(xhci,
1544 ep_ctx, trb_comp_code)) {
1545 /* Other types of errors halt the endpoint, but the
1546 * class driver doesn't call usb_reset_endpoint() unless
1547 * the error is -EPIPE. Clear the halted status in the
1548 * xHCI hardware manually.
1549 */
1550 xhci_cleanup_halted_endpoint(xhci,
1551 slot_id, ep_index, ep_ring->stream_id,
1552 td, event_trb);
1553 } else {
1554 /* Update ring dequeue pointer */
1555 while (ep_ring->dequeue != td->last_trb)
1556 inc_deq(xhci, ep_ring, false);
1557 inc_deq(xhci, ep_ring, false);
1558 }
1559
1560td_cleanup:
1561 /* Clean up the endpoint's TD list */
1562 urb = td->urb;
1563 urb_priv = urb->hcpriv;
1564
1565 /* Do one last check of the actual transfer length.
1566 * If the host controller said we transferred more data than
1567 * the buffer length, urb->actual_length will be a very big
1568 * number (since it's unsigned). Play it safe and say we didn't
1569 * transfer anything.
1570 */
1571 if (urb->actual_length > urb->transfer_buffer_length) {
1572 xhci_warn(xhci, "URB transfer length is wrong, "
1573 "xHC issue? req. len = %u, "
1574 "act. len = %u\n",
1575 urb->transfer_buffer_length,
1576 urb->actual_length);
1577 urb->actual_length = 0;
1578 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1579 *status = -EREMOTEIO;
1580 else
1581 *status = 0;
1582 }
1583 list_del_init(&td->td_list);
1584 /* Was this TD slated to be cancelled but completed anyway? */
1585 if (!list_empty(&td->cancelled_td_list))
1586 list_del_init(&td->cancelled_td_list);
1587
1588 urb_priv->td_cnt++;
1589 /* Giveback the urb when all the tds are completed */
1590 if (urb_priv->td_cnt == urb_priv->length) {
1591 ret = 1;
1592 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1593 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1594 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1595 == 0) {
1596 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1597 usb_amd_quirk_pll_enable();
1598 }
1599 }
1600 }
1601 }
1602
1603 return ret;
1604}
1605
1606/*
1607 * Process control tds, update urb status and actual_length.
1608 */
1609static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1610 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1611 struct xhci_virt_ep *ep, int *status)
1612{
1613 struct xhci_virt_device *xdev;
1614 struct xhci_ring *ep_ring;
1615 unsigned int slot_id;
1616 int ep_index;
1617 struct xhci_ep_ctx *ep_ctx;
1618 u32 trb_comp_code;
1619
1620 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1621 xdev = xhci->devs[slot_id];
1622 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1623 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1624 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1625 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1626
1627 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1628 switch (trb_comp_code) {
1629 case COMP_SUCCESS:
1630 if (event_trb == ep_ring->dequeue) {
1631 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1632 "without IOC set??\n");
1633 *status = -ESHUTDOWN;
1634 } else if (event_trb != td->last_trb) {
1635 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1636 "without IOC set??\n");
1637 *status = -ESHUTDOWN;
1638 } else {
1639 *status = 0;
1640 }
1641 break;
1642 case COMP_SHORT_TX:
1643 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1644 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1645 *status = -EREMOTEIO;
1646 else
1647 *status = 0;
1648 break;
1649 case COMP_STOP_INVAL:
1650 case COMP_STOP:
1651 return finish_td(xhci, td, event_trb, event, ep, status, false);
1652 default:
1653 if (!xhci_requires_manual_halt_cleanup(xhci,
1654 ep_ctx, trb_comp_code))
1655 break;
1656 xhci_dbg(xhci, "TRB error code %u, "
1657 "halted endpoint index = %u\n",
1658 trb_comp_code, ep_index);
1659 /* else fall through */
1660 case COMP_STALL:
1661 /* Did we transfer part of the data (middle) phase? */
1662 if (event_trb != ep_ring->dequeue &&
1663 event_trb != td->last_trb)
1664 td->urb->actual_length =
1665 td->urb->transfer_buffer_length
1666 - TRB_LEN(le32_to_cpu(event->transfer_len));
1667 else
1668 td->urb->actual_length = 0;
1669
1670 xhci_cleanup_halted_endpoint(xhci,
1671 slot_id, ep_index, 0, td, event_trb);
1672 return finish_td(xhci, td, event_trb, event, ep, status, true);
1673 }
1674 /*
1675 * Did we transfer any data, despite the errors that might have
1676 * happened? I.e. did we get past the setup stage?
1677 */
1678 if (event_trb != ep_ring->dequeue) {
1679 /* The event was for the status stage */
1680 if (event_trb == td->last_trb) {
1681 if (td->urb->actual_length != 0) {
1682 /* Don't overwrite a previously set error code
1683 */
1684 if ((*status == -EINPROGRESS || *status == 0) &&
1685 (td->urb->transfer_flags
1686 & URB_SHORT_NOT_OK))
1687 /* Did we already see a short data
1688 * stage? */
1689 *status = -EREMOTEIO;
1690 } else {
1691 td->urb->actual_length =
1692 td->urb->transfer_buffer_length;
1693 }
1694 } else {
1695 /* Maybe the event was for the data stage? */
1696 td->urb->actual_length =
1697 td->urb->transfer_buffer_length -
1698 TRB_LEN(le32_to_cpu(event->transfer_len));
1699 xhci_dbg(xhci, "Waiting for status "
1700 "stage event\n");
1701 return 0;
1702 }
1703 }
1704
1705 return finish_td(xhci, td, event_trb, event, ep, status, false);
1706}
1707
1708/*
1709 * Process isochronous tds, update urb packet status and actual_length.
1710 */
1711static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1712 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1713 struct xhci_virt_ep *ep, int *status)
1714{
1715 struct xhci_ring *ep_ring;
1716 struct urb_priv *urb_priv;
1717 int idx;
1718 int len = 0;
1719 union xhci_trb *cur_trb;
1720 struct xhci_segment *cur_seg;
1721 struct usb_iso_packet_descriptor *frame;
1722 u32 trb_comp_code;
1723 bool skip_td = false;
1724
1725 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1726 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1727 urb_priv = td->urb->hcpriv;
1728 idx = urb_priv->td_cnt;
1729 frame = &td->urb->iso_frame_desc[idx];
1730
1731 /* handle completion code */
1732 switch (trb_comp_code) {
1733 case COMP_SUCCESS:
1734 frame->status = 0;
1735 break;
1736 case COMP_SHORT_TX:
1737 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1738 -EREMOTEIO : 0;
1739 break;
1740 case COMP_BW_OVER:
1741 frame->status = -ECOMM;
1742 skip_td = true;
1743 break;
1744 case COMP_BUFF_OVER:
1745 case COMP_BABBLE:
1746 frame->status = -EOVERFLOW;
1747 skip_td = true;
1748 break;
1749 case COMP_DEV_ERR:
1750 case COMP_STALL:
1751 frame->status = -EPROTO;
1752 skip_td = true;
1753 break;
1754 case COMP_STOP:
1755 case COMP_STOP_INVAL:
1756 break;
1757 default:
1758 frame->status = -1;
1759 break;
1760 }
1761
1762 if (trb_comp_code == COMP_SUCCESS || skip_td) {
1763 frame->actual_length = frame->length;
1764 td->urb->actual_length += frame->length;
1765 } else {
1766 for (cur_trb = ep_ring->dequeue,
1767 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1768 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1769 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1770 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1771 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1772 }
1773 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1774 TRB_LEN(le32_to_cpu(event->transfer_len));
1775
1776 if (trb_comp_code != COMP_STOP_INVAL) {
1777 frame->actual_length = len;
1778 td->urb->actual_length += len;
1779 }
1780 }
1781
1782 return finish_td(xhci, td, event_trb, event, ep, status, false);
1783}
1784
1785static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1786 struct xhci_transfer_event *event,
1787 struct xhci_virt_ep *ep, int *status)
1788{
1789 struct xhci_ring *ep_ring;
1790 struct urb_priv *urb_priv;
1791 struct usb_iso_packet_descriptor *frame;
1792 int idx;
1793
1794 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1795 urb_priv = td->urb->hcpriv;
1796 idx = urb_priv->td_cnt;
1797 frame = &td->urb->iso_frame_desc[idx];
1798
1799 /* The transfer is partly done. */
1800 frame->status = -EXDEV;
1801
1802 /* calc actual length */
1803 frame->actual_length = 0;
1804
1805 /* Update ring dequeue pointer */
1806 while (ep_ring->dequeue != td->last_trb)
1807 inc_deq(xhci, ep_ring, false);
1808 inc_deq(xhci, ep_ring, false);
1809
1810 return finish_td(xhci, td, NULL, event, ep, status, true);
1811}
1812
1813/*
1814 * Process bulk and interrupt tds, update urb status and actual_length.
1815 */
1816static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1817 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1818 struct xhci_virt_ep *ep, int *status)
1819{
1820 struct xhci_ring *ep_ring;
1821 union xhci_trb *cur_trb;
1822 struct xhci_segment *cur_seg;
1823 u32 trb_comp_code;
1824
1825 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1826 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1827
1828 switch (trb_comp_code) {
1829 case COMP_SUCCESS:
1830 /* Double check that the HW transferred everything. */
1831 if (event_trb != td->last_trb) {
1832 xhci_warn(xhci, "WARN Successful completion "
1833 "on short TX\n");
1834 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1835 *status = -EREMOTEIO;
1836 else
1837 *status = 0;
1838 } else {
1839 *status = 0;
1840 }
1841 break;
1842 case COMP_SHORT_TX:
1843 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1844 *status = -EREMOTEIO;
1845 else
1846 *status = 0;
1847 break;
1848 default:
1849 /* Others already handled above */
1850 break;
1851 }
1852 if (trb_comp_code == COMP_SHORT_TX)
1853 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1854 "%d bytes untransferred\n",
1855 td->urb->ep->desc.bEndpointAddress,
1856 td->urb->transfer_buffer_length,
1857 TRB_LEN(le32_to_cpu(event->transfer_len)));
1858 /* Fast path - was this the last TRB in the TD for this URB? */
1859 if (event_trb == td->last_trb) {
1860 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1861 td->urb->actual_length =
1862 td->urb->transfer_buffer_length -
1863 TRB_LEN(le32_to_cpu(event->transfer_len));
1864 if (td->urb->transfer_buffer_length <
1865 td->urb->actual_length) {
1866 xhci_warn(xhci, "HC gave bad length "
1867 "of %d bytes left\n",
1868 TRB_LEN(le32_to_cpu(event->transfer_len)));
1869 td->urb->actual_length = 0;
1870 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1871 *status = -EREMOTEIO;
1872 else
1873 *status = 0;
1874 }
1875 /* Don't overwrite a previously set error code */
1876 if (*status == -EINPROGRESS) {
1877 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1878 *status = -EREMOTEIO;
1879 else
1880 *status = 0;
1881 }
1882 } else {
1883 td->urb->actual_length =
1884 td->urb->transfer_buffer_length;
1885 /* Ignore a short packet completion if the
1886 * untransferred length was zero.
1887 */
1888 if (*status == -EREMOTEIO)
1889 *status = 0;
1890 }
1891 } else {
1892 /* Slow path - walk the list, starting from the dequeue
1893 * pointer, to get the actual length transferred.
1894 */
1895 td->urb->actual_length = 0;
1896 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1897 cur_trb != event_trb;
1898 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1899 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1900 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1901 td->urb->actual_length +=
1902 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1903 }
1904 /* If the ring didn't stop on a Link or No-op TRB, add
1905 * in the actual bytes transferred from the Normal TRB
1906 */
1907 if (trb_comp_code != COMP_STOP_INVAL)
1908 td->urb->actual_length +=
1909 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1910 TRB_LEN(le32_to_cpu(event->transfer_len));
1911 }
1912
1913 return finish_td(xhci, td, event_trb, event, ep, status, false);
1914}
1915
1916/*
1917 * If this function returns an error condition, it means it got a Transfer
1918 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1919 * At this point, the host controller is probably hosed and should be reset.
1920 */
1921static int handle_tx_event(struct xhci_hcd *xhci,
1922 struct xhci_transfer_event *event)
1923{
1924 struct xhci_virt_device *xdev;
1925 struct xhci_virt_ep *ep;
1926 struct xhci_ring *ep_ring;
1927 unsigned int slot_id;
1928 int ep_index;
1929 struct xhci_td *td = NULL;
1930 dma_addr_t event_dma;
1931 struct xhci_segment *event_seg;
1932 union xhci_trb *event_trb;
1933 struct urb *urb = NULL;
1934 int status = -EINPROGRESS;
1935 struct urb_priv *urb_priv;
1936 struct xhci_ep_ctx *ep_ctx;
1937 struct list_head *tmp;
1938 u32 trb_comp_code;
1939 int ret = 0;
1940 int td_num = 0;
1941
1942 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1943 xdev = xhci->devs[slot_id];
1944 if (!xdev) {
1945 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1946 return -ENODEV;
1947 }
1948
1949 /* Endpoint ID is 1 based, our index is zero based */
1950 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1951 ep = &xdev->eps[ep_index];
1952 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1953 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1954 if (!ep_ring ||
1955 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
1956 EP_STATE_DISABLED) {
1957 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1958 "or incorrect stream ring\n");
1959 return -ENODEV;
1960 }
1961
1962 /* Count current td numbers if ep->skip is set */
1963 if (ep->skip) {
1964 list_for_each(tmp, &ep_ring->td_list)
1965 td_num++;
1966 }
1967
1968 event_dma = le64_to_cpu(event->buffer);
1969 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1970 /* Look for common error cases */
1971 switch (trb_comp_code) {
1972 /* Skip codes that require special handling depending on
1973 * transfer type
1974 */
1975 case COMP_SUCCESS:
1976 case COMP_SHORT_TX:
1977 break;
1978 case COMP_STOP:
1979 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1980 break;
1981 case COMP_STOP_INVAL:
1982 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1983 break;
1984 case COMP_STALL:
1985 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1986 ep->ep_state |= EP_HALTED;
1987 status = -EPIPE;
1988 break;
1989 case COMP_TRB_ERR:
1990 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1991 status = -EILSEQ;
1992 break;
1993 case COMP_SPLIT_ERR:
1994 case COMP_TX_ERR:
1995 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1996 status = -EPROTO;
1997 break;
1998 case COMP_BABBLE:
1999 xhci_warn(xhci, "WARN: babble error on endpoint\n");
2000 status = -EOVERFLOW;
2001 break;
2002 case COMP_DB_ERR:
2003 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2004 status = -ENOSR;
2005 break;
2006 case COMP_BW_OVER:
2007 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2008 break;
2009 case COMP_BUFF_OVER:
2010 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2011 break;
2012 case COMP_UNDERRUN:
2013 /*
2014 * When the Isoch ring is empty, the xHC will generate
2015 * a Ring Overrun Event for IN Isoch endpoint or Ring
2016 * Underrun Event for OUT Isoch endpoint.
2017 */
2018 xhci_dbg(xhci, "underrun event on endpoint\n");
2019 if (!list_empty(&ep_ring->td_list))
2020 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2021 "still with TDs queued?\n",
2022 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2023 ep_index);
2024 goto cleanup;
2025 case COMP_OVERRUN:
2026 xhci_dbg(xhci, "overrun event on endpoint\n");
2027 if (!list_empty(&ep_ring->td_list))
2028 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2029 "still with TDs queued?\n",
2030 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2031 ep_index);
2032 goto cleanup;
2033 case COMP_DEV_ERR:
2034 xhci_warn(xhci, "WARN: detect an incompatible device");
2035 status = -EPROTO;
2036 break;
2037 case COMP_MISSED_INT:
2038 /*
2039 * When encounter missed service error, one or more isoc tds
2040 * may be missed by xHC.
2041 * Set skip flag of the ep_ring; Complete the missed tds as
2042 * short transfer when process the ep_ring next time.
2043 */
2044 ep->skip = true;
2045 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2046 goto cleanup;
2047 default:
2048 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2049 status = 0;
2050 break;
2051 }
2052 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2053 "busted\n");
2054 goto cleanup;
2055 }
2056
2057 do {
2058 /* This TRB should be in the TD at the head of this ring's
2059 * TD list.
2060 */
2061 if (list_empty(&ep_ring->td_list)) {
2062 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2063 "with no TDs queued?\n",
2064 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2065 ep_index);
2066 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2067 (le32_to_cpu(event->flags) &
2068 TRB_TYPE_BITMASK)>>10);
2069 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2070 if (ep->skip) {
2071 ep->skip = false;
2072 xhci_dbg(xhci, "td_list is empty while skip "
2073 "flag set. Clear skip flag.\n");
2074 }
2075 ret = 0;
2076 goto cleanup;
2077 }
2078
2079 /* We've skipped all the TDs on the ep ring when ep->skip set */
2080 if (ep->skip && td_num == 0) {
2081 ep->skip = false;
2082 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2083 "Clear skip flag.\n");
2084 ret = 0;
2085 goto cleanup;
2086 }
2087
2088 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2089 if (ep->skip)
2090 td_num--;
2091
2092 /* Is this a TRB in the currently executing TD? */
2093 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2094 td->last_trb, event_dma);
2095
2096 /*
2097 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2098 * is not in the current TD pointed by ep_ring->dequeue because
2099 * that the hardware dequeue pointer still at the previous TRB
2100 * of the current TD. The previous TRB maybe a Link TD or the
2101 * last TRB of the previous TD. The command completion handle
2102 * will take care the rest.
2103 */
2104 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2105 ret = 0;
2106 goto cleanup;
2107 }
2108
2109 if (!event_seg) {
2110 if (!ep->skip ||
2111 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2112 /* Some host controllers give a spurious
2113 * successful event after a short transfer.
2114 * Ignore it.
2115 */
2116 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2117 ep_ring->last_td_was_short) {
2118 ep_ring->last_td_was_short = false;
2119 ret = 0;
2120 goto cleanup;
2121 }
2122 /* HC is busted, give up! */
2123 xhci_err(xhci,
2124 "ERROR Transfer event TRB DMA ptr not "
2125 "part of current TD\n");
2126 return -ESHUTDOWN;
2127 }
2128
2129 ret = skip_isoc_td(xhci, td, event, ep, &status);
2130 goto cleanup;
2131 }
2132 if (trb_comp_code == COMP_SHORT_TX)
2133 ep_ring->last_td_was_short = true;
2134 else
2135 ep_ring->last_td_was_short = false;
2136
2137 if (ep->skip) {
2138 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2139 ep->skip = false;
2140 }
2141
2142 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2143 sizeof(*event_trb)];
2144 /*
2145 * No-op TRB should not trigger interrupts.
2146 * If event_trb is a no-op TRB, it means the
2147 * corresponding TD has been cancelled. Just ignore
2148 * the TD.
2149 */
2150 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2151 xhci_dbg(xhci,
2152 "event_trb is a no-op TRB. Skip it\n");
2153 goto cleanup;
2154 }
2155
2156 /* Now update the urb's actual_length and give back to
2157 * the core
2158 */
2159 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2160 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2161 &status);
2162 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2163 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2164 &status);
2165 else
2166 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2167 ep, &status);
2168
2169cleanup:
2170 /*
2171 * Do not update event ring dequeue pointer if ep->skip is set.
2172 * Will roll back to continue process missed tds.
2173 */
2174 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2175 inc_deq(xhci, xhci->event_ring, true);
2176 }
2177
2178 if (ret) {
2179 urb = td->urb;
2180 urb_priv = urb->hcpriv;
2181 /* Leave the TD around for the reset endpoint function
2182 * to use(but only if it's not a control endpoint,
2183 * since we already queued the Set TR dequeue pointer
2184 * command for stalled control endpoints).
2185 */
2186 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2187 (trb_comp_code != COMP_STALL &&
2188 trb_comp_code != COMP_BABBLE))
2189 xhci_urb_free_priv(xhci, urb_priv);
2190
2191 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2192 if ((urb->actual_length != urb->transfer_buffer_length &&
2193 (urb->transfer_flags &
2194 URB_SHORT_NOT_OK)) ||
2195 status != 0)
2196 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2197 "expected = %x, status = %d\n",
2198 urb, urb->actual_length,
2199 urb->transfer_buffer_length,
2200 status);
2201 spin_unlock(&xhci->lock);
2202 /* EHCI, UHCI, and OHCI always unconditionally set the
2203 * urb->status of an isochronous endpoint to 0.
2204 */
2205 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2206 status = 0;
2207 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2208 spin_lock(&xhci->lock);
2209 }
2210
2211 /*
2212 * If ep->skip is set, it means there are missed tds on the
2213 * endpoint ring need to take care of.
2214 * Process them as short transfer until reach the td pointed by
2215 * the event.
2216 */
2217 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2218
2219 return 0;
2220}
2221
2222/*
2223 * This function handles all OS-owned events on the event ring. It may drop
2224 * xhci->lock between event processing (e.g. to pass up port status changes).
2225 * Returns >0 for "possibly more events to process" (caller should call again),
2226 * otherwise 0 if done. In future, <0 returns should indicate error code.
2227 */
2228static int xhci_handle_event(struct xhci_hcd *xhci)
2229{
2230 union xhci_trb *event;
2231 int update_ptrs = 1;
2232 int ret;
2233
2234 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2235 xhci->error_bitmask |= 1 << 1;
2236 return 0;
2237 }
2238
2239 event = xhci->event_ring->dequeue;
2240 /* Does the HC or OS own the TRB? */
2241 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2242 xhci->event_ring->cycle_state) {
2243 xhci->error_bitmask |= 1 << 2;
2244 return 0;
2245 }
2246
2247 /*
2248 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2249 * speculative reads of the event's flags/data below.
2250 */
2251 rmb();
2252 /* FIXME: Handle more event types. */
2253 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2254 case TRB_TYPE(TRB_COMPLETION):
2255 handle_cmd_completion(xhci, &event->event_cmd);
2256 break;
2257 case TRB_TYPE(TRB_PORT_STATUS):
2258 handle_port_status(xhci, event);
2259 update_ptrs = 0;
2260 break;
2261 case TRB_TYPE(TRB_TRANSFER):
2262 ret = handle_tx_event(xhci, &event->trans_event);
2263 if (ret < 0)
2264 xhci->error_bitmask |= 1 << 9;
2265 else
2266 update_ptrs = 0;
2267 break;
2268 default:
2269 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2270 TRB_TYPE(48))
2271 handle_vendor_event(xhci, event);
2272 else
2273 xhci->error_bitmask |= 1 << 3;
2274 }
2275 /* Any of the above functions may drop and re-acquire the lock, so check
2276 * to make sure a watchdog timer didn't mark the host as non-responsive.
2277 */
2278 if (xhci->xhc_state & XHCI_STATE_DYING) {
2279 xhci_dbg(xhci, "xHCI host dying, returning from "
2280 "event handler.\n");
2281 return 0;
2282 }
2283
2284 if (update_ptrs)
2285 /* Update SW event ring dequeue pointer */
2286 inc_deq(xhci, xhci->event_ring, true);
2287
2288 /* Are there more items on the event ring? Caller will call us again to
2289 * check.
2290 */
2291 return 1;
2292}
2293
2294/*
2295 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2296 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2297 * indicators of an event TRB error, but we check the status *first* to be safe.
2298 */
2299irqreturn_t xhci_irq(struct usb_hcd *hcd)
2300{
2301 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2302 u32 status;
2303 union xhci_trb *trb;
2304 u64 temp_64;
2305 union xhci_trb *event_ring_deq;
2306 dma_addr_t deq;
2307
2308 spin_lock(&xhci->lock);
2309 trb = xhci->event_ring->dequeue;
2310 /* Check if the xHC generated the interrupt, or the irq is shared */
2311 status = xhci_readl(xhci, &xhci->op_regs->status);
2312 if (status == 0xffffffff)
2313 goto hw_died;
2314
2315 if (!(status & STS_EINT)) {
2316 spin_unlock(&xhci->lock);
2317 return IRQ_NONE;
2318 }
2319 if (status & STS_FATAL) {
2320 xhci_warn(xhci, "WARNING: Host System Error\n");
2321 xhci_halt(xhci);
2322hw_died:
2323 spin_unlock(&xhci->lock);
2324 return -ESHUTDOWN;
2325 }
2326
2327 /*
2328 * Clear the op reg interrupt status first,
2329 * so we can receive interrupts from other MSI-X interrupters.
2330 * Write 1 to clear the interrupt status.
2331 */
2332 status |= STS_EINT;
2333 xhci_writel(xhci, status, &xhci->op_regs->status);
2334 /* FIXME when MSI-X is supported and there are multiple vectors */
2335 /* Clear the MSI-X event interrupt status */
2336
2337 if (hcd->irq != -1) {
2338 u32 irq_pending;
2339 /* Acknowledge the PCI interrupt */
2340 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2341 irq_pending |= 0x3;
2342 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2343 }
2344
2345 if (xhci->xhc_state & XHCI_STATE_DYING) {
2346 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2347 "Shouldn't IRQs be disabled?\n");
2348 /* Clear the event handler busy flag (RW1C);
2349 * the event ring should be empty.
2350 */
2351 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2352 xhci_write_64(xhci, temp_64 | ERST_EHB,
2353 &xhci->ir_set->erst_dequeue);
2354 spin_unlock(&xhci->lock);
2355
2356 return IRQ_HANDLED;
2357 }
2358
2359 event_ring_deq = xhci->event_ring->dequeue;
2360 /* FIXME this should be a delayed service routine
2361 * that clears the EHB.
2362 */
2363 while (xhci_handle_event(xhci) > 0) {}
2364
2365 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2366 /* If necessary, update the HW's version of the event ring deq ptr. */
2367 if (event_ring_deq != xhci->event_ring->dequeue) {
2368 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2369 xhci->event_ring->dequeue);
2370 if (deq == 0)
2371 xhci_warn(xhci, "WARN something wrong with SW event "
2372 "ring dequeue ptr.\n");
2373 /* Update HC event ring dequeue pointer */
2374 temp_64 &= ERST_PTR_MASK;
2375 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2376 }
2377
2378 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2379 temp_64 |= ERST_EHB;
2380 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2381
2382 spin_unlock(&xhci->lock);
2383
2384 return IRQ_HANDLED;
2385}
2386
2387irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2388{
2389 irqreturn_t ret;
2390 struct xhci_hcd *xhci;
2391
2392 xhci = hcd_to_xhci(hcd);
2393 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2394 if (xhci->shared_hcd)
2395 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2396
2397 ret = xhci_irq(hcd);
2398
2399 return ret;
2400}
2401
2402/**** Endpoint Ring Operations ****/
2403
2404/*
2405 * Generic function for queueing a TRB on a ring.
2406 * The caller must have checked to make sure there's room on the ring.
2407 *
2408 * @more_trbs_coming: Will you enqueue more TRBs before calling
2409 * prepare_transfer()?
2410 */
2411static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2412 bool consumer, bool more_trbs_coming,
2413 u32 field1, u32 field2, u32 field3, u32 field4)
2414{
2415 struct xhci_generic_trb *trb;
2416
2417 trb = &ring->enqueue->generic;
2418 trb->field[0] = cpu_to_le32(field1);
2419 trb->field[1] = cpu_to_le32(field2);
2420 trb->field[2] = cpu_to_le32(field3);
2421 trb->field[3] = cpu_to_le32(field4);
2422 inc_enq(xhci, ring, consumer, more_trbs_coming);
2423}
2424
2425/*
2426 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2427 * FIXME allocate segments if the ring is full.
2428 */
2429static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2430 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2431{
2432 /* Make sure the endpoint has been added to xHC schedule */
2433 switch (ep_state) {
2434 case EP_STATE_DISABLED:
2435 /*
2436 * USB core changed config/interfaces without notifying us,
2437 * or hardware is reporting the wrong state.
2438 */
2439 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2440 return -ENOENT;
2441 case EP_STATE_ERROR:
2442 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2443 /* FIXME event handling code for error needs to clear it */
2444 /* XXX not sure if this should be -ENOENT or not */
2445 return -EINVAL;
2446 case EP_STATE_HALTED:
2447 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2448 case EP_STATE_STOPPED:
2449 case EP_STATE_RUNNING:
2450 break;
2451 default:
2452 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2453 /*
2454 * FIXME issue Configure Endpoint command to try to get the HC
2455 * back into a known state.
2456 */
2457 return -EINVAL;
2458 }
2459 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2460 /* FIXME allocate more room */
2461 xhci_err(xhci, "ERROR no room on ep ring\n");
2462 return -ENOMEM;
2463 }
2464
2465 if (enqueue_is_link_trb(ep_ring)) {
2466 struct xhci_ring *ring = ep_ring;
2467 union xhci_trb *next;
2468
2469 next = ring->enqueue;
2470
2471 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2472 /* If we're not dealing with 0.95 hardware,
2473 * clear the chain bit.
2474 */
2475 if (!xhci_link_trb_quirk(xhci))
2476 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2477 else
2478 next->link.control |= cpu_to_le32(TRB_CHAIN);
2479
2480 wmb();
2481 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2482
2483 /* Toggle the cycle bit after the last ring segment. */
2484 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2485 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2486 if (!in_interrupt()) {
2487 xhci_dbg(xhci, "queue_trb: Toggle cycle "
2488 "state for ring %p = %i\n",
2489 ring, (unsigned int)ring->cycle_state);
2490 }
2491 }
2492 ring->enq_seg = ring->enq_seg->next;
2493 ring->enqueue = ring->enq_seg->trbs;
2494 next = ring->enqueue;
2495 }
2496 }
2497
2498 return 0;
2499}
2500
2501static int prepare_transfer(struct xhci_hcd *xhci,
2502 struct xhci_virt_device *xdev,
2503 unsigned int ep_index,
2504 unsigned int stream_id,
2505 unsigned int num_trbs,
2506 struct urb *urb,
2507 unsigned int td_index,
2508 gfp_t mem_flags)
2509{
2510 int ret;
2511 struct urb_priv *urb_priv;
2512 struct xhci_td *td;
2513 struct xhci_ring *ep_ring;
2514 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2515
2516 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2517 if (!ep_ring) {
2518 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2519 stream_id);
2520 return -EINVAL;
2521 }
2522
2523 ret = prepare_ring(xhci, ep_ring,
2524 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2525 num_trbs, mem_flags);
2526 if (ret)
2527 return ret;
2528
2529 urb_priv = urb->hcpriv;
2530 td = urb_priv->td[td_index];
2531
2532 INIT_LIST_HEAD(&td->td_list);
2533 INIT_LIST_HEAD(&td->cancelled_td_list);
2534
2535 if (td_index == 0) {
2536 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2537 if (unlikely(ret))
2538 return ret;
2539 }
2540
2541 td->urb = urb;
2542 /* Add this TD to the tail of the endpoint ring's TD list */
2543 list_add_tail(&td->td_list, &ep_ring->td_list);
2544 td->start_seg = ep_ring->enq_seg;
2545 td->first_trb = ep_ring->enqueue;
2546
2547 urb_priv->td[td_index] = td;
2548
2549 return 0;
2550}
2551
2552static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2553{
2554 int num_sgs, num_trbs, running_total, temp, i;
2555 struct scatterlist *sg;
2556
2557 sg = NULL;
2558 num_sgs = urb->num_sgs;
2559 temp = urb->transfer_buffer_length;
2560
2561 xhci_dbg(xhci, "count sg list trbs: \n");
2562 num_trbs = 0;
2563 for_each_sg(urb->sg, sg, num_sgs, i) {
2564 unsigned int previous_total_trbs = num_trbs;
2565 unsigned int len = sg_dma_len(sg);
2566
2567 /* Scatter gather list entries may cross 64KB boundaries */
2568 running_total = TRB_MAX_BUFF_SIZE -
2569 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2570 running_total &= TRB_MAX_BUFF_SIZE - 1;
2571 if (running_total != 0)
2572 num_trbs++;
2573
2574 /* How many more 64KB chunks to transfer, how many more TRBs? */
2575 while (running_total < sg_dma_len(sg) && running_total < temp) {
2576 num_trbs++;
2577 running_total += TRB_MAX_BUFF_SIZE;
2578 }
2579 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2580 i, (unsigned long long)sg_dma_address(sg),
2581 len, len, num_trbs - previous_total_trbs);
2582
2583 len = min_t(int, len, temp);
2584 temp -= len;
2585 if (temp == 0)
2586 break;
2587 }
2588 xhci_dbg(xhci, "\n");
2589 if (!in_interrupt())
2590 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2591 "num_trbs = %d\n",
2592 urb->ep->desc.bEndpointAddress,
2593 urb->transfer_buffer_length,
2594 num_trbs);
2595 return num_trbs;
2596}
2597
2598static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2599{
2600 if (num_trbs != 0)
2601 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2602 "TRBs, %d left\n", __func__,
2603 urb->ep->desc.bEndpointAddress, num_trbs);
2604 if (running_total != urb->transfer_buffer_length)
2605 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2606 "queued %#x (%d), asked for %#x (%d)\n",
2607 __func__,
2608 urb->ep->desc.bEndpointAddress,
2609 running_total, running_total,
2610 urb->transfer_buffer_length,
2611 urb->transfer_buffer_length);
2612}
2613
2614static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2615 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2616 struct xhci_generic_trb *start_trb)
2617{
2618 /*
2619 * Pass all the TRBs to the hardware at once and make sure this write
2620 * isn't reordered.
2621 */
2622 wmb();
2623 if (start_cycle)
2624 start_trb->field[3] |= cpu_to_le32(start_cycle);
2625 else
2626 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2627 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2628}
2629
2630/*
2631 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2632 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2633 * (comprised of sg list entries) can take several service intervals to
2634 * transmit.
2635 */
2636int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2637 struct urb *urb, int slot_id, unsigned int ep_index)
2638{
2639 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2640 xhci->devs[slot_id]->out_ctx, ep_index);
2641 int xhci_interval;
2642 int ep_interval;
2643
2644 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2645 ep_interval = urb->interval;
2646 /* Convert to microframes */
2647 if (urb->dev->speed == USB_SPEED_LOW ||
2648 urb->dev->speed == USB_SPEED_FULL)
2649 ep_interval *= 8;
2650 /* FIXME change this to a warning and a suggestion to use the new API
2651 * to set the polling interval (once the API is added).
2652 */
2653 if (xhci_interval != ep_interval) {
2654 if (printk_ratelimit())
2655 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2656 " (%d microframe%s) than xHCI "
2657 "(%d microframe%s)\n",
2658 ep_interval,
2659 ep_interval == 1 ? "" : "s",
2660 xhci_interval,
2661 xhci_interval == 1 ? "" : "s");
2662 urb->interval = xhci_interval;
2663 /* Convert back to frames for LS/FS devices */
2664 if (urb->dev->speed == USB_SPEED_LOW ||
2665 urb->dev->speed == USB_SPEED_FULL)
2666 urb->interval /= 8;
2667 }
2668 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2669}
2670
2671/*
2672 * The TD size is the number of bytes remaining in the TD (including this TRB),
2673 * right shifted by 10.
2674 * It must fit in bits 21:17, so it can't be bigger than 31.
2675 */
2676static u32 xhci_td_remainder(unsigned int remainder)
2677{
2678 u32 max = (1 << (21 - 17 + 1)) - 1;
2679
2680 if ((remainder >> 10) >= max)
2681 return max << 17;
2682 else
2683 return (remainder >> 10) << 17;
2684}
2685
2686/*
2687 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2688 * the TD (*not* including this TRB).
2689 *
2690 * Total TD packet count = total_packet_count =
2691 * roundup(TD size in bytes / wMaxPacketSize)
2692 *
2693 * Packets transferred up to and including this TRB = packets_transferred =
2694 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2695 *
2696 * TD size = total_packet_count - packets_transferred
2697 *
2698 * It must fit in bits 21:17, so it can't be bigger than 31.
2699 */
2700
2701static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2702 unsigned int total_packet_count, struct urb *urb)
2703{
2704 int packets_transferred;
2705
2706 /* One TRB with a zero-length data packet. */
2707 if (running_total == 0 && trb_buff_len == 0)
2708 return 0;
2709
2710 /* All the TRB queueing functions don't count the current TRB in
2711 * running_total.
2712 */
2713 packets_transferred = (running_total + trb_buff_len) /
2714 le16_to_cpu(urb->ep->desc.wMaxPacketSize);
2715
2716 return xhci_td_remainder(total_packet_count - packets_transferred);
2717}
2718
2719static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2720 struct urb *urb, int slot_id, unsigned int ep_index)
2721{
2722 struct xhci_ring *ep_ring;
2723 unsigned int num_trbs;
2724 struct urb_priv *urb_priv;
2725 struct xhci_td *td;
2726 struct scatterlist *sg;
2727 int num_sgs;
2728 int trb_buff_len, this_sg_len, running_total;
2729 unsigned int total_packet_count;
2730 bool first_trb;
2731 u64 addr;
2732 bool more_trbs_coming;
2733
2734 struct xhci_generic_trb *start_trb;
2735 int start_cycle;
2736
2737 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2738 if (!ep_ring)
2739 return -EINVAL;
2740
2741 num_trbs = count_sg_trbs_needed(xhci, urb);
2742 num_sgs = urb->num_sgs;
2743 total_packet_count = roundup(urb->transfer_buffer_length,
2744 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
2745
2746 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2747 ep_index, urb->stream_id,
2748 num_trbs, urb, 0, mem_flags);
2749 if (trb_buff_len < 0)
2750 return trb_buff_len;
2751
2752 urb_priv = urb->hcpriv;
2753 td = urb_priv->td[0];
2754
2755 /*
2756 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2757 * until we've finished creating all the other TRBs. The ring's cycle
2758 * state may change as we enqueue the other TRBs, so save it too.
2759 */
2760 start_trb = &ep_ring->enqueue->generic;
2761 start_cycle = ep_ring->cycle_state;
2762
2763 running_total = 0;
2764 /*
2765 * How much data is in the first TRB?
2766 *
2767 * There are three forces at work for TRB buffer pointers and lengths:
2768 * 1. We don't want to walk off the end of this sg-list entry buffer.
2769 * 2. The transfer length that the driver requested may be smaller than
2770 * the amount of memory allocated for this scatter-gather list.
2771 * 3. TRBs buffers can't cross 64KB boundaries.
2772 */
2773 sg = urb->sg;
2774 addr = (u64) sg_dma_address(sg);
2775 this_sg_len = sg_dma_len(sg);
2776 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2777 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2778 if (trb_buff_len > urb->transfer_buffer_length)
2779 trb_buff_len = urb->transfer_buffer_length;
2780 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2781 trb_buff_len);
2782
2783 first_trb = true;
2784 /* Queue the first TRB, even if it's zero-length */
2785 do {
2786 u32 field = 0;
2787 u32 length_field = 0;
2788 u32 remainder = 0;
2789
2790 /* Don't change the cycle bit of the first TRB until later */
2791 if (first_trb) {
2792 first_trb = false;
2793 if (start_cycle == 0)
2794 field |= 0x1;
2795 } else
2796 field |= ep_ring->cycle_state;
2797
2798 /* Chain all the TRBs together; clear the chain bit in the last
2799 * TRB to indicate it's the last TRB in the chain.
2800 */
2801 if (num_trbs > 1) {
2802 field |= TRB_CHAIN;
2803 } else {
2804 /* FIXME - add check for ZERO_PACKET flag before this */
2805 td->last_trb = ep_ring->enqueue;
2806 field |= TRB_IOC;
2807 }
2808
2809 /* Only set interrupt on short packet for IN endpoints */
2810 if (usb_urb_dir_in(urb))
2811 field |= TRB_ISP;
2812
2813 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2814 "64KB boundary at %#x, end dma = %#x\n",
2815 (unsigned int) addr, trb_buff_len, trb_buff_len,
2816 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2817 (unsigned int) addr + trb_buff_len);
2818 if (TRB_MAX_BUFF_SIZE -
2819 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2820 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2821 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2822 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2823 (unsigned int) addr + trb_buff_len);
2824 }
2825
2826 /* Set the TRB length, TD size, and interrupter fields. */
2827 if (xhci->hci_version < 0x100) {
2828 remainder = xhci_td_remainder(
2829 urb->transfer_buffer_length -
2830 running_total);
2831 } else {
2832 remainder = xhci_v1_0_td_remainder(running_total,
2833 trb_buff_len, total_packet_count, urb);
2834 }
2835 length_field = TRB_LEN(trb_buff_len) |
2836 remainder |
2837 TRB_INTR_TARGET(0);
2838
2839 if (num_trbs > 1)
2840 more_trbs_coming = true;
2841 else
2842 more_trbs_coming = false;
2843 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2844 lower_32_bits(addr),
2845 upper_32_bits(addr),
2846 length_field,
2847 field | TRB_TYPE(TRB_NORMAL));
2848 --num_trbs;
2849 running_total += trb_buff_len;
2850
2851 /* Calculate length for next transfer --
2852 * Are we done queueing all the TRBs for this sg entry?
2853 */
2854 this_sg_len -= trb_buff_len;
2855 if (this_sg_len == 0) {
2856 --num_sgs;
2857 if (num_sgs == 0)
2858 break;
2859 sg = sg_next(sg);
2860 addr = (u64) sg_dma_address(sg);
2861 this_sg_len = sg_dma_len(sg);
2862 } else {
2863 addr += trb_buff_len;
2864 }
2865
2866 trb_buff_len = TRB_MAX_BUFF_SIZE -
2867 (addr & (TRB_MAX_BUFF_SIZE - 1));
2868 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2869 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2870 trb_buff_len =
2871 urb->transfer_buffer_length - running_total;
2872 } while (running_total < urb->transfer_buffer_length);
2873
2874 check_trb_math(urb, num_trbs, running_total);
2875 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2876 start_cycle, start_trb);
2877 return 0;
2878}
2879
2880/* This is very similar to what ehci-q.c qtd_fill() does */
2881int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2882 struct urb *urb, int slot_id, unsigned int ep_index)
2883{
2884 struct xhci_ring *ep_ring;
2885 struct urb_priv *urb_priv;
2886 struct xhci_td *td;
2887 int num_trbs;
2888 struct xhci_generic_trb *start_trb;
2889 bool first_trb;
2890 bool more_trbs_coming;
2891 int start_cycle;
2892 u32 field, length_field;
2893
2894 int running_total, trb_buff_len, ret;
2895 unsigned int total_packet_count;
2896 u64 addr;
2897
2898 if (urb->num_sgs)
2899 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2900
2901 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2902 if (!ep_ring)
2903 return -EINVAL;
2904
2905 num_trbs = 0;
2906 /* How much data is (potentially) left before the 64KB boundary? */
2907 running_total = TRB_MAX_BUFF_SIZE -
2908 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2909 running_total &= TRB_MAX_BUFF_SIZE - 1;
2910
2911 /* If there's some data on this 64KB chunk, or we have to send a
2912 * zero-length transfer, we need at least one TRB
2913 */
2914 if (running_total != 0 || urb->transfer_buffer_length == 0)
2915 num_trbs++;
2916 /* How many more 64KB chunks to transfer, how many more TRBs? */
2917 while (running_total < urb->transfer_buffer_length) {
2918 num_trbs++;
2919 running_total += TRB_MAX_BUFF_SIZE;
2920 }
2921 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2922
2923 if (!in_interrupt())
2924 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2925 "addr = %#llx, num_trbs = %d\n",
2926 urb->ep->desc.bEndpointAddress,
2927 urb->transfer_buffer_length,
2928 urb->transfer_buffer_length,
2929 (unsigned long long)urb->transfer_dma,
2930 num_trbs);
2931
2932 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2933 ep_index, urb->stream_id,
2934 num_trbs, urb, 0, mem_flags);
2935 if (ret < 0)
2936 return ret;
2937
2938 urb_priv = urb->hcpriv;
2939 td = urb_priv->td[0];
2940
2941 /*
2942 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2943 * until we've finished creating all the other TRBs. The ring's cycle
2944 * state may change as we enqueue the other TRBs, so save it too.
2945 */
2946 start_trb = &ep_ring->enqueue->generic;
2947 start_cycle = ep_ring->cycle_state;
2948
2949 running_total = 0;
2950 total_packet_count = roundup(urb->transfer_buffer_length,
2951 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
2952 /* How much data is in the first TRB? */
2953 addr = (u64) urb->transfer_dma;
2954 trb_buff_len = TRB_MAX_BUFF_SIZE -
2955 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2956 if (trb_buff_len > urb->transfer_buffer_length)
2957 trb_buff_len = urb->transfer_buffer_length;
2958
2959 first_trb = true;
2960
2961 /* Queue the first TRB, even if it's zero-length */
2962 do {
2963 u32 remainder = 0;
2964 field = 0;
2965
2966 /* Don't change the cycle bit of the first TRB until later */
2967 if (first_trb) {
2968 first_trb = false;
2969 if (start_cycle == 0)
2970 field |= 0x1;
2971 } else
2972 field |= ep_ring->cycle_state;
2973
2974 /* Chain all the TRBs together; clear the chain bit in the last
2975 * TRB to indicate it's the last TRB in the chain.
2976 */
2977 if (num_trbs > 1) {
2978 field |= TRB_CHAIN;
2979 } else {
2980 /* FIXME - add check for ZERO_PACKET flag before this */
2981 td->last_trb = ep_ring->enqueue;
2982 field |= TRB_IOC;
2983 }
2984
2985 /* Only set interrupt on short packet for IN endpoints */
2986 if (usb_urb_dir_in(urb))
2987 field |= TRB_ISP;
2988
2989 /* Set the TRB length, TD size, and interrupter fields. */
2990 if (xhci->hci_version < 0x100) {
2991 remainder = xhci_td_remainder(
2992 urb->transfer_buffer_length -
2993 running_total);
2994 } else {
2995 remainder = xhci_v1_0_td_remainder(running_total,
2996 trb_buff_len, total_packet_count, urb);
2997 }
2998 length_field = TRB_LEN(trb_buff_len) |
2999 remainder |
3000 TRB_INTR_TARGET(0);
3001
3002 if (num_trbs > 1)
3003 more_trbs_coming = true;
3004 else
3005 more_trbs_coming = false;
3006 queue_trb(xhci, ep_ring, false, more_trbs_coming,
3007 lower_32_bits(addr),
3008 upper_32_bits(addr),
3009 length_field,
3010 field | TRB_TYPE(TRB_NORMAL));
3011 --num_trbs;
3012 running_total += trb_buff_len;
3013
3014 /* Calculate length for next transfer */
3015 addr += trb_buff_len;
3016 trb_buff_len = urb->transfer_buffer_length - running_total;
3017 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3018 trb_buff_len = TRB_MAX_BUFF_SIZE;
3019 } while (running_total < urb->transfer_buffer_length);
3020
3021 check_trb_math(urb, num_trbs, running_total);
3022 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3023 start_cycle, start_trb);
3024 return 0;
3025}
3026
3027/* Caller must have locked xhci->lock */
3028int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3029 struct urb *urb, int slot_id, unsigned int ep_index)
3030{
3031 struct xhci_ring *ep_ring;
3032 int num_trbs;
3033 int ret;
3034 struct usb_ctrlrequest *setup;
3035 struct xhci_generic_trb *start_trb;
3036 int start_cycle;
3037 u32 field, length_field;
3038 struct urb_priv *urb_priv;
3039 struct xhci_td *td;
3040
3041 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3042 if (!ep_ring)
3043 return -EINVAL;
3044
3045 /*
3046 * Need to copy setup packet into setup TRB, so we can't use the setup
3047 * DMA address.
3048 */
3049 if (!urb->setup_packet)
3050 return -EINVAL;
3051
3052 if (!in_interrupt())
3053 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3054 slot_id, ep_index);
3055 /* 1 TRB for setup, 1 for status */
3056 num_trbs = 2;
3057 /*
3058 * Don't need to check if we need additional event data and normal TRBs,
3059 * since data in control transfers will never get bigger than 16MB
3060 * XXX: can we get a buffer that crosses 64KB boundaries?
3061 */
3062 if (urb->transfer_buffer_length > 0)
3063 num_trbs++;
3064 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3065 ep_index, urb->stream_id,
3066 num_trbs, urb, 0, mem_flags);
3067 if (ret < 0)
3068 return ret;
3069
3070 urb_priv = urb->hcpriv;
3071 td = urb_priv->td[0];
3072
3073 /*
3074 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3075 * until we've finished creating all the other TRBs. The ring's cycle
3076 * state may change as we enqueue the other TRBs, so save it too.
3077 */
3078 start_trb = &ep_ring->enqueue->generic;
3079 start_cycle = ep_ring->cycle_state;
3080
3081 /* Queue setup TRB - see section 6.4.1.2.1 */
3082 /* FIXME better way to translate setup_packet into two u32 fields? */
3083 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3084 field = 0;
3085 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3086 if (start_cycle == 0)
3087 field |= 0x1;
3088
3089 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3090 if (xhci->hci_version == 0x100) {
3091 if (urb->transfer_buffer_length > 0) {
3092 if (setup->bRequestType & USB_DIR_IN)
3093 field |= TRB_TX_TYPE(TRB_DATA_IN);
3094 else
3095 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3096 }
3097 }
3098
3099 queue_trb(xhci, ep_ring, false, true,
3100 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3101 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3102 TRB_LEN(8) | TRB_INTR_TARGET(0),
3103 /* Immediate data in pointer */
3104 field);
3105
3106 /* If there's data, queue data TRBs */
3107 /* Only set interrupt on short packet for IN endpoints */
3108 if (usb_urb_dir_in(urb))
3109 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3110 else
3111 field = TRB_TYPE(TRB_DATA);
3112
3113 length_field = TRB_LEN(urb->transfer_buffer_length) |
3114 xhci_td_remainder(urb->transfer_buffer_length) |
3115 TRB_INTR_TARGET(0);
3116 if (urb->transfer_buffer_length > 0) {
3117 if (setup->bRequestType & USB_DIR_IN)
3118 field |= TRB_DIR_IN;
3119 queue_trb(xhci, ep_ring, false, true,
3120 lower_32_bits(urb->transfer_dma),
3121 upper_32_bits(urb->transfer_dma),
3122 length_field,
3123 field | ep_ring->cycle_state);
3124 }
3125
3126 /* Save the DMA address of the last TRB in the TD */
3127 td->last_trb = ep_ring->enqueue;
3128
3129 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3130 /* If the device sent data, the status stage is an OUT transfer */
3131 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3132 field = 0;
3133 else
3134 field = TRB_DIR_IN;
3135 queue_trb(xhci, ep_ring, false, false,
3136 0,
3137 0,
3138 TRB_INTR_TARGET(0),
3139 /* Event on completion */
3140 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3141
3142 giveback_first_trb(xhci, slot_id, ep_index, 0,
3143 start_cycle, start_trb);
3144 return 0;
3145}
3146
3147static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3148 struct urb *urb, int i)
3149{
3150 int num_trbs = 0;
3151 u64 addr, td_len;
3152
3153 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3154 td_len = urb->iso_frame_desc[i].length;
3155
3156 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3157 TRB_MAX_BUFF_SIZE);
3158 if (num_trbs == 0)
3159 num_trbs++;
3160
3161 return num_trbs;
3162}
3163
3164/*
3165 * The transfer burst count field of the isochronous TRB defines the number of
3166 * bursts that are required to move all packets in this TD. Only SuperSpeed
3167 * devices can burst up to bMaxBurst number of packets per service interval.
3168 * This field is zero based, meaning a value of zero in the field means one
3169 * burst. Basically, for everything but SuperSpeed devices, this field will be
3170 * zero. Only xHCI 1.0 host controllers support this field.
3171 */
3172static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3173 struct usb_device *udev,
3174 struct urb *urb, unsigned int total_packet_count)
3175{
3176 unsigned int max_burst;
3177
3178 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3179 return 0;
3180
3181 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3182 return roundup(total_packet_count, max_burst + 1) - 1;
3183}
3184
3185/*
3186 * Returns the number of packets in the last "burst" of packets. This field is
3187 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3188 * the last burst packet count is equal to the total number of packets in the
3189 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3190 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3191 * contain 1 to (bMaxBurst + 1) packets.
3192 */
3193static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3194 struct usb_device *udev,
3195 struct urb *urb, unsigned int total_packet_count)
3196{
3197 unsigned int max_burst;
3198 unsigned int residue;
3199
3200 if (xhci->hci_version < 0x100)
3201 return 0;
3202
3203 switch (udev->speed) {
3204 case USB_SPEED_SUPER:
3205 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3206 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3207 residue = total_packet_count % (max_burst + 1);
3208 /* If residue is zero, the last burst contains (max_burst + 1)
3209 * number of packets, but the TLBPC field is zero-based.
3210 */
3211 if (residue == 0)
3212 return max_burst;
3213 return residue - 1;
3214 default:
3215 if (total_packet_count == 0)
3216 return 0;
3217 return total_packet_count - 1;
3218 }
3219}
3220
3221/* This is for isoc transfer */
3222static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3223 struct urb *urb, int slot_id, unsigned int ep_index)
3224{
3225 struct xhci_ring *ep_ring;
3226 struct urb_priv *urb_priv;
3227 struct xhci_td *td;
3228 int num_tds, trbs_per_td;
3229 struct xhci_generic_trb *start_trb;
3230 bool first_trb;
3231 int start_cycle;
3232 u32 field, length_field;
3233 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3234 u64 start_addr, addr;
3235 int i, j;
3236 bool more_trbs_coming;
3237
3238 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3239
3240 num_tds = urb->number_of_packets;
3241 if (num_tds < 1) {
3242 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3243 return -EINVAL;
3244 }
3245
3246 if (!in_interrupt())
3247 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3248 " addr = %#llx, num_tds = %d\n",
3249 urb->ep->desc.bEndpointAddress,
3250 urb->transfer_buffer_length,
3251 urb->transfer_buffer_length,
3252 (unsigned long long)urb->transfer_dma,
3253 num_tds);
3254
3255 start_addr = (u64) urb->transfer_dma;
3256 start_trb = &ep_ring->enqueue->generic;
3257 start_cycle = ep_ring->cycle_state;
3258
3259 urb_priv = urb->hcpriv;
3260 /* Queue the first TRB, even if it's zero-length */
3261 for (i = 0; i < num_tds; i++) {
3262 unsigned int total_packet_count;
3263 unsigned int burst_count;
3264 unsigned int residue;
3265
3266 first_trb = true;
3267 running_total = 0;
3268 addr = start_addr + urb->iso_frame_desc[i].offset;
3269 td_len = urb->iso_frame_desc[i].length;
3270 td_remain_len = td_len;
3271 total_packet_count = roundup(td_len,
3272 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
3273 /* A zero-length transfer still involves at least one packet. */
3274 if (total_packet_count == 0)
3275 total_packet_count++;
3276 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3277 total_packet_count);
3278 residue = xhci_get_last_burst_packet_count(xhci,
3279 urb->dev, urb, total_packet_count);
3280
3281 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3282
3283 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3284 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3285 if (ret < 0) {
3286 if (i == 0)
3287 return ret;
3288 goto cleanup;
3289 }
3290
3291 td = urb_priv->td[i];
3292 for (j = 0; j < trbs_per_td; j++) {
3293 u32 remainder = 0;
3294 field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3295
3296 if (first_trb) {
3297 /* Queue the isoc TRB */
3298 field |= TRB_TYPE(TRB_ISOC);
3299 /* Assume URB_ISO_ASAP is set */
3300 field |= TRB_SIA;
3301 if (i == 0) {
3302 if (start_cycle == 0)
3303 field |= 0x1;
3304 } else
3305 field |= ep_ring->cycle_state;
3306 first_trb = false;
3307 } else {
3308 /* Queue other normal TRBs */
3309 field |= TRB_TYPE(TRB_NORMAL);
3310 field |= ep_ring->cycle_state;
3311 }
3312
3313 /* Only set interrupt on short packet for IN EPs */
3314 if (usb_urb_dir_in(urb))
3315 field |= TRB_ISP;
3316
3317 /* Chain all the TRBs together; clear the chain bit in
3318 * the last TRB to indicate it's the last TRB in the
3319 * chain.
3320 */
3321 if (j < trbs_per_td - 1) {
3322 field |= TRB_CHAIN;
3323 more_trbs_coming = true;
3324 } else {
3325 td->last_trb = ep_ring->enqueue;
3326 field |= TRB_IOC;
3327 if (xhci->hci_version == 0x100) {
3328 /* Set BEI bit except for the last td */
3329 if (i < num_tds - 1)
3330 field |= TRB_BEI;
3331 }
3332 more_trbs_coming = false;
3333 }
3334
3335 /* Calculate TRB length */
3336 trb_buff_len = TRB_MAX_BUFF_SIZE -
3337 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3338 if (trb_buff_len > td_remain_len)
3339 trb_buff_len = td_remain_len;
3340
3341 /* Set the TRB length, TD size, & interrupter fields. */
3342 if (xhci->hci_version < 0x100) {
3343 remainder = xhci_td_remainder(
3344 td_len - running_total);
3345 } else {
3346 remainder = xhci_v1_0_td_remainder(
3347 running_total, trb_buff_len,
3348 total_packet_count, urb);
3349 }
3350 length_field = TRB_LEN(trb_buff_len) |
3351 remainder |
3352 TRB_INTR_TARGET(0);
3353
3354 queue_trb(xhci, ep_ring, false, more_trbs_coming,
3355 lower_32_bits(addr),
3356 upper_32_bits(addr),
3357 length_field,
3358 field);
3359 running_total += trb_buff_len;
3360
3361 addr += trb_buff_len;
3362 td_remain_len -= trb_buff_len;
3363 }
3364
3365 /* Check TD length */
3366 if (running_total != td_len) {
3367 xhci_err(xhci, "ISOC TD length unmatch\n");
3368 return -EINVAL;
3369 }
3370 }
3371
3372 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3373 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3374 usb_amd_quirk_pll_disable();
3375 }
3376 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3377
3378 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3379 start_cycle, start_trb);
3380 return 0;
3381cleanup:
3382 /* Clean up a partially enqueued isoc transfer. */
3383
3384 for (i--; i >= 0; i--)
3385 list_del_init(&urb_priv->td[i]->td_list);
3386
3387 /* Use the first TD as a temporary variable to turn the TDs we've queued
3388 * into No-ops with a software-owned cycle bit. That way the hardware
3389 * won't accidentally start executing bogus TDs when we partially
3390 * overwrite them. td->first_trb and td->start_seg are already set.
3391 */
3392 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3393 /* Every TRB except the first & last will have its cycle bit flipped. */
3394 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3395
3396 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3397 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3398 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3399 ep_ring->cycle_state = start_cycle;
3400 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3401 return ret;
3402}
3403
3404/*
3405 * Check transfer ring to guarantee there is enough room for the urb.
3406 * Update ISO URB start_frame and interval.
3407 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3408 * update the urb->start_frame by now.
3409 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3410 */
3411int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3412 struct urb *urb, int slot_id, unsigned int ep_index)
3413{
3414 struct xhci_virt_device *xdev;
3415 struct xhci_ring *ep_ring;
3416 struct xhci_ep_ctx *ep_ctx;
3417 int start_frame;
3418 int xhci_interval;
3419 int ep_interval;
3420 int num_tds, num_trbs, i;
3421 int ret;
3422
3423 xdev = xhci->devs[slot_id];
3424 ep_ring = xdev->eps[ep_index].ring;
3425 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3426
3427 num_trbs = 0;
3428 num_tds = urb->number_of_packets;
3429 for (i = 0; i < num_tds; i++)
3430 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3431
3432 /* Check the ring to guarantee there is enough room for the whole urb.
3433 * Do not insert any td of the urb to the ring if the check failed.
3434 */
3435 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3436 num_trbs, mem_flags);
3437 if (ret)
3438 return ret;
3439
3440 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3441 start_frame &= 0x3fff;
3442
3443 urb->start_frame = start_frame;
3444 if (urb->dev->speed == USB_SPEED_LOW ||
3445 urb->dev->speed == USB_SPEED_FULL)
3446 urb->start_frame >>= 3;
3447
3448 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3449 ep_interval = urb->interval;
3450 /* Convert to microframes */
3451 if (urb->dev->speed == USB_SPEED_LOW ||
3452 urb->dev->speed == USB_SPEED_FULL)
3453 ep_interval *= 8;
3454 /* FIXME change this to a warning and a suggestion to use the new API
3455 * to set the polling interval (once the API is added).
3456 */
3457 if (xhci_interval != ep_interval) {
3458 if (printk_ratelimit())
3459 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3460 " (%d microframe%s) than xHCI "
3461 "(%d microframe%s)\n",
3462 ep_interval,
3463 ep_interval == 1 ? "" : "s",
3464 xhci_interval,
3465 xhci_interval == 1 ? "" : "s");
3466 urb->interval = xhci_interval;
3467 /* Convert back to frames for LS/FS devices */
3468 if (urb->dev->speed == USB_SPEED_LOW ||
3469 urb->dev->speed == USB_SPEED_FULL)
3470 urb->interval /= 8;
3471 }
3472 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3473}
3474
3475/**** Command Ring Operations ****/
3476
3477/* Generic function for queueing a command TRB on the command ring.
3478 * Check to make sure there's room on the command ring for one command TRB.
3479 * Also check that there's room reserved for commands that must not fail.
3480 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3481 * then only check for the number of reserved spots.
3482 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3483 * because the command event handler may want to resubmit a failed command.
3484 */
3485static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3486 u32 field3, u32 field4, bool command_must_succeed)
3487{
3488 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3489 int ret;
3490
3491 if (!command_must_succeed)
3492 reserved_trbs++;
3493
3494 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3495 reserved_trbs, GFP_ATOMIC);
3496 if (ret < 0) {
3497 xhci_err(xhci, "ERR: No room for command on command ring\n");
3498 if (command_must_succeed)
3499 xhci_err(xhci, "ERR: Reserved TRB counting for "
3500 "unfailable commands failed.\n");
3501 return ret;
3502 }
3503 queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
3504 field4 | xhci->cmd_ring->cycle_state);
3505 return 0;
3506}
3507
3508/* Queue a slot enable or disable request on the command ring */
3509int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3510{
3511 return queue_command(xhci, 0, 0, 0,
3512 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3513}
3514
3515/* Queue an address device command TRB */
3516int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3517 u32 slot_id)
3518{
3519 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3520 upper_32_bits(in_ctx_ptr), 0,
3521 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3522 false);
3523}
3524
3525int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3526 u32 field1, u32 field2, u32 field3, u32 field4)
3527{
3528 return queue_command(xhci, field1, field2, field3, field4, false);
3529}
3530
3531/* Queue a reset device command TRB */
3532int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3533{
3534 return queue_command(xhci, 0, 0, 0,
3535 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3536 false);
3537}
3538
3539/* Queue a configure endpoint command TRB */
3540int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3541 u32 slot_id, bool command_must_succeed)
3542{
3543 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3544 upper_32_bits(in_ctx_ptr), 0,
3545 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3546 command_must_succeed);
3547}
3548
3549/* Queue an evaluate context command TRB */
3550int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3551 u32 slot_id)
3552{
3553 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3554 upper_32_bits(in_ctx_ptr), 0,
3555 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3556 false);
3557}
3558
3559/*
3560 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3561 * activity on an endpoint that is about to be suspended.
3562 */
3563int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3564 unsigned int ep_index, int suspend)
3565{
3566 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3567 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3568 u32 type = TRB_TYPE(TRB_STOP_RING);
3569 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3570
3571 return queue_command(xhci, 0, 0, 0,
3572 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3573}
3574
3575/* Set Transfer Ring Dequeue Pointer command.
3576 * This should not be used for endpoints that have streams enabled.
3577 */
3578static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3579 unsigned int ep_index, unsigned int stream_id,
3580 struct xhci_segment *deq_seg,
3581 union xhci_trb *deq_ptr, u32 cycle_state)
3582{
3583 dma_addr_t addr;
3584 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3585 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3586 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3587 u32 type = TRB_TYPE(TRB_SET_DEQ);
3588 struct xhci_virt_ep *ep;
3589
3590 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3591 if (addr == 0) {
3592 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3593 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3594 deq_seg, deq_ptr);
3595 return 0;
3596 }
3597 ep = &xhci->devs[slot_id]->eps[ep_index];
3598 if ((ep->ep_state & SET_DEQ_PENDING)) {
3599 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3600 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3601 return 0;
3602 }
3603 ep->queued_deq_seg = deq_seg;
3604 ep->queued_deq_ptr = deq_ptr;
3605 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3606 upper_32_bits(addr), trb_stream_id,
3607 trb_slot_id | trb_ep_index | type, false);
3608}
3609
3610int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3611 unsigned int ep_index)
3612{
3613 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3614 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3615 u32 type = TRB_TYPE(TRB_RESET_EP);
3616
3617 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3618 false);
3619}
1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
29 *
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
41 *
42 * Cycle bit rules:
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
47 *
48 * Producer rules:
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
52 * cycle state).
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
56 *
57 * Consumer rules:
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
65 */
66
67#include <linux/scatterlist.h>
68#include <linux/slab.h>
69#include "xhci.h"
70
71static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
74
75/*
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
77 * address of the TRB.
78 */
79dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
80 union xhci_trb *trb)
81{
82 unsigned long segment_offset;
83
84 if (!seg || !trb || trb < seg->trbs)
85 return 0;
86 /* offset in TRBs */
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
89 return 0;
90 return seg->dma + (segment_offset * sizeof(*trb));
91}
92
93/* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
95 */
96static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
98{
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
102 else
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
104}
105
106/* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
108 * event seg?
109 */
110static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
112{
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
115 else
116 return TRB_TYPE_LINK_LE32(trb->link.control);
117}
118
119static int enqueue_is_link_trb(struct xhci_ring *ring)
120{
121 struct xhci_link_trb *link = &ring->enqueue->link;
122 return TRB_TYPE_LINK_LE32(link->control);
123}
124
125/* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
128 */
129static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
133{
134 if (last_trb(xhci, ring, *seg, *trb)) {
135 *seg = (*seg)->next;
136 *trb = ((*seg)->trbs);
137 } else {
138 (*trb)++;
139 }
140}
141
142/*
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
145 */
146static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
147{
148 unsigned long long addr;
149
150 ring->deq_updates++;
151
152 /*
153 * If this is not event ring, and the dequeue pointer
154 * is not on a link TRB, there is one more usable TRB
155 */
156 if (ring->type != TYPE_EVENT &&
157 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
158 ring->num_trbs_free++;
159
160 do {
161 /*
162 * Update the dequeue pointer further if that was a link TRB or
163 * we're at the end of an event ring segment (which doesn't have
164 * link TRBS)
165 */
166 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
167 if (ring->type == TYPE_EVENT &&
168 last_trb_on_last_seg(xhci, ring,
169 ring->deq_seg, ring->dequeue)) {
170 ring->cycle_state = (ring->cycle_state ? 0 : 1);
171 }
172 ring->deq_seg = ring->deq_seg->next;
173 ring->dequeue = ring->deq_seg->trbs;
174 } else {
175 ring->dequeue++;
176 }
177 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
178
179 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
180}
181
182/*
183 * See Cycle bit rules. SW is the consumer for the event ring only.
184 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
185 *
186 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
187 * chain bit is set), then set the chain bit in all the following link TRBs.
188 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
189 * have their chain bit cleared (so that each Link TRB is a separate TD).
190 *
191 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
192 * set, but other sections talk about dealing with the chain bit set. This was
193 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
194 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
195 *
196 * @more_trbs_coming: Will you enqueue more TRBs before calling
197 * prepare_transfer()?
198 */
199static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
200 bool more_trbs_coming)
201{
202 u32 chain;
203 union xhci_trb *next;
204 unsigned long long addr;
205
206 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
207 /* If this is not event ring, there is one less usable TRB */
208 if (ring->type != TYPE_EVENT &&
209 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
210 ring->num_trbs_free--;
211 next = ++(ring->enqueue);
212
213 ring->enq_updates++;
214 /* Update the dequeue pointer further if that was a link TRB or we're at
215 * the end of an event ring segment (which doesn't have link TRBS)
216 */
217 while (last_trb(xhci, ring, ring->enq_seg, next)) {
218 if (ring->type != TYPE_EVENT) {
219 /*
220 * If the caller doesn't plan on enqueueing more
221 * TDs before ringing the doorbell, then we
222 * don't want to give the link TRB to the
223 * hardware just yet. We'll give the link TRB
224 * back in prepare_ring() just before we enqueue
225 * the TD at the top of the ring.
226 */
227 if (!chain && !more_trbs_coming)
228 break;
229
230 /* If we're not dealing with 0.95 hardware or
231 * isoc rings on AMD 0.96 host,
232 * carry over the chain bit of the previous TRB
233 * (which may mean the chain bit is cleared).
234 */
235 if (!(ring->type == TYPE_ISOC &&
236 (xhci->quirks & XHCI_AMD_0x96_HOST))
237 && !xhci_link_trb_quirk(xhci)) {
238 next->link.control &=
239 cpu_to_le32(~TRB_CHAIN);
240 next->link.control |=
241 cpu_to_le32(chain);
242 }
243 /* Give this link TRB to the hardware */
244 wmb();
245 next->link.control ^= cpu_to_le32(TRB_CYCLE);
246
247 /* Toggle the cycle bit after the last ring segment. */
248 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
249 ring->cycle_state = (ring->cycle_state ? 0 : 1);
250 }
251 }
252 ring->enq_seg = ring->enq_seg->next;
253 ring->enqueue = ring->enq_seg->trbs;
254 next = ring->enqueue;
255 }
256 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
257}
258
259/*
260 * Check to see if there's room to enqueue num_trbs on the ring and make sure
261 * enqueue pointer will not advance into dequeue segment. See rules above.
262 */
263static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
264 unsigned int num_trbs)
265{
266 int num_trbs_in_deq_seg;
267
268 if (ring->num_trbs_free < num_trbs)
269 return 0;
270
271 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
272 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
273 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
274 return 0;
275 }
276
277 return 1;
278}
279
280/* Ring the host controller doorbell after placing a command on the ring */
281void xhci_ring_cmd_db(struct xhci_hcd *xhci)
282{
283 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
284 return;
285
286 xhci_dbg(xhci, "// Ding dong!\n");
287 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
288 /* Flush PCI posted writes */
289 xhci_readl(xhci, &xhci->dba->doorbell[0]);
290}
291
292static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
293{
294 u64 temp_64;
295 int ret;
296
297 xhci_dbg(xhci, "Abort command ring\n");
298
299 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
300 xhci_dbg(xhci, "The command ring isn't running, "
301 "Have the command ring been stopped?\n");
302 return 0;
303 }
304
305 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
306 if (!(temp_64 & CMD_RING_RUNNING)) {
307 xhci_dbg(xhci, "Command ring had been stopped\n");
308 return 0;
309 }
310 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
311 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
312 &xhci->op_regs->cmd_ring);
313
314 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
315 * time the completion od all xHCI commands, including
316 * the Command Abort operation. If software doesn't see
317 * CRR negated in a timely manner (e.g. longer than 5
318 * seconds), then it should assume that the there are
319 * larger problems with the xHC and assert HCRST.
320 */
321 ret = handshake(xhci, &xhci->op_regs->cmd_ring,
322 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
323 if (ret < 0) {
324 xhci_err(xhci, "Stopped the command ring failed, "
325 "maybe the host is dead\n");
326 xhci->xhc_state |= XHCI_STATE_DYING;
327 xhci_quiesce(xhci);
328 xhci_halt(xhci);
329 return -ESHUTDOWN;
330 }
331
332 return 0;
333}
334
335static int xhci_queue_cd(struct xhci_hcd *xhci,
336 struct xhci_command *command,
337 union xhci_trb *cmd_trb)
338{
339 struct xhci_cd *cd;
340 cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
341 if (!cd)
342 return -ENOMEM;
343 INIT_LIST_HEAD(&cd->cancel_cmd_list);
344
345 cd->command = command;
346 cd->cmd_trb = cmd_trb;
347 list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
348
349 return 0;
350}
351
352/*
353 * Cancel the command which has issue.
354 *
355 * Some commands may hang due to waiting for acknowledgement from
356 * usb device. It is outside of the xHC's ability to control and
357 * will cause the command ring is blocked. When it occurs software
358 * should intervene to recover the command ring.
359 * See Section 4.6.1.1 and 4.6.1.2
360 */
361int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
362 union xhci_trb *cmd_trb)
363{
364 int retval = 0;
365 unsigned long flags;
366
367 spin_lock_irqsave(&xhci->lock, flags);
368
369 if (xhci->xhc_state & XHCI_STATE_DYING) {
370 xhci_warn(xhci, "Abort the command ring,"
371 " but the xHCI is dead.\n");
372 retval = -ESHUTDOWN;
373 goto fail;
374 }
375
376 /* queue the cmd desriptor to cancel_cmd_list */
377 retval = xhci_queue_cd(xhci, command, cmd_trb);
378 if (retval) {
379 xhci_warn(xhci, "Queuing command descriptor failed.\n");
380 goto fail;
381 }
382
383 /* abort command ring */
384 retval = xhci_abort_cmd_ring(xhci);
385 if (retval) {
386 xhci_err(xhci, "Abort command ring failed\n");
387 if (unlikely(retval == -ESHUTDOWN)) {
388 spin_unlock_irqrestore(&xhci->lock, flags);
389 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
390 xhci_dbg(xhci, "xHCI host controller is dead.\n");
391 return retval;
392 }
393 }
394
395fail:
396 spin_unlock_irqrestore(&xhci->lock, flags);
397 return retval;
398}
399
400void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
401 unsigned int slot_id,
402 unsigned int ep_index,
403 unsigned int stream_id)
404{
405 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
406 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
407 unsigned int ep_state = ep->ep_state;
408
409 /* Don't ring the doorbell for this endpoint if there are pending
410 * cancellations because we don't want to interrupt processing.
411 * We don't want to restart any stream rings if there's a set dequeue
412 * pointer command pending because the device can choose to start any
413 * stream once the endpoint is on the HW schedule.
414 * FIXME - check all the stream rings for pending cancellations.
415 */
416 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
417 (ep_state & EP_HALTED))
418 return;
419 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
420 /* The CPU has better things to do at this point than wait for a
421 * write-posting flush. It'll get there soon enough.
422 */
423}
424
425/* Ring the doorbell for any rings with pending URBs */
426static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
427 unsigned int slot_id,
428 unsigned int ep_index)
429{
430 unsigned int stream_id;
431 struct xhci_virt_ep *ep;
432
433 ep = &xhci->devs[slot_id]->eps[ep_index];
434
435 /* A ring has pending URBs if its TD list is not empty */
436 if (!(ep->ep_state & EP_HAS_STREAMS)) {
437 if (!(list_empty(&ep->ring->td_list)))
438 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
439 return;
440 }
441
442 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
443 stream_id++) {
444 struct xhci_stream_info *stream_info = ep->stream_info;
445 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
446 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
447 stream_id);
448 }
449}
450
451/*
452 * Find the segment that trb is in. Start searching in start_seg.
453 * If we must move past a segment that has a link TRB with a toggle cycle state
454 * bit set, then we will toggle the value pointed at by cycle_state.
455 */
456static struct xhci_segment *find_trb_seg(
457 struct xhci_segment *start_seg,
458 union xhci_trb *trb, int *cycle_state)
459{
460 struct xhci_segment *cur_seg = start_seg;
461 struct xhci_generic_trb *generic_trb;
462
463 while (cur_seg->trbs > trb ||
464 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
465 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
466 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
467 *cycle_state ^= 0x1;
468 cur_seg = cur_seg->next;
469 if (cur_seg == start_seg)
470 /* Looped over the entire list. Oops! */
471 return NULL;
472 }
473 return cur_seg;
474}
475
476
477static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
478 unsigned int slot_id, unsigned int ep_index,
479 unsigned int stream_id)
480{
481 struct xhci_virt_ep *ep;
482
483 ep = &xhci->devs[slot_id]->eps[ep_index];
484 /* Common case: no streams */
485 if (!(ep->ep_state & EP_HAS_STREAMS))
486 return ep->ring;
487
488 if (stream_id == 0) {
489 xhci_warn(xhci,
490 "WARN: Slot ID %u, ep index %u has streams, "
491 "but URB has no stream ID.\n",
492 slot_id, ep_index);
493 return NULL;
494 }
495
496 if (stream_id < ep->stream_info->num_streams)
497 return ep->stream_info->stream_rings[stream_id];
498
499 xhci_warn(xhci,
500 "WARN: Slot ID %u, ep index %u has "
501 "stream IDs 1 to %u allocated, "
502 "but stream ID %u is requested.\n",
503 slot_id, ep_index,
504 ep->stream_info->num_streams - 1,
505 stream_id);
506 return NULL;
507}
508
509/* Get the right ring for the given URB.
510 * If the endpoint supports streams, boundary check the URB's stream ID.
511 * If the endpoint doesn't support streams, return the singular endpoint ring.
512 */
513static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
514 struct urb *urb)
515{
516 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
517 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
518}
519
520/*
521 * Move the xHC's endpoint ring dequeue pointer past cur_td.
522 * Record the new state of the xHC's endpoint ring dequeue segment,
523 * dequeue pointer, and new consumer cycle state in state.
524 * Update our internal representation of the ring's dequeue pointer.
525 *
526 * We do this in three jumps:
527 * - First we update our new ring state to be the same as when the xHC stopped.
528 * - Then we traverse the ring to find the segment that contains
529 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
530 * any link TRBs with the toggle cycle bit set.
531 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
532 * if we've moved it past a link TRB with the toggle cycle bit set.
533 *
534 * Some of the uses of xhci_generic_trb are grotty, but if they're done
535 * with correct __le32 accesses they should work fine. Only users of this are
536 * in here.
537 */
538void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
539 unsigned int slot_id, unsigned int ep_index,
540 unsigned int stream_id, struct xhci_td *cur_td,
541 struct xhci_dequeue_state *state)
542{
543 struct xhci_virt_device *dev = xhci->devs[slot_id];
544 struct xhci_ring *ep_ring;
545 struct xhci_generic_trb *trb;
546 struct xhci_ep_ctx *ep_ctx;
547 dma_addr_t addr;
548
549 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
550 ep_index, stream_id);
551 if (!ep_ring) {
552 xhci_warn(xhci, "WARN can't find new dequeue state "
553 "for invalid stream ID %u.\n",
554 stream_id);
555 return;
556 }
557 state->new_cycle_state = 0;
558 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
559 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
560 dev->eps[ep_index].stopped_trb,
561 &state->new_cycle_state);
562 if (!state->new_deq_seg) {
563 WARN_ON(1);
564 return;
565 }
566
567 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
568 xhci_dbg(xhci, "Finding endpoint context\n");
569 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
570 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
571
572 state->new_deq_ptr = cur_td->last_trb;
573 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
574 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
575 state->new_deq_ptr,
576 &state->new_cycle_state);
577 if (!state->new_deq_seg) {
578 WARN_ON(1);
579 return;
580 }
581
582 trb = &state->new_deq_ptr->generic;
583 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
584 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
585 state->new_cycle_state ^= 0x1;
586 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
587
588 /*
589 * If there is only one segment in a ring, find_trb_seg()'s while loop
590 * will not run, and it will return before it has a chance to see if it
591 * needs to toggle the cycle bit. It can't tell if the stalled transfer
592 * ended just before the link TRB on a one-segment ring, or if the TD
593 * wrapped around the top of the ring, because it doesn't have the TD in
594 * question. Look for the one-segment case where stalled TRB's address
595 * is greater than the new dequeue pointer address.
596 */
597 if (ep_ring->first_seg == ep_ring->first_seg->next &&
598 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
599 state->new_cycle_state ^= 0x1;
600 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
601
602 /* Don't update the ring cycle state for the producer (us). */
603 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
604 state->new_deq_seg);
605 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
606 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
607 (unsigned long long) addr);
608}
609
610/* flip_cycle means flip the cycle bit of all but the first and last TRB.
611 * (The last TRB actually points to the ring enqueue pointer, which is not part
612 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
613 */
614static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
615 struct xhci_td *cur_td, bool flip_cycle)
616{
617 struct xhci_segment *cur_seg;
618 union xhci_trb *cur_trb;
619
620 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
621 true;
622 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
623 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
624 /* Unchain any chained Link TRBs, but
625 * leave the pointers intact.
626 */
627 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
628 /* Flip the cycle bit (link TRBs can't be the first
629 * or last TRB).
630 */
631 if (flip_cycle)
632 cur_trb->generic.field[3] ^=
633 cpu_to_le32(TRB_CYCLE);
634 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
635 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
636 "in seg %p (0x%llx dma)\n",
637 cur_trb,
638 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
639 cur_seg,
640 (unsigned long long)cur_seg->dma);
641 } else {
642 cur_trb->generic.field[0] = 0;
643 cur_trb->generic.field[1] = 0;
644 cur_trb->generic.field[2] = 0;
645 /* Preserve only the cycle bit of this TRB */
646 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
647 /* Flip the cycle bit except on the first or last TRB */
648 if (flip_cycle && cur_trb != cur_td->first_trb &&
649 cur_trb != cur_td->last_trb)
650 cur_trb->generic.field[3] ^=
651 cpu_to_le32(TRB_CYCLE);
652 cur_trb->generic.field[3] |= cpu_to_le32(
653 TRB_TYPE(TRB_TR_NOOP));
654 xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n",
655 (unsigned long long)
656 xhci_trb_virt_to_dma(cur_seg, cur_trb));
657 }
658 if (cur_trb == cur_td->last_trb)
659 break;
660 }
661}
662
663static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
664 unsigned int ep_index, unsigned int stream_id,
665 struct xhci_segment *deq_seg,
666 union xhci_trb *deq_ptr, u32 cycle_state);
667
668void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
669 unsigned int slot_id, unsigned int ep_index,
670 unsigned int stream_id,
671 struct xhci_dequeue_state *deq_state)
672{
673 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
674
675 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
676 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
677 deq_state->new_deq_seg,
678 (unsigned long long)deq_state->new_deq_seg->dma,
679 deq_state->new_deq_ptr,
680 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
681 deq_state->new_cycle_state);
682 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
683 deq_state->new_deq_seg,
684 deq_state->new_deq_ptr,
685 (u32) deq_state->new_cycle_state);
686 /* Stop the TD queueing code from ringing the doorbell until
687 * this command completes. The HC won't set the dequeue pointer
688 * if the ring is running, and ringing the doorbell starts the
689 * ring running.
690 */
691 ep->ep_state |= SET_DEQ_PENDING;
692}
693
694static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
695 struct xhci_virt_ep *ep)
696{
697 ep->ep_state &= ~EP_HALT_PENDING;
698 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
699 * timer is running on another CPU, we don't decrement stop_cmds_pending
700 * (since we didn't successfully stop the watchdog timer).
701 */
702 if (del_timer(&ep->stop_cmd_timer))
703 ep->stop_cmds_pending--;
704}
705
706/* Must be called with xhci->lock held in interrupt context */
707static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
708 struct xhci_td *cur_td, int status, char *adjective)
709{
710 struct usb_hcd *hcd;
711 struct urb *urb;
712 struct urb_priv *urb_priv;
713
714 urb = cur_td->urb;
715 urb_priv = urb->hcpriv;
716 urb_priv->td_cnt++;
717 hcd = bus_to_hcd(urb->dev->bus);
718
719 /* Only giveback urb when this is the last td in urb */
720 if (urb_priv->td_cnt == urb_priv->length) {
721 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
722 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
723 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
724 if (xhci->quirks & XHCI_AMD_PLL_FIX)
725 usb_amd_quirk_pll_enable();
726 }
727 }
728 usb_hcd_unlink_urb_from_ep(hcd, urb);
729
730 spin_unlock(&xhci->lock);
731 usb_hcd_giveback_urb(hcd, urb, status);
732 xhci_urb_free_priv(xhci, urb_priv);
733 spin_lock(&xhci->lock);
734 }
735}
736
737/*
738 * When we get a command completion for a Stop Endpoint Command, we need to
739 * unlink any cancelled TDs from the ring. There are two ways to do that:
740 *
741 * 1. If the HW was in the middle of processing the TD that needs to be
742 * cancelled, then we must move the ring's dequeue pointer past the last TRB
743 * in the TD with a Set Dequeue Pointer Command.
744 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
745 * bit cleared) so that the HW will skip over them.
746 */
747static void handle_stopped_endpoint(struct xhci_hcd *xhci,
748 union xhci_trb *trb, struct xhci_event_cmd *event)
749{
750 unsigned int slot_id;
751 unsigned int ep_index;
752 struct xhci_virt_device *virt_dev;
753 struct xhci_ring *ep_ring;
754 struct xhci_virt_ep *ep;
755 struct list_head *entry;
756 struct xhci_td *cur_td = NULL;
757 struct xhci_td *last_unlinked_td;
758
759 struct xhci_dequeue_state deq_state;
760
761 if (unlikely(TRB_TO_SUSPEND_PORT(
762 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
763 slot_id = TRB_TO_SLOT_ID(
764 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
765 virt_dev = xhci->devs[slot_id];
766 if (virt_dev)
767 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
768 event);
769 else
770 xhci_warn(xhci, "Stop endpoint command "
771 "completion for disabled slot %u\n",
772 slot_id);
773 return;
774 }
775
776 memset(&deq_state, 0, sizeof(deq_state));
777 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
778 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
779 ep = &xhci->devs[slot_id]->eps[ep_index];
780
781 if (list_empty(&ep->cancelled_td_list)) {
782 xhci_stop_watchdog_timer_in_irq(xhci, ep);
783 ep->stopped_td = NULL;
784 ep->stopped_trb = NULL;
785 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
786 return;
787 }
788
789 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
790 * We have the xHCI lock, so nothing can modify this list until we drop
791 * it. We're also in the event handler, so we can't get re-interrupted
792 * if another Stop Endpoint command completes
793 */
794 list_for_each(entry, &ep->cancelled_td_list) {
795 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
796 xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n",
797 (unsigned long long)xhci_trb_virt_to_dma(
798 cur_td->start_seg, cur_td->first_trb));
799 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
800 if (!ep_ring) {
801 /* This shouldn't happen unless a driver is mucking
802 * with the stream ID after submission. This will
803 * leave the TD on the hardware ring, and the hardware
804 * will try to execute it, and may access a buffer
805 * that has already been freed. In the best case, the
806 * hardware will execute it, and the event handler will
807 * ignore the completion event for that TD, since it was
808 * removed from the td_list for that endpoint. In
809 * short, don't muck with the stream ID after
810 * submission.
811 */
812 xhci_warn(xhci, "WARN Cancelled URB %p "
813 "has invalid stream ID %u.\n",
814 cur_td->urb,
815 cur_td->urb->stream_id);
816 goto remove_finished_td;
817 }
818 /*
819 * If we stopped on the TD we need to cancel, then we have to
820 * move the xHC endpoint ring dequeue pointer past this TD.
821 */
822 if (cur_td == ep->stopped_td)
823 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
824 cur_td->urb->stream_id,
825 cur_td, &deq_state);
826 else
827 td_to_noop(xhci, ep_ring, cur_td, false);
828remove_finished_td:
829 /*
830 * The event handler won't see a completion for this TD anymore,
831 * so remove it from the endpoint ring's TD list. Keep it in
832 * the cancelled TD list for URB completion later.
833 */
834 list_del_init(&cur_td->td_list);
835 }
836 last_unlinked_td = cur_td;
837 xhci_stop_watchdog_timer_in_irq(xhci, ep);
838
839 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
840 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
841 xhci_queue_new_dequeue_state(xhci,
842 slot_id, ep_index,
843 ep->stopped_td->urb->stream_id,
844 &deq_state);
845 xhci_ring_cmd_db(xhci);
846 } else {
847 /* Otherwise ring the doorbell(s) to restart queued transfers */
848 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
849 }
850 ep->stopped_td = NULL;
851 ep->stopped_trb = NULL;
852
853 /*
854 * Drop the lock and complete the URBs in the cancelled TD list.
855 * New TDs to be cancelled might be added to the end of the list before
856 * we can complete all the URBs for the TDs we already unlinked.
857 * So stop when we've completed the URB for the last TD we unlinked.
858 */
859 do {
860 cur_td = list_entry(ep->cancelled_td_list.next,
861 struct xhci_td, cancelled_td_list);
862 list_del_init(&cur_td->cancelled_td_list);
863
864 /* Clean up the cancelled URB */
865 /* Doesn't matter what we pass for status, since the core will
866 * just overwrite it (because the URB has been unlinked).
867 */
868 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
869
870 /* Stop processing the cancelled list if the watchdog timer is
871 * running.
872 */
873 if (xhci->xhc_state & XHCI_STATE_DYING)
874 return;
875 } while (cur_td != last_unlinked_td);
876
877 /* Return to the event handler with xhci->lock re-acquired */
878}
879
880/* Watchdog timer function for when a stop endpoint command fails to complete.
881 * In this case, we assume the host controller is broken or dying or dead. The
882 * host may still be completing some other events, so we have to be careful to
883 * let the event ring handler and the URB dequeueing/enqueueing functions know
884 * through xhci->state.
885 *
886 * The timer may also fire if the host takes a very long time to respond to the
887 * command, and the stop endpoint command completion handler cannot delete the
888 * timer before the timer function is called. Another endpoint cancellation may
889 * sneak in before the timer function can grab the lock, and that may queue
890 * another stop endpoint command and add the timer back. So we cannot use a
891 * simple flag to say whether there is a pending stop endpoint command for a
892 * particular endpoint.
893 *
894 * Instead we use a combination of that flag and a counter for the number of
895 * pending stop endpoint commands. If the timer is the tail end of the last
896 * stop endpoint command, and the endpoint's command is still pending, we assume
897 * the host is dying.
898 */
899void xhci_stop_endpoint_command_watchdog(unsigned long arg)
900{
901 struct xhci_hcd *xhci;
902 struct xhci_virt_ep *ep;
903 struct xhci_virt_ep *temp_ep;
904 struct xhci_ring *ring;
905 struct xhci_td *cur_td;
906 int ret, i, j;
907 unsigned long flags;
908
909 ep = (struct xhci_virt_ep *) arg;
910 xhci = ep->xhci;
911
912 spin_lock_irqsave(&xhci->lock, flags);
913
914 ep->stop_cmds_pending--;
915 if (xhci->xhc_state & XHCI_STATE_DYING) {
916 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
917 "xHCI as DYING, exiting.\n");
918 spin_unlock_irqrestore(&xhci->lock, flags);
919 return;
920 }
921 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
922 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
923 "exiting.\n");
924 spin_unlock_irqrestore(&xhci->lock, flags);
925 return;
926 }
927
928 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
929 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
930 /* Oops, HC is dead or dying or at least not responding to the stop
931 * endpoint command.
932 */
933 xhci->xhc_state |= XHCI_STATE_DYING;
934 /* Disable interrupts from the host controller and start halting it */
935 xhci_quiesce(xhci);
936 spin_unlock_irqrestore(&xhci->lock, flags);
937
938 ret = xhci_halt(xhci);
939
940 spin_lock_irqsave(&xhci->lock, flags);
941 if (ret < 0) {
942 /* This is bad; the host is not responding to commands and it's
943 * not allowing itself to be halted. At least interrupts are
944 * disabled. If we call usb_hc_died(), it will attempt to
945 * disconnect all device drivers under this host. Those
946 * disconnect() methods will wait for all URBs to be unlinked,
947 * so we must complete them.
948 */
949 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
950 xhci_warn(xhci, "Completing active URBs anyway.\n");
951 /* We could turn all TDs on the rings to no-ops. This won't
952 * help if the host has cached part of the ring, and is slow if
953 * we want to preserve the cycle bit. Skip it and hope the host
954 * doesn't touch the memory.
955 */
956 }
957 for (i = 0; i < MAX_HC_SLOTS; i++) {
958 if (!xhci->devs[i])
959 continue;
960 for (j = 0; j < 31; j++) {
961 temp_ep = &xhci->devs[i]->eps[j];
962 ring = temp_ep->ring;
963 if (!ring)
964 continue;
965 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
966 "ep index %u\n", i, j);
967 while (!list_empty(&ring->td_list)) {
968 cur_td = list_first_entry(&ring->td_list,
969 struct xhci_td,
970 td_list);
971 list_del_init(&cur_td->td_list);
972 if (!list_empty(&cur_td->cancelled_td_list))
973 list_del_init(&cur_td->cancelled_td_list);
974 xhci_giveback_urb_in_irq(xhci, cur_td,
975 -ESHUTDOWN, "killed");
976 }
977 while (!list_empty(&temp_ep->cancelled_td_list)) {
978 cur_td = list_first_entry(
979 &temp_ep->cancelled_td_list,
980 struct xhci_td,
981 cancelled_td_list);
982 list_del_init(&cur_td->cancelled_td_list);
983 xhci_giveback_urb_in_irq(xhci, cur_td,
984 -ESHUTDOWN, "killed");
985 }
986 }
987 }
988 spin_unlock_irqrestore(&xhci->lock, flags);
989 xhci_dbg(xhci, "Calling usb_hc_died()\n");
990 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
991 xhci_dbg(xhci, "xHCI host controller is dead.\n");
992}
993
994
995static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
996 struct xhci_virt_device *dev,
997 struct xhci_ring *ep_ring,
998 unsigned int ep_index)
999{
1000 union xhci_trb *dequeue_temp;
1001 int num_trbs_free_temp;
1002 bool revert = false;
1003
1004 num_trbs_free_temp = ep_ring->num_trbs_free;
1005 dequeue_temp = ep_ring->dequeue;
1006
1007 /* If we get two back-to-back stalls, and the first stalled transfer
1008 * ends just before a link TRB, the dequeue pointer will be left on
1009 * the link TRB by the code in the while loop. So we have to update
1010 * the dequeue pointer one segment further, or we'll jump off
1011 * the segment into la-la-land.
1012 */
1013 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1014 ep_ring->deq_seg = ep_ring->deq_seg->next;
1015 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1016 }
1017
1018 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1019 /* We have more usable TRBs */
1020 ep_ring->num_trbs_free++;
1021 ep_ring->dequeue++;
1022 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1023 ep_ring->dequeue)) {
1024 if (ep_ring->dequeue ==
1025 dev->eps[ep_index].queued_deq_ptr)
1026 break;
1027 ep_ring->deq_seg = ep_ring->deq_seg->next;
1028 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1029 }
1030 if (ep_ring->dequeue == dequeue_temp) {
1031 revert = true;
1032 break;
1033 }
1034 }
1035
1036 if (revert) {
1037 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1038 ep_ring->num_trbs_free = num_trbs_free_temp;
1039 }
1040}
1041
1042/*
1043 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1044 * we need to clear the set deq pending flag in the endpoint ring state, so that
1045 * the TD queueing code can ring the doorbell again. We also need to ring the
1046 * endpoint doorbell to restart the ring, but only if there aren't more
1047 * cancellations pending.
1048 */
1049static void handle_set_deq_completion(struct xhci_hcd *xhci,
1050 struct xhci_event_cmd *event,
1051 union xhci_trb *trb)
1052{
1053 unsigned int slot_id;
1054 unsigned int ep_index;
1055 unsigned int stream_id;
1056 struct xhci_ring *ep_ring;
1057 struct xhci_virt_device *dev;
1058 struct xhci_ep_ctx *ep_ctx;
1059 struct xhci_slot_ctx *slot_ctx;
1060
1061 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1062 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1063 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1064 dev = xhci->devs[slot_id];
1065
1066 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1067 if (!ep_ring) {
1068 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1069 "freed stream ID %u\n",
1070 stream_id);
1071 /* XXX: Harmless??? */
1072 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1073 return;
1074 }
1075
1076 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1077 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1078
1079 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1080 unsigned int ep_state;
1081 unsigned int slot_state;
1082
1083 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1084 case COMP_TRB_ERR:
1085 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1086 "of stream ID configuration\n");
1087 break;
1088 case COMP_CTX_STATE:
1089 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1090 "to incorrect slot or ep state.\n");
1091 ep_state = le32_to_cpu(ep_ctx->ep_info);
1092 ep_state &= EP_STATE_MASK;
1093 slot_state = le32_to_cpu(slot_ctx->dev_state);
1094 slot_state = GET_SLOT_STATE(slot_state);
1095 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1096 slot_state, ep_state);
1097 break;
1098 case COMP_EBADSLT:
1099 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1100 "slot %u was not enabled.\n", slot_id);
1101 break;
1102 default:
1103 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1104 "completion code of %u.\n",
1105 GET_COMP_CODE(le32_to_cpu(event->status)));
1106 break;
1107 }
1108 /* OK what do we do now? The endpoint state is hosed, and we
1109 * should never get to this point if the synchronization between
1110 * queueing, and endpoint state are correct. This might happen
1111 * if the device gets disconnected after we've finished
1112 * cancelling URBs, which might not be an error...
1113 */
1114 } else {
1115 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1116 le64_to_cpu(ep_ctx->deq));
1117 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1118 dev->eps[ep_index].queued_deq_ptr) ==
1119 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1120 /* Update the ring's dequeue segment and dequeue pointer
1121 * to reflect the new position.
1122 */
1123 update_ring_for_set_deq_completion(xhci, dev,
1124 ep_ring, ep_index);
1125 } else {
1126 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1127 "Ptr command & xHCI internal state.\n");
1128 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1129 dev->eps[ep_index].queued_deq_seg,
1130 dev->eps[ep_index].queued_deq_ptr);
1131 }
1132 }
1133
1134 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1135 dev->eps[ep_index].queued_deq_seg = NULL;
1136 dev->eps[ep_index].queued_deq_ptr = NULL;
1137 /* Restart any rings with pending URBs */
1138 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1139}
1140
1141static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1142 struct xhci_event_cmd *event,
1143 union xhci_trb *trb)
1144{
1145 int slot_id;
1146 unsigned int ep_index;
1147
1148 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1149 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1150 /* This command will only fail if the endpoint wasn't halted,
1151 * but we don't care.
1152 */
1153 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1154 GET_COMP_CODE(le32_to_cpu(event->status)));
1155
1156 /* HW with the reset endpoint quirk needs to have a configure endpoint
1157 * command complete before the endpoint can be used. Queue that here
1158 * because the HW can't handle two commands being queued in a row.
1159 */
1160 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1161 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1162 xhci_queue_configure_endpoint(xhci,
1163 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1164 false);
1165 xhci_ring_cmd_db(xhci);
1166 } else {
1167 /* Clear our internal halted state and restart the ring(s) */
1168 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1169 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1170 }
1171}
1172
1173/* Complete the command and detele it from the devcie's command queue.
1174 */
1175static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1176 struct xhci_command *command, u32 status)
1177{
1178 command->status = status;
1179 list_del(&command->cmd_list);
1180 if (command->completion)
1181 complete(command->completion);
1182 else
1183 xhci_free_command(xhci, command);
1184}
1185
1186
1187/* Check to see if a command in the device's command queue matches this one.
1188 * Signal the completion or free the command, and return 1. Return 0 if the
1189 * completed command isn't at the head of the command list.
1190 */
1191static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1192 struct xhci_virt_device *virt_dev,
1193 struct xhci_event_cmd *event)
1194{
1195 struct xhci_command *command;
1196
1197 if (list_empty(&virt_dev->cmd_list))
1198 return 0;
1199
1200 command = list_entry(virt_dev->cmd_list.next,
1201 struct xhci_command, cmd_list);
1202 if (xhci->cmd_ring->dequeue != command->command_trb)
1203 return 0;
1204
1205 xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1206 GET_COMP_CODE(le32_to_cpu(event->status)));
1207 return 1;
1208}
1209
1210/*
1211 * Finding the command trb need to be cancelled and modifying it to
1212 * NO OP command. And if the command is in device's command wait
1213 * list, finishing and freeing it.
1214 *
1215 * If we can't find the command trb, we think it had already been
1216 * executed.
1217 */
1218static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1219{
1220 struct xhci_segment *cur_seg;
1221 union xhci_trb *cmd_trb;
1222 u32 cycle_state;
1223
1224 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1225 return;
1226
1227 /* find the current segment of command ring */
1228 cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1229 xhci->cmd_ring->dequeue, &cycle_state);
1230
1231 /* find the command trb matched by cd from command ring */
1232 for (cmd_trb = xhci->cmd_ring->dequeue;
1233 cmd_trb != xhci->cmd_ring->enqueue;
1234 next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1235 /* If the trb is link trb, continue */
1236 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1237 continue;
1238
1239 if (cur_cd->cmd_trb == cmd_trb) {
1240
1241 /* If the command in device's command list, we should
1242 * finish it and free the command structure.
1243 */
1244 if (cur_cd->command)
1245 xhci_complete_cmd_in_cmd_wait_list(xhci,
1246 cur_cd->command, COMP_CMD_STOP);
1247
1248 /* get cycle state from the origin command trb */
1249 cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1250 & TRB_CYCLE;
1251
1252 /* modify the command trb to NO OP command */
1253 cmd_trb->generic.field[0] = 0;
1254 cmd_trb->generic.field[1] = 0;
1255 cmd_trb->generic.field[2] = 0;
1256 cmd_trb->generic.field[3] = cpu_to_le32(
1257 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1258 break;
1259 }
1260 }
1261}
1262
1263static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1264{
1265 struct xhci_cd *cur_cd, *next_cd;
1266
1267 if (list_empty(&xhci->cancel_cmd_list))
1268 return;
1269
1270 list_for_each_entry_safe(cur_cd, next_cd,
1271 &xhci->cancel_cmd_list, cancel_cmd_list) {
1272 xhci_cmd_to_noop(xhci, cur_cd);
1273 list_del(&cur_cd->cancel_cmd_list);
1274 kfree(cur_cd);
1275 }
1276}
1277
1278/*
1279 * traversing the cancel_cmd_list. If the command descriptor according
1280 * to cmd_trb is found, the function free it and return 1, otherwise
1281 * return 0.
1282 */
1283static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1284 union xhci_trb *cmd_trb)
1285{
1286 struct xhci_cd *cur_cd, *next_cd;
1287
1288 if (list_empty(&xhci->cancel_cmd_list))
1289 return 0;
1290
1291 list_for_each_entry_safe(cur_cd, next_cd,
1292 &xhci->cancel_cmd_list, cancel_cmd_list) {
1293 if (cur_cd->cmd_trb == cmd_trb) {
1294 if (cur_cd->command)
1295 xhci_complete_cmd_in_cmd_wait_list(xhci,
1296 cur_cd->command, COMP_CMD_STOP);
1297 list_del(&cur_cd->cancel_cmd_list);
1298 kfree(cur_cd);
1299 return 1;
1300 }
1301 }
1302
1303 return 0;
1304}
1305
1306/*
1307 * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1308 * trb pointed by the command ring dequeue pointer is the trb we want to
1309 * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1310 * traverse the cancel_cmd_list to trun the all of the commands according
1311 * to command descriptor to NO-OP trb.
1312 */
1313static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1314 int cmd_trb_comp_code)
1315{
1316 int cur_trb_is_good = 0;
1317
1318 /* Searching the cmd trb pointed by the command ring dequeue
1319 * pointer in command descriptor list. If it is found, free it.
1320 */
1321 cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1322 xhci->cmd_ring->dequeue);
1323
1324 if (cmd_trb_comp_code == COMP_CMD_ABORT)
1325 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1326 else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1327 /* traversing the cancel_cmd_list and canceling
1328 * the command according to command descriptor
1329 */
1330 xhci_cancel_cmd_in_cd_list(xhci);
1331
1332 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1333 /*
1334 * ring command ring doorbell again to restart the
1335 * command ring
1336 */
1337 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1338 xhci_ring_cmd_db(xhci);
1339 }
1340 return cur_trb_is_good;
1341}
1342
1343static void handle_cmd_completion(struct xhci_hcd *xhci,
1344 struct xhci_event_cmd *event)
1345{
1346 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1347 u64 cmd_dma;
1348 dma_addr_t cmd_dequeue_dma;
1349 struct xhci_input_control_ctx *ctrl_ctx;
1350 struct xhci_virt_device *virt_dev;
1351 unsigned int ep_index;
1352 struct xhci_ring *ep_ring;
1353 unsigned int ep_state;
1354
1355 cmd_dma = le64_to_cpu(event->cmd_trb);
1356 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1357 xhci->cmd_ring->dequeue);
1358 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1359 if (cmd_dequeue_dma == 0) {
1360 xhci->error_bitmask |= 1 << 4;
1361 return;
1362 }
1363 /* Does the DMA address match our internal dequeue pointer address? */
1364 if (cmd_dma != (u64) cmd_dequeue_dma) {
1365 xhci->error_bitmask |= 1 << 5;
1366 return;
1367 }
1368
1369 if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1370 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1371 /* If the return value is 0, we think the trb pointed by
1372 * command ring dequeue pointer is a good trb. The good
1373 * trb means we don't want to cancel the trb, but it have
1374 * been stopped by host. So we should handle it normally.
1375 * Otherwise, driver should invoke inc_deq() and return.
1376 */
1377 if (handle_stopped_cmd_ring(xhci,
1378 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1379 inc_deq(xhci, xhci->cmd_ring);
1380 return;
1381 }
1382 }
1383
1384 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1385 & TRB_TYPE_BITMASK) {
1386 case TRB_TYPE(TRB_ENABLE_SLOT):
1387 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1388 xhci->slot_id = slot_id;
1389 else
1390 xhci->slot_id = 0;
1391 complete(&xhci->addr_dev);
1392 break;
1393 case TRB_TYPE(TRB_DISABLE_SLOT):
1394 if (xhci->devs[slot_id]) {
1395 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1396 /* Delete default control endpoint resources */
1397 xhci_free_device_endpoint_resources(xhci,
1398 xhci->devs[slot_id], true);
1399 xhci_free_virt_device(xhci, slot_id);
1400 }
1401 break;
1402 case TRB_TYPE(TRB_CONFIG_EP):
1403 virt_dev = xhci->devs[slot_id];
1404 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1405 break;
1406 /*
1407 * Configure endpoint commands can come from the USB core
1408 * configuration or alt setting changes, or because the HW
1409 * needed an extra configure endpoint command after a reset
1410 * endpoint command or streams were being configured.
1411 * If the command was for a halted endpoint, the xHCI driver
1412 * is not waiting on the configure endpoint command.
1413 */
1414 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1415 virt_dev->in_ctx);
1416 /* Input ctx add_flags are the endpoint index plus one */
1417 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1418 /* A usb_set_interface() call directly after clearing a halted
1419 * condition may race on this quirky hardware. Not worth
1420 * worrying about, since this is prototype hardware. Not sure
1421 * if this will work for streams, but streams support was
1422 * untested on this prototype.
1423 */
1424 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1425 ep_index != (unsigned int) -1 &&
1426 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1427 le32_to_cpu(ctrl_ctx->drop_flags)) {
1428 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1429 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1430 if (!(ep_state & EP_HALTED))
1431 goto bandwidth_change;
1432 xhci_dbg(xhci, "Completed config ep cmd - "
1433 "last ep index = %d, state = %d\n",
1434 ep_index, ep_state);
1435 /* Clear internal halted state and restart ring(s) */
1436 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1437 ~EP_HALTED;
1438 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1439 break;
1440 }
1441bandwidth_change:
1442 xhci_dbg(xhci, "Completed config ep cmd\n");
1443 xhci->devs[slot_id]->cmd_status =
1444 GET_COMP_CODE(le32_to_cpu(event->status));
1445 complete(&xhci->devs[slot_id]->cmd_completion);
1446 break;
1447 case TRB_TYPE(TRB_EVAL_CONTEXT):
1448 virt_dev = xhci->devs[slot_id];
1449 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1450 break;
1451 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1452 complete(&xhci->devs[slot_id]->cmd_completion);
1453 break;
1454 case TRB_TYPE(TRB_ADDR_DEV):
1455 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1456 complete(&xhci->addr_dev);
1457 break;
1458 case TRB_TYPE(TRB_STOP_RING):
1459 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1460 break;
1461 case TRB_TYPE(TRB_SET_DEQ):
1462 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1463 break;
1464 case TRB_TYPE(TRB_CMD_NOOP):
1465 break;
1466 case TRB_TYPE(TRB_RESET_EP):
1467 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1468 break;
1469 case TRB_TYPE(TRB_RESET_DEV):
1470 xhci_dbg(xhci, "Completed reset device command.\n");
1471 slot_id = TRB_TO_SLOT_ID(
1472 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1473 virt_dev = xhci->devs[slot_id];
1474 if (virt_dev)
1475 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1476 else
1477 xhci_warn(xhci, "Reset device command completion "
1478 "for disabled slot %u\n", slot_id);
1479 break;
1480 case TRB_TYPE(TRB_NEC_GET_FW):
1481 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1482 xhci->error_bitmask |= 1 << 6;
1483 break;
1484 }
1485 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1486 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1487 NEC_FW_MINOR(le32_to_cpu(event->status)));
1488 break;
1489 default:
1490 /* Skip over unknown commands on the event ring */
1491 xhci->error_bitmask |= 1 << 6;
1492 break;
1493 }
1494 inc_deq(xhci, xhci->cmd_ring);
1495}
1496
1497static void handle_vendor_event(struct xhci_hcd *xhci,
1498 union xhci_trb *event)
1499{
1500 u32 trb_type;
1501
1502 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1503 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1504 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1505 handle_cmd_completion(xhci, &event->event_cmd);
1506}
1507
1508/* @port_id: the one-based port ID from the hardware (indexed from array of all
1509 * port registers -- USB 3.0 and USB 2.0).
1510 *
1511 * Returns a zero-based port number, which is suitable for indexing into each of
1512 * the split roothubs' port arrays and bus state arrays.
1513 * Add one to it in order to call xhci_find_slot_id_by_port.
1514 */
1515static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1516 struct xhci_hcd *xhci, u32 port_id)
1517{
1518 unsigned int i;
1519 unsigned int num_similar_speed_ports = 0;
1520
1521 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1522 * and usb2_ports are 0-based indexes. Count the number of similar
1523 * speed ports, up to 1 port before this port.
1524 */
1525 for (i = 0; i < (port_id - 1); i++) {
1526 u8 port_speed = xhci->port_array[i];
1527
1528 /*
1529 * Skip ports that don't have known speeds, or have duplicate
1530 * Extended Capabilities port speed entries.
1531 */
1532 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1533 continue;
1534
1535 /*
1536 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1537 * 1.1 ports are under the USB 2.0 hub. If the port speed
1538 * matches the device speed, it's a similar speed port.
1539 */
1540 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1541 num_similar_speed_ports++;
1542 }
1543 return num_similar_speed_ports;
1544}
1545
1546static void handle_device_notification(struct xhci_hcd *xhci,
1547 union xhci_trb *event)
1548{
1549 u32 slot_id;
1550 struct usb_device *udev;
1551
1552 slot_id = TRB_TO_SLOT_ID(event->generic.field[3]);
1553 if (!xhci->devs[slot_id]) {
1554 xhci_warn(xhci, "Device Notification event for "
1555 "unused slot %u\n", slot_id);
1556 return;
1557 }
1558
1559 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1560 slot_id);
1561 udev = xhci->devs[slot_id]->udev;
1562 if (udev && udev->parent)
1563 usb_wakeup_notification(udev->parent, udev->portnum);
1564}
1565
1566static void handle_port_status(struct xhci_hcd *xhci,
1567 union xhci_trb *event)
1568{
1569 struct usb_hcd *hcd;
1570 u32 port_id;
1571 u32 temp, temp1;
1572 int max_ports;
1573 int slot_id;
1574 unsigned int faked_port_index;
1575 u8 major_revision;
1576 struct xhci_bus_state *bus_state;
1577 __le32 __iomem **port_array;
1578 bool bogus_port_status = false;
1579
1580 /* Port status change events always have a successful completion code */
1581 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1582 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1583 xhci->error_bitmask |= 1 << 8;
1584 }
1585 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1586 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1587
1588 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1589 if ((port_id <= 0) || (port_id > max_ports)) {
1590 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1591 bogus_port_status = true;
1592 goto cleanup;
1593 }
1594
1595 /* Figure out which usb_hcd this port is attached to:
1596 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1597 */
1598 major_revision = xhci->port_array[port_id - 1];
1599 if (major_revision == 0) {
1600 xhci_warn(xhci, "Event for port %u not in "
1601 "Extended Capabilities, ignoring.\n",
1602 port_id);
1603 bogus_port_status = true;
1604 goto cleanup;
1605 }
1606 if (major_revision == DUPLICATE_ENTRY) {
1607 xhci_warn(xhci, "Event for port %u duplicated in"
1608 "Extended Capabilities, ignoring.\n",
1609 port_id);
1610 bogus_port_status = true;
1611 goto cleanup;
1612 }
1613
1614 /*
1615 * Hardware port IDs reported by a Port Status Change Event include USB
1616 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1617 * resume event, but we first need to translate the hardware port ID
1618 * into the index into the ports on the correct split roothub, and the
1619 * correct bus_state structure.
1620 */
1621 /* Find the right roothub. */
1622 hcd = xhci_to_hcd(xhci);
1623 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1624 hcd = xhci->shared_hcd;
1625 bus_state = &xhci->bus_state[hcd_index(hcd)];
1626 if (hcd->speed == HCD_USB3)
1627 port_array = xhci->usb3_ports;
1628 else
1629 port_array = xhci->usb2_ports;
1630 /* Find the faked port hub number */
1631 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1632 port_id);
1633
1634 temp = xhci_readl(xhci, port_array[faked_port_index]);
1635 if (hcd->state == HC_STATE_SUSPENDED) {
1636 xhci_dbg(xhci, "resume root hub\n");
1637 usb_hcd_resume_root_hub(hcd);
1638 }
1639
1640 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1641 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1642
1643 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1644 if (!(temp1 & CMD_RUN)) {
1645 xhci_warn(xhci, "xHC is not running.\n");
1646 goto cleanup;
1647 }
1648
1649 if (DEV_SUPERSPEED(temp)) {
1650 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1651 /* Set a flag to say the port signaled remote wakeup,
1652 * so we can tell the difference between the end of
1653 * device and host initiated resume.
1654 */
1655 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1656 xhci_test_and_clear_bit(xhci, port_array,
1657 faked_port_index, PORT_PLC);
1658 xhci_set_link_state(xhci, port_array, faked_port_index,
1659 XDEV_U0);
1660 /* Need to wait until the next link state change
1661 * indicates the device is actually in U0.
1662 */
1663 bogus_port_status = true;
1664 goto cleanup;
1665 } else {
1666 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1667 bus_state->resume_done[faked_port_index] = jiffies +
1668 msecs_to_jiffies(20);
1669 set_bit(faked_port_index, &bus_state->resuming_ports);
1670 mod_timer(&hcd->rh_timer,
1671 bus_state->resume_done[faked_port_index]);
1672 /* Do the rest in GetPortStatus */
1673 }
1674 }
1675
1676 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1677 DEV_SUPERSPEED(temp)) {
1678 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1679 /* We've just brought the device into U0 through either the
1680 * Resume state after a device remote wakeup, or through the
1681 * U3Exit state after a host-initiated resume. If it's a device
1682 * initiated remote wake, don't pass up the link state change,
1683 * so the roothub behavior is consistent with external
1684 * USB 3.0 hub behavior.
1685 */
1686 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1687 faked_port_index + 1);
1688 if (slot_id && xhci->devs[slot_id])
1689 xhci_ring_device(xhci, slot_id);
1690 if (bus_state->port_remote_wakeup && (1 << faked_port_index)) {
1691 bus_state->port_remote_wakeup &=
1692 ~(1 << faked_port_index);
1693 xhci_test_and_clear_bit(xhci, port_array,
1694 faked_port_index, PORT_PLC);
1695 usb_wakeup_notification(hcd->self.root_hub,
1696 faked_port_index + 1);
1697 bogus_port_status = true;
1698 goto cleanup;
1699 }
1700 }
1701
1702 if (hcd->speed != HCD_USB3)
1703 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1704 PORT_PLC);
1705
1706cleanup:
1707 /* Update event ring dequeue pointer before dropping the lock */
1708 inc_deq(xhci, xhci->event_ring);
1709
1710 /* Don't make the USB core poll the roothub if we got a bad port status
1711 * change event. Besides, at that point we can't tell which roothub
1712 * (USB 2.0 or USB 3.0) to kick.
1713 */
1714 if (bogus_port_status)
1715 return;
1716
1717 spin_unlock(&xhci->lock);
1718 /* Pass this up to the core */
1719 usb_hcd_poll_rh_status(hcd);
1720 spin_lock(&xhci->lock);
1721}
1722
1723/*
1724 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1725 * at end_trb, which may be in another segment. If the suspect DMA address is a
1726 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1727 * returns 0.
1728 */
1729struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1730 union xhci_trb *start_trb,
1731 union xhci_trb *end_trb,
1732 dma_addr_t suspect_dma)
1733{
1734 dma_addr_t start_dma;
1735 dma_addr_t end_seg_dma;
1736 dma_addr_t end_trb_dma;
1737 struct xhci_segment *cur_seg;
1738
1739 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1740 cur_seg = start_seg;
1741
1742 do {
1743 if (start_dma == 0)
1744 return NULL;
1745 /* We may get an event for a Link TRB in the middle of a TD */
1746 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1747 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1748 /* If the end TRB isn't in this segment, this is set to 0 */
1749 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1750
1751 if (end_trb_dma > 0) {
1752 /* The end TRB is in this segment, so suspect should be here */
1753 if (start_dma <= end_trb_dma) {
1754 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1755 return cur_seg;
1756 } else {
1757 /* Case for one segment with
1758 * a TD wrapped around to the top
1759 */
1760 if ((suspect_dma >= start_dma &&
1761 suspect_dma <= end_seg_dma) ||
1762 (suspect_dma >= cur_seg->dma &&
1763 suspect_dma <= end_trb_dma))
1764 return cur_seg;
1765 }
1766 return NULL;
1767 } else {
1768 /* Might still be somewhere in this segment */
1769 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1770 return cur_seg;
1771 }
1772 cur_seg = cur_seg->next;
1773 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1774 } while (cur_seg != start_seg);
1775
1776 return NULL;
1777}
1778
1779static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1780 unsigned int slot_id, unsigned int ep_index,
1781 unsigned int stream_id,
1782 struct xhci_td *td, union xhci_trb *event_trb)
1783{
1784 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1785 ep->ep_state |= EP_HALTED;
1786 ep->stopped_td = td;
1787 ep->stopped_trb = event_trb;
1788 ep->stopped_stream = stream_id;
1789
1790 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1791 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1792
1793 ep->stopped_td = NULL;
1794 ep->stopped_trb = NULL;
1795 ep->stopped_stream = 0;
1796
1797 xhci_ring_cmd_db(xhci);
1798}
1799
1800/* Check if an error has halted the endpoint ring. The class driver will
1801 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1802 * However, a babble and other errors also halt the endpoint ring, and the class
1803 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1804 * Ring Dequeue Pointer command manually.
1805 */
1806static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1807 struct xhci_ep_ctx *ep_ctx,
1808 unsigned int trb_comp_code)
1809{
1810 /* TRB completion codes that may require a manual halt cleanup */
1811 if (trb_comp_code == COMP_TX_ERR ||
1812 trb_comp_code == COMP_BABBLE ||
1813 trb_comp_code == COMP_SPLIT_ERR)
1814 /* The 0.96 spec says a babbling control endpoint
1815 * is not halted. The 0.96 spec says it is. Some HW
1816 * claims to be 0.95 compliant, but it halts the control
1817 * endpoint anyway. Check if a babble halted the
1818 * endpoint.
1819 */
1820 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1821 cpu_to_le32(EP_STATE_HALTED))
1822 return 1;
1823
1824 return 0;
1825}
1826
1827int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1828{
1829 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1830 /* Vendor defined "informational" completion code,
1831 * treat as not-an-error.
1832 */
1833 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1834 trb_comp_code);
1835 xhci_dbg(xhci, "Treating code as success.\n");
1836 return 1;
1837 }
1838 return 0;
1839}
1840
1841/*
1842 * Finish the td processing, remove the td from td list;
1843 * Return 1 if the urb can be given back.
1844 */
1845static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1846 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1847 struct xhci_virt_ep *ep, int *status, bool skip)
1848{
1849 struct xhci_virt_device *xdev;
1850 struct xhci_ring *ep_ring;
1851 unsigned int slot_id;
1852 int ep_index;
1853 struct urb *urb = NULL;
1854 struct xhci_ep_ctx *ep_ctx;
1855 int ret = 0;
1856 struct urb_priv *urb_priv;
1857 u32 trb_comp_code;
1858
1859 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1860 xdev = xhci->devs[slot_id];
1861 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1862 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1863 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1864 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1865
1866 if (skip)
1867 goto td_cleanup;
1868
1869 if (trb_comp_code == COMP_STOP_INVAL ||
1870 trb_comp_code == COMP_STOP) {
1871 /* The Endpoint Stop Command completion will take care of any
1872 * stopped TDs. A stopped TD may be restarted, so don't update
1873 * the ring dequeue pointer or take this TD off any lists yet.
1874 */
1875 ep->stopped_td = td;
1876 ep->stopped_trb = event_trb;
1877 return 0;
1878 } else {
1879 if (trb_comp_code == COMP_STALL) {
1880 /* The transfer is completed from the driver's
1881 * perspective, but we need to issue a set dequeue
1882 * command for this stalled endpoint to move the dequeue
1883 * pointer past the TD. We can't do that here because
1884 * the halt condition must be cleared first. Let the
1885 * USB class driver clear the stall later.
1886 */
1887 ep->stopped_td = td;
1888 ep->stopped_trb = event_trb;
1889 ep->stopped_stream = ep_ring->stream_id;
1890 } else if (xhci_requires_manual_halt_cleanup(xhci,
1891 ep_ctx, trb_comp_code)) {
1892 /* Other types of errors halt the endpoint, but the
1893 * class driver doesn't call usb_reset_endpoint() unless
1894 * the error is -EPIPE. Clear the halted status in the
1895 * xHCI hardware manually.
1896 */
1897 xhci_cleanup_halted_endpoint(xhci,
1898 slot_id, ep_index, ep_ring->stream_id,
1899 td, event_trb);
1900 } else {
1901 /* Update ring dequeue pointer */
1902 while (ep_ring->dequeue != td->last_trb)
1903 inc_deq(xhci, ep_ring);
1904 inc_deq(xhci, ep_ring);
1905 }
1906
1907td_cleanup:
1908 /* Clean up the endpoint's TD list */
1909 urb = td->urb;
1910 urb_priv = urb->hcpriv;
1911
1912 /* Do one last check of the actual transfer length.
1913 * If the host controller said we transferred more data than
1914 * the buffer length, urb->actual_length will be a very big
1915 * number (since it's unsigned). Play it safe and say we didn't
1916 * transfer anything.
1917 */
1918 if (urb->actual_length > urb->transfer_buffer_length) {
1919 xhci_warn(xhci, "URB transfer length is wrong, "
1920 "xHC issue? req. len = %u, "
1921 "act. len = %u\n",
1922 urb->transfer_buffer_length,
1923 urb->actual_length);
1924 urb->actual_length = 0;
1925 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1926 *status = -EREMOTEIO;
1927 else
1928 *status = 0;
1929 }
1930 list_del_init(&td->td_list);
1931 /* Was this TD slated to be cancelled but completed anyway? */
1932 if (!list_empty(&td->cancelled_td_list))
1933 list_del_init(&td->cancelled_td_list);
1934
1935 urb_priv->td_cnt++;
1936 /* Giveback the urb when all the tds are completed */
1937 if (urb_priv->td_cnt == urb_priv->length) {
1938 ret = 1;
1939 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1940 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1941 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1942 == 0) {
1943 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1944 usb_amd_quirk_pll_enable();
1945 }
1946 }
1947 }
1948 }
1949
1950 return ret;
1951}
1952
1953/*
1954 * Process control tds, update urb status and actual_length.
1955 */
1956static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1957 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1958 struct xhci_virt_ep *ep, int *status)
1959{
1960 struct xhci_virt_device *xdev;
1961 struct xhci_ring *ep_ring;
1962 unsigned int slot_id;
1963 int ep_index;
1964 struct xhci_ep_ctx *ep_ctx;
1965 u32 trb_comp_code;
1966
1967 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1968 xdev = xhci->devs[slot_id];
1969 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1970 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1971 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1972 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1973
1974 switch (trb_comp_code) {
1975 case COMP_SUCCESS:
1976 if (event_trb == ep_ring->dequeue) {
1977 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1978 "without IOC set??\n");
1979 *status = -ESHUTDOWN;
1980 } else if (event_trb != td->last_trb) {
1981 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1982 "without IOC set??\n");
1983 *status = -ESHUTDOWN;
1984 } else {
1985 *status = 0;
1986 }
1987 break;
1988 case COMP_SHORT_TX:
1989 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1990 *status = -EREMOTEIO;
1991 else
1992 *status = 0;
1993 break;
1994 case COMP_STOP_INVAL:
1995 case COMP_STOP:
1996 return finish_td(xhci, td, event_trb, event, ep, status, false);
1997 default:
1998 if (!xhci_requires_manual_halt_cleanup(xhci,
1999 ep_ctx, trb_comp_code))
2000 break;
2001 xhci_dbg(xhci, "TRB error code %u, "
2002 "halted endpoint index = %u\n",
2003 trb_comp_code, ep_index);
2004 /* else fall through */
2005 case COMP_STALL:
2006 /* Did we transfer part of the data (middle) phase? */
2007 if (event_trb != ep_ring->dequeue &&
2008 event_trb != td->last_trb)
2009 td->urb->actual_length =
2010 td->urb->transfer_buffer_length
2011 - TRB_LEN(le32_to_cpu(event->transfer_len));
2012 else
2013 td->urb->actual_length = 0;
2014
2015 xhci_cleanup_halted_endpoint(xhci,
2016 slot_id, ep_index, 0, td, event_trb);
2017 return finish_td(xhci, td, event_trb, event, ep, status, true);
2018 }
2019 /*
2020 * Did we transfer any data, despite the errors that might have
2021 * happened? I.e. did we get past the setup stage?
2022 */
2023 if (event_trb != ep_ring->dequeue) {
2024 /* The event was for the status stage */
2025 if (event_trb == td->last_trb) {
2026 if (td->urb->actual_length != 0) {
2027 /* Don't overwrite a previously set error code
2028 */
2029 if ((*status == -EINPROGRESS || *status == 0) &&
2030 (td->urb->transfer_flags
2031 & URB_SHORT_NOT_OK))
2032 /* Did we already see a short data
2033 * stage? */
2034 *status = -EREMOTEIO;
2035 } else {
2036 td->urb->actual_length =
2037 td->urb->transfer_buffer_length;
2038 }
2039 } else {
2040 /* Maybe the event was for the data stage? */
2041 td->urb->actual_length =
2042 td->urb->transfer_buffer_length -
2043 TRB_LEN(le32_to_cpu(event->transfer_len));
2044 xhci_dbg(xhci, "Waiting for status "
2045 "stage event\n");
2046 return 0;
2047 }
2048 }
2049
2050 return finish_td(xhci, td, event_trb, event, ep, status, false);
2051}
2052
2053/*
2054 * Process isochronous tds, update urb packet status and actual_length.
2055 */
2056static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2057 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2058 struct xhci_virt_ep *ep, int *status)
2059{
2060 struct xhci_ring *ep_ring;
2061 struct urb_priv *urb_priv;
2062 int idx;
2063 int len = 0;
2064 union xhci_trb *cur_trb;
2065 struct xhci_segment *cur_seg;
2066 struct usb_iso_packet_descriptor *frame;
2067 u32 trb_comp_code;
2068 bool skip_td = false;
2069
2070 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2071 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2072 urb_priv = td->urb->hcpriv;
2073 idx = urb_priv->td_cnt;
2074 frame = &td->urb->iso_frame_desc[idx];
2075
2076 /* handle completion code */
2077 switch (trb_comp_code) {
2078 case COMP_SUCCESS:
2079 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2080 frame->status = 0;
2081 break;
2082 }
2083 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2084 trb_comp_code = COMP_SHORT_TX;
2085 case COMP_SHORT_TX:
2086 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2087 -EREMOTEIO : 0;
2088 break;
2089 case COMP_BW_OVER:
2090 frame->status = -ECOMM;
2091 skip_td = true;
2092 break;
2093 case COMP_BUFF_OVER:
2094 case COMP_BABBLE:
2095 frame->status = -EOVERFLOW;
2096 skip_td = true;
2097 break;
2098 case COMP_DEV_ERR:
2099 case COMP_STALL:
2100 case COMP_TX_ERR:
2101 frame->status = -EPROTO;
2102 skip_td = true;
2103 break;
2104 case COMP_STOP:
2105 case COMP_STOP_INVAL:
2106 break;
2107 default:
2108 frame->status = -1;
2109 break;
2110 }
2111
2112 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2113 frame->actual_length = frame->length;
2114 td->urb->actual_length += frame->length;
2115 } else {
2116 for (cur_trb = ep_ring->dequeue,
2117 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2118 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2119 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2120 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2121 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2122 }
2123 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2124 TRB_LEN(le32_to_cpu(event->transfer_len));
2125
2126 if (trb_comp_code != COMP_STOP_INVAL) {
2127 frame->actual_length = len;
2128 td->urb->actual_length += len;
2129 }
2130 }
2131
2132 return finish_td(xhci, td, event_trb, event, ep, status, false);
2133}
2134
2135static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2136 struct xhci_transfer_event *event,
2137 struct xhci_virt_ep *ep, int *status)
2138{
2139 struct xhci_ring *ep_ring;
2140 struct urb_priv *urb_priv;
2141 struct usb_iso_packet_descriptor *frame;
2142 int idx;
2143
2144 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2145 urb_priv = td->urb->hcpriv;
2146 idx = urb_priv->td_cnt;
2147 frame = &td->urb->iso_frame_desc[idx];
2148
2149 /* The transfer is partly done. */
2150 frame->status = -EXDEV;
2151
2152 /* calc actual length */
2153 frame->actual_length = 0;
2154
2155 /* Update ring dequeue pointer */
2156 while (ep_ring->dequeue != td->last_trb)
2157 inc_deq(xhci, ep_ring);
2158 inc_deq(xhci, ep_ring);
2159
2160 return finish_td(xhci, td, NULL, event, ep, status, true);
2161}
2162
2163/*
2164 * Process bulk and interrupt tds, update urb status and actual_length.
2165 */
2166static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2167 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2168 struct xhci_virt_ep *ep, int *status)
2169{
2170 struct xhci_ring *ep_ring;
2171 union xhci_trb *cur_trb;
2172 struct xhci_segment *cur_seg;
2173 u32 trb_comp_code;
2174
2175 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2176 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2177
2178 switch (trb_comp_code) {
2179 case COMP_SUCCESS:
2180 /* Double check that the HW transferred everything. */
2181 if (event_trb != td->last_trb ||
2182 TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2183 xhci_warn(xhci, "WARN Successful completion "
2184 "on short TX\n");
2185 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2186 *status = -EREMOTEIO;
2187 else
2188 *status = 0;
2189 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2190 trb_comp_code = COMP_SHORT_TX;
2191 } else {
2192 *status = 0;
2193 }
2194 break;
2195 case COMP_SHORT_TX:
2196 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2197 *status = -EREMOTEIO;
2198 else
2199 *status = 0;
2200 break;
2201 default:
2202 /* Others already handled above */
2203 break;
2204 }
2205 if (trb_comp_code == COMP_SHORT_TX)
2206 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2207 "%d bytes untransferred\n",
2208 td->urb->ep->desc.bEndpointAddress,
2209 td->urb->transfer_buffer_length,
2210 TRB_LEN(le32_to_cpu(event->transfer_len)));
2211 /* Fast path - was this the last TRB in the TD for this URB? */
2212 if (event_trb == td->last_trb) {
2213 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2214 td->urb->actual_length =
2215 td->urb->transfer_buffer_length -
2216 TRB_LEN(le32_to_cpu(event->transfer_len));
2217 if (td->urb->transfer_buffer_length <
2218 td->urb->actual_length) {
2219 xhci_warn(xhci, "HC gave bad length "
2220 "of %d bytes left\n",
2221 TRB_LEN(le32_to_cpu(event->transfer_len)));
2222 td->urb->actual_length = 0;
2223 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2224 *status = -EREMOTEIO;
2225 else
2226 *status = 0;
2227 }
2228 /* Don't overwrite a previously set error code */
2229 if (*status == -EINPROGRESS) {
2230 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2231 *status = -EREMOTEIO;
2232 else
2233 *status = 0;
2234 }
2235 } else {
2236 td->urb->actual_length =
2237 td->urb->transfer_buffer_length;
2238 /* Ignore a short packet completion if the
2239 * untransferred length was zero.
2240 */
2241 if (*status == -EREMOTEIO)
2242 *status = 0;
2243 }
2244 } else {
2245 /* Slow path - walk the list, starting from the dequeue
2246 * pointer, to get the actual length transferred.
2247 */
2248 td->urb->actual_length = 0;
2249 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2250 cur_trb != event_trb;
2251 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2252 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2253 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2254 td->urb->actual_length +=
2255 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2256 }
2257 /* If the ring didn't stop on a Link or No-op TRB, add
2258 * in the actual bytes transferred from the Normal TRB
2259 */
2260 if (trb_comp_code != COMP_STOP_INVAL)
2261 td->urb->actual_length +=
2262 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2263 TRB_LEN(le32_to_cpu(event->transfer_len));
2264 }
2265
2266 return finish_td(xhci, td, event_trb, event, ep, status, false);
2267}
2268
2269/*
2270 * If this function returns an error condition, it means it got a Transfer
2271 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2272 * At this point, the host controller is probably hosed and should be reset.
2273 */
2274static int handle_tx_event(struct xhci_hcd *xhci,
2275 struct xhci_transfer_event *event)
2276{
2277 struct xhci_virt_device *xdev;
2278 struct xhci_virt_ep *ep;
2279 struct xhci_ring *ep_ring;
2280 unsigned int slot_id;
2281 int ep_index;
2282 struct xhci_td *td = NULL;
2283 dma_addr_t event_dma;
2284 struct xhci_segment *event_seg;
2285 union xhci_trb *event_trb;
2286 struct urb *urb = NULL;
2287 int status = -EINPROGRESS;
2288 struct urb_priv *urb_priv;
2289 struct xhci_ep_ctx *ep_ctx;
2290 struct list_head *tmp;
2291 u32 trb_comp_code;
2292 int ret = 0;
2293 int td_num = 0;
2294
2295 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2296 xdev = xhci->devs[slot_id];
2297 if (!xdev) {
2298 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2299 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2300 (unsigned long long) xhci_trb_virt_to_dma(
2301 xhci->event_ring->deq_seg,
2302 xhci->event_ring->dequeue),
2303 lower_32_bits(le64_to_cpu(event->buffer)),
2304 upper_32_bits(le64_to_cpu(event->buffer)),
2305 le32_to_cpu(event->transfer_len),
2306 le32_to_cpu(event->flags));
2307 xhci_dbg(xhci, "Event ring:\n");
2308 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2309 return -ENODEV;
2310 }
2311
2312 /* Endpoint ID is 1 based, our index is zero based */
2313 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2314 ep = &xdev->eps[ep_index];
2315 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2316 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2317 if (!ep_ring ||
2318 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2319 EP_STATE_DISABLED) {
2320 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2321 "or incorrect stream ring\n");
2322 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2323 (unsigned long long) xhci_trb_virt_to_dma(
2324 xhci->event_ring->deq_seg,
2325 xhci->event_ring->dequeue),
2326 lower_32_bits(le64_to_cpu(event->buffer)),
2327 upper_32_bits(le64_to_cpu(event->buffer)),
2328 le32_to_cpu(event->transfer_len),
2329 le32_to_cpu(event->flags));
2330 xhci_dbg(xhci, "Event ring:\n");
2331 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2332 return -ENODEV;
2333 }
2334
2335 /* Count current td numbers if ep->skip is set */
2336 if (ep->skip) {
2337 list_for_each(tmp, &ep_ring->td_list)
2338 td_num++;
2339 }
2340
2341 event_dma = le64_to_cpu(event->buffer);
2342 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2343 /* Look for common error cases */
2344 switch (trb_comp_code) {
2345 /* Skip codes that require special handling depending on
2346 * transfer type
2347 */
2348 case COMP_SUCCESS:
2349 if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2350 break;
2351 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2352 trb_comp_code = COMP_SHORT_TX;
2353 else
2354 xhci_warn(xhci, "WARN Successful completion on short TX: "
2355 "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2356 case COMP_SHORT_TX:
2357 break;
2358 case COMP_STOP:
2359 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2360 break;
2361 case COMP_STOP_INVAL:
2362 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2363 break;
2364 case COMP_STALL:
2365 xhci_dbg(xhci, "Stalled endpoint\n");
2366 ep->ep_state |= EP_HALTED;
2367 status = -EPIPE;
2368 break;
2369 case COMP_TRB_ERR:
2370 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2371 status = -EILSEQ;
2372 break;
2373 case COMP_SPLIT_ERR:
2374 case COMP_TX_ERR:
2375 xhci_dbg(xhci, "Transfer error on endpoint\n");
2376 status = -EPROTO;
2377 break;
2378 case COMP_BABBLE:
2379 xhci_dbg(xhci, "Babble error on endpoint\n");
2380 status = -EOVERFLOW;
2381 break;
2382 case COMP_DB_ERR:
2383 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2384 status = -ENOSR;
2385 break;
2386 case COMP_BW_OVER:
2387 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2388 break;
2389 case COMP_BUFF_OVER:
2390 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2391 break;
2392 case COMP_UNDERRUN:
2393 /*
2394 * When the Isoch ring is empty, the xHC will generate
2395 * a Ring Overrun Event for IN Isoch endpoint or Ring
2396 * Underrun Event for OUT Isoch endpoint.
2397 */
2398 xhci_dbg(xhci, "underrun event on endpoint\n");
2399 if (!list_empty(&ep_ring->td_list))
2400 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2401 "still with TDs queued?\n",
2402 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2403 ep_index);
2404 goto cleanup;
2405 case COMP_OVERRUN:
2406 xhci_dbg(xhci, "overrun event on endpoint\n");
2407 if (!list_empty(&ep_ring->td_list))
2408 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2409 "still with TDs queued?\n",
2410 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2411 ep_index);
2412 goto cleanup;
2413 case COMP_DEV_ERR:
2414 xhci_warn(xhci, "WARN: detect an incompatible device");
2415 status = -EPROTO;
2416 break;
2417 case COMP_MISSED_INT:
2418 /*
2419 * When encounter missed service error, one or more isoc tds
2420 * may be missed by xHC.
2421 * Set skip flag of the ep_ring; Complete the missed tds as
2422 * short transfer when process the ep_ring next time.
2423 */
2424 ep->skip = true;
2425 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2426 goto cleanup;
2427 default:
2428 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2429 status = 0;
2430 break;
2431 }
2432 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2433 "busted\n");
2434 goto cleanup;
2435 }
2436
2437 do {
2438 /* This TRB should be in the TD at the head of this ring's
2439 * TD list.
2440 */
2441 if (list_empty(&ep_ring->td_list)) {
2442 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2443 "with no TDs queued?\n",
2444 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2445 ep_index);
2446 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2447 (le32_to_cpu(event->flags) &
2448 TRB_TYPE_BITMASK)>>10);
2449 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2450 if (ep->skip) {
2451 ep->skip = false;
2452 xhci_dbg(xhci, "td_list is empty while skip "
2453 "flag set. Clear skip flag.\n");
2454 }
2455 ret = 0;
2456 goto cleanup;
2457 }
2458
2459 /* We've skipped all the TDs on the ep ring when ep->skip set */
2460 if (ep->skip && td_num == 0) {
2461 ep->skip = false;
2462 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2463 "Clear skip flag.\n");
2464 ret = 0;
2465 goto cleanup;
2466 }
2467
2468 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2469 if (ep->skip)
2470 td_num--;
2471
2472 /* Is this a TRB in the currently executing TD? */
2473 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2474 td->last_trb, event_dma);
2475
2476 /*
2477 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2478 * is not in the current TD pointed by ep_ring->dequeue because
2479 * that the hardware dequeue pointer still at the previous TRB
2480 * of the current TD. The previous TRB maybe a Link TD or the
2481 * last TRB of the previous TD. The command completion handle
2482 * will take care the rest.
2483 */
2484 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2485 ret = 0;
2486 goto cleanup;
2487 }
2488
2489 if (!event_seg) {
2490 if (!ep->skip ||
2491 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2492 /* Some host controllers give a spurious
2493 * successful event after a short transfer.
2494 * Ignore it.
2495 */
2496 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2497 ep_ring->last_td_was_short) {
2498 ep_ring->last_td_was_short = false;
2499 ret = 0;
2500 goto cleanup;
2501 }
2502 /* HC is busted, give up! */
2503 xhci_err(xhci,
2504 "ERROR Transfer event TRB DMA ptr not "
2505 "part of current TD\n");
2506 return -ESHUTDOWN;
2507 }
2508
2509 ret = skip_isoc_td(xhci, td, event, ep, &status);
2510 goto cleanup;
2511 }
2512 if (trb_comp_code == COMP_SHORT_TX)
2513 ep_ring->last_td_was_short = true;
2514 else
2515 ep_ring->last_td_was_short = false;
2516
2517 if (ep->skip) {
2518 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2519 ep->skip = false;
2520 }
2521
2522 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2523 sizeof(*event_trb)];
2524 /*
2525 * No-op TRB should not trigger interrupts.
2526 * If event_trb is a no-op TRB, it means the
2527 * corresponding TD has been cancelled. Just ignore
2528 * the TD.
2529 */
2530 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2531 xhci_dbg(xhci,
2532 "event_trb is a no-op TRB. Skip it\n");
2533 goto cleanup;
2534 }
2535
2536 /* Now update the urb's actual_length and give back to
2537 * the core
2538 */
2539 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2540 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2541 &status);
2542 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2543 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2544 &status);
2545 else
2546 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2547 ep, &status);
2548
2549cleanup:
2550 /*
2551 * Do not update event ring dequeue pointer if ep->skip is set.
2552 * Will roll back to continue process missed tds.
2553 */
2554 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2555 inc_deq(xhci, xhci->event_ring);
2556 }
2557
2558 if (ret) {
2559 urb = td->urb;
2560 urb_priv = urb->hcpriv;
2561 /* Leave the TD around for the reset endpoint function
2562 * to use(but only if it's not a control endpoint,
2563 * since we already queued the Set TR dequeue pointer
2564 * command for stalled control endpoints).
2565 */
2566 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2567 (trb_comp_code != COMP_STALL &&
2568 trb_comp_code != COMP_BABBLE))
2569 xhci_urb_free_priv(xhci, urb_priv);
2570
2571 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2572 if ((urb->actual_length != urb->transfer_buffer_length &&
2573 (urb->transfer_flags &
2574 URB_SHORT_NOT_OK)) ||
2575 (status != 0 &&
2576 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2577 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2578 "expected = %d, status = %d\n",
2579 urb, urb->actual_length,
2580 urb->transfer_buffer_length,
2581 status);
2582 spin_unlock(&xhci->lock);
2583 /* EHCI, UHCI, and OHCI always unconditionally set the
2584 * urb->status of an isochronous endpoint to 0.
2585 */
2586 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2587 status = 0;
2588 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2589 spin_lock(&xhci->lock);
2590 }
2591
2592 /*
2593 * If ep->skip is set, it means there are missed tds on the
2594 * endpoint ring need to take care of.
2595 * Process them as short transfer until reach the td pointed by
2596 * the event.
2597 */
2598 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2599
2600 return 0;
2601}
2602
2603/*
2604 * This function handles all OS-owned events on the event ring. It may drop
2605 * xhci->lock between event processing (e.g. to pass up port status changes).
2606 * Returns >0 for "possibly more events to process" (caller should call again),
2607 * otherwise 0 if done. In future, <0 returns should indicate error code.
2608 */
2609static int xhci_handle_event(struct xhci_hcd *xhci)
2610{
2611 union xhci_trb *event;
2612 int update_ptrs = 1;
2613 int ret;
2614
2615 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2616 xhci->error_bitmask |= 1 << 1;
2617 return 0;
2618 }
2619
2620 event = xhci->event_ring->dequeue;
2621 /* Does the HC or OS own the TRB? */
2622 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2623 xhci->event_ring->cycle_state) {
2624 xhci->error_bitmask |= 1 << 2;
2625 return 0;
2626 }
2627
2628 /*
2629 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2630 * speculative reads of the event's flags/data below.
2631 */
2632 rmb();
2633 /* FIXME: Handle more event types. */
2634 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2635 case TRB_TYPE(TRB_COMPLETION):
2636 handle_cmd_completion(xhci, &event->event_cmd);
2637 break;
2638 case TRB_TYPE(TRB_PORT_STATUS):
2639 handle_port_status(xhci, event);
2640 update_ptrs = 0;
2641 break;
2642 case TRB_TYPE(TRB_TRANSFER):
2643 ret = handle_tx_event(xhci, &event->trans_event);
2644 if (ret < 0)
2645 xhci->error_bitmask |= 1 << 9;
2646 else
2647 update_ptrs = 0;
2648 break;
2649 case TRB_TYPE(TRB_DEV_NOTE):
2650 handle_device_notification(xhci, event);
2651 break;
2652 default:
2653 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2654 TRB_TYPE(48))
2655 handle_vendor_event(xhci, event);
2656 else
2657 xhci->error_bitmask |= 1 << 3;
2658 }
2659 /* Any of the above functions may drop and re-acquire the lock, so check
2660 * to make sure a watchdog timer didn't mark the host as non-responsive.
2661 */
2662 if (xhci->xhc_state & XHCI_STATE_DYING) {
2663 xhci_dbg(xhci, "xHCI host dying, returning from "
2664 "event handler.\n");
2665 return 0;
2666 }
2667
2668 if (update_ptrs)
2669 /* Update SW event ring dequeue pointer */
2670 inc_deq(xhci, xhci->event_ring);
2671
2672 /* Are there more items on the event ring? Caller will call us again to
2673 * check.
2674 */
2675 return 1;
2676}
2677
2678/*
2679 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2680 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2681 * indicators of an event TRB error, but we check the status *first* to be safe.
2682 */
2683irqreturn_t xhci_irq(struct usb_hcd *hcd)
2684{
2685 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2686 u32 status;
2687 union xhci_trb *trb;
2688 u64 temp_64;
2689 union xhci_trb *event_ring_deq;
2690 dma_addr_t deq;
2691
2692 spin_lock(&xhci->lock);
2693 trb = xhci->event_ring->dequeue;
2694 /* Check if the xHC generated the interrupt, or the irq is shared */
2695 status = xhci_readl(xhci, &xhci->op_regs->status);
2696 if (status == 0xffffffff)
2697 goto hw_died;
2698
2699 if (!(status & STS_EINT)) {
2700 spin_unlock(&xhci->lock);
2701 return IRQ_NONE;
2702 }
2703 if (status & STS_FATAL) {
2704 xhci_warn(xhci, "WARNING: Host System Error\n");
2705 xhci_halt(xhci);
2706hw_died:
2707 spin_unlock(&xhci->lock);
2708 return -ESHUTDOWN;
2709 }
2710
2711 /*
2712 * Clear the op reg interrupt status first,
2713 * so we can receive interrupts from other MSI-X interrupters.
2714 * Write 1 to clear the interrupt status.
2715 */
2716 status |= STS_EINT;
2717 xhci_writel(xhci, status, &xhci->op_regs->status);
2718 /* FIXME when MSI-X is supported and there are multiple vectors */
2719 /* Clear the MSI-X event interrupt status */
2720
2721 if (hcd->irq) {
2722 u32 irq_pending;
2723 /* Acknowledge the PCI interrupt */
2724 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2725 irq_pending |= IMAN_IP;
2726 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2727 }
2728
2729 if (xhci->xhc_state & XHCI_STATE_DYING) {
2730 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2731 "Shouldn't IRQs be disabled?\n");
2732 /* Clear the event handler busy flag (RW1C);
2733 * the event ring should be empty.
2734 */
2735 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2736 xhci_write_64(xhci, temp_64 | ERST_EHB,
2737 &xhci->ir_set->erst_dequeue);
2738 spin_unlock(&xhci->lock);
2739
2740 return IRQ_HANDLED;
2741 }
2742
2743 event_ring_deq = xhci->event_ring->dequeue;
2744 /* FIXME this should be a delayed service routine
2745 * that clears the EHB.
2746 */
2747 while (xhci_handle_event(xhci) > 0) {}
2748
2749 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2750 /* If necessary, update the HW's version of the event ring deq ptr. */
2751 if (event_ring_deq != xhci->event_ring->dequeue) {
2752 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2753 xhci->event_ring->dequeue);
2754 if (deq == 0)
2755 xhci_warn(xhci, "WARN something wrong with SW event "
2756 "ring dequeue ptr.\n");
2757 /* Update HC event ring dequeue pointer */
2758 temp_64 &= ERST_PTR_MASK;
2759 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2760 }
2761
2762 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2763 temp_64 |= ERST_EHB;
2764 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2765
2766 spin_unlock(&xhci->lock);
2767
2768 return IRQ_HANDLED;
2769}
2770
2771irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2772{
2773 return xhci_irq(hcd);
2774}
2775
2776/**** Endpoint Ring Operations ****/
2777
2778/*
2779 * Generic function for queueing a TRB on a ring.
2780 * The caller must have checked to make sure there's room on the ring.
2781 *
2782 * @more_trbs_coming: Will you enqueue more TRBs before calling
2783 * prepare_transfer()?
2784 */
2785static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2786 bool more_trbs_coming,
2787 u32 field1, u32 field2, u32 field3, u32 field4)
2788{
2789 struct xhci_generic_trb *trb;
2790
2791 trb = &ring->enqueue->generic;
2792 trb->field[0] = cpu_to_le32(field1);
2793 trb->field[1] = cpu_to_le32(field2);
2794 trb->field[2] = cpu_to_le32(field3);
2795 trb->field[3] = cpu_to_le32(field4);
2796 inc_enq(xhci, ring, more_trbs_coming);
2797}
2798
2799/*
2800 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2801 * FIXME allocate segments if the ring is full.
2802 */
2803static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2804 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2805{
2806 unsigned int num_trbs_needed;
2807
2808 /* Make sure the endpoint has been added to xHC schedule */
2809 switch (ep_state) {
2810 case EP_STATE_DISABLED:
2811 /*
2812 * USB core changed config/interfaces without notifying us,
2813 * or hardware is reporting the wrong state.
2814 */
2815 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2816 return -ENOENT;
2817 case EP_STATE_ERROR:
2818 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2819 /* FIXME event handling code for error needs to clear it */
2820 /* XXX not sure if this should be -ENOENT or not */
2821 return -EINVAL;
2822 case EP_STATE_HALTED:
2823 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2824 case EP_STATE_STOPPED:
2825 case EP_STATE_RUNNING:
2826 break;
2827 default:
2828 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2829 /*
2830 * FIXME issue Configure Endpoint command to try to get the HC
2831 * back into a known state.
2832 */
2833 return -EINVAL;
2834 }
2835
2836 while (1) {
2837 if (room_on_ring(xhci, ep_ring, num_trbs))
2838 break;
2839
2840 if (ep_ring == xhci->cmd_ring) {
2841 xhci_err(xhci, "Do not support expand command ring\n");
2842 return -ENOMEM;
2843 }
2844
2845 xhci_dbg(xhci, "ERROR no room on ep ring, "
2846 "try ring expansion\n");
2847 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2848 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2849 mem_flags)) {
2850 xhci_err(xhci, "Ring expansion failed\n");
2851 return -ENOMEM;
2852 }
2853 };
2854
2855 if (enqueue_is_link_trb(ep_ring)) {
2856 struct xhci_ring *ring = ep_ring;
2857 union xhci_trb *next;
2858
2859 next = ring->enqueue;
2860
2861 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2862 /* If we're not dealing with 0.95 hardware or isoc rings
2863 * on AMD 0.96 host, clear the chain bit.
2864 */
2865 if (!xhci_link_trb_quirk(xhci) &&
2866 !(ring->type == TYPE_ISOC &&
2867 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2868 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2869 else
2870 next->link.control |= cpu_to_le32(TRB_CHAIN);
2871
2872 wmb();
2873 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2874
2875 /* Toggle the cycle bit after the last ring segment. */
2876 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2877 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2878 }
2879 ring->enq_seg = ring->enq_seg->next;
2880 ring->enqueue = ring->enq_seg->trbs;
2881 next = ring->enqueue;
2882 }
2883 }
2884
2885 return 0;
2886}
2887
2888static int prepare_transfer(struct xhci_hcd *xhci,
2889 struct xhci_virt_device *xdev,
2890 unsigned int ep_index,
2891 unsigned int stream_id,
2892 unsigned int num_trbs,
2893 struct urb *urb,
2894 unsigned int td_index,
2895 gfp_t mem_flags)
2896{
2897 int ret;
2898 struct urb_priv *urb_priv;
2899 struct xhci_td *td;
2900 struct xhci_ring *ep_ring;
2901 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2902
2903 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2904 if (!ep_ring) {
2905 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2906 stream_id);
2907 return -EINVAL;
2908 }
2909
2910 ret = prepare_ring(xhci, ep_ring,
2911 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2912 num_trbs, mem_flags);
2913 if (ret)
2914 return ret;
2915
2916 urb_priv = urb->hcpriv;
2917 td = urb_priv->td[td_index];
2918
2919 INIT_LIST_HEAD(&td->td_list);
2920 INIT_LIST_HEAD(&td->cancelled_td_list);
2921
2922 if (td_index == 0) {
2923 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2924 if (unlikely(ret))
2925 return ret;
2926 }
2927
2928 td->urb = urb;
2929 /* Add this TD to the tail of the endpoint ring's TD list */
2930 list_add_tail(&td->td_list, &ep_ring->td_list);
2931 td->start_seg = ep_ring->enq_seg;
2932 td->first_trb = ep_ring->enqueue;
2933
2934 urb_priv->td[td_index] = td;
2935
2936 return 0;
2937}
2938
2939static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2940{
2941 int num_sgs, num_trbs, running_total, temp, i;
2942 struct scatterlist *sg;
2943
2944 sg = NULL;
2945 num_sgs = urb->num_mapped_sgs;
2946 temp = urb->transfer_buffer_length;
2947
2948 num_trbs = 0;
2949 for_each_sg(urb->sg, sg, num_sgs, i) {
2950 unsigned int len = sg_dma_len(sg);
2951
2952 /* Scatter gather list entries may cross 64KB boundaries */
2953 running_total = TRB_MAX_BUFF_SIZE -
2954 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2955 running_total &= TRB_MAX_BUFF_SIZE - 1;
2956 if (running_total != 0)
2957 num_trbs++;
2958
2959 /* How many more 64KB chunks to transfer, how many more TRBs? */
2960 while (running_total < sg_dma_len(sg) && running_total < temp) {
2961 num_trbs++;
2962 running_total += TRB_MAX_BUFF_SIZE;
2963 }
2964 len = min_t(int, len, temp);
2965 temp -= len;
2966 if (temp == 0)
2967 break;
2968 }
2969 return num_trbs;
2970}
2971
2972static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2973{
2974 if (num_trbs != 0)
2975 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2976 "TRBs, %d left\n", __func__,
2977 urb->ep->desc.bEndpointAddress, num_trbs);
2978 if (running_total != urb->transfer_buffer_length)
2979 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2980 "queued %#x (%d), asked for %#x (%d)\n",
2981 __func__,
2982 urb->ep->desc.bEndpointAddress,
2983 running_total, running_total,
2984 urb->transfer_buffer_length,
2985 urb->transfer_buffer_length);
2986}
2987
2988static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2989 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2990 struct xhci_generic_trb *start_trb)
2991{
2992 /*
2993 * Pass all the TRBs to the hardware at once and make sure this write
2994 * isn't reordered.
2995 */
2996 wmb();
2997 if (start_cycle)
2998 start_trb->field[3] |= cpu_to_le32(start_cycle);
2999 else
3000 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3001 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3002}
3003
3004/*
3005 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3006 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3007 * (comprised of sg list entries) can take several service intervals to
3008 * transmit.
3009 */
3010int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3011 struct urb *urb, int slot_id, unsigned int ep_index)
3012{
3013 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3014 xhci->devs[slot_id]->out_ctx, ep_index);
3015 int xhci_interval;
3016 int ep_interval;
3017
3018 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3019 ep_interval = urb->interval;
3020 /* Convert to microframes */
3021 if (urb->dev->speed == USB_SPEED_LOW ||
3022 urb->dev->speed == USB_SPEED_FULL)
3023 ep_interval *= 8;
3024 /* FIXME change this to a warning and a suggestion to use the new API
3025 * to set the polling interval (once the API is added).
3026 */
3027 if (xhci_interval != ep_interval) {
3028 if (printk_ratelimit())
3029 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3030 " (%d microframe%s) than xHCI "
3031 "(%d microframe%s)\n",
3032 ep_interval,
3033 ep_interval == 1 ? "" : "s",
3034 xhci_interval,
3035 xhci_interval == 1 ? "" : "s");
3036 urb->interval = xhci_interval;
3037 /* Convert back to frames for LS/FS devices */
3038 if (urb->dev->speed == USB_SPEED_LOW ||
3039 urb->dev->speed == USB_SPEED_FULL)
3040 urb->interval /= 8;
3041 }
3042 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3043}
3044
3045/*
3046 * The TD size is the number of bytes remaining in the TD (including this TRB),
3047 * right shifted by 10.
3048 * It must fit in bits 21:17, so it can't be bigger than 31.
3049 */
3050static u32 xhci_td_remainder(unsigned int remainder)
3051{
3052 u32 max = (1 << (21 - 17 + 1)) - 1;
3053
3054 if ((remainder >> 10) >= max)
3055 return max << 17;
3056 else
3057 return (remainder >> 10) << 17;
3058}
3059
3060/*
3061 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
3062 * the TD (*not* including this TRB).
3063 *
3064 * Total TD packet count = total_packet_count =
3065 * roundup(TD size in bytes / wMaxPacketSize)
3066 *
3067 * Packets transferred up to and including this TRB = packets_transferred =
3068 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3069 *
3070 * TD size = total_packet_count - packets_transferred
3071 *
3072 * It must fit in bits 21:17, so it can't be bigger than 31.
3073 */
3074
3075static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3076 unsigned int total_packet_count, struct urb *urb)
3077{
3078 int packets_transferred;
3079
3080 /* One TRB with a zero-length data packet. */
3081 if (running_total == 0 && trb_buff_len == 0)
3082 return 0;
3083
3084 /* All the TRB queueing functions don't count the current TRB in
3085 * running_total.
3086 */
3087 packets_transferred = (running_total + trb_buff_len) /
3088 usb_endpoint_maxp(&urb->ep->desc);
3089
3090 return xhci_td_remainder(total_packet_count - packets_transferred);
3091}
3092
3093static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3094 struct urb *urb, int slot_id, unsigned int ep_index)
3095{
3096 struct xhci_ring *ep_ring;
3097 unsigned int num_trbs;
3098 struct urb_priv *urb_priv;
3099 struct xhci_td *td;
3100 struct scatterlist *sg;
3101 int num_sgs;
3102 int trb_buff_len, this_sg_len, running_total;
3103 unsigned int total_packet_count;
3104 bool first_trb;
3105 u64 addr;
3106 bool more_trbs_coming;
3107
3108 struct xhci_generic_trb *start_trb;
3109 int start_cycle;
3110
3111 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3112 if (!ep_ring)
3113 return -EINVAL;
3114
3115 num_trbs = count_sg_trbs_needed(xhci, urb);
3116 num_sgs = urb->num_mapped_sgs;
3117 total_packet_count = roundup(urb->transfer_buffer_length,
3118 usb_endpoint_maxp(&urb->ep->desc));
3119
3120 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3121 ep_index, urb->stream_id,
3122 num_trbs, urb, 0, mem_flags);
3123 if (trb_buff_len < 0)
3124 return trb_buff_len;
3125
3126 urb_priv = urb->hcpriv;
3127 td = urb_priv->td[0];
3128
3129 /*
3130 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3131 * until we've finished creating all the other TRBs. The ring's cycle
3132 * state may change as we enqueue the other TRBs, so save it too.
3133 */
3134 start_trb = &ep_ring->enqueue->generic;
3135 start_cycle = ep_ring->cycle_state;
3136
3137 running_total = 0;
3138 /*
3139 * How much data is in the first TRB?
3140 *
3141 * There are three forces at work for TRB buffer pointers and lengths:
3142 * 1. We don't want to walk off the end of this sg-list entry buffer.
3143 * 2. The transfer length that the driver requested may be smaller than
3144 * the amount of memory allocated for this scatter-gather list.
3145 * 3. TRBs buffers can't cross 64KB boundaries.
3146 */
3147 sg = urb->sg;
3148 addr = (u64) sg_dma_address(sg);
3149 this_sg_len = sg_dma_len(sg);
3150 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3151 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3152 if (trb_buff_len > urb->transfer_buffer_length)
3153 trb_buff_len = urb->transfer_buffer_length;
3154
3155 first_trb = true;
3156 /* Queue the first TRB, even if it's zero-length */
3157 do {
3158 u32 field = 0;
3159 u32 length_field = 0;
3160 u32 remainder = 0;
3161
3162 /* Don't change the cycle bit of the first TRB until later */
3163 if (first_trb) {
3164 first_trb = false;
3165 if (start_cycle == 0)
3166 field |= 0x1;
3167 } else
3168 field |= ep_ring->cycle_state;
3169
3170 /* Chain all the TRBs together; clear the chain bit in the last
3171 * TRB to indicate it's the last TRB in the chain.
3172 */
3173 if (num_trbs > 1) {
3174 field |= TRB_CHAIN;
3175 } else {
3176 /* FIXME - add check for ZERO_PACKET flag before this */
3177 td->last_trb = ep_ring->enqueue;
3178 field |= TRB_IOC;
3179 }
3180
3181 /* Only set interrupt on short packet for IN endpoints */
3182 if (usb_urb_dir_in(urb))
3183 field |= TRB_ISP;
3184
3185 if (TRB_MAX_BUFF_SIZE -
3186 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3187 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3188 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3189 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3190 (unsigned int) addr + trb_buff_len);
3191 }
3192
3193 /* Set the TRB length, TD size, and interrupter fields. */
3194 if (xhci->hci_version < 0x100) {
3195 remainder = xhci_td_remainder(
3196 urb->transfer_buffer_length -
3197 running_total);
3198 } else {
3199 remainder = xhci_v1_0_td_remainder(running_total,
3200 trb_buff_len, total_packet_count, urb);
3201 }
3202 length_field = TRB_LEN(trb_buff_len) |
3203 remainder |
3204 TRB_INTR_TARGET(0);
3205
3206 if (num_trbs > 1)
3207 more_trbs_coming = true;
3208 else
3209 more_trbs_coming = false;
3210 queue_trb(xhci, ep_ring, more_trbs_coming,
3211 lower_32_bits(addr),
3212 upper_32_bits(addr),
3213 length_field,
3214 field | TRB_TYPE(TRB_NORMAL));
3215 --num_trbs;
3216 running_total += trb_buff_len;
3217
3218 /* Calculate length for next transfer --
3219 * Are we done queueing all the TRBs for this sg entry?
3220 */
3221 this_sg_len -= trb_buff_len;
3222 if (this_sg_len == 0) {
3223 --num_sgs;
3224 if (num_sgs == 0)
3225 break;
3226 sg = sg_next(sg);
3227 addr = (u64) sg_dma_address(sg);
3228 this_sg_len = sg_dma_len(sg);
3229 } else {
3230 addr += trb_buff_len;
3231 }
3232
3233 trb_buff_len = TRB_MAX_BUFF_SIZE -
3234 (addr & (TRB_MAX_BUFF_SIZE - 1));
3235 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3236 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3237 trb_buff_len =
3238 urb->transfer_buffer_length - running_total;
3239 } while (running_total < urb->transfer_buffer_length);
3240
3241 check_trb_math(urb, num_trbs, running_total);
3242 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3243 start_cycle, start_trb);
3244 return 0;
3245}
3246
3247/* This is very similar to what ehci-q.c qtd_fill() does */
3248int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3249 struct urb *urb, int slot_id, unsigned int ep_index)
3250{
3251 struct xhci_ring *ep_ring;
3252 struct urb_priv *urb_priv;
3253 struct xhci_td *td;
3254 int num_trbs;
3255 struct xhci_generic_trb *start_trb;
3256 bool first_trb;
3257 bool more_trbs_coming;
3258 int start_cycle;
3259 u32 field, length_field;
3260
3261 int running_total, trb_buff_len, ret;
3262 unsigned int total_packet_count;
3263 u64 addr;
3264
3265 if (urb->num_sgs)
3266 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3267
3268 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3269 if (!ep_ring)
3270 return -EINVAL;
3271
3272 num_trbs = 0;
3273 /* How much data is (potentially) left before the 64KB boundary? */
3274 running_total = TRB_MAX_BUFF_SIZE -
3275 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3276 running_total &= TRB_MAX_BUFF_SIZE - 1;
3277
3278 /* If there's some data on this 64KB chunk, or we have to send a
3279 * zero-length transfer, we need at least one TRB
3280 */
3281 if (running_total != 0 || urb->transfer_buffer_length == 0)
3282 num_trbs++;
3283 /* How many more 64KB chunks to transfer, how many more TRBs? */
3284 while (running_total < urb->transfer_buffer_length) {
3285 num_trbs++;
3286 running_total += TRB_MAX_BUFF_SIZE;
3287 }
3288 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3289
3290 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3291 ep_index, urb->stream_id,
3292 num_trbs, urb, 0, mem_flags);
3293 if (ret < 0)
3294 return ret;
3295
3296 urb_priv = urb->hcpriv;
3297 td = urb_priv->td[0];
3298
3299 /*
3300 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3301 * until we've finished creating all the other TRBs. The ring's cycle
3302 * state may change as we enqueue the other TRBs, so save it too.
3303 */
3304 start_trb = &ep_ring->enqueue->generic;
3305 start_cycle = ep_ring->cycle_state;
3306
3307 running_total = 0;
3308 total_packet_count = roundup(urb->transfer_buffer_length,
3309 usb_endpoint_maxp(&urb->ep->desc));
3310 /* How much data is in the first TRB? */
3311 addr = (u64) urb->transfer_dma;
3312 trb_buff_len = TRB_MAX_BUFF_SIZE -
3313 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3314 if (trb_buff_len > urb->transfer_buffer_length)
3315 trb_buff_len = urb->transfer_buffer_length;
3316
3317 first_trb = true;
3318
3319 /* Queue the first TRB, even if it's zero-length */
3320 do {
3321 u32 remainder = 0;
3322 field = 0;
3323
3324 /* Don't change the cycle bit of the first TRB until later */
3325 if (first_trb) {
3326 first_trb = false;
3327 if (start_cycle == 0)
3328 field |= 0x1;
3329 } else
3330 field |= ep_ring->cycle_state;
3331
3332 /* Chain all the TRBs together; clear the chain bit in the last
3333 * TRB to indicate it's the last TRB in the chain.
3334 */
3335 if (num_trbs > 1) {
3336 field |= TRB_CHAIN;
3337 } else {
3338 /* FIXME - add check for ZERO_PACKET flag before this */
3339 td->last_trb = ep_ring->enqueue;
3340 field |= TRB_IOC;
3341 }
3342
3343 /* Only set interrupt on short packet for IN endpoints */
3344 if (usb_urb_dir_in(urb))
3345 field |= TRB_ISP;
3346
3347 /* Set the TRB length, TD size, and interrupter fields. */
3348 if (xhci->hci_version < 0x100) {
3349 remainder = xhci_td_remainder(
3350 urb->transfer_buffer_length -
3351 running_total);
3352 } else {
3353 remainder = xhci_v1_0_td_remainder(running_total,
3354 trb_buff_len, total_packet_count, urb);
3355 }
3356 length_field = TRB_LEN(trb_buff_len) |
3357 remainder |
3358 TRB_INTR_TARGET(0);
3359
3360 if (num_trbs > 1)
3361 more_trbs_coming = true;
3362 else
3363 more_trbs_coming = false;
3364 queue_trb(xhci, ep_ring, more_trbs_coming,
3365 lower_32_bits(addr),
3366 upper_32_bits(addr),
3367 length_field,
3368 field | TRB_TYPE(TRB_NORMAL));
3369 --num_trbs;
3370 running_total += trb_buff_len;
3371
3372 /* Calculate length for next transfer */
3373 addr += trb_buff_len;
3374 trb_buff_len = urb->transfer_buffer_length - running_total;
3375 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3376 trb_buff_len = TRB_MAX_BUFF_SIZE;
3377 } while (running_total < urb->transfer_buffer_length);
3378
3379 check_trb_math(urb, num_trbs, running_total);
3380 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3381 start_cycle, start_trb);
3382 return 0;
3383}
3384
3385/* Caller must have locked xhci->lock */
3386int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3387 struct urb *urb, int slot_id, unsigned int ep_index)
3388{
3389 struct xhci_ring *ep_ring;
3390 int num_trbs;
3391 int ret;
3392 struct usb_ctrlrequest *setup;
3393 struct xhci_generic_trb *start_trb;
3394 int start_cycle;
3395 u32 field, length_field;
3396 struct urb_priv *urb_priv;
3397 struct xhci_td *td;
3398
3399 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3400 if (!ep_ring)
3401 return -EINVAL;
3402
3403 /*
3404 * Need to copy setup packet into setup TRB, so we can't use the setup
3405 * DMA address.
3406 */
3407 if (!urb->setup_packet)
3408 return -EINVAL;
3409
3410 /* 1 TRB for setup, 1 for status */
3411 num_trbs = 2;
3412 /*
3413 * Don't need to check if we need additional event data and normal TRBs,
3414 * since data in control transfers will never get bigger than 16MB
3415 * XXX: can we get a buffer that crosses 64KB boundaries?
3416 */
3417 if (urb->transfer_buffer_length > 0)
3418 num_trbs++;
3419 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3420 ep_index, urb->stream_id,
3421 num_trbs, urb, 0, mem_flags);
3422 if (ret < 0)
3423 return ret;
3424
3425 urb_priv = urb->hcpriv;
3426 td = urb_priv->td[0];
3427
3428 /*
3429 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3430 * until we've finished creating all the other TRBs. The ring's cycle
3431 * state may change as we enqueue the other TRBs, so save it too.
3432 */
3433 start_trb = &ep_ring->enqueue->generic;
3434 start_cycle = ep_ring->cycle_state;
3435
3436 /* Queue setup TRB - see section 6.4.1.2.1 */
3437 /* FIXME better way to translate setup_packet into two u32 fields? */
3438 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3439 field = 0;
3440 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3441 if (start_cycle == 0)
3442 field |= 0x1;
3443
3444 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3445 if (xhci->hci_version == 0x100) {
3446 if (urb->transfer_buffer_length > 0) {
3447 if (setup->bRequestType & USB_DIR_IN)
3448 field |= TRB_TX_TYPE(TRB_DATA_IN);
3449 else
3450 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3451 }
3452 }
3453
3454 queue_trb(xhci, ep_ring, true,
3455 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3456 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3457 TRB_LEN(8) | TRB_INTR_TARGET(0),
3458 /* Immediate data in pointer */
3459 field);
3460
3461 /* If there's data, queue data TRBs */
3462 /* Only set interrupt on short packet for IN endpoints */
3463 if (usb_urb_dir_in(urb))
3464 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3465 else
3466 field = TRB_TYPE(TRB_DATA);
3467
3468 length_field = TRB_LEN(urb->transfer_buffer_length) |
3469 xhci_td_remainder(urb->transfer_buffer_length) |
3470 TRB_INTR_TARGET(0);
3471 if (urb->transfer_buffer_length > 0) {
3472 if (setup->bRequestType & USB_DIR_IN)
3473 field |= TRB_DIR_IN;
3474 queue_trb(xhci, ep_ring, true,
3475 lower_32_bits(urb->transfer_dma),
3476 upper_32_bits(urb->transfer_dma),
3477 length_field,
3478 field | ep_ring->cycle_state);
3479 }
3480
3481 /* Save the DMA address of the last TRB in the TD */
3482 td->last_trb = ep_ring->enqueue;
3483
3484 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3485 /* If the device sent data, the status stage is an OUT transfer */
3486 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3487 field = 0;
3488 else
3489 field = TRB_DIR_IN;
3490 queue_trb(xhci, ep_ring, false,
3491 0,
3492 0,
3493 TRB_INTR_TARGET(0),
3494 /* Event on completion */
3495 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3496
3497 giveback_first_trb(xhci, slot_id, ep_index, 0,
3498 start_cycle, start_trb);
3499 return 0;
3500}
3501
3502static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3503 struct urb *urb, int i)
3504{
3505 int num_trbs = 0;
3506 u64 addr, td_len;
3507
3508 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3509 td_len = urb->iso_frame_desc[i].length;
3510
3511 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3512 TRB_MAX_BUFF_SIZE);
3513 if (num_trbs == 0)
3514 num_trbs++;
3515
3516 return num_trbs;
3517}
3518
3519/*
3520 * The transfer burst count field of the isochronous TRB defines the number of
3521 * bursts that are required to move all packets in this TD. Only SuperSpeed
3522 * devices can burst up to bMaxBurst number of packets per service interval.
3523 * This field is zero based, meaning a value of zero in the field means one
3524 * burst. Basically, for everything but SuperSpeed devices, this field will be
3525 * zero. Only xHCI 1.0 host controllers support this field.
3526 */
3527static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3528 struct usb_device *udev,
3529 struct urb *urb, unsigned int total_packet_count)
3530{
3531 unsigned int max_burst;
3532
3533 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3534 return 0;
3535
3536 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3537 return roundup(total_packet_count, max_burst + 1) - 1;
3538}
3539
3540/*
3541 * Returns the number of packets in the last "burst" of packets. This field is
3542 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3543 * the last burst packet count is equal to the total number of packets in the
3544 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3545 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3546 * contain 1 to (bMaxBurst + 1) packets.
3547 */
3548static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3549 struct usb_device *udev,
3550 struct urb *urb, unsigned int total_packet_count)
3551{
3552 unsigned int max_burst;
3553 unsigned int residue;
3554
3555 if (xhci->hci_version < 0x100)
3556 return 0;
3557
3558 switch (udev->speed) {
3559 case USB_SPEED_SUPER:
3560 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3561 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3562 residue = total_packet_count % (max_burst + 1);
3563 /* If residue is zero, the last burst contains (max_burst + 1)
3564 * number of packets, but the TLBPC field is zero-based.
3565 */
3566 if (residue == 0)
3567 return max_burst;
3568 return residue - 1;
3569 default:
3570 if (total_packet_count == 0)
3571 return 0;
3572 return total_packet_count - 1;
3573 }
3574}
3575
3576/* This is for isoc transfer */
3577static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3578 struct urb *urb, int slot_id, unsigned int ep_index)
3579{
3580 struct xhci_ring *ep_ring;
3581 struct urb_priv *urb_priv;
3582 struct xhci_td *td;
3583 int num_tds, trbs_per_td;
3584 struct xhci_generic_trb *start_trb;
3585 bool first_trb;
3586 int start_cycle;
3587 u32 field, length_field;
3588 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3589 u64 start_addr, addr;
3590 int i, j;
3591 bool more_trbs_coming;
3592
3593 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3594
3595 num_tds = urb->number_of_packets;
3596 if (num_tds < 1) {
3597 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3598 return -EINVAL;
3599 }
3600
3601 start_addr = (u64) urb->transfer_dma;
3602 start_trb = &ep_ring->enqueue->generic;
3603 start_cycle = ep_ring->cycle_state;
3604
3605 urb_priv = urb->hcpriv;
3606 /* Queue the first TRB, even if it's zero-length */
3607 for (i = 0; i < num_tds; i++) {
3608 unsigned int total_packet_count;
3609 unsigned int burst_count;
3610 unsigned int residue;
3611
3612 first_trb = true;
3613 running_total = 0;
3614 addr = start_addr + urb->iso_frame_desc[i].offset;
3615 td_len = urb->iso_frame_desc[i].length;
3616 td_remain_len = td_len;
3617 total_packet_count = roundup(td_len,
3618 usb_endpoint_maxp(&urb->ep->desc));
3619 /* A zero-length transfer still involves at least one packet. */
3620 if (total_packet_count == 0)
3621 total_packet_count++;
3622 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3623 total_packet_count);
3624 residue = xhci_get_last_burst_packet_count(xhci,
3625 urb->dev, urb, total_packet_count);
3626
3627 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3628
3629 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3630 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3631 if (ret < 0) {
3632 if (i == 0)
3633 return ret;
3634 goto cleanup;
3635 }
3636
3637 td = urb_priv->td[i];
3638 for (j = 0; j < trbs_per_td; j++) {
3639 u32 remainder = 0;
3640 field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3641
3642 if (first_trb) {
3643 /* Queue the isoc TRB */
3644 field |= TRB_TYPE(TRB_ISOC);
3645 /* Assume URB_ISO_ASAP is set */
3646 field |= TRB_SIA;
3647 if (i == 0) {
3648 if (start_cycle == 0)
3649 field |= 0x1;
3650 } else
3651 field |= ep_ring->cycle_state;
3652 first_trb = false;
3653 } else {
3654 /* Queue other normal TRBs */
3655 field |= TRB_TYPE(TRB_NORMAL);
3656 field |= ep_ring->cycle_state;
3657 }
3658
3659 /* Only set interrupt on short packet for IN EPs */
3660 if (usb_urb_dir_in(urb))
3661 field |= TRB_ISP;
3662
3663 /* Chain all the TRBs together; clear the chain bit in
3664 * the last TRB to indicate it's the last TRB in the
3665 * chain.
3666 */
3667 if (j < trbs_per_td - 1) {
3668 field |= TRB_CHAIN;
3669 more_trbs_coming = true;
3670 } else {
3671 td->last_trb = ep_ring->enqueue;
3672 field |= TRB_IOC;
3673 if (xhci->hci_version == 0x100 &&
3674 !(xhci->quirks &
3675 XHCI_AVOID_BEI)) {
3676 /* Set BEI bit except for the last td */
3677 if (i < num_tds - 1)
3678 field |= TRB_BEI;
3679 }
3680 more_trbs_coming = false;
3681 }
3682
3683 /* Calculate TRB length */
3684 trb_buff_len = TRB_MAX_BUFF_SIZE -
3685 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3686 if (trb_buff_len > td_remain_len)
3687 trb_buff_len = td_remain_len;
3688
3689 /* Set the TRB length, TD size, & interrupter fields. */
3690 if (xhci->hci_version < 0x100) {
3691 remainder = xhci_td_remainder(
3692 td_len - running_total);
3693 } else {
3694 remainder = xhci_v1_0_td_remainder(
3695 running_total, trb_buff_len,
3696 total_packet_count, urb);
3697 }
3698 length_field = TRB_LEN(trb_buff_len) |
3699 remainder |
3700 TRB_INTR_TARGET(0);
3701
3702 queue_trb(xhci, ep_ring, more_trbs_coming,
3703 lower_32_bits(addr),
3704 upper_32_bits(addr),
3705 length_field,
3706 field);
3707 running_total += trb_buff_len;
3708
3709 addr += trb_buff_len;
3710 td_remain_len -= trb_buff_len;
3711 }
3712
3713 /* Check TD length */
3714 if (running_total != td_len) {
3715 xhci_err(xhci, "ISOC TD length unmatch\n");
3716 ret = -EINVAL;
3717 goto cleanup;
3718 }
3719 }
3720
3721 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3722 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3723 usb_amd_quirk_pll_disable();
3724 }
3725 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3726
3727 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3728 start_cycle, start_trb);
3729 return 0;
3730cleanup:
3731 /* Clean up a partially enqueued isoc transfer. */
3732
3733 for (i--; i >= 0; i--)
3734 list_del_init(&urb_priv->td[i]->td_list);
3735
3736 /* Use the first TD as a temporary variable to turn the TDs we've queued
3737 * into No-ops with a software-owned cycle bit. That way the hardware
3738 * won't accidentally start executing bogus TDs when we partially
3739 * overwrite them. td->first_trb and td->start_seg are already set.
3740 */
3741 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3742 /* Every TRB except the first & last will have its cycle bit flipped. */
3743 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3744
3745 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3746 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3747 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3748 ep_ring->cycle_state = start_cycle;
3749 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3750 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3751 return ret;
3752}
3753
3754/*
3755 * Check transfer ring to guarantee there is enough room for the urb.
3756 * Update ISO URB start_frame and interval.
3757 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3758 * update the urb->start_frame by now.
3759 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3760 */
3761int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3762 struct urb *urb, int slot_id, unsigned int ep_index)
3763{
3764 struct xhci_virt_device *xdev;
3765 struct xhci_ring *ep_ring;
3766 struct xhci_ep_ctx *ep_ctx;
3767 int start_frame;
3768 int xhci_interval;
3769 int ep_interval;
3770 int num_tds, num_trbs, i;
3771 int ret;
3772
3773 xdev = xhci->devs[slot_id];
3774 ep_ring = xdev->eps[ep_index].ring;
3775 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3776
3777 num_trbs = 0;
3778 num_tds = urb->number_of_packets;
3779 for (i = 0; i < num_tds; i++)
3780 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3781
3782 /* Check the ring to guarantee there is enough room for the whole urb.
3783 * Do not insert any td of the urb to the ring if the check failed.
3784 */
3785 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3786 num_trbs, mem_flags);
3787 if (ret)
3788 return ret;
3789
3790 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3791 start_frame &= 0x3fff;
3792
3793 urb->start_frame = start_frame;
3794 if (urb->dev->speed == USB_SPEED_LOW ||
3795 urb->dev->speed == USB_SPEED_FULL)
3796 urb->start_frame >>= 3;
3797
3798 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3799 ep_interval = urb->interval;
3800 /* Convert to microframes */
3801 if (urb->dev->speed == USB_SPEED_LOW ||
3802 urb->dev->speed == USB_SPEED_FULL)
3803 ep_interval *= 8;
3804 /* FIXME change this to a warning and a suggestion to use the new API
3805 * to set the polling interval (once the API is added).
3806 */
3807 if (xhci_interval != ep_interval) {
3808 if (printk_ratelimit())
3809 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3810 " (%d microframe%s) than xHCI "
3811 "(%d microframe%s)\n",
3812 ep_interval,
3813 ep_interval == 1 ? "" : "s",
3814 xhci_interval,
3815 xhci_interval == 1 ? "" : "s");
3816 urb->interval = xhci_interval;
3817 /* Convert back to frames for LS/FS devices */
3818 if (urb->dev->speed == USB_SPEED_LOW ||
3819 urb->dev->speed == USB_SPEED_FULL)
3820 urb->interval /= 8;
3821 }
3822 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3823
3824 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3825}
3826
3827/**** Command Ring Operations ****/
3828
3829/* Generic function for queueing a command TRB on the command ring.
3830 * Check to make sure there's room on the command ring for one command TRB.
3831 * Also check that there's room reserved for commands that must not fail.
3832 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3833 * then only check for the number of reserved spots.
3834 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3835 * because the command event handler may want to resubmit a failed command.
3836 */
3837static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3838 u32 field3, u32 field4, bool command_must_succeed)
3839{
3840 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3841 int ret;
3842
3843 if (!command_must_succeed)
3844 reserved_trbs++;
3845
3846 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3847 reserved_trbs, GFP_ATOMIC);
3848 if (ret < 0) {
3849 xhci_err(xhci, "ERR: No room for command on command ring\n");
3850 if (command_must_succeed)
3851 xhci_err(xhci, "ERR: Reserved TRB counting for "
3852 "unfailable commands failed.\n");
3853 return ret;
3854 }
3855 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3856 field4 | xhci->cmd_ring->cycle_state);
3857 return 0;
3858}
3859
3860/* Queue a slot enable or disable request on the command ring */
3861int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3862{
3863 return queue_command(xhci, 0, 0, 0,
3864 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3865}
3866
3867/* Queue an address device command TRB */
3868int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3869 u32 slot_id)
3870{
3871 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3872 upper_32_bits(in_ctx_ptr), 0,
3873 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3874 false);
3875}
3876
3877int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3878 u32 field1, u32 field2, u32 field3, u32 field4)
3879{
3880 return queue_command(xhci, field1, field2, field3, field4, false);
3881}
3882
3883/* Queue a reset device command TRB */
3884int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3885{
3886 return queue_command(xhci, 0, 0, 0,
3887 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3888 false);
3889}
3890
3891/* Queue a configure endpoint command TRB */
3892int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3893 u32 slot_id, bool command_must_succeed)
3894{
3895 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3896 upper_32_bits(in_ctx_ptr), 0,
3897 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3898 command_must_succeed);
3899}
3900
3901/* Queue an evaluate context command TRB */
3902int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3903 u32 slot_id, bool command_must_succeed)
3904{
3905 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3906 upper_32_bits(in_ctx_ptr), 0,
3907 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3908 command_must_succeed);
3909}
3910
3911/*
3912 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3913 * activity on an endpoint that is about to be suspended.
3914 */
3915int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3916 unsigned int ep_index, int suspend)
3917{
3918 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3919 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3920 u32 type = TRB_TYPE(TRB_STOP_RING);
3921 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3922
3923 return queue_command(xhci, 0, 0, 0,
3924 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3925}
3926
3927/* Set Transfer Ring Dequeue Pointer command.
3928 * This should not be used for endpoints that have streams enabled.
3929 */
3930static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3931 unsigned int ep_index, unsigned int stream_id,
3932 struct xhci_segment *deq_seg,
3933 union xhci_trb *deq_ptr, u32 cycle_state)
3934{
3935 dma_addr_t addr;
3936 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3937 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3938 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3939 u32 type = TRB_TYPE(TRB_SET_DEQ);
3940 struct xhci_virt_ep *ep;
3941
3942 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3943 if (addr == 0) {
3944 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3945 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3946 deq_seg, deq_ptr);
3947 return 0;
3948 }
3949 ep = &xhci->devs[slot_id]->eps[ep_index];
3950 if ((ep->ep_state & SET_DEQ_PENDING)) {
3951 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3952 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3953 return 0;
3954 }
3955 ep->queued_deq_seg = deq_seg;
3956 ep->queued_deq_ptr = deq_ptr;
3957 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3958 upper_32_bits(addr), trb_stream_id,
3959 trb_slot_id | trb_ep_index | type, false);
3960}
3961
3962int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3963 unsigned int ep_index)
3964{
3965 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3966 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3967 u32 type = TRB_TYPE(TRB_RESET_EP);
3968
3969 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3970 false);
3971}