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1/**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/module.h>
40#include <linux/kernel.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/ioport.h>
47#include <linux/io.h>
48#include <linux/list.h>
49#include <linux/delay.h>
50#include <linux/dma-mapping.h>
51#include <linux/of.h>
52
53#include <linux/usb/ch9.h>
54#include <linux/usb/gadget.h>
55
56#include "core.h"
57#include "gadget.h"
58#include "io.h"
59
60#include "debug.h"
61
62static char *maximum_speed = "super";
63module_param(maximum_speed, charp, 0);
64MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
65
66/* -------------------------------------------------------------------------- */
67
68#define DWC3_DEVS_POSSIBLE 32
69
70static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE);
71
72int dwc3_get_device_id(void)
73{
74 int id;
75
76again:
77 id = find_first_zero_bit(dwc3_devs, DWC3_DEVS_POSSIBLE);
78 if (id < DWC3_DEVS_POSSIBLE) {
79 int old;
80
81 old = test_and_set_bit(id, dwc3_devs);
82 if (old)
83 goto again;
84 } else {
85 pr_err("dwc3: no space for new device\n");
86 id = -ENOMEM;
87 }
88
89 return id;
90}
91EXPORT_SYMBOL_GPL(dwc3_get_device_id);
92
93void dwc3_put_device_id(int id)
94{
95 int ret;
96
97 if (id < 0)
98 return;
99
100 ret = test_bit(id, dwc3_devs);
101 WARN(!ret, "dwc3: ID %d not in use\n", id);
102 clear_bit(id, dwc3_devs);
103}
104EXPORT_SYMBOL_GPL(dwc3_put_device_id);
105
106void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
107{
108 u32 reg;
109
110 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
111 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
112 reg |= DWC3_GCTL_PRTCAPDIR(mode);
113 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
114}
115
116/**
117 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
118 * @dwc: pointer to our context structure
119 */
120static void dwc3_core_soft_reset(struct dwc3 *dwc)
121{
122 u32 reg;
123
124 /* Before Resetting PHY, put Core in Reset */
125 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
126 reg |= DWC3_GCTL_CORESOFTRESET;
127 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
128
129 /* Assert USB3 PHY reset */
130 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
131 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
132 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
133
134 /* Assert USB2 PHY reset */
135 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
136 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
137 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
138
139 mdelay(100);
140
141 /* Clear USB3 PHY reset */
142 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
143 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
144 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
145
146 /* Clear USB2 PHY reset */
147 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
148 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
149 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
150
151 /* After PHYs are stable we can take Core out of reset state */
152 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
153 reg &= ~DWC3_GCTL_CORESOFTRESET;
154 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
155}
156
157/**
158 * dwc3_free_one_event_buffer - Frees one event buffer
159 * @dwc: Pointer to our controller context structure
160 * @evt: Pointer to event buffer to be freed
161 */
162static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
163 struct dwc3_event_buffer *evt)
164{
165 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
166 kfree(evt);
167}
168
169/**
170 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
171 * @dwc: Pointer to our controller context structure
172 * @length: size of the event buffer
173 *
174 * Returns a pointer to the allocated event buffer structure on success
175 * otherwise ERR_PTR(errno).
176 */
177static struct dwc3_event_buffer *__devinit
178dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
179{
180 struct dwc3_event_buffer *evt;
181
182 evt = kzalloc(sizeof(*evt), GFP_KERNEL);
183 if (!evt)
184 return ERR_PTR(-ENOMEM);
185
186 evt->dwc = dwc;
187 evt->length = length;
188 evt->buf = dma_alloc_coherent(dwc->dev, length,
189 &evt->dma, GFP_KERNEL);
190 if (!evt->buf) {
191 kfree(evt);
192 return ERR_PTR(-ENOMEM);
193 }
194
195 return evt;
196}
197
198/**
199 * dwc3_free_event_buffers - frees all allocated event buffers
200 * @dwc: Pointer to our controller context structure
201 */
202static void dwc3_free_event_buffers(struct dwc3 *dwc)
203{
204 struct dwc3_event_buffer *evt;
205 int i;
206
207 for (i = 0; i < dwc->num_event_buffers; i++) {
208 evt = dwc->ev_buffs[i];
209 if (evt)
210 dwc3_free_one_event_buffer(dwc, evt);
211 }
212
213 kfree(dwc->ev_buffs);
214}
215
216/**
217 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
218 * @dwc: pointer to our controller context structure
219 * @length: size of event buffer
220 *
221 * Returns 0 on success otherwise negative errno. In the error case, dwc
222 * may contain some buffers allocated but not all which were requested.
223 */
224static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
225{
226 int num;
227 int i;
228
229 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
230 dwc->num_event_buffers = num;
231
232 dwc->ev_buffs = kzalloc(sizeof(*dwc->ev_buffs) * num, GFP_KERNEL);
233 if (!dwc->ev_buffs) {
234 dev_err(dwc->dev, "can't allocate event buffers array\n");
235 return -ENOMEM;
236 }
237
238 for (i = 0; i < num; i++) {
239 struct dwc3_event_buffer *evt;
240
241 evt = dwc3_alloc_one_event_buffer(dwc, length);
242 if (IS_ERR(evt)) {
243 dev_err(dwc->dev, "can't allocate event buffer\n");
244 return PTR_ERR(evt);
245 }
246 dwc->ev_buffs[i] = evt;
247 }
248
249 return 0;
250}
251
252/**
253 * dwc3_event_buffers_setup - setup our allocated event buffers
254 * @dwc: pointer to our controller context structure
255 *
256 * Returns 0 on success otherwise negative errno.
257 */
258static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
259{
260 struct dwc3_event_buffer *evt;
261 int n;
262
263 for (n = 0; n < dwc->num_event_buffers; n++) {
264 evt = dwc->ev_buffs[n];
265 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
266 evt->buf, (unsigned long long) evt->dma,
267 evt->length);
268
269 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
270 lower_32_bits(evt->dma));
271 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
272 upper_32_bits(evt->dma));
273 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
274 evt->length & 0xffff);
275 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
276 }
277
278 return 0;
279}
280
281static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
282{
283 struct dwc3_event_buffer *evt;
284 int n;
285
286 for (n = 0; n < dwc->num_event_buffers; n++) {
287 evt = dwc->ev_buffs[n];
288 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
289 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
290 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
291 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
292 }
293}
294
295static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
296{
297 struct dwc3_hwparams *parms = &dwc->hwparams;
298
299 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
300 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
301 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
302 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
303 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
304 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
305 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
306 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
307 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
308}
309
310/**
311 * dwc3_core_init - Low-level initialization of DWC3 Core
312 * @dwc: Pointer to our controller context structure
313 *
314 * Returns 0 on success otherwise negative errno.
315 */
316static int __devinit dwc3_core_init(struct dwc3 *dwc)
317{
318 unsigned long timeout;
319 u32 reg;
320 int ret;
321
322 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
323 /* This should read as U3 followed by revision number */
324 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
325 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
326 ret = -ENODEV;
327 goto err0;
328 }
329 dwc->revision = reg;
330
331 dwc3_core_soft_reset(dwc);
332
333 /* issue device SoftReset too */
334 timeout = jiffies + msecs_to_jiffies(500);
335 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
336 do {
337 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
338 if (!(reg & DWC3_DCTL_CSFTRST))
339 break;
340
341 if (time_after(jiffies, timeout)) {
342 dev_err(dwc->dev, "Reset Timed Out\n");
343 ret = -ETIMEDOUT;
344 goto err0;
345 }
346
347 cpu_relax();
348 } while (true);
349
350 dwc3_cache_hwparams(dwc);
351
352 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
353 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
354 reg &= ~DWC3_GCTL_DISSCRAMBLE;
355
356 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
357 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
358 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
359 break;
360 default:
361 dev_dbg(dwc->dev, "No power optimization available\n");
362 }
363
364 /*
365 * WORKAROUND: DWC3 revisions <1.90a have a bug
366 * where the device can fail to connect at SuperSpeed
367 * and falls back to high-speed mode which causes
368 * the device to enter a Connect/Disconnect loop
369 */
370 if (dwc->revision < DWC3_REVISION_190A)
371 reg |= DWC3_GCTL_U2RSTECN;
372
373 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
374
375 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
376 if (ret) {
377 dev_err(dwc->dev, "failed to allocate event buffers\n");
378 ret = -ENOMEM;
379 goto err1;
380 }
381
382 ret = dwc3_event_buffers_setup(dwc);
383 if (ret) {
384 dev_err(dwc->dev, "failed to setup event buffers\n");
385 goto err1;
386 }
387
388 return 0;
389
390err1:
391 dwc3_free_event_buffers(dwc);
392
393err0:
394 return ret;
395}
396
397static void dwc3_core_exit(struct dwc3 *dwc)
398{
399 dwc3_event_buffers_cleanup(dwc);
400 dwc3_free_event_buffers(dwc);
401}
402
403#define DWC3_ALIGN_MASK (16 - 1)
404
405static int __devinit dwc3_probe(struct platform_device *pdev)
406{
407 struct device_node *node = pdev->dev.of_node;
408 struct resource *res;
409 struct dwc3 *dwc;
410 struct device *dev = &pdev->dev;
411
412 int ret = -ENOMEM;
413
414 void __iomem *regs;
415 void *mem;
416
417 u8 mode;
418
419 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
420 if (!mem) {
421 dev_err(dev, "not enough memory\n");
422 return -ENOMEM;
423 }
424 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
425 dwc->mem = mem;
426
427 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
428 if (!res) {
429 dev_err(dev, "missing IRQ\n");
430 return -ENODEV;
431 }
432 dwc->xhci_resources[1].start = res->start;
433 dwc->xhci_resources[1].end = res->end;
434 dwc->xhci_resources[1].flags = res->flags;
435 dwc->xhci_resources[1].name = res->name;
436
437 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
438 if (!res) {
439 dev_err(dev, "missing memory resource\n");
440 return -ENODEV;
441 }
442 dwc->xhci_resources[0].start = res->start;
443 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
444 DWC3_XHCI_REGS_END;
445 dwc->xhci_resources[0].flags = res->flags;
446 dwc->xhci_resources[0].name = res->name;
447
448 /*
449 * Request memory region but exclude xHCI regs,
450 * since it will be requested by the xhci-plat driver.
451 */
452 res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
453 resource_size(res) - DWC3_GLOBALS_REGS_START,
454 dev_name(dev));
455 if (!res) {
456 dev_err(dev, "can't request mem region\n");
457 return -ENOMEM;
458 }
459
460 regs = devm_ioremap(dev, res->start, resource_size(res));
461 if (!regs) {
462 dev_err(dev, "ioremap failed\n");
463 return -ENOMEM;
464 }
465
466 spin_lock_init(&dwc->lock);
467 platform_set_drvdata(pdev, dwc);
468
469 dwc->regs = regs;
470 dwc->regs_size = resource_size(res);
471 dwc->dev = dev;
472
473 if (!strncmp("super", maximum_speed, 5))
474 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
475 else if (!strncmp("high", maximum_speed, 4))
476 dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
477 else if (!strncmp("full", maximum_speed, 4))
478 dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
479 else if (!strncmp("low", maximum_speed, 3))
480 dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
481 else
482 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
483
484 if (of_get_property(node, "tx-fifo-resize", NULL))
485 dwc->needs_fifo_resize = true;
486
487 pm_runtime_enable(dev);
488 pm_runtime_get_sync(dev);
489 pm_runtime_forbid(dev);
490
491 ret = dwc3_core_init(dwc);
492 if (ret) {
493 dev_err(dev, "failed to initialize core\n");
494 return ret;
495 }
496
497 mode = DWC3_MODE(dwc->hwparams.hwparams0);
498
499 switch (mode) {
500 case DWC3_MODE_DEVICE:
501 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
502 ret = dwc3_gadget_init(dwc);
503 if (ret) {
504 dev_err(dev, "failed to initialize gadget\n");
505 goto err1;
506 }
507 break;
508 case DWC3_MODE_HOST:
509 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
510 ret = dwc3_host_init(dwc);
511 if (ret) {
512 dev_err(dev, "failed to initialize host\n");
513 goto err1;
514 }
515 break;
516 case DWC3_MODE_DRD:
517 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
518 ret = dwc3_host_init(dwc);
519 if (ret) {
520 dev_err(dev, "failed to initialize host\n");
521 goto err1;
522 }
523
524 ret = dwc3_gadget_init(dwc);
525 if (ret) {
526 dev_err(dev, "failed to initialize gadget\n");
527 goto err1;
528 }
529 break;
530 default:
531 dev_err(dev, "Unsupported mode of operation %d\n", mode);
532 goto err1;
533 }
534 dwc->mode = mode;
535
536 ret = dwc3_debugfs_init(dwc);
537 if (ret) {
538 dev_err(dev, "failed to initialize debugfs\n");
539 goto err2;
540 }
541
542 pm_runtime_allow(dev);
543
544 return 0;
545
546err2:
547 switch (mode) {
548 case DWC3_MODE_DEVICE:
549 dwc3_gadget_exit(dwc);
550 break;
551 case DWC3_MODE_HOST:
552 dwc3_host_exit(dwc);
553 break;
554 case DWC3_MODE_DRD:
555 dwc3_host_exit(dwc);
556 dwc3_gadget_exit(dwc);
557 break;
558 default:
559 /* do nothing */
560 break;
561 }
562
563err1:
564 dwc3_core_exit(dwc);
565
566 return ret;
567}
568
569static int __devexit dwc3_remove(struct platform_device *pdev)
570{
571 struct dwc3 *dwc = platform_get_drvdata(pdev);
572 struct resource *res;
573
574 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
575
576 pm_runtime_put(&pdev->dev);
577 pm_runtime_disable(&pdev->dev);
578
579 dwc3_debugfs_exit(dwc);
580
581 switch (dwc->mode) {
582 case DWC3_MODE_DEVICE:
583 dwc3_gadget_exit(dwc);
584 break;
585 case DWC3_MODE_HOST:
586 dwc3_host_exit(dwc);
587 break;
588 case DWC3_MODE_DRD:
589 dwc3_host_exit(dwc);
590 dwc3_gadget_exit(dwc);
591 break;
592 default:
593 /* do nothing */
594 break;
595 }
596
597 dwc3_core_exit(dwc);
598
599 return 0;
600}
601
602static struct platform_driver dwc3_driver = {
603 .probe = dwc3_probe,
604 .remove = __devexit_p(dwc3_remove),
605 .driver = {
606 .name = "dwc3",
607 },
608};
609
610module_platform_driver(dwc3_driver);
611
612MODULE_ALIAS("platform:dwc3");
613MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
614MODULE_LICENSE("Dual BSD/GPL");
615MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");