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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device, u16 caps);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
53
54/* from radeon_legacy_encoder.c */
55extern void
56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
58
59union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63};
64
65static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
67{
68 struct atom_context *ctx = rdev->mode_info.atom_context;
69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
73 uint16_t data_offset, size;
74 int i, num_indices;
75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
86 gpio = &i2c_info->asGPIO_Info[i];
87
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
91 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
101 /* some DCE3 boards have bad data for this entry */
102 if (ASIC_IS_DCE3(rdev)) {
103 if ((i == 4) &&
104 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
105 (gpio->sucI2cId.ucAccess == 0x94))
106 gpio->sucI2cId.ucAccess = 0x14;
107 }
108
109 if (gpio->sucI2cId.ucAccess == id) {
110 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
111 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
112 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
113 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
114 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
115 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
116 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
117 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
118 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
119 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
120 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
121 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
122 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
123 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
124 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
125 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
126
127 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
128 i2c.hw_capable = true;
129 else
130 i2c.hw_capable = false;
131
132 if (gpio->sucI2cId.ucAccess == 0xa0)
133 i2c.mm_i2c = true;
134 else
135 i2c.mm_i2c = false;
136
137 i2c.i2c_id = gpio->sucI2cId.ucAccess;
138
139 if (i2c.mask_clk_reg)
140 i2c.valid = true;
141 break;
142 }
143 }
144 }
145
146 return i2c;
147}
148
149void radeon_atombios_i2c_init(struct radeon_device *rdev)
150{
151 struct atom_context *ctx = rdev->mode_info.atom_context;
152 ATOM_GPIO_I2C_ASSIGMENT *gpio;
153 struct radeon_i2c_bus_rec i2c;
154 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
155 struct _ATOM_GPIO_I2C_INFO *i2c_info;
156 uint16_t data_offset, size;
157 int i, num_indices;
158 char stmp[32];
159
160 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
161
162 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
163 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
164
165 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
166 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
167
168 for (i = 0; i < num_indices; i++) {
169 gpio = &i2c_info->asGPIO_Info[i];
170 i2c.valid = false;
171
172 /* some evergreen boards have bad data for this entry */
173 if (ASIC_IS_DCE4(rdev)) {
174 if ((i == 7) &&
175 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
176 (gpio->sucI2cId.ucAccess == 0)) {
177 gpio->sucI2cId.ucAccess = 0x97;
178 gpio->ucDataMaskShift = 8;
179 gpio->ucDataEnShift = 8;
180 gpio->ucDataY_Shift = 8;
181 gpio->ucDataA_Shift = 8;
182 }
183 }
184
185 /* some DCE3 boards have bad data for this entry */
186 if (ASIC_IS_DCE3(rdev)) {
187 if ((i == 4) &&
188 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
189 (gpio->sucI2cId.ucAccess == 0x94))
190 gpio->sucI2cId.ucAccess = 0x14;
191 }
192
193 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
194 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
195 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
196 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
197 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
198 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
199 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
200 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
201 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
202 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
203 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
204 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
205 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
206 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
207 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
208 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
209
210 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
211 i2c.hw_capable = true;
212 else
213 i2c.hw_capable = false;
214
215 if (gpio->sucI2cId.ucAccess == 0xa0)
216 i2c.mm_i2c = true;
217 else
218 i2c.mm_i2c = false;
219
220 i2c.i2c_id = gpio->sucI2cId.ucAccess;
221
222 if (i2c.mask_clk_reg) {
223 i2c.valid = true;
224 sprintf(stmp, "0x%x", i2c.i2c_id);
225 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
226 }
227 }
228 }
229}
230
231static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
232 u8 id)
233{
234 struct atom_context *ctx = rdev->mode_info.atom_context;
235 struct radeon_gpio_rec gpio;
236 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
237 struct _ATOM_GPIO_PIN_LUT *gpio_info;
238 ATOM_GPIO_PIN_ASSIGNMENT *pin;
239 u16 data_offset, size;
240 int i, num_indices;
241
242 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
243 gpio.valid = false;
244
245 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
246 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
247
248 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
249 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
250
251 for (i = 0; i < num_indices; i++) {
252 pin = &gpio_info->asGPIO_Pin[i];
253 if (id == pin->ucGPIO_ID) {
254 gpio.id = pin->ucGPIO_ID;
255 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
256 gpio.mask = (1 << pin->ucGpioPinBitShift);
257 gpio.valid = true;
258 break;
259 }
260 }
261 }
262
263 return gpio;
264}
265
266static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
267 struct radeon_gpio_rec *gpio)
268{
269 struct radeon_hpd hpd;
270 u32 reg;
271
272 memset(&hpd, 0, sizeof(struct radeon_hpd));
273
274 if (ASIC_IS_DCE4(rdev))
275 reg = EVERGREEN_DC_GPIO_HPD_A;
276 else
277 reg = AVIVO_DC_GPIO_HPD_A;
278
279 hpd.gpio = *gpio;
280 if (gpio->reg == reg) {
281 switch(gpio->mask) {
282 case (1 << 0):
283 hpd.hpd = RADEON_HPD_1;
284 break;
285 case (1 << 8):
286 hpd.hpd = RADEON_HPD_2;
287 break;
288 case (1 << 16):
289 hpd.hpd = RADEON_HPD_3;
290 break;
291 case (1 << 24):
292 hpd.hpd = RADEON_HPD_4;
293 break;
294 case (1 << 26):
295 hpd.hpd = RADEON_HPD_5;
296 break;
297 case (1 << 28):
298 hpd.hpd = RADEON_HPD_6;
299 break;
300 default:
301 hpd.hpd = RADEON_HPD_NONE;
302 break;
303 }
304 } else
305 hpd.hpd = RADEON_HPD_NONE;
306 return hpd;
307}
308
309static bool radeon_atom_apply_quirks(struct drm_device *dev,
310 uint32_t supported_device,
311 int *connector_type,
312 struct radeon_i2c_bus_rec *i2c_bus,
313 uint16_t *line_mux,
314 struct radeon_hpd *hpd)
315{
316
317 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
318 if ((dev->pdev->device == 0x791e) &&
319 (dev->pdev->subsystem_vendor == 0x1043) &&
320 (dev->pdev->subsystem_device == 0x826d)) {
321 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
322 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
323 *connector_type = DRM_MODE_CONNECTOR_DVID;
324 }
325
326 /* Asrock RS600 board lists the DVI port as HDMI */
327 if ((dev->pdev->device == 0x7941) &&
328 (dev->pdev->subsystem_vendor == 0x1849) &&
329 (dev->pdev->subsystem_device == 0x7941)) {
330 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
331 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
332 *connector_type = DRM_MODE_CONNECTOR_DVID;
333 }
334
335 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
336 if ((dev->pdev->device == 0x796e) &&
337 (dev->pdev->subsystem_vendor == 0x1462) &&
338 (dev->pdev->subsystem_device == 0x7302)) {
339 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
340 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
341 return false;
342 }
343
344 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
345 if ((dev->pdev->device == 0x7941) &&
346 (dev->pdev->subsystem_vendor == 0x147b) &&
347 (dev->pdev->subsystem_device == 0x2412)) {
348 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
349 return false;
350 }
351
352 /* Falcon NW laptop lists vga ddc line for LVDS */
353 if ((dev->pdev->device == 0x5653) &&
354 (dev->pdev->subsystem_vendor == 0x1462) &&
355 (dev->pdev->subsystem_device == 0x0291)) {
356 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
357 i2c_bus->valid = false;
358 *line_mux = 53;
359 }
360 }
361
362 /* HIS X1300 is DVI+VGA, not DVI+DVI */
363 if ((dev->pdev->device == 0x7146) &&
364 (dev->pdev->subsystem_vendor == 0x17af) &&
365 (dev->pdev->subsystem_device == 0x2058)) {
366 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
367 return false;
368 }
369
370 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
371 if ((dev->pdev->device == 0x7142) &&
372 (dev->pdev->subsystem_vendor == 0x1458) &&
373 (dev->pdev->subsystem_device == 0x2134)) {
374 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
375 return false;
376 }
377
378
379 /* Funky macbooks */
380 if ((dev->pdev->device == 0x71C5) &&
381 (dev->pdev->subsystem_vendor == 0x106b) &&
382 (dev->pdev->subsystem_device == 0x0080)) {
383 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
384 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
385 return false;
386 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
387 *line_mux = 0x90;
388 }
389
390 /* mac rv630, rv730, others */
391 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
392 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
393 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
394 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
395 }
396
397 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
398 if ((dev->pdev->device == 0x9598) &&
399 (dev->pdev->subsystem_vendor == 0x1043) &&
400 (dev->pdev->subsystem_device == 0x01da)) {
401 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
402 *connector_type = DRM_MODE_CONNECTOR_DVII;
403 }
404 }
405
406 /* ASUS HD 3600 board lists the DVI port as HDMI */
407 if ((dev->pdev->device == 0x9598) &&
408 (dev->pdev->subsystem_vendor == 0x1043) &&
409 (dev->pdev->subsystem_device == 0x01e4)) {
410 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
411 *connector_type = DRM_MODE_CONNECTOR_DVII;
412 }
413 }
414
415 /* ASUS HD 3450 board lists the DVI port as HDMI */
416 if ((dev->pdev->device == 0x95C5) &&
417 (dev->pdev->subsystem_vendor == 0x1043) &&
418 (dev->pdev->subsystem_device == 0x01e2)) {
419 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
420 *connector_type = DRM_MODE_CONNECTOR_DVII;
421 }
422 }
423
424 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
425 * HDMI + VGA reporting as HDMI
426 */
427 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
428 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
429 *connector_type = DRM_MODE_CONNECTOR_VGA;
430 *line_mux = 0;
431 }
432 }
433
434 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
435 * on the laptop and a DVI port on the docking station and
436 * both share the same encoder, hpd pin, and ddc line.
437 * So while the bios table is technically correct,
438 * we drop the DVI port here since xrandr has no concept of
439 * encoders and will try and drive both connectors
440 * with different crtcs which isn't possible on the hardware
441 * side and leaves no crtcs for LVDS or VGA.
442 */
443 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
444 (dev->pdev->subsystem_vendor == 0x1025) &&
445 (dev->pdev->subsystem_device == 0x013c)) {
446 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
447 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
448 /* actually it's a DVI-D port not DVI-I */
449 *connector_type = DRM_MODE_CONNECTOR_DVID;
450 return false;
451 }
452 }
453
454 /* XFX Pine Group device rv730 reports no VGA DDC lines
455 * even though they are wired up to record 0x93
456 */
457 if ((dev->pdev->device == 0x9498) &&
458 (dev->pdev->subsystem_vendor == 0x1682) &&
459 (dev->pdev->subsystem_device == 0x2452)) {
460 struct radeon_device *rdev = dev->dev_private;
461 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
462 }
463 return true;
464}
465
466const int supported_devices_connector_convert[] = {
467 DRM_MODE_CONNECTOR_Unknown,
468 DRM_MODE_CONNECTOR_VGA,
469 DRM_MODE_CONNECTOR_DVII,
470 DRM_MODE_CONNECTOR_DVID,
471 DRM_MODE_CONNECTOR_DVIA,
472 DRM_MODE_CONNECTOR_SVIDEO,
473 DRM_MODE_CONNECTOR_Composite,
474 DRM_MODE_CONNECTOR_LVDS,
475 DRM_MODE_CONNECTOR_Unknown,
476 DRM_MODE_CONNECTOR_Unknown,
477 DRM_MODE_CONNECTOR_HDMIA,
478 DRM_MODE_CONNECTOR_HDMIB,
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_Unknown,
481 DRM_MODE_CONNECTOR_9PinDIN,
482 DRM_MODE_CONNECTOR_DisplayPort
483};
484
485const uint16_t supported_devices_connector_object_id_convert[] = {
486 CONNECTOR_OBJECT_ID_NONE,
487 CONNECTOR_OBJECT_ID_VGA,
488 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
489 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
490 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
491 CONNECTOR_OBJECT_ID_COMPOSITE,
492 CONNECTOR_OBJECT_ID_SVIDEO,
493 CONNECTOR_OBJECT_ID_LVDS,
494 CONNECTOR_OBJECT_ID_9PIN_DIN,
495 CONNECTOR_OBJECT_ID_9PIN_DIN,
496 CONNECTOR_OBJECT_ID_DISPLAYPORT,
497 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
498 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
499 CONNECTOR_OBJECT_ID_SVIDEO
500};
501
502const int object_connector_convert[] = {
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_DVII,
505 DRM_MODE_CONNECTOR_DVII,
506 DRM_MODE_CONNECTOR_DVID,
507 DRM_MODE_CONNECTOR_DVID,
508 DRM_MODE_CONNECTOR_VGA,
509 DRM_MODE_CONNECTOR_Composite,
510 DRM_MODE_CONNECTOR_SVIDEO,
511 DRM_MODE_CONNECTOR_Unknown,
512 DRM_MODE_CONNECTOR_Unknown,
513 DRM_MODE_CONNECTOR_9PinDIN,
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_HDMIA,
516 DRM_MODE_CONNECTOR_HDMIB,
517 DRM_MODE_CONNECTOR_LVDS,
518 DRM_MODE_CONNECTOR_9PinDIN,
519 DRM_MODE_CONNECTOR_Unknown,
520 DRM_MODE_CONNECTOR_Unknown,
521 DRM_MODE_CONNECTOR_Unknown,
522 DRM_MODE_CONNECTOR_DisplayPort,
523 DRM_MODE_CONNECTOR_eDP,
524 DRM_MODE_CONNECTOR_Unknown
525};
526
527bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
528{
529 struct radeon_device *rdev = dev->dev_private;
530 struct radeon_mode_info *mode_info = &rdev->mode_info;
531 struct atom_context *ctx = mode_info->atom_context;
532 int index = GetIndexIntoMasterTable(DATA, Object_Header);
533 u16 size, data_offset;
534 u8 frev, crev;
535 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
536 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
537 ATOM_OBJECT_TABLE *router_obj;
538 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
539 ATOM_OBJECT_HEADER *obj_header;
540 int i, j, k, path_size, device_support;
541 int connector_type;
542 u16 igp_lane_info, conn_id, connector_object_id;
543 struct radeon_i2c_bus_rec ddc_bus;
544 struct radeon_router router;
545 struct radeon_gpio_rec gpio;
546 struct radeon_hpd hpd;
547
548 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
549 return false;
550
551 if (crev < 2)
552 return false;
553
554 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
555 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
556 (ctx->bios + data_offset +
557 le16_to_cpu(obj_header->usDisplayPathTableOffset));
558 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
559 (ctx->bios + data_offset +
560 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
561 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
562 (ctx->bios + data_offset +
563 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
564 router_obj = (ATOM_OBJECT_TABLE *)
565 (ctx->bios + data_offset +
566 le16_to_cpu(obj_header->usRouterObjectTableOffset));
567 device_support = le16_to_cpu(obj_header->usDeviceSupport);
568
569 path_size = 0;
570 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
571 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
572 ATOM_DISPLAY_OBJECT_PATH *path;
573 addr += path_size;
574 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
575 path_size += le16_to_cpu(path->usSize);
576
577 if (device_support & le16_to_cpu(path->usDeviceTag)) {
578 uint8_t con_obj_id, con_obj_num, con_obj_type;
579
580 con_obj_id =
581 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
582 >> OBJECT_ID_SHIFT;
583 con_obj_num =
584 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
585 >> ENUM_ID_SHIFT;
586 con_obj_type =
587 (le16_to_cpu(path->usConnObjectId) &
588 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
589
590 /* TODO CV support */
591 if (le16_to_cpu(path->usDeviceTag) ==
592 ATOM_DEVICE_CV_SUPPORT)
593 continue;
594
595 /* IGP chips */
596 if ((rdev->flags & RADEON_IS_IGP) &&
597 (con_obj_id ==
598 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
599 uint16_t igp_offset = 0;
600 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
601
602 index =
603 GetIndexIntoMasterTable(DATA,
604 IntegratedSystemInfo);
605
606 if (atom_parse_data_header(ctx, index, &size, &frev,
607 &crev, &igp_offset)) {
608
609 if (crev >= 2) {
610 igp_obj =
611 (ATOM_INTEGRATED_SYSTEM_INFO_V2
612 *) (ctx->bios + igp_offset);
613
614 if (igp_obj) {
615 uint32_t slot_config, ct;
616
617 if (con_obj_num == 1)
618 slot_config =
619 igp_obj->
620 ulDDISlot1Config;
621 else
622 slot_config =
623 igp_obj->
624 ulDDISlot2Config;
625
626 ct = (slot_config >> 16) & 0xff;
627 connector_type =
628 object_connector_convert
629 [ct];
630 connector_object_id = ct;
631 igp_lane_info =
632 slot_config & 0xffff;
633 } else
634 continue;
635 } else
636 continue;
637 } else {
638 igp_lane_info = 0;
639 connector_type =
640 object_connector_convert[con_obj_id];
641 connector_object_id = con_obj_id;
642 }
643 } else {
644 igp_lane_info = 0;
645 connector_type =
646 object_connector_convert[con_obj_id];
647 connector_object_id = con_obj_id;
648 }
649
650 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
651 continue;
652
653 router.ddc_valid = false;
654 router.cd_valid = false;
655 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
656 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
657
658 grph_obj_id =
659 (le16_to_cpu(path->usGraphicObjIds[j]) &
660 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
661 grph_obj_num =
662 (le16_to_cpu(path->usGraphicObjIds[j]) &
663 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
664 grph_obj_type =
665 (le16_to_cpu(path->usGraphicObjIds[j]) &
666 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
667
668 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
669 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
670 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
671 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
672 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
673 (ctx->bios + data_offset +
674 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
675 ATOM_ENCODER_CAP_RECORD *cap_record;
676 u16 caps = 0;
677
678 while (record->ucRecordSize > 0 &&
679 record->ucRecordType > 0 &&
680 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
681 switch (record->ucRecordType) {
682 case ATOM_ENCODER_CAP_RECORD_TYPE:
683 cap_record =(ATOM_ENCODER_CAP_RECORD *)
684 record;
685 caps = le16_to_cpu(cap_record->usEncoderCap);
686 break;
687 }
688 record = (ATOM_COMMON_RECORD_HEADER *)
689 ((char *)record + record->ucRecordSize);
690 }
691 radeon_add_atom_encoder(dev,
692 encoder_obj,
693 le16_to_cpu
694 (path->
695 usDeviceTag),
696 caps);
697 }
698 }
699 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
700 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
701 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
702 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
703 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
704 (ctx->bios + data_offset +
705 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
706 ATOM_I2C_RECORD *i2c_record;
707 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
708 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
709 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
710 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
711 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
712 (ctx->bios + data_offset +
713 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
714 int enum_id;
715
716 router.router_id = router_obj_id;
717 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
718 enum_id++) {
719 if (le16_to_cpu(path->usConnObjectId) ==
720 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
721 break;
722 }
723
724 while (record->ucRecordSize > 0 &&
725 record->ucRecordType > 0 &&
726 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
727 switch (record->ucRecordType) {
728 case ATOM_I2C_RECORD_TYPE:
729 i2c_record =
730 (ATOM_I2C_RECORD *)
731 record;
732 i2c_config =
733 (ATOM_I2C_ID_CONFIG_ACCESS *)
734 &i2c_record->sucI2cId;
735 router.i2c_info =
736 radeon_lookup_i2c_gpio(rdev,
737 i2c_config->
738 ucAccess);
739 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
740 break;
741 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
742 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
743 record;
744 router.ddc_valid = true;
745 router.ddc_mux_type = ddc_path->ucMuxType;
746 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
747 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
748 break;
749 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
750 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
751 record;
752 router.cd_valid = true;
753 router.cd_mux_type = cd_path->ucMuxType;
754 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
755 router.cd_mux_state = cd_path->ucMuxState[enum_id];
756 break;
757 }
758 record = (ATOM_COMMON_RECORD_HEADER *)
759 ((char *)record + record->ucRecordSize);
760 }
761 }
762 }
763 }
764 }
765
766 /* look up gpio for ddc, hpd */
767 ddc_bus.valid = false;
768 hpd.hpd = RADEON_HPD_NONE;
769 if ((le16_to_cpu(path->usDeviceTag) &
770 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
772 if (le16_to_cpu(path->usConnObjectId) ==
773 le16_to_cpu(con_obj->asObjects[j].
774 usObjectID)) {
775 ATOM_COMMON_RECORD_HEADER
776 *record =
777 (ATOM_COMMON_RECORD_HEADER
778 *)
779 (ctx->bios + data_offset +
780 le16_to_cpu(con_obj->
781 asObjects[j].
782 usRecordOffset));
783 ATOM_I2C_RECORD *i2c_record;
784 ATOM_HPD_INT_RECORD *hpd_record;
785 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
786
787 while (record->ucRecordSize > 0 &&
788 record->ucRecordType > 0 &&
789 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
790 switch (record->ucRecordType) {
791 case ATOM_I2C_RECORD_TYPE:
792 i2c_record =
793 (ATOM_I2C_RECORD *)
794 record;
795 i2c_config =
796 (ATOM_I2C_ID_CONFIG_ACCESS *)
797 &i2c_record->sucI2cId;
798 ddc_bus = radeon_lookup_i2c_gpio(rdev,
799 i2c_config->
800 ucAccess);
801 break;
802 case ATOM_HPD_INT_RECORD_TYPE:
803 hpd_record =
804 (ATOM_HPD_INT_RECORD *)
805 record;
806 gpio = radeon_lookup_gpio(rdev,
807 hpd_record->ucHPDIntGPIOID);
808 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
809 hpd.plugged_state = hpd_record->ucPlugged_PinState;
810 break;
811 }
812 record =
813 (ATOM_COMMON_RECORD_HEADER
814 *) ((char *)record
815 +
816 record->
817 ucRecordSize);
818 }
819 break;
820 }
821 }
822 }
823
824 /* needed for aux chan transactions */
825 ddc_bus.hpd = hpd.hpd;
826
827 conn_id = le16_to_cpu(path->usConnObjectId);
828
829 if (!radeon_atom_apply_quirks
830 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
831 &ddc_bus, &conn_id, &hpd))
832 continue;
833
834 radeon_add_atom_connector(dev,
835 conn_id,
836 le16_to_cpu(path->
837 usDeviceTag),
838 connector_type, &ddc_bus,
839 igp_lane_info,
840 connector_object_id,
841 &hpd,
842 &router);
843
844 }
845 }
846
847 radeon_link_encoder_connector(dev);
848
849 return true;
850}
851
852static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
853 int connector_type,
854 uint16_t devices)
855{
856 struct radeon_device *rdev = dev->dev_private;
857
858 if (rdev->flags & RADEON_IS_IGP) {
859 return supported_devices_connector_object_id_convert
860 [connector_type];
861 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
862 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
863 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
864 struct radeon_mode_info *mode_info = &rdev->mode_info;
865 struct atom_context *ctx = mode_info->atom_context;
866 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
867 uint16_t size, data_offset;
868 uint8_t frev, crev;
869 ATOM_XTMDS_INFO *xtmds;
870
871 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
872 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
873
874 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
875 if (connector_type == DRM_MODE_CONNECTOR_DVII)
876 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
877 else
878 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
879 } else {
880 if (connector_type == DRM_MODE_CONNECTOR_DVII)
881 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
882 else
883 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
884 }
885 } else
886 return supported_devices_connector_object_id_convert
887 [connector_type];
888 } else {
889 return supported_devices_connector_object_id_convert
890 [connector_type];
891 }
892}
893
894struct bios_connector {
895 bool valid;
896 uint16_t line_mux;
897 uint16_t devices;
898 int connector_type;
899 struct radeon_i2c_bus_rec ddc_bus;
900 struct radeon_hpd hpd;
901};
902
903bool radeon_get_atom_connector_info_from_supported_devices_table(struct
904 drm_device
905 *dev)
906{
907 struct radeon_device *rdev = dev->dev_private;
908 struct radeon_mode_info *mode_info = &rdev->mode_info;
909 struct atom_context *ctx = mode_info->atom_context;
910 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
911 uint16_t size, data_offset;
912 uint8_t frev, crev;
913 uint16_t device_support;
914 uint8_t dac;
915 union atom_supported_devices *supported_devices;
916 int i, j, max_device;
917 struct bios_connector *bios_connectors;
918 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
919 struct radeon_router router;
920
921 router.ddc_valid = false;
922 router.cd_valid = false;
923
924 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
925 if (!bios_connectors)
926 return false;
927
928 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
929 &data_offset)) {
930 kfree(bios_connectors);
931 return false;
932 }
933
934 supported_devices =
935 (union atom_supported_devices *)(ctx->bios + data_offset);
936
937 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
938
939 if (frev > 1)
940 max_device = ATOM_MAX_SUPPORTED_DEVICE;
941 else
942 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
943
944 for (i = 0; i < max_device; i++) {
945 ATOM_CONNECTOR_INFO_I2C ci =
946 supported_devices->info.asConnInfo[i];
947
948 bios_connectors[i].valid = false;
949
950 if (!(device_support & (1 << i))) {
951 continue;
952 }
953
954 if (i == ATOM_DEVICE_CV_INDEX) {
955 DRM_DEBUG_KMS("Skipping Component Video\n");
956 continue;
957 }
958
959 bios_connectors[i].connector_type =
960 supported_devices_connector_convert[ci.sucConnectorInfo.
961 sbfAccess.
962 bfConnectorType];
963
964 if (bios_connectors[i].connector_type ==
965 DRM_MODE_CONNECTOR_Unknown)
966 continue;
967
968 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
969
970 bios_connectors[i].line_mux =
971 ci.sucI2cId.ucAccess;
972
973 /* give tv unique connector ids */
974 if (i == ATOM_DEVICE_TV1_INDEX) {
975 bios_connectors[i].ddc_bus.valid = false;
976 bios_connectors[i].line_mux = 50;
977 } else if (i == ATOM_DEVICE_TV2_INDEX) {
978 bios_connectors[i].ddc_bus.valid = false;
979 bios_connectors[i].line_mux = 51;
980 } else if (i == ATOM_DEVICE_CV_INDEX) {
981 bios_connectors[i].ddc_bus.valid = false;
982 bios_connectors[i].line_mux = 52;
983 } else
984 bios_connectors[i].ddc_bus =
985 radeon_lookup_i2c_gpio(rdev,
986 bios_connectors[i].line_mux);
987
988 if ((crev > 1) && (frev > 1)) {
989 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
990 switch (isb) {
991 case 0x4:
992 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
993 break;
994 case 0xa:
995 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
996 break;
997 default:
998 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
999 break;
1000 }
1001 } else {
1002 if (i == ATOM_DEVICE_DFP1_INDEX)
1003 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1004 else if (i == ATOM_DEVICE_DFP2_INDEX)
1005 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1006 else
1007 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1008 }
1009
1010 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1011 * shared with a DVI port, we'll pick up the DVI connector when we
1012 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1013 */
1014 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1015 bios_connectors[i].connector_type =
1016 DRM_MODE_CONNECTOR_VGA;
1017
1018 if (!radeon_atom_apply_quirks
1019 (dev, (1 << i), &bios_connectors[i].connector_type,
1020 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1021 &bios_connectors[i].hpd))
1022 continue;
1023
1024 bios_connectors[i].valid = true;
1025 bios_connectors[i].devices = (1 << i);
1026
1027 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1028 radeon_add_atom_encoder(dev,
1029 radeon_get_encoder_enum(dev,
1030 (1 << i),
1031 dac),
1032 (1 << i),
1033 0);
1034 else
1035 radeon_add_legacy_encoder(dev,
1036 radeon_get_encoder_enum(dev,
1037 (1 << i),
1038 dac),
1039 (1 << i));
1040 }
1041
1042 /* combine shared connectors */
1043 for (i = 0; i < max_device; i++) {
1044 if (bios_connectors[i].valid) {
1045 for (j = 0; j < max_device; j++) {
1046 if (bios_connectors[j].valid && (i != j)) {
1047 if (bios_connectors[i].line_mux ==
1048 bios_connectors[j].line_mux) {
1049 /* make sure not to combine LVDS */
1050 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1051 bios_connectors[i].line_mux = 53;
1052 bios_connectors[i].ddc_bus.valid = false;
1053 continue;
1054 }
1055 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1056 bios_connectors[j].line_mux = 53;
1057 bios_connectors[j].ddc_bus.valid = false;
1058 continue;
1059 }
1060 /* combine analog and digital for DVI-I */
1061 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1062 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1063 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1064 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1065 bios_connectors[i].devices |=
1066 bios_connectors[j].devices;
1067 bios_connectors[i].connector_type =
1068 DRM_MODE_CONNECTOR_DVII;
1069 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1070 bios_connectors[i].hpd =
1071 bios_connectors[j].hpd;
1072 bios_connectors[j].valid = false;
1073 }
1074 }
1075 }
1076 }
1077 }
1078 }
1079
1080 /* add the connectors */
1081 for (i = 0; i < max_device; i++) {
1082 if (bios_connectors[i].valid) {
1083 uint16_t connector_object_id =
1084 atombios_get_connector_object_id(dev,
1085 bios_connectors[i].connector_type,
1086 bios_connectors[i].devices);
1087 radeon_add_atom_connector(dev,
1088 bios_connectors[i].line_mux,
1089 bios_connectors[i].devices,
1090 bios_connectors[i].
1091 connector_type,
1092 &bios_connectors[i].ddc_bus,
1093 0,
1094 connector_object_id,
1095 &bios_connectors[i].hpd,
1096 &router);
1097 }
1098 }
1099
1100 radeon_link_encoder_connector(dev);
1101
1102 kfree(bios_connectors);
1103 return true;
1104}
1105
1106union firmware_info {
1107 ATOM_FIRMWARE_INFO info;
1108 ATOM_FIRMWARE_INFO_V1_2 info_12;
1109 ATOM_FIRMWARE_INFO_V1_3 info_13;
1110 ATOM_FIRMWARE_INFO_V1_4 info_14;
1111 ATOM_FIRMWARE_INFO_V2_1 info_21;
1112 ATOM_FIRMWARE_INFO_V2_2 info_22;
1113};
1114
1115bool radeon_atom_get_clock_info(struct drm_device *dev)
1116{
1117 struct radeon_device *rdev = dev->dev_private;
1118 struct radeon_mode_info *mode_info = &rdev->mode_info;
1119 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1120 union firmware_info *firmware_info;
1121 uint8_t frev, crev;
1122 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1123 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1124 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1125 struct radeon_pll *spll = &rdev->clock.spll;
1126 struct radeon_pll *mpll = &rdev->clock.mpll;
1127 uint16_t data_offset;
1128
1129 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1130 &frev, &crev, &data_offset)) {
1131 firmware_info =
1132 (union firmware_info *)(mode_info->atom_context->bios +
1133 data_offset);
1134 /* pixel clocks */
1135 p1pll->reference_freq =
1136 le16_to_cpu(firmware_info->info.usReferenceClock);
1137 p1pll->reference_div = 0;
1138
1139 if (crev < 2)
1140 p1pll->pll_out_min =
1141 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1142 else
1143 p1pll->pll_out_min =
1144 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1145 p1pll->pll_out_max =
1146 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1147
1148 if (crev >= 4) {
1149 p1pll->lcd_pll_out_min =
1150 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1151 if (p1pll->lcd_pll_out_min == 0)
1152 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1153 p1pll->lcd_pll_out_max =
1154 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1155 if (p1pll->lcd_pll_out_max == 0)
1156 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1157 } else {
1158 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1159 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1160 }
1161
1162 if (p1pll->pll_out_min == 0) {
1163 if (ASIC_IS_AVIVO(rdev))
1164 p1pll->pll_out_min = 64800;
1165 else
1166 p1pll->pll_out_min = 20000;
1167 }
1168
1169 p1pll->pll_in_min =
1170 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1171 p1pll->pll_in_max =
1172 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1173
1174 *p2pll = *p1pll;
1175
1176 /* system clock */
1177 if (ASIC_IS_DCE4(rdev))
1178 spll->reference_freq =
1179 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1180 else
1181 spll->reference_freq =
1182 le16_to_cpu(firmware_info->info.usReferenceClock);
1183 spll->reference_div = 0;
1184
1185 spll->pll_out_min =
1186 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1187 spll->pll_out_max =
1188 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1189
1190 /* ??? */
1191 if (spll->pll_out_min == 0) {
1192 if (ASIC_IS_AVIVO(rdev))
1193 spll->pll_out_min = 64800;
1194 else
1195 spll->pll_out_min = 20000;
1196 }
1197
1198 spll->pll_in_min =
1199 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1200 spll->pll_in_max =
1201 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1202
1203 /* memory clock */
1204 if (ASIC_IS_DCE4(rdev))
1205 mpll->reference_freq =
1206 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1207 else
1208 mpll->reference_freq =
1209 le16_to_cpu(firmware_info->info.usReferenceClock);
1210 mpll->reference_div = 0;
1211
1212 mpll->pll_out_min =
1213 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1214 mpll->pll_out_max =
1215 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1216
1217 /* ??? */
1218 if (mpll->pll_out_min == 0) {
1219 if (ASIC_IS_AVIVO(rdev))
1220 mpll->pll_out_min = 64800;
1221 else
1222 mpll->pll_out_min = 20000;
1223 }
1224
1225 mpll->pll_in_min =
1226 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1227 mpll->pll_in_max =
1228 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1229
1230 rdev->clock.default_sclk =
1231 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1232 rdev->clock.default_mclk =
1233 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1234
1235 if (ASIC_IS_DCE4(rdev)) {
1236 rdev->clock.default_dispclk =
1237 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1238 if (rdev->clock.default_dispclk == 0) {
1239 if (ASIC_IS_DCE5(rdev))
1240 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1241 else
1242 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1243 }
1244 rdev->clock.dp_extclk =
1245 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1246 }
1247 *dcpll = *p1pll;
1248
1249 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1250 if (rdev->clock.max_pixel_clock == 0)
1251 rdev->clock.max_pixel_clock = 40000;
1252
1253 return true;
1254 }
1255
1256 return false;
1257}
1258
1259union igp_info {
1260 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1261 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1262};
1263
1264bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1265{
1266 struct radeon_mode_info *mode_info = &rdev->mode_info;
1267 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1268 union igp_info *igp_info;
1269 u8 frev, crev;
1270 u16 data_offset;
1271
1272 /* sideport is AMD only */
1273 if (rdev->family == CHIP_RS600)
1274 return false;
1275
1276 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1277 &frev, &crev, &data_offset)) {
1278 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1279 data_offset);
1280 switch (crev) {
1281 case 1:
1282 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1283 return true;
1284 break;
1285 case 2:
1286 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1287 return true;
1288 break;
1289 default:
1290 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1291 break;
1292 }
1293 }
1294 return false;
1295}
1296
1297bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1298 struct radeon_encoder_int_tmds *tmds)
1299{
1300 struct drm_device *dev = encoder->base.dev;
1301 struct radeon_device *rdev = dev->dev_private;
1302 struct radeon_mode_info *mode_info = &rdev->mode_info;
1303 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1304 uint16_t data_offset;
1305 struct _ATOM_TMDS_INFO *tmds_info;
1306 uint8_t frev, crev;
1307 uint16_t maxfreq;
1308 int i;
1309
1310 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1311 &frev, &crev, &data_offset)) {
1312 tmds_info =
1313 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1314 data_offset);
1315
1316 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1317 for (i = 0; i < 4; i++) {
1318 tmds->tmds_pll[i].freq =
1319 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1320 tmds->tmds_pll[i].value =
1321 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1322 tmds->tmds_pll[i].value |=
1323 (tmds_info->asMiscInfo[i].
1324 ucPLL_VCO_Gain & 0x3f) << 6;
1325 tmds->tmds_pll[i].value |=
1326 (tmds_info->asMiscInfo[i].
1327 ucPLL_DutyCycle & 0xf) << 12;
1328 tmds->tmds_pll[i].value |=
1329 (tmds_info->asMiscInfo[i].
1330 ucPLL_VoltageSwing & 0xf) << 16;
1331
1332 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1333 tmds->tmds_pll[i].freq,
1334 tmds->tmds_pll[i].value);
1335
1336 if (maxfreq == tmds->tmds_pll[i].freq) {
1337 tmds->tmds_pll[i].freq = 0xffffffff;
1338 break;
1339 }
1340 }
1341 return true;
1342 }
1343 return false;
1344}
1345
1346bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1347 struct radeon_atom_ss *ss,
1348 int id)
1349{
1350 struct radeon_mode_info *mode_info = &rdev->mode_info;
1351 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1352 uint16_t data_offset, size;
1353 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1354 uint8_t frev, crev;
1355 int i, num_indices;
1356
1357 memset(ss, 0, sizeof(struct radeon_atom_ss));
1358 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1359 &frev, &crev, &data_offset)) {
1360 ss_info =
1361 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1362
1363 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1364 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1365
1366 for (i = 0; i < num_indices; i++) {
1367 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1368 ss->percentage =
1369 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1370 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1371 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1372 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1373 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1374 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1375 return true;
1376 }
1377 }
1378 }
1379 return false;
1380}
1381
1382static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1383 struct radeon_atom_ss *ss,
1384 int id)
1385{
1386 struct radeon_mode_info *mode_info = &rdev->mode_info;
1387 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1388 u16 data_offset, size;
1389 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1390 u8 frev, crev;
1391 u16 percentage = 0, rate = 0;
1392
1393 /* get any igp specific overrides */
1394 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1395 &frev, &crev, &data_offset)) {
1396 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1397 (mode_info->atom_context->bios + data_offset);
1398 switch (id) {
1399 case ASIC_INTERNAL_SS_ON_TMDS:
1400 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1401 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1402 break;
1403 case ASIC_INTERNAL_SS_ON_HDMI:
1404 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1405 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1406 break;
1407 case ASIC_INTERNAL_SS_ON_LVDS:
1408 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1409 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1410 break;
1411 }
1412 if (percentage)
1413 ss->percentage = percentage;
1414 if (rate)
1415 ss->rate = rate;
1416 }
1417}
1418
1419union asic_ss_info {
1420 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1421 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1422 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1423};
1424
1425bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1426 struct radeon_atom_ss *ss,
1427 int id, u32 clock)
1428{
1429 struct radeon_mode_info *mode_info = &rdev->mode_info;
1430 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1431 uint16_t data_offset, size;
1432 union asic_ss_info *ss_info;
1433 uint8_t frev, crev;
1434 int i, num_indices;
1435
1436 memset(ss, 0, sizeof(struct radeon_atom_ss));
1437 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1438 &frev, &crev, &data_offset)) {
1439
1440 ss_info =
1441 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1442
1443 switch (frev) {
1444 case 1:
1445 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1446 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1447
1448 for (i = 0; i < num_indices; i++) {
1449 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1450 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1451 ss->percentage =
1452 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1453 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1454 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1455 return true;
1456 }
1457 }
1458 break;
1459 case 2:
1460 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1461 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1462 for (i = 0; i < num_indices; i++) {
1463 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1464 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1465 ss->percentage =
1466 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1467 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1468 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1469 return true;
1470 }
1471 }
1472 break;
1473 case 3:
1474 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1475 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1476 for (i = 0; i < num_indices; i++) {
1477 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1478 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1479 ss->percentage =
1480 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1481 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1482 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1483 if (rdev->flags & RADEON_IS_IGP)
1484 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1485 return true;
1486 }
1487 }
1488 break;
1489 default:
1490 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1491 break;
1492 }
1493
1494 }
1495 return false;
1496}
1497
1498union lvds_info {
1499 struct _ATOM_LVDS_INFO info;
1500 struct _ATOM_LVDS_INFO_V12 info_12;
1501};
1502
1503struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1504 radeon_encoder
1505 *encoder)
1506{
1507 struct drm_device *dev = encoder->base.dev;
1508 struct radeon_device *rdev = dev->dev_private;
1509 struct radeon_mode_info *mode_info = &rdev->mode_info;
1510 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1511 uint16_t data_offset, misc;
1512 union lvds_info *lvds_info;
1513 uint8_t frev, crev;
1514 struct radeon_encoder_atom_dig *lvds = NULL;
1515 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1516
1517 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1518 &frev, &crev, &data_offset)) {
1519 lvds_info =
1520 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1521 lvds =
1522 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1523
1524 if (!lvds)
1525 return NULL;
1526
1527 lvds->native_mode.clock =
1528 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1529 lvds->native_mode.hdisplay =
1530 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1531 lvds->native_mode.vdisplay =
1532 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1533 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1534 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1535 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1536 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1537 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1538 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1539 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1540 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1541 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1542 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1543 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1544 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1545 lvds->panel_pwr_delay =
1546 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1547 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1548
1549 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1550 if (misc & ATOM_VSYNC_POLARITY)
1551 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1552 if (misc & ATOM_HSYNC_POLARITY)
1553 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1554 if (misc & ATOM_COMPOSITESYNC)
1555 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1556 if (misc & ATOM_INTERLACE)
1557 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1558 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1559 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1560
1561 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1562 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1563
1564 /* set crtc values */
1565 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1566
1567 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1568
1569 encoder->native_mode = lvds->native_mode;
1570
1571 if (encoder_enum == 2)
1572 lvds->linkb = true;
1573 else
1574 lvds->linkb = false;
1575
1576 /* parse the lcd record table */
1577 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1578 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1579 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1580 bool bad_record = false;
1581 u8 *record;
1582
1583 if ((frev == 1) && (crev < 2))
1584 /* absolute */
1585 record = (u8 *)(mode_info->atom_context->bios +
1586 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1587 else
1588 /* relative */
1589 record = (u8 *)(mode_info->atom_context->bios +
1590 data_offset +
1591 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1592 while (*record != ATOM_RECORD_END_TYPE) {
1593 switch (*record) {
1594 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1595 record += sizeof(ATOM_PATCH_RECORD_MODE);
1596 break;
1597 case LCD_RTS_RECORD_TYPE:
1598 record += sizeof(ATOM_LCD_RTS_RECORD);
1599 break;
1600 case LCD_CAP_RECORD_TYPE:
1601 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1602 break;
1603 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1604 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1605 if (fake_edid_record->ucFakeEDIDLength) {
1606 struct edid *edid;
1607 int edid_size =
1608 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1609 edid = kmalloc(edid_size, GFP_KERNEL);
1610 if (edid) {
1611 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1612 fake_edid_record->ucFakeEDIDLength);
1613
1614 if (drm_edid_is_valid(edid)) {
1615 rdev->mode_info.bios_hardcoded_edid = edid;
1616 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1617 } else
1618 kfree(edid);
1619 }
1620 }
1621 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1622 break;
1623 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1624 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1625 lvds->native_mode.width_mm = panel_res_record->usHSize;
1626 lvds->native_mode.height_mm = panel_res_record->usVSize;
1627 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1628 break;
1629 default:
1630 DRM_ERROR("Bad LCD record %d\n", *record);
1631 bad_record = true;
1632 break;
1633 }
1634 if (bad_record)
1635 break;
1636 }
1637 }
1638 }
1639 return lvds;
1640}
1641
1642struct radeon_encoder_primary_dac *
1643radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1644{
1645 struct drm_device *dev = encoder->base.dev;
1646 struct radeon_device *rdev = dev->dev_private;
1647 struct radeon_mode_info *mode_info = &rdev->mode_info;
1648 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1649 uint16_t data_offset;
1650 struct _COMPASSIONATE_DATA *dac_info;
1651 uint8_t frev, crev;
1652 uint8_t bg, dac;
1653 struct radeon_encoder_primary_dac *p_dac = NULL;
1654
1655 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1656 &frev, &crev, &data_offset)) {
1657 dac_info = (struct _COMPASSIONATE_DATA *)
1658 (mode_info->atom_context->bios + data_offset);
1659
1660 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1661
1662 if (!p_dac)
1663 return NULL;
1664
1665 bg = dac_info->ucDAC1_BG_Adjustment;
1666 dac = dac_info->ucDAC1_DAC_Adjustment;
1667 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1668
1669 }
1670 return p_dac;
1671}
1672
1673bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1674 struct drm_display_mode *mode)
1675{
1676 struct radeon_mode_info *mode_info = &rdev->mode_info;
1677 ATOM_ANALOG_TV_INFO *tv_info;
1678 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1679 ATOM_DTD_FORMAT *dtd_timings;
1680 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1681 u8 frev, crev;
1682 u16 data_offset, misc;
1683
1684 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1685 &frev, &crev, &data_offset))
1686 return false;
1687
1688 switch (crev) {
1689 case 1:
1690 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1691 if (index >= MAX_SUPPORTED_TV_TIMING)
1692 return false;
1693
1694 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1695 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1696 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1697 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1698 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1699
1700 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1701 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1702 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1703 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1704 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1705
1706 mode->flags = 0;
1707 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1708 if (misc & ATOM_VSYNC_POLARITY)
1709 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1710 if (misc & ATOM_HSYNC_POLARITY)
1711 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1712 if (misc & ATOM_COMPOSITESYNC)
1713 mode->flags |= DRM_MODE_FLAG_CSYNC;
1714 if (misc & ATOM_INTERLACE)
1715 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1716 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1717 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1718
1719 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1720
1721 if (index == 1) {
1722 /* PAL timings appear to have wrong values for totals */
1723 mode->crtc_htotal -= 1;
1724 mode->crtc_vtotal -= 1;
1725 }
1726 break;
1727 case 2:
1728 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1729 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1730 return false;
1731
1732 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1733 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1734 le16_to_cpu(dtd_timings->usHBlanking_Time);
1735 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1736 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1737 le16_to_cpu(dtd_timings->usHSyncOffset);
1738 mode->crtc_hsync_end = mode->crtc_hsync_start +
1739 le16_to_cpu(dtd_timings->usHSyncWidth);
1740
1741 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1742 le16_to_cpu(dtd_timings->usVBlanking_Time);
1743 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1744 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1745 le16_to_cpu(dtd_timings->usVSyncOffset);
1746 mode->crtc_vsync_end = mode->crtc_vsync_start +
1747 le16_to_cpu(dtd_timings->usVSyncWidth);
1748
1749 mode->flags = 0;
1750 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1751 if (misc & ATOM_VSYNC_POLARITY)
1752 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1753 if (misc & ATOM_HSYNC_POLARITY)
1754 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1755 if (misc & ATOM_COMPOSITESYNC)
1756 mode->flags |= DRM_MODE_FLAG_CSYNC;
1757 if (misc & ATOM_INTERLACE)
1758 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1759 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1760 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1761
1762 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1763 break;
1764 }
1765 return true;
1766}
1767
1768enum radeon_tv_std
1769radeon_atombios_get_tv_info(struct radeon_device *rdev)
1770{
1771 struct radeon_mode_info *mode_info = &rdev->mode_info;
1772 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1773 uint16_t data_offset;
1774 uint8_t frev, crev;
1775 struct _ATOM_ANALOG_TV_INFO *tv_info;
1776 enum radeon_tv_std tv_std = TV_STD_NTSC;
1777
1778 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1779 &frev, &crev, &data_offset)) {
1780
1781 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1782 (mode_info->atom_context->bios + data_offset);
1783
1784 switch (tv_info->ucTV_BootUpDefaultStandard) {
1785 case ATOM_TV_NTSC:
1786 tv_std = TV_STD_NTSC;
1787 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1788 break;
1789 case ATOM_TV_NTSCJ:
1790 tv_std = TV_STD_NTSC_J;
1791 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1792 break;
1793 case ATOM_TV_PAL:
1794 tv_std = TV_STD_PAL;
1795 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1796 break;
1797 case ATOM_TV_PALM:
1798 tv_std = TV_STD_PAL_M;
1799 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1800 break;
1801 case ATOM_TV_PALN:
1802 tv_std = TV_STD_PAL_N;
1803 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1804 break;
1805 case ATOM_TV_PALCN:
1806 tv_std = TV_STD_PAL_CN;
1807 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1808 break;
1809 case ATOM_TV_PAL60:
1810 tv_std = TV_STD_PAL_60;
1811 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1812 break;
1813 case ATOM_TV_SECAM:
1814 tv_std = TV_STD_SECAM;
1815 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1816 break;
1817 default:
1818 tv_std = TV_STD_NTSC;
1819 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1820 break;
1821 }
1822 }
1823 return tv_std;
1824}
1825
1826struct radeon_encoder_tv_dac *
1827radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1828{
1829 struct drm_device *dev = encoder->base.dev;
1830 struct radeon_device *rdev = dev->dev_private;
1831 struct radeon_mode_info *mode_info = &rdev->mode_info;
1832 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1833 uint16_t data_offset;
1834 struct _COMPASSIONATE_DATA *dac_info;
1835 uint8_t frev, crev;
1836 uint8_t bg, dac;
1837 struct radeon_encoder_tv_dac *tv_dac = NULL;
1838
1839 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1840 &frev, &crev, &data_offset)) {
1841
1842 dac_info = (struct _COMPASSIONATE_DATA *)
1843 (mode_info->atom_context->bios + data_offset);
1844
1845 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1846
1847 if (!tv_dac)
1848 return NULL;
1849
1850 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1851 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1852 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1853
1854 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1855 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1856 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1857
1858 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1859 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1860 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1861
1862 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1863 }
1864 return tv_dac;
1865}
1866
1867static const char *thermal_controller_names[] = {
1868 "NONE",
1869 "lm63",
1870 "adm1032",
1871 "adm1030",
1872 "max6649",
1873 "lm64",
1874 "f75375",
1875 "asc7xxx",
1876};
1877
1878static const char *pp_lib_thermal_controller_names[] = {
1879 "NONE",
1880 "lm63",
1881 "adm1032",
1882 "adm1030",
1883 "max6649",
1884 "lm64",
1885 "f75375",
1886 "RV6xx",
1887 "RV770",
1888 "adt7473",
1889 "NONE",
1890 "External GPIO",
1891 "Evergreen",
1892 "emc2103",
1893 "Sumo",
1894 "Northern Islands",
1895};
1896
1897union power_info {
1898 struct _ATOM_POWERPLAY_INFO info;
1899 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1900 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1901 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1902 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1903 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1904};
1905
1906union pplib_clock_info {
1907 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1908 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1909 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1910 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1911};
1912
1913union pplib_power_state {
1914 struct _ATOM_PPLIB_STATE v1;
1915 struct _ATOM_PPLIB_STATE_V2 v2;
1916};
1917
1918static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1919 int state_index,
1920 u32 misc, u32 misc2)
1921{
1922 rdev->pm.power_state[state_index].misc = misc;
1923 rdev->pm.power_state[state_index].misc2 = misc2;
1924 /* order matters! */
1925 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1926 rdev->pm.power_state[state_index].type =
1927 POWER_STATE_TYPE_POWERSAVE;
1928 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1929 rdev->pm.power_state[state_index].type =
1930 POWER_STATE_TYPE_BATTERY;
1931 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1932 rdev->pm.power_state[state_index].type =
1933 POWER_STATE_TYPE_BATTERY;
1934 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1935 rdev->pm.power_state[state_index].type =
1936 POWER_STATE_TYPE_BALANCED;
1937 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1938 rdev->pm.power_state[state_index].type =
1939 POWER_STATE_TYPE_PERFORMANCE;
1940 rdev->pm.power_state[state_index].flags &=
1941 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1942 }
1943 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1944 rdev->pm.power_state[state_index].type =
1945 POWER_STATE_TYPE_BALANCED;
1946 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1947 rdev->pm.power_state[state_index].type =
1948 POWER_STATE_TYPE_DEFAULT;
1949 rdev->pm.default_power_state_index = state_index;
1950 rdev->pm.power_state[state_index].default_clock_mode =
1951 &rdev->pm.power_state[state_index].clock_info[0];
1952 } else if (state_index == 0) {
1953 rdev->pm.power_state[state_index].clock_info[0].flags |=
1954 RADEON_PM_MODE_NO_DISPLAY;
1955 }
1956}
1957
1958static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1959{
1960 struct radeon_mode_info *mode_info = &rdev->mode_info;
1961 u32 misc, misc2 = 0;
1962 int num_modes = 0, i;
1963 int state_index = 0;
1964 struct radeon_i2c_bus_rec i2c_bus;
1965 union power_info *power_info;
1966 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1967 u16 data_offset;
1968 u8 frev, crev;
1969
1970 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1971 &frev, &crev, &data_offset))
1972 return state_index;
1973 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1974
1975 /* add the i2c bus for thermal/fan chip */
1976 if (power_info->info.ucOverdriveThermalController > 0) {
1977 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1978 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1979 power_info->info.ucOverdriveControllerAddress >> 1);
1980 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1981 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1982 if (rdev->pm.i2c_bus) {
1983 struct i2c_board_info info = { };
1984 const char *name = thermal_controller_names[power_info->info.
1985 ucOverdriveThermalController];
1986 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1987 strlcpy(info.type, name, sizeof(info.type));
1988 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1989 }
1990 }
1991 num_modes = power_info->info.ucNumOfPowerModeEntries;
1992 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1993 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1994 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
1995 if (!rdev->pm.power_state)
1996 return state_index;
1997 /* last mode is usually default, array is low to high */
1998 for (i = 0; i < num_modes; i++) {
1999 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2000 switch (frev) {
2001 case 1:
2002 rdev->pm.power_state[state_index].num_clock_modes = 1;
2003 rdev->pm.power_state[state_index].clock_info[0].mclk =
2004 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2005 rdev->pm.power_state[state_index].clock_info[0].sclk =
2006 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2007 /* skip invalid modes */
2008 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2009 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2010 continue;
2011 rdev->pm.power_state[state_index].pcie_lanes =
2012 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2013 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2014 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2015 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2016 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2017 VOLTAGE_GPIO;
2018 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2019 radeon_lookup_gpio(rdev,
2020 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2021 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2022 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2023 true;
2024 else
2025 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2026 false;
2027 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2028 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2029 VOLTAGE_VDDC;
2030 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2031 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2032 }
2033 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2034 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2035 state_index++;
2036 break;
2037 case 2:
2038 rdev->pm.power_state[state_index].num_clock_modes = 1;
2039 rdev->pm.power_state[state_index].clock_info[0].mclk =
2040 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2041 rdev->pm.power_state[state_index].clock_info[0].sclk =
2042 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2043 /* skip invalid modes */
2044 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2045 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2046 continue;
2047 rdev->pm.power_state[state_index].pcie_lanes =
2048 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2049 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2050 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2051 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2052 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2053 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2054 VOLTAGE_GPIO;
2055 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2056 radeon_lookup_gpio(rdev,
2057 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2058 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2059 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2060 true;
2061 else
2062 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2063 false;
2064 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2065 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2066 VOLTAGE_VDDC;
2067 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2068 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2069 }
2070 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2071 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2072 state_index++;
2073 break;
2074 case 3:
2075 rdev->pm.power_state[state_index].num_clock_modes = 1;
2076 rdev->pm.power_state[state_index].clock_info[0].mclk =
2077 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2078 rdev->pm.power_state[state_index].clock_info[0].sclk =
2079 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2080 /* skip invalid modes */
2081 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2082 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2083 continue;
2084 rdev->pm.power_state[state_index].pcie_lanes =
2085 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2086 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2087 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2088 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2089 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2090 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2091 VOLTAGE_GPIO;
2092 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2093 radeon_lookup_gpio(rdev,
2094 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2095 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2096 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2097 true;
2098 else
2099 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2100 false;
2101 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2102 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2103 VOLTAGE_VDDC;
2104 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2105 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2106 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2107 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2108 true;
2109 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2110 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2111 }
2112 }
2113 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2114 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2115 state_index++;
2116 break;
2117 }
2118 }
2119 /* last mode is usually default */
2120 if (rdev->pm.default_power_state_index == -1) {
2121 rdev->pm.power_state[state_index - 1].type =
2122 POWER_STATE_TYPE_DEFAULT;
2123 rdev->pm.default_power_state_index = state_index - 1;
2124 rdev->pm.power_state[state_index - 1].default_clock_mode =
2125 &rdev->pm.power_state[state_index - 1].clock_info[0];
2126 rdev->pm.power_state[state_index].flags &=
2127 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2128 rdev->pm.power_state[state_index].misc = 0;
2129 rdev->pm.power_state[state_index].misc2 = 0;
2130 }
2131 return state_index;
2132}
2133
2134static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2135 ATOM_PPLIB_THERMALCONTROLLER *controller)
2136{
2137 struct radeon_i2c_bus_rec i2c_bus;
2138
2139 /* add the i2c bus for thermal/fan chip */
2140 if (controller->ucType > 0) {
2141 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2142 DRM_INFO("Internal thermal controller %s fan control\n",
2143 (controller->ucFanParameters &
2144 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2145 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2146 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2147 DRM_INFO("Internal thermal controller %s fan control\n",
2148 (controller->ucFanParameters &
2149 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2150 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2151 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2152 DRM_INFO("Internal thermal controller %s fan control\n",
2153 (controller->ucFanParameters &
2154 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2155 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2156 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2157 DRM_INFO("Internal thermal controller %s fan control\n",
2158 (controller->ucFanParameters &
2159 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2160 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2161 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2162 DRM_INFO("Internal thermal controller %s fan control\n",
2163 (controller->ucFanParameters &
2164 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2165 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2166 } else if ((controller->ucType ==
2167 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2168 (controller->ucType ==
2169 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2170 (controller->ucType ==
2171 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2172 DRM_INFO("Special thermal controller config\n");
2173 } else {
2174 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2175 pp_lib_thermal_controller_names[controller->ucType],
2176 controller->ucI2cAddress >> 1,
2177 (controller->ucFanParameters &
2178 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2179 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2180 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2181 if (rdev->pm.i2c_bus) {
2182 struct i2c_board_info info = { };
2183 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2184 info.addr = controller->ucI2cAddress >> 1;
2185 strlcpy(info.type, name, sizeof(info.type));
2186 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2187 }
2188 }
2189 }
2190}
2191
2192static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2193 u16 *vddc, u16 *vddci)
2194{
2195 struct radeon_mode_info *mode_info = &rdev->mode_info;
2196 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2197 u8 frev, crev;
2198 u16 data_offset;
2199 union firmware_info *firmware_info;
2200
2201 *vddc = 0;
2202 *vddci = 0;
2203
2204 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2205 &frev, &crev, &data_offset)) {
2206 firmware_info =
2207 (union firmware_info *)(mode_info->atom_context->bios +
2208 data_offset);
2209 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2210 if ((frev == 2) && (crev >= 2))
2211 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2212 }
2213}
2214
2215static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2216 int state_index, int mode_index,
2217 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2218{
2219 int j;
2220 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2221 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2222 u16 vddc, vddci;
2223
2224 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2225
2226 rdev->pm.power_state[state_index].misc = misc;
2227 rdev->pm.power_state[state_index].misc2 = misc2;
2228 rdev->pm.power_state[state_index].pcie_lanes =
2229 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2230 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2231 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2232 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2233 rdev->pm.power_state[state_index].type =
2234 POWER_STATE_TYPE_BATTERY;
2235 break;
2236 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2237 rdev->pm.power_state[state_index].type =
2238 POWER_STATE_TYPE_BALANCED;
2239 break;
2240 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2241 rdev->pm.power_state[state_index].type =
2242 POWER_STATE_TYPE_PERFORMANCE;
2243 break;
2244 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2245 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2246 rdev->pm.power_state[state_index].type =
2247 POWER_STATE_TYPE_PERFORMANCE;
2248 break;
2249 }
2250 rdev->pm.power_state[state_index].flags = 0;
2251 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2252 rdev->pm.power_state[state_index].flags |=
2253 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2254 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2255 rdev->pm.power_state[state_index].type =
2256 POWER_STATE_TYPE_DEFAULT;
2257 rdev->pm.default_power_state_index = state_index;
2258 rdev->pm.power_state[state_index].default_clock_mode =
2259 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2260 if (ASIC_IS_DCE5(rdev)) {
2261 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2262 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2263 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2264 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2265 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2266 } else {
2267 /* patch the table values with the default slck/mclk from firmware info */
2268 for (j = 0; j < mode_index; j++) {
2269 rdev->pm.power_state[state_index].clock_info[j].mclk =
2270 rdev->clock.default_mclk;
2271 rdev->pm.power_state[state_index].clock_info[j].sclk =
2272 rdev->clock.default_sclk;
2273 if (vddc)
2274 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2275 vddc;
2276 }
2277 }
2278 }
2279}
2280
2281static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2282 int state_index, int mode_index,
2283 union pplib_clock_info *clock_info)
2284{
2285 u32 sclk, mclk;
2286
2287 if (rdev->flags & RADEON_IS_IGP) {
2288 if (rdev->family >= CHIP_PALM) {
2289 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2290 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2291 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2292 } else {
2293 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2294 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2295 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2296 }
2297 } else if (ASIC_IS_DCE4(rdev)) {
2298 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2299 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2300 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2301 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2302 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2303 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2304 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2305 VOLTAGE_SW;
2306 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2307 le16_to_cpu(clock_info->evergreen.usVDDC);
2308 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2309 le16_to_cpu(clock_info->evergreen.usVDDCI);
2310 } else {
2311 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2312 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2313 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2314 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2315 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2316 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2317 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2318 VOLTAGE_SW;
2319 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2320 le16_to_cpu(clock_info->r600.usVDDC);
2321 }
2322
2323 /* patch up vddc if necessary */
2324 if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) {
2325 u16 vddc;
2326
2327 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
2328 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2329 }
2330
2331 if (rdev->flags & RADEON_IS_IGP) {
2332 /* skip invalid modes */
2333 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2334 return false;
2335 } else {
2336 /* skip invalid modes */
2337 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2338 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2339 return false;
2340 }
2341 return true;
2342}
2343
2344static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2345{
2346 struct radeon_mode_info *mode_info = &rdev->mode_info;
2347 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2348 union pplib_power_state *power_state;
2349 int i, j;
2350 int state_index = 0, mode_index = 0;
2351 union pplib_clock_info *clock_info;
2352 bool valid;
2353 union power_info *power_info;
2354 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2355 u16 data_offset;
2356 u8 frev, crev;
2357
2358 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2359 &frev, &crev, &data_offset))
2360 return state_index;
2361 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2362
2363 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2364 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2365 power_info->pplib.ucNumStates, GFP_KERNEL);
2366 if (!rdev->pm.power_state)
2367 return state_index;
2368 /* first mode is usually default, followed by low to high */
2369 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2370 mode_index = 0;
2371 power_state = (union pplib_power_state *)
2372 (mode_info->atom_context->bios + data_offset +
2373 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2374 i * power_info->pplib.ucStateEntrySize);
2375 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2376 (mode_info->atom_context->bios + data_offset +
2377 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2378 (power_state->v1.ucNonClockStateIndex *
2379 power_info->pplib.ucNonClockSize));
2380 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2381 clock_info = (union pplib_clock_info *)
2382 (mode_info->atom_context->bios + data_offset +
2383 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2384 (power_state->v1.ucClockStateIndices[j] *
2385 power_info->pplib.ucClockInfoSize));
2386 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2387 state_index, mode_index,
2388 clock_info);
2389 if (valid)
2390 mode_index++;
2391 }
2392 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2393 if (mode_index) {
2394 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2395 non_clock_info);
2396 state_index++;
2397 }
2398 }
2399 /* if multiple clock modes, mark the lowest as no display */
2400 for (i = 0; i < state_index; i++) {
2401 if (rdev->pm.power_state[i].num_clock_modes > 1)
2402 rdev->pm.power_state[i].clock_info[0].flags |=
2403 RADEON_PM_MODE_NO_DISPLAY;
2404 }
2405 /* first mode is usually default */
2406 if (rdev->pm.default_power_state_index == -1) {
2407 rdev->pm.power_state[0].type =
2408 POWER_STATE_TYPE_DEFAULT;
2409 rdev->pm.default_power_state_index = 0;
2410 rdev->pm.power_state[0].default_clock_mode =
2411 &rdev->pm.power_state[0].clock_info[0];
2412 }
2413 return state_index;
2414}
2415
2416static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2417{
2418 struct radeon_mode_info *mode_info = &rdev->mode_info;
2419 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2420 union pplib_power_state *power_state;
2421 int i, j, non_clock_array_index, clock_array_index;
2422 int state_index = 0, mode_index = 0;
2423 union pplib_clock_info *clock_info;
2424 struct StateArray *state_array;
2425 struct ClockInfoArray *clock_info_array;
2426 struct NonClockInfoArray *non_clock_info_array;
2427 bool valid;
2428 union power_info *power_info;
2429 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2430 u16 data_offset;
2431 u8 frev, crev;
2432
2433 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2434 &frev, &crev, &data_offset))
2435 return state_index;
2436 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2437
2438 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2439 state_array = (struct StateArray *)
2440 (mode_info->atom_context->bios + data_offset +
2441 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2442 clock_info_array = (struct ClockInfoArray *)
2443 (mode_info->atom_context->bios + data_offset +
2444 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2445 non_clock_info_array = (struct NonClockInfoArray *)
2446 (mode_info->atom_context->bios + data_offset +
2447 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2448 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2449 state_array->ucNumEntries, GFP_KERNEL);
2450 if (!rdev->pm.power_state)
2451 return state_index;
2452 for (i = 0; i < state_array->ucNumEntries; i++) {
2453 mode_index = 0;
2454 power_state = (union pplib_power_state *)&state_array->states[i];
2455 /* XXX this might be an inagua bug... */
2456 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2457 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2458 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2459 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2460 clock_array_index = power_state->v2.clockInfoIndex[j];
2461 /* XXX this might be an inagua bug... */
2462 if (clock_array_index >= clock_info_array->ucNumEntries)
2463 continue;
2464 clock_info = (union pplib_clock_info *)
2465 &clock_info_array->clockInfo[clock_array_index];
2466 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2467 state_index, mode_index,
2468 clock_info);
2469 if (valid)
2470 mode_index++;
2471 }
2472 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2473 if (mode_index) {
2474 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2475 non_clock_info);
2476 state_index++;
2477 }
2478 }
2479 /* if multiple clock modes, mark the lowest as no display */
2480 for (i = 0; i < state_index; i++) {
2481 if (rdev->pm.power_state[i].num_clock_modes > 1)
2482 rdev->pm.power_state[i].clock_info[0].flags |=
2483 RADEON_PM_MODE_NO_DISPLAY;
2484 }
2485 /* first mode is usually default */
2486 if (rdev->pm.default_power_state_index == -1) {
2487 rdev->pm.power_state[0].type =
2488 POWER_STATE_TYPE_DEFAULT;
2489 rdev->pm.default_power_state_index = 0;
2490 rdev->pm.power_state[0].default_clock_mode =
2491 &rdev->pm.power_state[0].clock_info[0];
2492 }
2493 return state_index;
2494}
2495
2496void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2497{
2498 struct radeon_mode_info *mode_info = &rdev->mode_info;
2499 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2500 u16 data_offset;
2501 u8 frev, crev;
2502 int state_index = 0;
2503
2504 rdev->pm.default_power_state_index = -1;
2505
2506 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2507 &frev, &crev, &data_offset)) {
2508 switch (frev) {
2509 case 1:
2510 case 2:
2511 case 3:
2512 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2513 break;
2514 case 4:
2515 case 5:
2516 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2517 break;
2518 case 6:
2519 state_index = radeon_atombios_parse_power_table_6(rdev);
2520 break;
2521 default:
2522 break;
2523 }
2524 } else {
2525 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2526 if (rdev->pm.power_state) {
2527 /* add the default mode */
2528 rdev->pm.power_state[state_index].type =
2529 POWER_STATE_TYPE_DEFAULT;
2530 rdev->pm.power_state[state_index].num_clock_modes = 1;
2531 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2532 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2533 rdev->pm.power_state[state_index].default_clock_mode =
2534 &rdev->pm.power_state[state_index].clock_info[0];
2535 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2536 rdev->pm.power_state[state_index].pcie_lanes = 16;
2537 rdev->pm.default_power_state_index = state_index;
2538 rdev->pm.power_state[state_index].flags = 0;
2539 state_index++;
2540 }
2541 }
2542
2543 rdev->pm.num_power_states = state_index;
2544
2545 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2546 rdev->pm.current_clock_mode_index = 0;
2547 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2548}
2549
2550void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2551{
2552 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2553 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2554
2555 args.ucEnable = enable;
2556
2557 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2558}
2559
2560uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2561{
2562 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2563 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2564
2565 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2566 return le32_to_cpu(args.ulReturnEngineClock);
2567}
2568
2569uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2570{
2571 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2572 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2573
2574 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2575 return le32_to_cpu(args.ulReturnMemoryClock);
2576}
2577
2578void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2579 uint32_t eng_clock)
2580{
2581 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2582 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2583
2584 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2585
2586 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2587}
2588
2589void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2590 uint32_t mem_clock)
2591{
2592 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2593 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2594
2595 if (rdev->flags & RADEON_IS_IGP)
2596 return;
2597
2598 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2599
2600 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2601}
2602
2603union set_voltage {
2604 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2605 struct _SET_VOLTAGE_PARAMETERS v1;
2606 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2607};
2608
2609void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2610{
2611 union set_voltage args;
2612 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2613 u8 frev, crev, volt_index = voltage_level;
2614
2615 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2616 return;
2617
2618 /* 0xff01 is a flag rather then an actual voltage */
2619 if (voltage_level == 0xff01)
2620 return;
2621
2622 switch (crev) {
2623 case 1:
2624 args.v1.ucVoltageType = voltage_type;
2625 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2626 args.v1.ucVoltageIndex = volt_index;
2627 break;
2628 case 2:
2629 args.v2.ucVoltageType = voltage_type;
2630 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2631 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2632 break;
2633 default:
2634 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2635 return;
2636 }
2637
2638 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2639}
2640
2641int radeon_atom_get_max_vddc(struct radeon_device *rdev,
2642 u16 *voltage)
2643{
2644 union set_voltage args;
2645 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2646 u8 frev, crev;
2647
2648 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2649 return -EINVAL;
2650
2651 switch (crev) {
2652 case 1:
2653 return -EINVAL;
2654 case 2:
2655 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2656 args.v2.ucVoltageMode = 0;
2657 args.v2.usVoltageLevel = 0;
2658
2659 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2660
2661 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2662 break;
2663 default:
2664 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2665 return -EINVAL;
2666 }
2667
2668 return 0;
2669}
2670
2671void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2672{
2673 struct radeon_device *rdev = dev->dev_private;
2674 uint32_t bios_2_scratch, bios_6_scratch;
2675
2676 if (rdev->family >= CHIP_R600) {
2677 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2678 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2679 } else {
2680 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2681 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2682 }
2683
2684 /* let the bios control the backlight */
2685 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2686
2687 /* tell the bios not to handle mode switching */
2688 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2689
2690 if (rdev->family >= CHIP_R600) {
2691 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2692 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2693 } else {
2694 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2695 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2696 }
2697
2698}
2699
2700void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2701{
2702 uint32_t scratch_reg;
2703 int i;
2704
2705 if (rdev->family >= CHIP_R600)
2706 scratch_reg = R600_BIOS_0_SCRATCH;
2707 else
2708 scratch_reg = RADEON_BIOS_0_SCRATCH;
2709
2710 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2711 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2712}
2713
2714void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2715{
2716 uint32_t scratch_reg;
2717 int i;
2718
2719 if (rdev->family >= CHIP_R600)
2720 scratch_reg = R600_BIOS_0_SCRATCH;
2721 else
2722 scratch_reg = RADEON_BIOS_0_SCRATCH;
2723
2724 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2725 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2726}
2727
2728void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2729{
2730 struct drm_device *dev = encoder->dev;
2731 struct radeon_device *rdev = dev->dev_private;
2732 uint32_t bios_6_scratch;
2733
2734 if (rdev->family >= CHIP_R600)
2735 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2736 else
2737 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2738
2739 if (lock) {
2740 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2741 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2742 } else {
2743 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2744 bios_6_scratch |= ATOM_S6_ACC_MODE;
2745 }
2746
2747 if (rdev->family >= CHIP_R600)
2748 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2749 else
2750 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2751}
2752
2753/* at some point we may want to break this out into individual functions */
2754void
2755radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2756 struct drm_encoder *encoder,
2757 bool connected)
2758{
2759 struct drm_device *dev = connector->dev;
2760 struct radeon_device *rdev = dev->dev_private;
2761 struct radeon_connector *radeon_connector =
2762 to_radeon_connector(connector);
2763 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2764 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2765
2766 if (rdev->family >= CHIP_R600) {
2767 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2768 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2769 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2770 } else {
2771 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2772 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2773 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2774 }
2775
2776 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2777 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2778 if (connected) {
2779 DRM_DEBUG_KMS("TV1 connected\n");
2780 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2781 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2782 } else {
2783 DRM_DEBUG_KMS("TV1 disconnected\n");
2784 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2785 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2786 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2787 }
2788 }
2789 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2790 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2791 if (connected) {
2792 DRM_DEBUG_KMS("CV connected\n");
2793 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2794 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2795 } else {
2796 DRM_DEBUG_KMS("CV disconnected\n");
2797 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2798 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2799 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2800 }
2801 }
2802 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2803 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2804 if (connected) {
2805 DRM_DEBUG_KMS("LCD1 connected\n");
2806 bios_0_scratch |= ATOM_S0_LCD1;
2807 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2808 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2809 } else {
2810 DRM_DEBUG_KMS("LCD1 disconnected\n");
2811 bios_0_scratch &= ~ATOM_S0_LCD1;
2812 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2813 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2814 }
2815 }
2816 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2817 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2818 if (connected) {
2819 DRM_DEBUG_KMS("CRT1 connected\n");
2820 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2821 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2822 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2823 } else {
2824 DRM_DEBUG_KMS("CRT1 disconnected\n");
2825 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2826 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2827 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2828 }
2829 }
2830 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2831 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2832 if (connected) {
2833 DRM_DEBUG_KMS("CRT2 connected\n");
2834 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2835 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2836 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2837 } else {
2838 DRM_DEBUG_KMS("CRT2 disconnected\n");
2839 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2840 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2841 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2842 }
2843 }
2844 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2845 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2846 if (connected) {
2847 DRM_DEBUG_KMS("DFP1 connected\n");
2848 bios_0_scratch |= ATOM_S0_DFP1;
2849 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2850 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2851 } else {
2852 DRM_DEBUG_KMS("DFP1 disconnected\n");
2853 bios_0_scratch &= ~ATOM_S0_DFP1;
2854 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2855 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2856 }
2857 }
2858 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2859 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2860 if (connected) {
2861 DRM_DEBUG_KMS("DFP2 connected\n");
2862 bios_0_scratch |= ATOM_S0_DFP2;
2863 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2864 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2865 } else {
2866 DRM_DEBUG_KMS("DFP2 disconnected\n");
2867 bios_0_scratch &= ~ATOM_S0_DFP2;
2868 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2869 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2870 }
2871 }
2872 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2873 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2874 if (connected) {
2875 DRM_DEBUG_KMS("DFP3 connected\n");
2876 bios_0_scratch |= ATOM_S0_DFP3;
2877 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2878 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2879 } else {
2880 DRM_DEBUG_KMS("DFP3 disconnected\n");
2881 bios_0_scratch &= ~ATOM_S0_DFP3;
2882 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2883 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2884 }
2885 }
2886 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2887 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2888 if (connected) {
2889 DRM_DEBUG_KMS("DFP4 connected\n");
2890 bios_0_scratch |= ATOM_S0_DFP4;
2891 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2892 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2893 } else {
2894 DRM_DEBUG_KMS("DFP4 disconnected\n");
2895 bios_0_scratch &= ~ATOM_S0_DFP4;
2896 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2897 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2898 }
2899 }
2900 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2901 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2902 if (connected) {
2903 DRM_DEBUG_KMS("DFP5 connected\n");
2904 bios_0_scratch |= ATOM_S0_DFP5;
2905 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2906 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2907 } else {
2908 DRM_DEBUG_KMS("DFP5 disconnected\n");
2909 bios_0_scratch &= ~ATOM_S0_DFP5;
2910 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2911 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2912 }
2913 }
2914
2915 if (rdev->family >= CHIP_R600) {
2916 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2917 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2918 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2919 } else {
2920 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2921 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2922 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2923 }
2924}
2925
2926void
2927radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2928{
2929 struct drm_device *dev = encoder->dev;
2930 struct radeon_device *rdev = dev->dev_private;
2931 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2932 uint32_t bios_3_scratch;
2933
2934 if (rdev->family >= CHIP_R600)
2935 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2936 else
2937 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2938
2939 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2940 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2941 bios_3_scratch |= (crtc << 18);
2942 }
2943 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2944 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2945 bios_3_scratch |= (crtc << 24);
2946 }
2947 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2948 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2949 bios_3_scratch |= (crtc << 16);
2950 }
2951 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2952 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2953 bios_3_scratch |= (crtc << 20);
2954 }
2955 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2956 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2957 bios_3_scratch |= (crtc << 17);
2958 }
2959 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2960 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2961 bios_3_scratch |= (crtc << 19);
2962 }
2963 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2964 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2965 bios_3_scratch |= (crtc << 23);
2966 }
2967 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2968 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2969 bios_3_scratch |= (crtc << 25);
2970 }
2971
2972 if (rdev->family >= CHIP_R600)
2973 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2974 else
2975 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2976}
2977
2978void
2979radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2980{
2981 struct drm_device *dev = encoder->dev;
2982 struct radeon_device *rdev = dev->dev_private;
2983 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2984 uint32_t bios_2_scratch;
2985
2986 if (rdev->family >= CHIP_R600)
2987 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2988 else
2989 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2990
2991 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2992 if (on)
2993 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2994 else
2995 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2996 }
2997 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2998 if (on)
2999 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3000 else
3001 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3002 }
3003 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3004 if (on)
3005 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3006 else
3007 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3008 }
3009 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3010 if (on)
3011 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3012 else
3013 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3014 }
3015 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3016 if (on)
3017 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3018 else
3019 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3020 }
3021 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3022 if (on)
3023 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3024 else
3025 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3026 }
3027 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3028 if (on)
3029 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3030 else
3031 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3032 }
3033 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3034 if (on)
3035 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3036 else
3037 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3038 }
3039 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3040 if (on)
3041 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3042 else
3043 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3044 }
3045 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3046 if (on)
3047 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3048 else
3049 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3050 }
3051
3052 if (rdev->family >= CHIP_R600)
3053 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3054 else
3055 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3056}
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device, u16 caps);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
53
54/* from radeon_legacy_encoder.c */
55extern void
56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
58
59/* local */
60static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
61 u16 voltage_id, u16 *voltage);
62
63union atom_supported_devices {
64 struct _ATOM_SUPPORTED_DEVICES_INFO info;
65 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
66 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
67};
68
69static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
70 ATOM_GPIO_I2C_ASSIGMENT *gpio,
71 u8 index)
72{
73 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
74 if ((rdev->family == CHIP_R420) ||
75 (rdev->family == CHIP_R423) ||
76 (rdev->family == CHIP_RV410)) {
77 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
78 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
79 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
80 gpio->ucClkMaskShift = 0x19;
81 gpio->ucDataMaskShift = 0x18;
82 }
83 }
84
85 /* some evergreen boards have bad data for this entry */
86 if (ASIC_IS_DCE4(rdev)) {
87 if ((index == 7) &&
88 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
89 (gpio->sucI2cId.ucAccess == 0)) {
90 gpio->sucI2cId.ucAccess = 0x97;
91 gpio->ucDataMaskShift = 8;
92 gpio->ucDataEnShift = 8;
93 gpio->ucDataY_Shift = 8;
94 gpio->ucDataA_Shift = 8;
95 }
96 }
97
98 /* some DCE3 boards have bad data for this entry */
99 if (ASIC_IS_DCE3(rdev)) {
100 if ((index == 4) &&
101 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
102 (gpio->sucI2cId.ucAccess == 0x94))
103 gpio->sucI2cId.ucAccess = 0x14;
104 }
105}
106
107static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
108{
109 struct radeon_i2c_bus_rec i2c;
110
111 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
112
113 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
114 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
115 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
116 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
117 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
118 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
119 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
120 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
121 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
122 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
123 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
124 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
125 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
126 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
127 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
128 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
129
130 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
131 i2c.hw_capable = true;
132 else
133 i2c.hw_capable = false;
134
135 if (gpio->sucI2cId.ucAccess == 0xa0)
136 i2c.mm_i2c = true;
137 else
138 i2c.mm_i2c = false;
139
140 i2c.i2c_id = gpio->sucI2cId.ucAccess;
141
142 if (i2c.mask_clk_reg)
143 i2c.valid = true;
144 else
145 i2c.valid = false;
146
147 return i2c;
148}
149
150static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
151 uint8_t id)
152{
153 struct atom_context *ctx = rdev->mode_info.atom_context;
154 ATOM_GPIO_I2C_ASSIGMENT *gpio;
155 struct radeon_i2c_bus_rec i2c;
156 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
157 struct _ATOM_GPIO_I2C_INFO *i2c_info;
158 uint16_t data_offset, size;
159 int i, num_indices;
160
161 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
162 i2c.valid = false;
163
164 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
165 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
166
167 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
168 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
169
170 for (i = 0; i < num_indices; i++) {
171 gpio = &i2c_info->asGPIO_Info[i];
172
173 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
174
175 if (gpio->sucI2cId.ucAccess == id) {
176 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
177 break;
178 }
179 }
180 }
181
182 return i2c;
183}
184
185void radeon_atombios_i2c_init(struct radeon_device *rdev)
186{
187 struct atom_context *ctx = rdev->mode_info.atom_context;
188 ATOM_GPIO_I2C_ASSIGMENT *gpio;
189 struct radeon_i2c_bus_rec i2c;
190 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
191 struct _ATOM_GPIO_I2C_INFO *i2c_info;
192 uint16_t data_offset, size;
193 int i, num_indices;
194 char stmp[32];
195
196 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
197 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
198
199 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
200 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
201
202 for (i = 0; i < num_indices; i++) {
203 gpio = &i2c_info->asGPIO_Info[i];
204
205 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
206
207 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
208
209 if (i2c.valid) {
210 sprintf(stmp, "0x%x", i2c.i2c_id);
211 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
212 }
213 }
214 }
215}
216
217static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
218 u8 id)
219{
220 struct atom_context *ctx = rdev->mode_info.atom_context;
221 struct radeon_gpio_rec gpio;
222 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
223 struct _ATOM_GPIO_PIN_LUT *gpio_info;
224 ATOM_GPIO_PIN_ASSIGNMENT *pin;
225 u16 data_offset, size;
226 int i, num_indices;
227
228 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
229 gpio.valid = false;
230
231 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
232 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
233
234 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
235 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
236
237 for (i = 0; i < num_indices; i++) {
238 pin = &gpio_info->asGPIO_Pin[i];
239 if (id == pin->ucGPIO_ID) {
240 gpio.id = pin->ucGPIO_ID;
241 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
242 gpio.mask = (1 << pin->ucGpioPinBitShift);
243 gpio.valid = true;
244 break;
245 }
246 }
247 }
248
249 return gpio;
250}
251
252static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
253 struct radeon_gpio_rec *gpio)
254{
255 struct radeon_hpd hpd;
256 u32 reg;
257
258 memset(&hpd, 0, sizeof(struct radeon_hpd));
259
260 if (ASIC_IS_DCE6(rdev))
261 reg = SI_DC_GPIO_HPD_A;
262 else if (ASIC_IS_DCE4(rdev))
263 reg = EVERGREEN_DC_GPIO_HPD_A;
264 else
265 reg = AVIVO_DC_GPIO_HPD_A;
266
267 hpd.gpio = *gpio;
268 if (gpio->reg == reg) {
269 switch(gpio->mask) {
270 case (1 << 0):
271 hpd.hpd = RADEON_HPD_1;
272 break;
273 case (1 << 8):
274 hpd.hpd = RADEON_HPD_2;
275 break;
276 case (1 << 16):
277 hpd.hpd = RADEON_HPD_3;
278 break;
279 case (1 << 24):
280 hpd.hpd = RADEON_HPD_4;
281 break;
282 case (1 << 26):
283 hpd.hpd = RADEON_HPD_5;
284 break;
285 case (1 << 28):
286 hpd.hpd = RADEON_HPD_6;
287 break;
288 default:
289 hpd.hpd = RADEON_HPD_NONE;
290 break;
291 }
292 } else
293 hpd.hpd = RADEON_HPD_NONE;
294 return hpd;
295}
296
297static bool radeon_atom_apply_quirks(struct drm_device *dev,
298 uint32_t supported_device,
299 int *connector_type,
300 struct radeon_i2c_bus_rec *i2c_bus,
301 uint16_t *line_mux,
302 struct radeon_hpd *hpd)
303{
304
305 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
306 if ((dev->pdev->device == 0x791e) &&
307 (dev->pdev->subsystem_vendor == 0x1043) &&
308 (dev->pdev->subsystem_device == 0x826d)) {
309 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
310 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
311 *connector_type = DRM_MODE_CONNECTOR_DVID;
312 }
313
314 /* Asrock RS600 board lists the DVI port as HDMI */
315 if ((dev->pdev->device == 0x7941) &&
316 (dev->pdev->subsystem_vendor == 0x1849) &&
317 (dev->pdev->subsystem_device == 0x7941)) {
318 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
319 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
320 *connector_type = DRM_MODE_CONNECTOR_DVID;
321 }
322
323 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
324 if ((dev->pdev->device == 0x796e) &&
325 (dev->pdev->subsystem_vendor == 0x1462) &&
326 (dev->pdev->subsystem_device == 0x7302)) {
327 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
328 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
329 return false;
330 }
331
332 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
333 if ((dev->pdev->device == 0x7941) &&
334 (dev->pdev->subsystem_vendor == 0x147b) &&
335 (dev->pdev->subsystem_device == 0x2412)) {
336 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
337 return false;
338 }
339
340 /* Falcon NW laptop lists vga ddc line for LVDS */
341 if ((dev->pdev->device == 0x5653) &&
342 (dev->pdev->subsystem_vendor == 0x1462) &&
343 (dev->pdev->subsystem_device == 0x0291)) {
344 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
345 i2c_bus->valid = false;
346 *line_mux = 53;
347 }
348 }
349
350 /* HIS X1300 is DVI+VGA, not DVI+DVI */
351 if ((dev->pdev->device == 0x7146) &&
352 (dev->pdev->subsystem_vendor == 0x17af) &&
353 (dev->pdev->subsystem_device == 0x2058)) {
354 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
355 return false;
356 }
357
358 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
359 if ((dev->pdev->device == 0x7142) &&
360 (dev->pdev->subsystem_vendor == 0x1458) &&
361 (dev->pdev->subsystem_device == 0x2134)) {
362 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
363 return false;
364 }
365
366
367 /* Funky macbooks */
368 if ((dev->pdev->device == 0x71C5) &&
369 (dev->pdev->subsystem_vendor == 0x106b) &&
370 (dev->pdev->subsystem_device == 0x0080)) {
371 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
372 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
373 return false;
374 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
375 *line_mux = 0x90;
376 }
377
378 /* mac rv630, rv730, others */
379 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
380 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
381 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
382 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
383 }
384
385 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
386 if ((dev->pdev->device == 0x9598) &&
387 (dev->pdev->subsystem_vendor == 0x1043) &&
388 (dev->pdev->subsystem_device == 0x01da)) {
389 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
390 *connector_type = DRM_MODE_CONNECTOR_DVII;
391 }
392 }
393
394 /* ASUS HD 3600 board lists the DVI port as HDMI */
395 if ((dev->pdev->device == 0x9598) &&
396 (dev->pdev->subsystem_vendor == 0x1043) &&
397 (dev->pdev->subsystem_device == 0x01e4)) {
398 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
399 *connector_type = DRM_MODE_CONNECTOR_DVII;
400 }
401 }
402
403 /* ASUS HD 3450 board lists the DVI port as HDMI */
404 if ((dev->pdev->device == 0x95C5) &&
405 (dev->pdev->subsystem_vendor == 0x1043) &&
406 (dev->pdev->subsystem_device == 0x01e2)) {
407 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
408 *connector_type = DRM_MODE_CONNECTOR_DVII;
409 }
410 }
411
412 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
413 * HDMI + VGA reporting as HDMI
414 */
415 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
416 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
417 *connector_type = DRM_MODE_CONNECTOR_VGA;
418 *line_mux = 0;
419 }
420 }
421
422 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
423 * on the laptop and a DVI port on the docking station and
424 * both share the same encoder, hpd pin, and ddc line.
425 * So while the bios table is technically correct,
426 * we drop the DVI port here since xrandr has no concept of
427 * encoders and will try and drive both connectors
428 * with different crtcs which isn't possible on the hardware
429 * side and leaves no crtcs for LVDS or VGA.
430 */
431 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
432 (dev->pdev->subsystem_vendor == 0x1025) &&
433 (dev->pdev->subsystem_device == 0x013c)) {
434 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
435 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
436 /* actually it's a DVI-D port not DVI-I */
437 *connector_type = DRM_MODE_CONNECTOR_DVID;
438 return false;
439 }
440 }
441
442 /* XFX Pine Group device rv730 reports no VGA DDC lines
443 * even though they are wired up to record 0x93
444 */
445 if ((dev->pdev->device == 0x9498) &&
446 (dev->pdev->subsystem_vendor == 0x1682) &&
447 (dev->pdev->subsystem_device == 0x2452) &&
448 (i2c_bus->valid == false) &&
449 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
450 struct radeon_device *rdev = dev->dev_private;
451 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
452 }
453
454 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
455 if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
456 (dev->pdev->subsystem_vendor == 0x1734) &&
457 (dev->pdev->subsystem_device == 0x11bd)) {
458 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
459 *connector_type = DRM_MODE_CONNECTOR_DVII;
460 *line_mux = 0x3103;
461 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
462 *connector_type = DRM_MODE_CONNECTOR_DVII;
463 }
464 }
465
466
467 return true;
468}
469
470const int supported_devices_connector_convert[] = {
471 DRM_MODE_CONNECTOR_Unknown,
472 DRM_MODE_CONNECTOR_VGA,
473 DRM_MODE_CONNECTOR_DVII,
474 DRM_MODE_CONNECTOR_DVID,
475 DRM_MODE_CONNECTOR_DVIA,
476 DRM_MODE_CONNECTOR_SVIDEO,
477 DRM_MODE_CONNECTOR_Composite,
478 DRM_MODE_CONNECTOR_LVDS,
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_Unknown,
481 DRM_MODE_CONNECTOR_HDMIA,
482 DRM_MODE_CONNECTOR_HDMIB,
483 DRM_MODE_CONNECTOR_Unknown,
484 DRM_MODE_CONNECTOR_Unknown,
485 DRM_MODE_CONNECTOR_9PinDIN,
486 DRM_MODE_CONNECTOR_DisplayPort
487};
488
489const uint16_t supported_devices_connector_object_id_convert[] = {
490 CONNECTOR_OBJECT_ID_NONE,
491 CONNECTOR_OBJECT_ID_VGA,
492 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
493 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
494 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
495 CONNECTOR_OBJECT_ID_COMPOSITE,
496 CONNECTOR_OBJECT_ID_SVIDEO,
497 CONNECTOR_OBJECT_ID_LVDS,
498 CONNECTOR_OBJECT_ID_9PIN_DIN,
499 CONNECTOR_OBJECT_ID_9PIN_DIN,
500 CONNECTOR_OBJECT_ID_DISPLAYPORT,
501 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
502 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
503 CONNECTOR_OBJECT_ID_SVIDEO
504};
505
506const int object_connector_convert[] = {
507 DRM_MODE_CONNECTOR_Unknown,
508 DRM_MODE_CONNECTOR_DVII,
509 DRM_MODE_CONNECTOR_DVII,
510 DRM_MODE_CONNECTOR_DVID,
511 DRM_MODE_CONNECTOR_DVID,
512 DRM_MODE_CONNECTOR_VGA,
513 DRM_MODE_CONNECTOR_Composite,
514 DRM_MODE_CONNECTOR_SVIDEO,
515 DRM_MODE_CONNECTOR_Unknown,
516 DRM_MODE_CONNECTOR_Unknown,
517 DRM_MODE_CONNECTOR_9PinDIN,
518 DRM_MODE_CONNECTOR_Unknown,
519 DRM_MODE_CONNECTOR_HDMIA,
520 DRM_MODE_CONNECTOR_HDMIB,
521 DRM_MODE_CONNECTOR_LVDS,
522 DRM_MODE_CONNECTOR_9PinDIN,
523 DRM_MODE_CONNECTOR_Unknown,
524 DRM_MODE_CONNECTOR_Unknown,
525 DRM_MODE_CONNECTOR_Unknown,
526 DRM_MODE_CONNECTOR_DisplayPort,
527 DRM_MODE_CONNECTOR_eDP,
528 DRM_MODE_CONNECTOR_Unknown
529};
530
531bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
532{
533 struct radeon_device *rdev = dev->dev_private;
534 struct radeon_mode_info *mode_info = &rdev->mode_info;
535 struct atom_context *ctx = mode_info->atom_context;
536 int index = GetIndexIntoMasterTable(DATA, Object_Header);
537 u16 size, data_offset;
538 u8 frev, crev;
539 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
540 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
541 ATOM_OBJECT_TABLE *router_obj;
542 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
543 ATOM_OBJECT_HEADER *obj_header;
544 int i, j, k, path_size, device_support;
545 int connector_type;
546 u16 igp_lane_info, conn_id, connector_object_id;
547 struct radeon_i2c_bus_rec ddc_bus;
548 struct radeon_router router;
549 struct radeon_gpio_rec gpio;
550 struct radeon_hpd hpd;
551
552 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
553 return false;
554
555 if (crev < 2)
556 return false;
557
558 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
559 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
560 (ctx->bios + data_offset +
561 le16_to_cpu(obj_header->usDisplayPathTableOffset));
562 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
563 (ctx->bios + data_offset +
564 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
565 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
566 (ctx->bios + data_offset +
567 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
568 router_obj = (ATOM_OBJECT_TABLE *)
569 (ctx->bios + data_offset +
570 le16_to_cpu(obj_header->usRouterObjectTableOffset));
571 device_support = le16_to_cpu(obj_header->usDeviceSupport);
572
573 path_size = 0;
574 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
575 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
576 ATOM_DISPLAY_OBJECT_PATH *path;
577 addr += path_size;
578 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
579 path_size += le16_to_cpu(path->usSize);
580
581 if (device_support & le16_to_cpu(path->usDeviceTag)) {
582 uint8_t con_obj_id, con_obj_num, con_obj_type;
583
584 con_obj_id =
585 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
586 >> OBJECT_ID_SHIFT;
587 con_obj_num =
588 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
589 >> ENUM_ID_SHIFT;
590 con_obj_type =
591 (le16_to_cpu(path->usConnObjectId) &
592 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
593
594 /* TODO CV support */
595 if (le16_to_cpu(path->usDeviceTag) ==
596 ATOM_DEVICE_CV_SUPPORT)
597 continue;
598
599 /* IGP chips */
600 if ((rdev->flags & RADEON_IS_IGP) &&
601 (con_obj_id ==
602 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
603 uint16_t igp_offset = 0;
604 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
605
606 index =
607 GetIndexIntoMasterTable(DATA,
608 IntegratedSystemInfo);
609
610 if (atom_parse_data_header(ctx, index, &size, &frev,
611 &crev, &igp_offset)) {
612
613 if (crev >= 2) {
614 igp_obj =
615 (ATOM_INTEGRATED_SYSTEM_INFO_V2
616 *) (ctx->bios + igp_offset);
617
618 if (igp_obj) {
619 uint32_t slot_config, ct;
620
621 if (con_obj_num == 1)
622 slot_config =
623 igp_obj->
624 ulDDISlot1Config;
625 else
626 slot_config =
627 igp_obj->
628 ulDDISlot2Config;
629
630 ct = (slot_config >> 16) & 0xff;
631 connector_type =
632 object_connector_convert
633 [ct];
634 connector_object_id = ct;
635 igp_lane_info =
636 slot_config & 0xffff;
637 } else
638 continue;
639 } else
640 continue;
641 } else {
642 igp_lane_info = 0;
643 connector_type =
644 object_connector_convert[con_obj_id];
645 connector_object_id = con_obj_id;
646 }
647 } else {
648 igp_lane_info = 0;
649 connector_type =
650 object_connector_convert[con_obj_id];
651 connector_object_id = con_obj_id;
652 }
653
654 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
655 continue;
656
657 router.ddc_valid = false;
658 router.cd_valid = false;
659 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
660 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
661
662 grph_obj_id =
663 (le16_to_cpu(path->usGraphicObjIds[j]) &
664 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
665 grph_obj_num =
666 (le16_to_cpu(path->usGraphicObjIds[j]) &
667 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
668 grph_obj_type =
669 (le16_to_cpu(path->usGraphicObjIds[j]) &
670 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
671
672 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
673 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
674 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
675 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
676 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
677 (ctx->bios + data_offset +
678 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
679 ATOM_ENCODER_CAP_RECORD *cap_record;
680 u16 caps = 0;
681
682 while (record->ucRecordSize > 0 &&
683 record->ucRecordType > 0 &&
684 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
685 switch (record->ucRecordType) {
686 case ATOM_ENCODER_CAP_RECORD_TYPE:
687 cap_record =(ATOM_ENCODER_CAP_RECORD *)
688 record;
689 caps = le16_to_cpu(cap_record->usEncoderCap);
690 break;
691 }
692 record = (ATOM_COMMON_RECORD_HEADER *)
693 ((char *)record + record->ucRecordSize);
694 }
695 radeon_add_atom_encoder(dev,
696 encoder_obj,
697 le16_to_cpu
698 (path->
699 usDeviceTag),
700 caps);
701 }
702 }
703 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
704 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
705 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
706 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
707 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
708 (ctx->bios + data_offset +
709 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
710 ATOM_I2C_RECORD *i2c_record;
711 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
712 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
713 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
714 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
715 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
716 (ctx->bios + data_offset +
717 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
718 int enum_id;
719
720 router.router_id = router_obj_id;
721 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
722 enum_id++) {
723 if (le16_to_cpu(path->usConnObjectId) ==
724 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
725 break;
726 }
727
728 while (record->ucRecordSize > 0 &&
729 record->ucRecordType > 0 &&
730 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
731 switch (record->ucRecordType) {
732 case ATOM_I2C_RECORD_TYPE:
733 i2c_record =
734 (ATOM_I2C_RECORD *)
735 record;
736 i2c_config =
737 (ATOM_I2C_ID_CONFIG_ACCESS *)
738 &i2c_record->sucI2cId;
739 router.i2c_info =
740 radeon_lookup_i2c_gpio(rdev,
741 i2c_config->
742 ucAccess);
743 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
744 break;
745 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
746 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
747 record;
748 router.ddc_valid = true;
749 router.ddc_mux_type = ddc_path->ucMuxType;
750 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
751 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
752 break;
753 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
754 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
755 record;
756 router.cd_valid = true;
757 router.cd_mux_type = cd_path->ucMuxType;
758 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
759 router.cd_mux_state = cd_path->ucMuxState[enum_id];
760 break;
761 }
762 record = (ATOM_COMMON_RECORD_HEADER *)
763 ((char *)record + record->ucRecordSize);
764 }
765 }
766 }
767 }
768 }
769
770 /* look up gpio for ddc, hpd */
771 ddc_bus.valid = false;
772 hpd.hpd = RADEON_HPD_NONE;
773 if ((le16_to_cpu(path->usDeviceTag) &
774 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
775 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
776 if (le16_to_cpu(path->usConnObjectId) ==
777 le16_to_cpu(con_obj->asObjects[j].
778 usObjectID)) {
779 ATOM_COMMON_RECORD_HEADER
780 *record =
781 (ATOM_COMMON_RECORD_HEADER
782 *)
783 (ctx->bios + data_offset +
784 le16_to_cpu(con_obj->
785 asObjects[j].
786 usRecordOffset));
787 ATOM_I2C_RECORD *i2c_record;
788 ATOM_HPD_INT_RECORD *hpd_record;
789 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
790
791 while (record->ucRecordSize > 0 &&
792 record->ucRecordType > 0 &&
793 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
794 switch (record->ucRecordType) {
795 case ATOM_I2C_RECORD_TYPE:
796 i2c_record =
797 (ATOM_I2C_RECORD *)
798 record;
799 i2c_config =
800 (ATOM_I2C_ID_CONFIG_ACCESS *)
801 &i2c_record->sucI2cId;
802 ddc_bus = radeon_lookup_i2c_gpio(rdev,
803 i2c_config->
804 ucAccess);
805 break;
806 case ATOM_HPD_INT_RECORD_TYPE:
807 hpd_record =
808 (ATOM_HPD_INT_RECORD *)
809 record;
810 gpio = radeon_lookup_gpio(rdev,
811 hpd_record->ucHPDIntGPIOID);
812 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
813 hpd.plugged_state = hpd_record->ucPlugged_PinState;
814 break;
815 }
816 record =
817 (ATOM_COMMON_RECORD_HEADER
818 *) ((char *)record
819 +
820 record->
821 ucRecordSize);
822 }
823 break;
824 }
825 }
826 }
827
828 /* needed for aux chan transactions */
829 ddc_bus.hpd = hpd.hpd;
830
831 conn_id = le16_to_cpu(path->usConnObjectId);
832
833 if (!radeon_atom_apply_quirks
834 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
835 &ddc_bus, &conn_id, &hpd))
836 continue;
837
838 radeon_add_atom_connector(dev,
839 conn_id,
840 le16_to_cpu(path->
841 usDeviceTag),
842 connector_type, &ddc_bus,
843 igp_lane_info,
844 connector_object_id,
845 &hpd,
846 &router);
847
848 }
849 }
850
851 radeon_link_encoder_connector(dev);
852
853 return true;
854}
855
856static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
857 int connector_type,
858 uint16_t devices)
859{
860 struct radeon_device *rdev = dev->dev_private;
861
862 if (rdev->flags & RADEON_IS_IGP) {
863 return supported_devices_connector_object_id_convert
864 [connector_type];
865 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
866 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
867 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
868 struct radeon_mode_info *mode_info = &rdev->mode_info;
869 struct atom_context *ctx = mode_info->atom_context;
870 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
871 uint16_t size, data_offset;
872 uint8_t frev, crev;
873 ATOM_XTMDS_INFO *xtmds;
874
875 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
876 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
877
878 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
879 if (connector_type == DRM_MODE_CONNECTOR_DVII)
880 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
881 else
882 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
883 } else {
884 if (connector_type == DRM_MODE_CONNECTOR_DVII)
885 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
886 else
887 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
888 }
889 } else
890 return supported_devices_connector_object_id_convert
891 [connector_type];
892 } else {
893 return supported_devices_connector_object_id_convert
894 [connector_type];
895 }
896}
897
898struct bios_connector {
899 bool valid;
900 uint16_t line_mux;
901 uint16_t devices;
902 int connector_type;
903 struct radeon_i2c_bus_rec ddc_bus;
904 struct radeon_hpd hpd;
905};
906
907bool radeon_get_atom_connector_info_from_supported_devices_table(struct
908 drm_device
909 *dev)
910{
911 struct radeon_device *rdev = dev->dev_private;
912 struct radeon_mode_info *mode_info = &rdev->mode_info;
913 struct atom_context *ctx = mode_info->atom_context;
914 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
915 uint16_t size, data_offset;
916 uint8_t frev, crev;
917 uint16_t device_support;
918 uint8_t dac;
919 union atom_supported_devices *supported_devices;
920 int i, j, max_device;
921 struct bios_connector *bios_connectors;
922 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
923 struct radeon_router router;
924
925 router.ddc_valid = false;
926 router.cd_valid = false;
927
928 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
929 if (!bios_connectors)
930 return false;
931
932 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
933 &data_offset)) {
934 kfree(bios_connectors);
935 return false;
936 }
937
938 supported_devices =
939 (union atom_supported_devices *)(ctx->bios + data_offset);
940
941 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
942
943 if (frev > 1)
944 max_device = ATOM_MAX_SUPPORTED_DEVICE;
945 else
946 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
947
948 for (i = 0; i < max_device; i++) {
949 ATOM_CONNECTOR_INFO_I2C ci =
950 supported_devices->info.asConnInfo[i];
951
952 bios_connectors[i].valid = false;
953
954 if (!(device_support & (1 << i))) {
955 continue;
956 }
957
958 if (i == ATOM_DEVICE_CV_INDEX) {
959 DRM_DEBUG_KMS("Skipping Component Video\n");
960 continue;
961 }
962
963 bios_connectors[i].connector_type =
964 supported_devices_connector_convert[ci.sucConnectorInfo.
965 sbfAccess.
966 bfConnectorType];
967
968 if (bios_connectors[i].connector_type ==
969 DRM_MODE_CONNECTOR_Unknown)
970 continue;
971
972 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
973
974 bios_connectors[i].line_mux =
975 ci.sucI2cId.ucAccess;
976
977 /* give tv unique connector ids */
978 if (i == ATOM_DEVICE_TV1_INDEX) {
979 bios_connectors[i].ddc_bus.valid = false;
980 bios_connectors[i].line_mux = 50;
981 } else if (i == ATOM_DEVICE_TV2_INDEX) {
982 bios_connectors[i].ddc_bus.valid = false;
983 bios_connectors[i].line_mux = 51;
984 } else if (i == ATOM_DEVICE_CV_INDEX) {
985 bios_connectors[i].ddc_bus.valid = false;
986 bios_connectors[i].line_mux = 52;
987 } else
988 bios_connectors[i].ddc_bus =
989 radeon_lookup_i2c_gpio(rdev,
990 bios_connectors[i].line_mux);
991
992 if ((crev > 1) && (frev > 1)) {
993 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
994 switch (isb) {
995 case 0x4:
996 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
997 break;
998 case 0xa:
999 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1000 break;
1001 default:
1002 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1003 break;
1004 }
1005 } else {
1006 if (i == ATOM_DEVICE_DFP1_INDEX)
1007 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1008 else if (i == ATOM_DEVICE_DFP2_INDEX)
1009 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1010 else
1011 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1012 }
1013
1014 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1015 * shared with a DVI port, we'll pick up the DVI connector when we
1016 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1017 */
1018 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1019 bios_connectors[i].connector_type =
1020 DRM_MODE_CONNECTOR_VGA;
1021
1022 if (!radeon_atom_apply_quirks
1023 (dev, (1 << i), &bios_connectors[i].connector_type,
1024 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1025 &bios_connectors[i].hpd))
1026 continue;
1027
1028 bios_connectors[i].valid = true;
1029 bios_connectors[i].devices = (1 << i);
1030
1031 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1032 radeon_add_atom_encoder(dev,
1033 radeon_get_encoder_enum(dev,
1034 (1 << i),
1035 dac),
1036 (1 << i),
1037 0);
1038 else
1039 radeon_add_legacy_encoder(dev,
1040 radeon_get_encoder_enum(dev,
1041 (1 << i),
1042 dac),
1043 (1 << i));
1044 }
1045
1046 /* combine shared connectors */
1047 for (i = 0; i < max_device; i++) {
1048 if (bios_connectors[i].valid) {
1049 for (j = 0; j < max_device; j++) {
1050 if (bios_connectors[j].valid && (i != j)) {
1051 if (bios_connectors[i].line_mux ==
1052 bios_connectors[j].line_mux) {
1053 /* make sure not to combine LVDS */
1054 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1055 bios_connectors[i].line_mux = 53;
1056 bios_connectors[i].ddc_bus.valid = false;
1057 continue;
1058 }
1059 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1060 bios_connectors[j].line_mux = 53;
1061 bios_connectors[j].ddc_bus.valid = false;
1062 continue;
1063 }
1064 /* combine analog and digital for DVI-I */
1065 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1066 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1067 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1068 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1069 bios_connectors[i].devices |=
1070 bios_connectors[j].devices;
1071 bios_connectors[i].connector_type =
1072 DRM_MODE_CONNECTOR_DVII;
1073 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1074 bios_connectors[i].hpd =
1075 bios_connectors[j].hpd;
1076 bios_connectors[j].valid = false;
1077 }
1078 }
1079 }
1080 }
1081 }
1082 }
1083
1084 /* add the connectors */
1085 for (i = 0; i < max_device; i++) {
1086 if (bios_connectors[i].valid) {
1087 uint16_t connector_object_id =
1088 atombios_get_connector_object_id(dev,
1089 bios_connectors[i].connector_type,
1090 bios_connectors[i].devices);
1091 radeon_add_atom_connector(dev,
1092 bios_connectors[i].line_mux,
1093 bios_connectors[i].devices,
1094 bios_connectors[i].
1095 connector_type,
1096 &bios_connectors[i].ddc_bus,
1097 0,
1098 connector_object_id,
1099 &bios_connectors[i].hpd,
1100 &router);
1101 }
1102 }
1103
1104 radeon_link_encoder_connector(dev);
1105
1106 kfree(bios_connectors);
1107 return true;
1108}
1109
1110union firmware_info {
1111 ATOM_FIRMWARE_INFO info;
1112 ATOM_FIRMWARE_INFO_V1_2 info_12;
1113 ATOM_FIRMWARE_INFO_V1_3 info_13;
1114 ATOM_FIRMWARE_INFO_V1_4 info_14;
1115 ATOM_FIRMWARE_INFO_V2_1 info_21;
1116 ATOM_FIRMWARE_INFO_V2_2 info_22;
1117};
1118
1119bool radeon_atom_get_clock_info(struct drm_device *dev)
1120{
1121 struct radeon_device *rdev = dev->dev_private;
1122 struct radeon_mode_info *mode_info = &rdev->mode_info;
1123 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1124 union firmware_info *firmware_info;
1125 uint8_t frev, crev;
1126 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1127 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1128 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1129 struct radeon_pll *spll = &rdev->clock.spll;
1130 struct radeon_pll *mpll = &rdev->clock.mpll;
1131 uint16_t data_offset;
1132
1133 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1134 &frev, &crev, &data_offset)) {
1135 firmware_info =
1136 (union firmware_info *)(mode_info->atom_context->bios +
1137 data_offset);
1138 /* pixel clocks */
1139 p1pll->reference_freq =
1140 le16_to_cpu(firmware_info->info.usReferenceClock);
1141 p1pll->reference_div = 0;
1142
1143 if (crev < 2)
1144 p1pll->pll_out_min =
1145 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1146 else
1147 p1pll->pll_out_min =
1148 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1149 p1pll->pll_out_max =
1150 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1151
1152 if (crev >= 4) {
1153 p1pll->lcd_pll_out_min =
1154 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1155 if (p1pll->lcd_pll_out_min == 0)
1156 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1157 p1pll->lcd_pll_out_max =
1158 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1159 if (p1pll->lcd_pll_out_max == 0)
1160 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1161 } else {
1162 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1163 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1164 }
1165
1166 if (p1pll->pll_out_min == 0) {
1167 if (ASIC_IS_AVIVO(rdev))
1168 p1pll->pll_out_min = 64800;
1169 else
1170 p1pll->pll_out_min = 20000;
1171 }
1172
1173 p1pll->pll_in_min =
1174 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1175 p1pll->pll_in_max =
1176 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1177
1178 *p2pll = *p1pll;
1179
1180 /* system clock */
1181 if (ASIC_IS_DCE4(rdev))
1182 spll->reference_freq =
1183 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1184 else
1185 spll->reference_freq =
1186 le16_to_cpu(firmware_info->info.usReferenceClock);
1187 spll->reference_div = 0;
1188
1189 spll->pll_out_min =
1190 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1191 spll->pll_out_max =
1192 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1193
1194 /* ??? */
1195 if (spll->pll_out_min == 0) {
1196 if (ASIC_IS_AVIVO(rdev))
1197 spll->pll_out_min = 64800;
1198 else
1199 spll->pll_out_min = 20000;
1200 }
1201
1202 spll->pll_in_min =
1203 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1204 spll->pll_in_max =
1205 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1206
1207 /* memory clock */
1208 if (ASIC_IS_DCE4(rdev))
1209 mpll->reference_freq =
1210 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1211 else
1212 mpll->reference_freq =
1213 le16_to_cpu(firmware_info->info.usReferenceClock);
1214 mpll->reference_div = 0;
1215
1216 mpll->pll_out_min =
1217 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1218 mpll->pll_out_max =
1219 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1220
1221 /* ??? */
1222 if (mpll->pll_out_min == 0) {
1223 if (ASIC_IS_AVIVO(rdev))
1224 mpll->pll_out_min = 64800;
1225 else
1226 mpll->pll_out_min = 20000;
1227 }
1228
1229 mpll->pll_in_min =
1230 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1231 mpll->pll_in_max =
1232 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1233
1234 rdev->clock.default_sclk =
1235 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1236 rdev->clock.default_mclk =
1237 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1238
1239 if (ASIC_IS_DCE4(rdev)) {
1240 rdev->clock.default_dispclk =
1241 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1242 if (rdev->clock.default_dispclk == 0) {
1243 if (ASIC_IS_DCE5(rdev))
1244 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1245 else
1246 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1247 }
1248 rdev->clock.dp_extclk =
1249 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1250 }
1251 *dcpll = *p1pll;
1252
1253 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1254 if (rdev->clock.max_pixel_clock == 0)
1255 rdev->clock.max_pixel_clock = 40000;
1256
1257 return true;
1258 }
1259
1260 return false;
1261}
1262
1263union igp_info {
1264 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1265 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1266};
1267
1268bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1269{
1270 struct radeon_mode_info *mode_info = &rdev->mode_info;
1271 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1272 union igp_info *igp_info;
1273 u8 frev, crev;
1274 u16 data_offset;
1275
1276 /* sideport is AMD only */
1277 if (rdev->family == CHIP_RS600)
1278 return false;
1279
1280 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1281 &frev, &crev, &data_offset)) {
1282 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1283 data_offset);
1284 switch (crev) {
1285 case 1:
1286 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1287 return true;
1288 break;
1289 case 2:
1290 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1291 return true;
1292 break;
1293 default:
1294 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1295 break;
1296 }
1297 }
1298 return false;
1299}
1300
1301bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1302 struct radeon_encoder_int_tmds *tmds)
1303{
1304 struct drm_device *dev = encoder->base.dev;
1305 struct radeon_device *rdev = dev->dev_private;
1306 struct radeon_mode_info *mode_info = &rdev->mode_info;
1307 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1308 uint16_t data_offset;
1309 struct _ATOM_TMDS_INFO *tmds_info;
1310 uint8_t frev, crev;
1311 uint16_t maxfreq;
1312 int i;
1313
1314 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1315 &frev, &crev, &data_offset)) {
1316 tmds_info =
1317 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1318 data_offset);
1319
1320 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1321 for (i = 0; i < 4; i++) {
1322 tmds->tmds_pll[i].freq =
1323 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1324 tmds->tmds_pll[i].value =
1325 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1326 tmds->tmds_pll[i].value |=
1327 (tmds_info->asMiscInfo[i].
1328 ucPLL_VCO_Gain & 0x3f) << 6;
1329 tmds->tmds_pll[i].value |=
1330 (tmds_info->asMiscInfo[i].
1331 ucPLL_DutyCycle & 0xf) << 12;
1332 tmds->tmds_pll[i].value |=
1333 (tmds_info->asMiscInfo[i].
1334 ucPLL_VoltageSwing & 0xf) << 16;
1335
1336 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1337 tmds->tmds_pll[i].freq,
1338 tmds->tmds_pll[i].value);
1339
1340 if (maxfreq == tmds->tmds_pll[i].freq) {
1341 tmds->tmds_pll[i].freq = 0xffffffff;
1342 break;
1343 }
1344 }
1345 return true;
1346 }
1347 return false;
1348}
1349
1350bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1351 struct radeon_atom_ss *ss,
1352 int id)
1353{
1354 struct radeon_mode_info *mode_info = &rdev->mode_info;
1355 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1356 uint16_t data_offset, size;
1357 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1358 uint8_t frev, crev;
1359 int i, num_indices;
1360
1361 memset(ss, 0, sizeof(struct radeon_atom_ss));
1362 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1363 &frev, &crev, &data_offset)) {
1364 ss_info =
1365 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1366
1367 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1368 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1369
1370 for (i = 0; i < num_indices; i++) {
1371 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1372 ss->percentage =
1373 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1374 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1375 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1376 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1377 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1378 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1379 return true;
1380 }
1381 }
1382 }
1383 return false;
1384}
1385
1386static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1387 struct radeon_atom_ss *ss,
1388 int id)
1389{
1390 struct radeon_mode_info *mode_info = &rdev->mode_info;
1391 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1392 u16 data_offset, size;
1393 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1394 u8 frev, crev;
1395 u16 percentage = 0, rate = 0;
1396
1397 /* get any igp specific overrides */
1398 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1399 &frev, &crev, &data_offset)) {
1400 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1401 (mode_info->atom_context->bios + data_offset);
1402 switch (id) {
1403 case ASIC_INTERNAL_SS_ON_TMDS:
1404 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1405 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1406 break;
1407 case ASIC_INTERNAL_SS_ON_HDMI:
1408 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1409 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1410 break;
1411 case ASIC_INTERNAL_SS_ON_LVDS:
1412 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1413 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1414 break;
1415 }
1416 if (percentage)
1417 ss->percentage = percentage;
1418 if (rate)
1419 ss->rate = rate;
1420 }
1421}
1422
1423union asic_ss_info {
1424 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1425 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1426 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1427};
1428
1429bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1430 struct radeon_atom_ss *ss,
1431 int id, u32 clock)
1432{
1433 struct radeon_mode_info *mode_info = &rdev->mode_info;
1434 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1435 uint16_t data_offset, size;
1436 union asic_ss_info *ss_info;
1437 uint8_t frev, crev;
1438 int i, num_indices;
1439
1440 memset(ss, 0, sizeof(struct radeon_atom_ss));
1441 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1442 &frev, &crev, &data_offset)) {
1443
1444 ss_info =
1445 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1446
1447 switch (frev) {
1448 case 1:
1449 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1450 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1451
1452 for (i = 0; i < num_indices; i++) {
1453 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1454 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1455 ss->percentage =
1456 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1457 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1458 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1459 return true;
1460 }
1461 }
1462 break;
1463 case 2:
1464 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1465 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1466 for (i = 0; i < num_indices; i++) {
1467 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1468 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1469 ss->percentage =
1470 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1471 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1472 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1473 return true;
1474 }
1475 }
1476 break;
1477 case 3:
1478 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1479 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1480 for (i = 0; i < num_indices; i++) {
1481 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1482 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1483 ss->percentage =
1484 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1485 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1486 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1487 if (rdev->flags & RADEON_IS_IGP)
1488 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1489 return true;
1490 }
1491 }
1492 break;
1493 default:
1494 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1495 break;
1496 }
1497
1498 }
1499 return false;
1500}
1501
1502union lvds_info {
1503 struct _ATOM_LVDS_INFO info;
1504 struct _ATOM_LVDS_INFO_V12 info_12;
1505};
1506
1507struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1508 radeon_encoder
1509 *encoder)
1510{
1511 struct drm_device *dev = encoder->base.dev;
1512 struct radeon_device *rdev = dev->dev_private;
1513 struct radeon_mode_info *mode_info = &rdev->mode_info;
1514 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1515 uint16_t data_offset, misc;
1516 union lvds_info *lvds_info;
1517 uint8_t frev, crev;
1518 struct radeon_encoder_atom_dig *lvds = NULL;
1519 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1520
1521 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1522 &frev, &crev, &data_offset)) {
1523 lvds_info =
1524 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1525 lvds =
1526 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1527
1528 if (!lvds)
1529 return NULL;
1530
1531 lvds->native_mode.clock =
1532 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1533 lvds->native_mode.hdisplay =
1534 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1535 lvds->native_mode.vdisplay =
1536 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1537 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1538 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1539 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1540 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1541 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1542 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1543 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1544 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1545 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1546 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1547 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1548 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1549 lvds->panel_pwr_delay =
1550 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1551 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1552
1553 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1554 if (misc & ATOM_VSYNC_POLARITY)
1555 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1556 if (misc & ATOM_HSYNC_POLARITY)
1557 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1558 if (misc & ATOM_COMPOSITESYNC)
1559 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1560 if (misc & ATOM_INTERLACE)
1561 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1562 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1563 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1564
1565 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1566 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1567
1568 /* set crtc values */
1569 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1570
1571 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1572
1573 encoder->native_mode = lvds->native_mode;
1574
1575 if (encoder_enum == 2)
1576 lvds->linkb = true;
1577 else
1578 lvds->linkb = false;
1579
1580 /* parse the lcd record table */
1581 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1582 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1583 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1584 bool bad_record = false;
1585 u8 *record;
1586
1587 if ((frev == 1) && (crev < 2))
1588 /* absolute */
1589 record = (u8 *)(mode_info->atom_context->bios +
1590 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1591 else
1592 /* relative */
1593 record = (u8 *)(mode_info->atom_context->bios +
1594 data_offset +
1595 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1596 while (*record != ATOM_RECORD_END_TYPE) {
1597 switch (*record) {
1598 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1599 record += sizeof(ATOM_PATCH_RECORD_MODE);
1600 break;
1601 case LCD_RTS_RECORD_TYPE:
1602 record += sizeof(ATOM_LCD_RTS_RECORD);
1603 break;
1604 case LCD_CAP_RECORD_TYPE:
1605 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1606 break;
1607 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1608 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1609 if (fake_edid_record->ucFakeEDIDLength) {
1610 struct edid *edid;
1611 int edid_size =
1612 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1613 edid = kmalloc(edid_size, GFP_KERNEL);
1614 if (edid) {
1615 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1616 fake_edid_record->ucFakeEDIDLength);
1617
1618 if (drm_edid_is_valid(edid)) {
1619 rdev->mode_info.bios_hardcoded_edid = edid;
1620 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1621 } else
1622 kfree(edid);
1623 }
1624 }
1625 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1626 break;
1627 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1628 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1629 lvds->native_mode.width_mm = panel_res_record->usHSize;
1630 lvds->native_mode.height_mm = panel_res_record->usVSize;
1631 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1632 break;
1633 default:
1634 DRM_ERROR("Bad LCD record %d\n", *record);
1635 bad_record = true;
1636 break;
1637 }
1638 if (bad_record)
1639 break;
1640 }
1641 }
1642 }
1643 return lvds;
1644}
1645
1646struct radeon_encoder_primary_dac *
1647radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1648{
1649 struct drm_device *dev = encoder->base.dev;
1650 struct radeon_device *rdev = dev->dev_private;
1651 struct radeon_mode_info *mode_info = &rdev->mode_info;
1652 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1653 uint16_t data_offset;
1654 struct _COMPASSIONATE_DATA *dac_info;
1655 uint8_t frev, crev;
1656 uint8_t bg, dac;
1657 struct radeon_encoder_primary_dac *p_dac = NULL;
1658
1659 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1660 &frev, &crev, &data_offset)) {
1661 dac_info = (struct _COMPASSIONATE_DATA *)
1662 (mode_info->atom_context->bios + data_offset);
1663
1664 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1665
1666 if (!p_dac)
1667 return NULL;
1668
1669 bg = dac_info->ucDAC1_BG_Adjustment;
1670 dac = dac_info->ucDAC1_DAC_Adjustment;
1671 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1672
1673 }
1674 return p_dac;
1675}
1676
1677bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1678 struct drm_display_mode *mode)
1679{
1680 struct radeon_mode_info *mode_info = &rdev->mode_info;
1681 ATOM_ANALOG_TV_INFO *tv_info;
1682 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1683 ATOM_DTD_FORMAT *dtd_timings;
1684 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1685 u8 frev, crev;
1686 u16 data_offset, misc;
1687
1688 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1689 &frev, &crev, &data_offset))
1690 return false;
1691
1692 switch (crev) {
1693 case 1:
1694 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1695 if (index >= MAX_SUPPORTED_TV_TIMING)
1696 return false;
1697
1698 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1699 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1700 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1701 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1702 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1703
1704 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1705 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1706 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1707 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1708 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1709
1710 mode->flags = 0;
1711 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1712 if (misc & ATOM_VSYNC_POLARITY)
1713 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1714 if (misc & ATOM_HSYNC_POLARITY)
1715 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1716 if (misc & ATOM_COMPOSITESYNC)
1717 mode->flags |= DRM_MODE_FLAG_CSYNC;
1718 if (misc & ATOM_INTERLACE)
1719 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1720 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1721 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1722
1723 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1724
1725 if (index == 1) {
1726 /* PAL timings appear to have wrong values for totals */
1727 mode->crtc_htotal -= 1;
1728 mode->crtc_vtotal -= 1;
1729 }
1730 break;
1731 case 2:
1732 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1733 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1734 return false;
1735
1736 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1737 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1738 le16_to_cpu(dtd_timings->usHBlanking_Time);
1739 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1740 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1741 le16_to_cpu(dtd_timings->usHSyncOffset);
1742 mode->crtc_hsync_end = mode->crtc_hsync_start +
1743 le16_to_cpu(dtd_timings->usHSyncWidth);
1744
1745 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1746 le16_to_cpu(dtd_timings->usVBlanking_Time);
1747 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1748 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1749 le16_to_cpu(dtd_timings->usVSyncOffset);
1750 mode->crtc_vsync_end = mode->crtc_vsync_start +
1751 le16_to_cpu(dtd_timings->usVSyncWidth);
1752
1753 mode->flags = 0;
1754 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1755 if (misc & ATOM_VSYNC_POLARITY)
1756 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1757 if (misc & ATOM_HSYNC_POLARITY)
1758 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1759 if (misc & ATOM_COMPOSITESYNC)
1760 mode->flags |= DRM_MODE_FLAG_CSYNC;
1761 if (misc & ATOM_INTERLACE)
1762 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1763 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1764 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1765
1766 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1767 break;
1768 }
1769 return true;
1770}
1771
1772enum radeon_tv_std
1773radeon_atombios_get_tv_info(struct radeon_device *rdev)
1774{
1775 struct radeon_mode_info *mode_info = &rdev->mode_info;
1776 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1777 uint16_t data_offset;
1778 uint8_t frev, crev;
1779 struct _ATOM_ANALOG_TV_INFO *tv_info;
1780 enum radeon_tv_std tv_std = TV_STD_NTSC;
1781
1782 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1783 &frev, &crev, &data_offset)) {
1784
1785 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1786 (mode_info->atom_context->bios + data_offset);
1787
1788 switch (tv_info->ucTV_BootUpDefaultStandard) {
1789 case ATOM_TV_NTSC:
1790 tv_std = TV_STD_NTSC;
1791 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1792 break;
1793 case ATOM_TV_NTSCJ:
1794 tv_std = TV_STD_NTSC_J;
1795 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1796 break;
1797 case ATOM_TV_PAL:
1798 tv_std = TV_STD_PAL;
1799 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1800 break;
1801 case ATOM_TV_PALM:
1802 tv_std = TV_STD_PAL_M;
1803 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1804 break;
1805 case ATOM_TV_PALN:
1806 tv_std = TV_STD_PAL_N;
1807 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1808 break;
1809 case ATOM_TV_PALCN:
1810 tv_std = TV_STD_PAL_CN;
1811 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1812 break;
1813 case ATOM_TV_PAL60:
1814 tv_std = TV_STD_PAL_60;
1815 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1816 break;
1817 case ATOM_TV_SECAM:
1818 tv_std = TV_STD_SECAM;
1819 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1820 break;
1821 default:
1822 tv_std = TV_STD_NTSC;
1823 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1824 break;
1825 }
1826 }
1827 return tv_std;
1828}
1829
1830struct radeon_encoder_tv_dac *
1831radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1832{
1833 struct drm_device *dev = encoder->base.dev;
1834 struct radeon_device *rdev = dev->dev_private;
1835 struct radeon_mode_info *mode_info = &rdev->mode_info;
1836 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1837 uint16_t data_offset;
1838 struct _COMPASSIONATE_DATA *dac_info;
1839 uint8_t frev, crev;
1840 uint8_t bg, dac;
1841 struct radeon_encoder_tv_dac *tv_dac = NULL;
1842
1843 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1844 &frev, &crev, &data_offset)) {
1845
1846 dac_info = (struct _COMPASSIONATE_DATA *)
1847 (mode_info->atom_context->bios + data_offset);
1848
1849 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1850
1851 if (!tv_dac)
1852 return NULL;
1853
1854 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1855 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1856 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1857
1858 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1859 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1860 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1861
1862 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1863 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1864 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1865
1866 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1867 }
1868 return tv_dac;
1869}
1870
1871static const char *thermal_controller_names[] = {
1872 "NONE",
1873 "lm63",
1874 "adm1032",
1875 "adm1030",
1876 "max6649",
1877 "lm64",
1878 "f75375",
1879 "asc7xxx",
1880};
1881
1882static const char *pp_lib_thermal_controller_names[] = {
1883 "NONE",
1884 "lm63",
1885 "adm1032",
1886 "adm1030",
1887 "max6649",
1888 "lm64",
1889 "f75375",
1890 "RV6xx",
1891 "RV770",
1892 "adt7473",
1893 "NONE",
1894 "External GPIO",
1895 "Evergreen",
1896 "emc2103",
1897 "Sumo",
1898 "Northern Islands",
1899 "Southern Islands",
1900 "lm96163",
1901};
1902
1903union power_info {
1904 struct _ATOM_POWERPLAY_INFO info;
1905 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1906 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1907 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1908 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1909 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1910};
1911
1912union pplib_clock_info {
1913 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1914 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1915 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1916 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1917 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
1918};
1919
1920union pplib_power_state {
1921 struct _ATOM_PPLIB_STATE v1;
1922 struct _ATOM_PPLIB_STATE_V2 v2;
1923};
1924
1925static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1926 int state_index,
1927 u32 misc, u32 misc2)
1928{
1929 rdev->pm.power_state[state_index].misc = misc;
1930 rdev->pm.power_state[state_index].misc2 = misc2;
1931 /* order matters! */
1932 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1933 rdev->pm.power_state[state_index].type =
1934 POWER_STATE_TYPE_POWERSAVE;
1935 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1936 rdev->pm.power_state[state_index].type =
1937 POWER_STATE_TYPE_BATTERY;
1938 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1939 rdev->pm.power_state[state_index].type =
1940 POWER_STATE_TYPE_BATTERY;
1941 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1942 rdev->pm.power_state[state_index].type =
1943 POWER_STATE_TYPE_BALANCED;
1944 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1945 rdev->pm.power_state[state_index].type =
1946 POWER_STATE_TYPE_PERFORMANCE;
1947 rdev->pm.power_state[state_index].flags &=
1948 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1949 }
1950 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1951 rdev->pm.power_state[state_index].type =
1952 POWER_STATE_TYPE_BALANCED;
1953 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1954 rdev->pm.power_state[state_index].type =
1955 POWER_STATE_TYPE_DEFAULT;
1956 rdev->pm.default_power_state_index = state_index;
1957 rdev->pm.power_state[state_index].default_clock_mode =
1958 &rdev->pm.power_state[state_index].clock_info[0];
1959 } else if (state_index == 0) {
1960 rdev->pm.power_state[state_index].clock_info[0].flags |=
1961 RADEON_PM_MODE_NO_DISPLAY;
1962 }
1963}
1964
1965static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1966{
1967 struct radeon_mode_info *mode_info = &rdev->mode_info;
1968 u32 misc, misc2 = 0;
1969 int num_modes = 0, i;
1970 int state_index = 0;
1971 struct radeon_i2c_bus_rec i2c_bus;
1972 union power_info *power_info;
1973 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1974 u16 data_offset;
1975 u8 frev, crev;
1976
1977 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1978 &frev, &crev, &data_offset))
1979 return state_index;
1980 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1981
1982 /* add the i2c bus for thermal/fan chip */
1983 if (power_info->info.ucOverdriveThermalController > 0) {
1984 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1985 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1986 power_info->info.ucOverdriveControllerAddress >> 1);
1987 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1988 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1989 if (rdev->pm.i2c_bus) {
1990 struct i2c_board_info info = { };
1991 const char *name = thermal_controller_names[power_info->info.
1992 ucOverdriveThermalController];
1993 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1994 strlcpy(info.type, name, sizeof(info.type));
1995 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1996 }
1997 }
1998 num_modes = power_info->info.ucNumOfPowerModeEntries;
1999 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2000 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2001 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2002 if (!rdev->pm.power_state)
2003 return state_index;
2004 /* last mode is usually default, array is low to high */
2005 for (i = 0; i < num_modes; i++) {
2006 rdev->pm.power_state[state_index].clock_info =
2007 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2008 if (!rdev->pm.power_state[state_index].clock_info)
2009 return state_index;
2010 rdev->pm.power_state[state_index].num_clock_modes = 1;
2011 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2012 switch (frev) {
2013 case 1:
2014 rdev->pm.power_state[state_index].clock_info[0].mclk =
2015 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2016 rdev->pm.power_state[state_index].clock_info[0].sclk =
2017 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2018 /* skip invalid modes */
2019 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2020 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2021 continue;
2022 rdev->pm.power_state[state_index].pcie_lanes =
2023 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2024 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2025 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2026 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2027 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2028 VOLTAGE_GPIO;
2029 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2030 radeon_lookup_gpio(rdev,
2031 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2032 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2033 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2034 true;
2035 else
2036 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2037 false;
2038 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2039 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2040 VOLTAGE_VDDC;
2041 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2042 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2043 }
2044 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2045 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2046 state_index++;
2047 break;
2048 case 2:
2049 rdev->pm.power_state[state_index].clock_info[0].mclk =
2050 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2051 rdev->pm.power_state[state_index].clock_info[0].sclk =
2052 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2053 /* skip invalid modes */
2054 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2055 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2056 continue;
2057 rdev->pm.power_state[state_index].pcie_lanes =
2058 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2059 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2060 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2061 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2062 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2063 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2064 VOLTAGE_GPIO;
2065 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2066 radeon_lookup_gpio(rdev,
2067 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2068 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2069 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2070 true;
2071 else
2072 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2073 false;
2074 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2075 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2076 VOLTAGE_VDDC;
2077 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2078 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2079 }
2080 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2081 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2082 state_index++;
2083 break;
2084 case 3:
2085 rdev->pm.power_state[state_index].clock_info[0].mclk =
2086 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2087 rdev->pm.power_state[state_index].clock_info[0].sclk =
2088 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2089 /* skip invalid modes */
2090 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2091 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2092 continue;
2093 rdev->pm.power_state[state_index].pcie_lanes =
2094 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2095 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2096 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2097 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2098 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2099 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2100 VOLTAGE_GPIO;
2101 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2102 radeon_lookup_gpio(rdev,
2103 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2104 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2105 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2106 true;
2107 else
2108 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2109 false;
2110 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2111 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2112 VOLTAGE_VDDC;
2113 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2114 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2115 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2116 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2117 true;
2118 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2119 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2120 }
2121 }
2122 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2123 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2124 state_index++;
2125 break;
2126 }
2127 }
2128 /* last mode is usually default */
2129 if (rdev->pm.default_power_state_index == -1) {
2130 rdev->pm.power_state[state_index - 1].type =
2131 POWER_STATE_TYPE_DEFAULT;
2132 rdev->pm.default_power_state_index = state_index - 1;
2133 rdev->pm.power_state[state_index - 1].default_clock_mode =
2134 &rdev->pm.power_state[state_index - 1].clock_info[0];
2135 rdev->pm.power_state[state_index].flags &=
2136 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2137 rdev->pm.power_state[state_index].misc = 0;
2138 rdev->pm.power_state[state_index].misc2 = 0;
2139 }
2140 return state_index;
2141}
2142
2143static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2144 ATOM_PPLIB_THERMALCONTROLLER *controller)
2145{
2146 struct radeon_i2c_bus_rec i2c_bus;
2147
2148 /* add the i2c bus for thermal/fan chip */
2149 if (controller->ucType > 0) {
2150 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2151 DRM_INFO("Internal thermal controller %s fan control\n",
2152 (controller->ucFanParameters &
2153 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2154 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2155 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2156 DRM_INFO("Internal thermal controller %s fan control\n",
2157 (controller->ucFanParameters &
2158 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2159 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2160 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2161 DRM_INFO("Internal thermal controller %s fan control\n",
2162 (controller->ucFanParameters &
2163 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2164 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2165 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2166 DRM_INFO("Internal thermal controller %s fan control\n",
2167 (controller->ucFanParameters &
2168 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2169 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2170 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2171 DRM_INFO("Internal thermal controller %s fan control\n",
2172 (controller->ucFanParameters &
2173 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2174 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2175 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2176 DRM_INFO("Internal thermal controller %s fan control\n",
2177 (controller->ucFanParameters &
2178 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2179 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2180 } else if ((controller->ucType ==
2181 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2182 (controller->ucType ==
2183 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2184 (controller->ucType ==
2185 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2186 DRM_INFO("Special thermal controller config\n");
2187 } else {
2188 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2189 pp_lib_thermal_controller_names[controller->ucType],
2190 controller->ucI2cAddress >> 1,
2191 (controller->ucFanParameters &
2192 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2193 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2194 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2195 if (rdev->pm.i2c_bus) {
2196 struct i2c_board_info info = { };
2197 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2198 info.addr = controller->ucI2cAddress >> 1;
2199 strlcpy(info.type, name, sizeof(info.type));
2200 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2201 }
2202 }
2203 }
2204}
2205
2206static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2207 u16 *vddc, u16 *vddci)
2208{
2209 struct radeon_mode_info *mode_info = &rdev->mode_info;
2210 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2211 u8 frev, crev;
2212 u16 data_offset;
2213 union firmware_info *firmware_info;
2214
2215 *vddc = 0;
2216 *vddci = 0;
2217
2218 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2219 &frev, &crev, &data_offset)) {
2220 firmware_info =
2221 (union firmware_info *)(mode_info->atom_context->bios +
2222 data_offset);
2223 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2224 if ((frev == 2) && (crev >= 2))
2225 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2226 }
2227}
2228
2229static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2230 int state_index, int mode_index,
2231 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2232{
2233 int j;
2234 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2235 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2236 u16 vddc, vddci;
2237
2238 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2239
2240 rdev->pm.power_state[state_index].misc = misc;
2241 rdev->pm.power_state[state_index].misc2 = misc2;
2242 rdev->pm.power_state[state_index].pcie_lanes =
2243 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2244 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2245 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2246 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2247 rdev->pm.power_state[state_index].type =
2248 POWER_STATE_TYPE_BATTERY;
2249 break;
2250 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2251 rdev->pm.power_state[state_index].type =
2252 POWER_STATE_TYPE_BALANCED;
2253 break;
2254 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2255 rdev->pm.power_state[state_index].type =
2256 POWER_STATE_TYPE_PERFORMANCE;
2257 break;
2258 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2259 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2260 rdev->pm.power_state[state_index].type =
2261 POWER_STATE_TYPE_PERFORMANCE;
2262 break;
2263 }
2264 rdev->pm.power_state[state_index].flags = 0;
2265 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2266 rdev->pm.power_state[state_index].flags |=
2267 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2268 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2269 rdev->pm.power_state[state_index].type =
2270 POWER_STATE_TYPE_DEFAULT;
2271 rdev->pm.default_power_state_index = state_index;
2272 rdev->pm.power_state[state_index].default_clock_mode =
2273 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2274 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2275 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2276 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2277 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2278 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2279 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2280 } else {
2281 /* patch the table values with the default slck/mclk from firmware info */
2282 for (j = 0; j < mode_index; j++) {
2283 rdev->pm.power_state[state_index].clock_info[j].mclk =
2284 rdev->clock.default_mclk;
2285 rdev->pm.power_state[state_index].clock_info[j].sclk =
2286 rdev->clock.default_sclk;
2287 if (vddc)
2288 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2289 vddc;
2290 }
2291 }
2292 }
2293}
2294
2295static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2296 int state_index, int mode_index,
2297 union pplib_clock_info *clock_info)
2298{
2299 u32 sclk, mclk;
2300 u16 vddc;
2301
2302 if (rdev->flags & RADEON_IS_IGP) {
2303 if (rdev->family >= CHIP_PALM) {
2304 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2305 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2306 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2307 } else {
2308 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2309 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2310 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2311 }
2312 } else if (ASIC_IS_DCE6(rdev)) {
2313 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2314 sclk |= clock_info->si.ucEngineClockHigh << 16;
2315 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2316 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2317 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2318 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2319 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2320 VOLTAGE_SW;
2321 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2322 le16_to_cpu(clock_info->si.usVDDC);
2323 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2324 le16_to_cpu(clock_info->si.usVDDCI);
2325 } else if (ASIC_IS_DCE4(rdev)) {
2326 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2327 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2328 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2329 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2330 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2331 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2332 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2333 VOLTAGE_SW;
2334 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2335 le16_to_cpu(clock_info->evergreen.usVDDC);
2336 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2337 le16_to_cpu(clock_info->evergreen.usVDDCI);
2338 } else {
2339 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2340 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2341 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2342 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2343 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2344 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2345 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2346 VOLTAGE_SW;
2347 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2348 le16_to_cpu(clock_info->r600.usVDDC);
2349 }
2350
2351 /* patch up vddc if necessary */
2352 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2353 case ATOM_VIRTUAL_VOLTAGE_ID0:
2354 case ATOM_VIRTUAL_VOLTAGE_ID1:
2355 case ATOM_VIRTUAL_VOLTAGE_ID2:
2356 case ATOM_VIRTUAL_VOLTAGE_ID3:
2357 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2358 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2359 &vddc) == 0)
2360 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2361 break;
2362 default:
2363 break;
2364 }
2365
2366 if (rdev->flags & RADEON_IS_IGP) {
2367 /* skip invalid modes */
2368 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2369 return false;
2370 } else {
2371 /* skip invalid modes */
2372 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2373 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2374 return false;
2375 }
2376 return true;
2377}
2378
2379static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2380{
2381 struct radeon_mode_info *mode_info = &rdev->mode_info;
2382 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2383 union pplib_power_state *power_state;
2384 int i, j;
2385 int state_index = 0, mode_index = 0;
2386 union pplib_clock_info *clock_info;
2387 bool valid;
2388 union power_info *power_info;
2389 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2390 u16 data_offset;
2391 u8 frev, crev;
2392
2393 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2394 &frev, &crev, &data_offset))
2395 return state_index;
2396 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2397
2398 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2399 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2400 power_info->pplib.ucNumStates, GFP_KERNEL);
2401 if (!rdev->pm.power_state)
2402 return state_index;
2403 /* first mode is usually default, followed by low to high */
2404 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2405 mode_index = 0;
2406 power_state = (union pplib_power_state *)
2407 (mode_info->atom_context->bios + data_offset +
2408 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2409 i * power_info->pplib.ucStateEntrySize);
2410 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2411 (mode_info->atom_context->bios + data_offset +
2412 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2413 (power_state->v1.ucNonClockStateIndex *
2414 power_info->pplib.ucNonClockSize));
2415 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2416 ((power_info->pplib.ucStateEntrySize - 1) ?
2417 (power_info->pplib.ucStateEntrySize - 1) : 1),
2418 GFP_KERNEL);
2419 if (!rdev->pm.power_state[i].clock_info)
2420 return state_index;
2421 if (power_info->pplib.ucStateEntrySize - 1) {
2422 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2423 clock_info = (union pplib_clock_info *)
2424 (mode_info->atom_context->bios + data_offset +
2425 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2426 (power_state->v1.ucClockStateIndices[j] *
2427 power_info->pplib.ucClockInfoSize));
2428 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2429 state_index, mode_index,
2430 clock_info);
2431 if (valid)
2432 mode_index++;
2433 }
2434 } else {
2435 rdev->pm.power_state[state_index].clock_info[0].mclk =
2436 rdev->clock.default_mclk;
2437 rdev->pm.power_state[state_index].clock_info[0].sclk =
2438 rdev->clock.default_sclk;
2439 mode_index++;
2440 }
2441 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2442 if (mode_index) {
2443 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2444 non_clock_info);
2445 state_index++;
2446 }
2447 }
2448 /* if multiple clock modes, mark the lowest as no display */
2449 for (i = 0; i < state_index; i++) {
2450 if (rdev->pm.power_state[i].num_clock_modes > 1)
2451 rdev->pm.power_state[i].clock_info[0].flags |=
2452 RADEON_PM_MODE_NO_DISPLAY;
2453 }
2454 /* first mode is usually default */
2455 if (rdev->pm.default_power_state_index == -1) {
2456 rdev->pm.power_state[0].type =
2457 POWER_STATE_TYPE_DEFAULT;
2458 rdev->pm.default_power_state_index = 0;
2459 rdev->pm.power_state[0].default_clock_mode =
2460 &rdev->pm.power_state[0].clock_info[0];
2461 }
2462 return state_index;
2463}
2464
2465static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2466{
2467 struct radeon_mode_info *mode_info = &rdev->mode_info;
2468 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2469 union pplib_power_state *power_state;
2470 int i, j, non_clock_array_index, clock_array_index;
2471 int state_index = 0, mode_index = 0;
2472 union pplib_clock_info *clock_info;
2473 struct _StateArray *state_array;
2474 struct _ClockInfoArray *clock_info_array;
2475 struct _NonClockInfoArray *non_clock_info_array;
2476 bool valid;
2477 union power_info *power_info;
2478 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2479 u16 data_offset;
2480 u8 frev, crev;
2481
2482 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2483 &frev, &crev, &data_offset))
2484 return state_index;
2485 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2486
2487 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2488 state_array = (struct _StateArray *)
2489 (mode_info->atom_context->bios + data_offset +
2490 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2491 clock_info_array = (struct _ClockInfoArray *)
2492 (mode_info->atom_context->bios + data_offset +
2493 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2494 non_clock_info_array = (struct _NonClockInfoArray *)
2495 (mode_info->atom_context->bios + data_offset +
2496 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2497 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2498 state_array->ucNumEntries, GFP_KERNEL);
2499 if (!rdev->pm.power_state)
2500 return state_index;
2501 for (i = 0; i < state_array->ucNumEntries; i++) {
2502 mode_index = 0;
2503 power_state = (union pplib_power_state *)&state_array->states[i];
2504 /* XXX this might be an inagua bug... */
2505 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2506 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2507 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2508 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2509 (power_state->v2.ucNumDPMLevels ?
2510 power_state->v2.ucNumDPMLevels : 1),
2511 GFP_KERNEL);
2512 if (!rdev->pm.power_state[i].clock_info)
2513 return state_index;
2514 if (power_state->v2.ucNumDPMLevels) {
2515 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2516 clock_array_index = power_state->v2.clockInfoIndex[j];
2517 /* XXX this might be an inagua bug... */
2518 if (clock_array_index >= clock_info_array->ucNumEntries)
2519 continue;
2520 clock_info = (union pplib_clock_info *)
2521 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2522 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2523 state_index, mode_index,
2524 clock_info);
2525 if (valid)
2526 mode_index++;
2527 }
2528 } else {
2529 rdev->pm.power_state[state_index].clock_info[0].mclk =
2530 rdev->clock.default_mclk;
2531 rdev->pm.power_state[state_index].clock_info[0].sclk =
2532 rdev->clock.default_sclk;
2533 mode_index++;
2534 }
2535 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2536 if (mode_index) {
2537 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2538 non_clock_info);
2539 state_index++;
2540 }
2541 }
2542 /* if multiple clock modes, mark the lowest as no display */
2543 for (i = 0; i < state_index; i++) {
2544 if (rdev->pm.power_state[i].num_clock_modes > 1)
2545 rdev->pm.power_state[i].clock_info[0].flags |=
2546 RADEON_PM_MODE_NO_DISPLAY;
2547 }
2548 /* first mode is usually default */
2549 if (rdev->pm.default_power_state_index == -1) {
2550 rdev->pm.power_state[0].type =
2551 POWER_STATE_TYPE_DEFAULT;
2552 rdev->pm.default_power_state_index = 0;
2553 rdev->pm.power_state[0].default_clock_mode =
2554 &rdev->pm.power_state[0].clock_info[0];
2555 }
2556 return state_index;
2557}
2558
2559void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2560{
2561 struct radeon_mode_info *mode_info = &rdev->mode_info;
2562 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2563 u16 data_offset;
2564 u8 frev, crev;
2565 int state_index = 0;
2566
2567 rdev->pm.default_power_state_index = -1;
2568
2569 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2570 &frev, &crev, &data_offset)) {
2571 switch (frev) {
2572 case 1:
2573 case 2:
2574 case 3:
2575 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2576 break;
2577 case 4:
2578 case 5:
2579 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2580 break;
2581 case 6:
2582 state_index = radeon_atombios_parse_power_table_6(rdev);
2583 break;
2584 default:
2585 break;
2586 }
2587 } else {
2588 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2589 if (rdev->pm.power_state) {
2590 rdev->pm.power_state[0].clock_info =
2591 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2592 if (rdev->pm.power_state[0].clock_info) {
2593 /* add the default mode */
2594 rdev->pm.power_state[state_index].type =
2595 POWER_STATE_TYPE_DEFAULT;
2596 rdev->pm.power_state[state_index].num_clock_modes = 1;
2597 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2598 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2599 rdev->pm.power_state[state_index].default_clock_mode =
2600 &rdev->pm.power_state[state_index].clock_info[0];
2601 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2602 rdev->pm.power_state[state_index].pcie_lanes = 16;
2603 rdev->pm.default_power_state_index = state_index;
2604 rdev->pm.power_state[state_index].flags = 0;
2605 state_index++;
2606 }
2607 }
2608 }
2609
2610 rdev->pm.num_power_states = state_index;
2611
2612 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2613 rdev->pm.current_clock_mode_index = 0;
2614 if (rdev->pm.default_power_state_index >= 0)
2615 rdev->pm.current_vddc =
2616 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2617 else
2618 rdev->pm.current_vddc = 0;
2619}
2620
2621void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2622{
2623 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2624 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2625
2626 args.ucEnable = enable;
2627
2628 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2629}
2630
2631uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2632{
2633 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2634 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2635
2636 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2637 return le32_to_cpu(args.ulReturnEngineClock);
2638}
2639
2640uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2641{
2642 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2643 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2644
2645 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2646 return le32_to_cpu(args.ulReturnMemoryClock);
2647}
2648
2649void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2650 uint32_t eng_clock)
2651{
2652 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2653 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2654
2655 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2656
2657 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2658}
2659
2660void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2661 uint32_t mem_clock)
2662{
2663 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2664 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2665
2666 if (rdev->flags & RADEON_IS_IGP)
2667 return;
2668
2669 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2670
2671 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2672}
2673
2674union set_voltage {
2675 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2676 struct _SET_VOLTAGE_PARAMETERS v1;
2677 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2678 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
2679};
2680
2681void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2682{
2683 union set_voltage args;
2684 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2685 u8 frev, crev, volt_index = voltage_level;
2686
2687 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2688 return;
2689
2690 /* 0xff01 is a flag rather then an actual voltage */
2691 if (voltage_level == 0xff01)
2692 return;
2693
2694 switch (crev) {
2695 case 1:
2696 args.v1.ucVoltageType = voltage_type;
2697 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2698 args.v1.ucVoltageIndex = volt_index;
2699 break;
2700 case 2:
2701 args.v2.ucVoltageType = voltage_type;
2702 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2703 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2704 break;
2705 case 3:
2706 args.v3.ucVoltageType = voltage_type;
2707 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
2708 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
2709 break;
2710 default:
2711 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2712 return;
2713 }
2714
2715 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2716}
2717
2718static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
2719 u16 voltage_id, u16 *voltage)
2720{
2721 union set_voltage args;
2722 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2723 u8 frev, crev;
2724
2725 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2726 return -EINVAL;
2727
2728 switch (crev) {
2729 case 1:
2730 return -EINVAL;
2731 case 2:
2732 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2733 args.v2.ucVoltageMode = 0;
2734 args.v2.usVoltageLevel = 0;
2735
2736 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2737
2738 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2739 break;
2740 case 3:
2741 args.v3.ucVoltageType = voltage_type;
2742 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
2743 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
2744
2745 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2746
2747 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
2748 break;
2749 default:
2750 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2751 return -EINVAL;
2752 }
2753
2754 return 0;
2755}
2756
2757void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2758{
2759 struct radeon_device *rdev = dev->dev_private;
2760 uint32_t bios_2_scratch, bios_6_scratch;
2761
2762 if (rdev->family >= CHIP_R600) {
2763 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2764 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2765 } else {
2766 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2767 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2768 }
2769
2770 /* let the bios control the backlight */
2771 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2772
2773 /* tell the bios not to handle mode switching */
2774 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2775
2776 if (rdev->family >= CHIP_R600) {
2777 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2778 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2779 } else {
2780 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2781 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2782 }
2783
2784}
2785
2786void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2787{
2788 uint32_t scratch_reg;
2789 int i;
2790
2791 if (rdev->family >= CHIP_R600)
2792 scratch_reg = R600_BIOS_0_SCRATCH;
2793 else
2794 scratch_reg = RADEON_BIOS_0_SCRATCH;
2795
2796 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2797 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2798}
2799
2800void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2801{
2802 uint32_t scratch_reg;
2803 int i;
2804
2805 if (rdev->family >= CHIP_R600)
2806 scratch_reg = R600_BIOS_0_SCRATCH;
2807 else
2808 scratch_reg = RADEON_BIOS_0_SCRATCH;
2809
2810 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2811 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2812}
2813
2814void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2815{
2816 struct drm_device *dev = encoder->dev;
2817 struct radeon_device *rdev = dev->dev_private;
2818 uint32_t bios_6_scratch;
2819
2820 if (rdev->family >= CHIP_R600)
2821 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2822 else
2823 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2824
2825 if (lock) {
2826 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2827 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2828 } else {
2829 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2830 bios_6_scratch |= ATOM_S6_ACC_MODE;
2831 }
2832
2833 if (rdev->family >= CHIP_R600)
2834 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2835 else
2836 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2837}
2838
2839/* at some point we may want to break this out into individual functions */
2840void
2841radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2842 struct drm_encoder *encoder,
2843 bool connected)
2844{
2845 struct drm_device *dev = connector->dev;
2846 struct radeon_device *rdev = dev->dev_private;
2847 struct radeon_connector *radeon_connector =
2848 to_radeon_connector(connector);
2849 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2850 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2851
2852 if (rdev->family >= CHIP_R600) {
2853 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2854 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2855 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2856 } else {
2857 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2858 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2859 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2860 }
2861
2862 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2863 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2864 if (connected) {
2865 DRM_DEBUG_KMS("TV1 connected\n");
2866 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2867 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2868 } else {
2869 DRM_DEBUG_KMS("TV1 disconnected\n");
2870 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2871 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2872 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2873 }
2874 }
2875 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2876 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2877 if (connected) {
2878 DRM_DEBUG_KMS("CV connected\n");
2879 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2880 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2881 } else {
2882 DRM_DEBUG_KMS("CV disconnected\n");
2883 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2884 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2885 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2886 }
2887 }
2888 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2889 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2890 if (connected) {
2891 DRM_DEBUG_KMS("LCD1 connected\n");
2892 bios_0_scratch |= ATOM_S0_LCD1;
2893 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2894 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2895 } else {
2896 DRM_DEBUG_KMS("LCD1 disconnected\n");
2897 bios_0_scratch &= ~ATOM_S0_LCD1;
2898 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2899 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2900 }
2901 }
2902 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2903 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2904 if (connected) {
2905 DRM_DEBUG_KMS("CRT1 connected\n");
2906 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2907 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2908 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2909 } else {
2910 DRM_DEBUG_KMS("CRT1 disconnected\n");
2911 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2912 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2913 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2914 }
2915 }
2916 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2917 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2918 if (connected) {
2919 DRM_DEBUG_KMS("CRT2 connected\n");
2920 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2921 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2922 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2923 } else {
2924 DRM_DEBUG_KMS("CRT2 disconnected\n");
2925 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2926 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2927 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2928 }
2929 }
2930 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2931 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2932 if (connected) {
2933 DRM_DEBUG_KMS("DFP1 connected\n");
2934 bios_0_scratch |= ATOM_S0_DFP1;
2935 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2936 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2937 } else {
2938 DRM_DEBUG_KMS("DFP1 disconnected\n");
2939 bios_0_scratch &= ~ATOM_S0_DFP1;
2940 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2941 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2942 }
2943 }
2944 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2945 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2946 if (connected) {
2947 DRM_DEBUG_KMS("DFP2 connected\n");
2948 bios_0_scratch |= ATOM_S0_DFP2;
2949 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2950 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2951 } else {
2952 DRM_DEBUG_KMS("DFP2 disconnected\n");
2953 bios_0_scratch &= ~ATOM_S0_DFP2;
2954 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2955 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2956 }
2957 }
2958 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2959 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2960 if (connected) {
2961 DRM_DEBUG_KMS("DFP3 connected\n");
2962 bios_0_scratch |= ATOM_S0_DFP3;
2963 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2964 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2965 } else {
2966 DRM_DEBUG_KMS("DFP3 disconnected\n");
2967 bios_0_scratch &= ~ATOM_S0_DFP3;
2968 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2969 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2970 }
2971 }
2972 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2973 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2974 if (connected) {
2975 DRM_DEBUG_KMS("DFP4 connected\n");
2976 bios_0_scratch |= ATOM_S0_DFP4;
2977 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2978 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2979 } else {
2980 DRM_DEBUG_KMS("DFP4 disconnected\n");
2981 bios_0_scratch &= ~ATOM_S0_DFP4;
2982 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2983 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2984 }
2985 }
2986 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2987 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2988 if (connected) {
2989 DRM_DEBUG_KMS("DFP5 connected\n");
2990 bios_0_scratch |= ATOM_S0_DFP5;
2991 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2992 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2993 } else {
2994 DRM_DEBUG_KMS("DFP5 disconnected\n");
2995 bios_0_scratch &= ~ATOM_S0_DFP5;
2996 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2997 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2998 }
2999 }
3000 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
3001 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
3002 if (connected) {
3003 DRM_DEBUG_KMS("DFP6 connected\n");
3004 bios_0_scratch |= ATOM_S0_DFP6;
3005 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
3006 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
3007 } else {
3008 DRM_DEBUG_KMS("DFP6 disconnected\n");
3009 bios_0_scratch &= ~ATOM_S0_DFP6;
3010 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
3011 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
3012 }
3013 }
3014
3015 if (rdev->family >= CHIP_R600) {
3016 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
3017 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3018 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3019 } else {
3020 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3021 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3022 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3023 }
3024}
3025
3026void
3027radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3028{
3029 struct drm_device *dev = encoder->dev;
3030 struct radeon_device *rdev = dev->dev_private;
3031 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3032 uint32_t bios_3_scratch;
3033
3034 if (ASIC_IS_DCE4(rdev))
3035 return;
3036
3037 if (rdev->family >= CHIP_R600)
3038 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
3039 else
3040 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
3041
3042 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3043 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
3044 bios_3_scratch |= (crtc << 18);
3045 }
3046 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3047 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
3048 bios_3_scratch |= (crtc << 24);
3049 }
3050 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3051 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
3052 bios_3_scratch |= (crtc << 16);
3053 }
3054 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3055 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
3056 bios_3_scratch |= (crtc << 20);
3057 }
3058 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3059 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3060 bios_3_scratch |= (crtc << 17);
3061 }
3062 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3063 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3064 bios_3_scratch |= (crtc << 19);
3065 }
3066 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3067 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3068 bios_3_scratch |= (crtc << 23);
3069 }
3070 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3071 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3072 bios_3_scratch |= (crtc << 25);
3073 }
3074
3075 if (rdev->family >= CHIP_R600)
3076 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3077 else
3078 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3079}
3080
3081void
3082radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3083{
3084 struct drm_device *dev = encoder->dev;
3085 struct radeon_device *rdev = dev->dev_private;
3086 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3087 uint32_t bios_2_scratch;
3088
3089 if (ASIC_IS_DCE4(rdev))
3090 return;
3091
3092 if (rdev->family >= CHIP_R600)
3093 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3094 else
3095 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3096
3097 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3098 if (on)
3099 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3100 else
3101 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3102 }
3103 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3104 if (on)
3105 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3106 else
3107 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3108 }
3109 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3110 if (on)
3111 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3112 else
3113 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3114 }
3115 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3116 if (on)
3117 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3118 else
3119 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3120 }
3121 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3122 if (on)
3123 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3124 else
3125 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3126 }
3127 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3128 if (on)
3129 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3130 else
3131 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3132 }
3133 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3134 if (on)
3135 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3136 else
3137 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3138 }
3139 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3140 if (on)
3141 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3142 else
3143 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3144 }
3145 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3146 if (on)
3147 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3148 else
3149 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3150 }
3151 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3152 if (on)
3153 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3154 else
3155 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3156 }
3157
3158 if (rdev->family >= CHIP_R600)
3159 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3160 else
3161 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3162}