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1/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
32#include "drmP.h"
33#include "drm_crtc.h"
34#include "drm_fourcc.h"
35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
38
39static void
40ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
41 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
42 unsigned int crtc_w, unsigned int crtc_h,
43 uint32_t x, uint32_t y,
44 uint32_t src_w, uint32_t src_h)
45{
46 struct drm_device *dev = plane->dev;
47 struct drm_i915_private *dev_priv = dev->dev_private;
48 struct intel_plane *intel_plane = to_intel_plane(plane);
49 int pipe = intel_plane->pipe;
50 u32 sprctl, sprscale = 0;
51 int pixel_size;
52
53 sprctl = I915_READ(SPRCTL(pipe));
54
55 /* Mask out pixel format bits in case we change it */
56 sprctl &= ~SPRITE_PIXFORMAT_MASK;
57 sprctl &= ~SPRITE_RGB_ORDER_RGBX;
58 sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
59
60 switch (fb->pixel_format) {
61 case DRM_FORMAT_XBGR8888:
62 sprctl |= SPRITE_FORMAT_RGBX888;
63 pixel_size = 4;
64 break;
65 case DRM_FORMAT_XRGB8888:
66 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
67 pixel_size = 4;
68 break;
69 case DRM_FORMAT_YUYV:
70 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
71 pixel_size = 2;
72 break;
73 case DRM_FORMAT_YVYU:
74 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
75 pixel_size = 2;
76 break;
77 case DRM_FORMAT_UYVY:
78 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
79 pixel_size = 2;
80 break;
81 case DRM_FORMAT_VYUY:
82 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
83 pixel_size = 2;
84 break;
85 default:
86 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
87 sprctl |= DVS_FORMAT_RGBX888;
88 pixel_size = 4;
89 break;
90 }
91
92 if (obj->tiling_mode != I915_TILING_NONE)
93 sprctl |= SPRITE_TILED;
94
95 /* must disable */
96 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
97 sprctl |= SPRITE_ENABLE;
98
99 /* Sizes are 0 based */
100 src_w--;
101 src_h--;
102 crtc_w--;
103 crtc_h--;
104
105 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
106
107 /*
108 * IVB workaround: must disable low power watermarks for at least
109 * one frame before enabling scaling. LP watermarks can be re-enabled
110 * when scaling is disabled.
111 */
112 if (crtc_w != src_w || crtc_h != src_h) {
113 if (!dev_priv->sprite_scaling_enabled) {
114 dev_priv->sprite_scaling_enabled = true;
115 intel_update_watermarks(dev);
116 intel_wait_for_vblank(dev, pipe);
117 }
118 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
119 } else {
120 if (dev_priv->sprite_scaling_enabled) {
121 dev_priv->sprite_scaling_enabled = false;
122 /* potentially re-enable LP watermarks */
123 intel_update_watermarks(dev);
124 }
125 }
126
127 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
128 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
129 if (obj->tiling_mode != I915_TILING_NONE) {
130 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
131 } else {
132 unsigned long offset;
133
134 offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
135 I915_WRITE(SPRLINOFF(pipe), offset);
136 }
137 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
138 I915_WRITE(SPRSCALE(pipe), sprscale);
139 I915_WRITE(SPRCTL(pipe), sprctl);
140 I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset);
141 POSTING_READ(SPRSURF(pipe));
142}
143
144static void
145ivb_disable_plane(struct drm_plane *plane)
146{
147 struct drm_device *dev = plane->dev;
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 struct intel_plane *intel_plane = to_intel_plane(plane);
150 int pipe = intel_plane->pipe;
151
152 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
153 /* Can't leave the scaler enabled... */
154 I915_WRITE(SPRSCALE(pipe), 0);
155 /* Activate double buffered register update */
156 I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
157 POSTING_READ(SPRSURF(pipe));
158
159 dev_priv->sprite_scaling_enabled = false;
160 intel_update_watermarks(dev);
161}
162
163static int
164ivb_update_colorkey(struct drm_plane *plane,
165 struct drm_intel_sprite_colorkey *key)
166{
167 struct drm_device *dev = plane->dev;
168 struct drm_i915_private *dev_priv = dev->dev_private;
169 struct intel_plane *intel_plane;
170 u32 sprctl;
171 int ret = 0;
172
173 intel_plane = to_intel_plane(plane);
174
175 I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
176 I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
177 I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
178
179 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
180 sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
181 if (key->flags & I915_SET_COLORKEY_DESTINATION)
182 sprctl |= SPRITE_DEST_KEY;
183 else if (key->flags & I915_SET_COLORKEY_SOURCE)
184 sprctl |= SPRITE_SOURCE_KEY;
185 I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
186
187 POSTING_READ(SPRKEYMSK(intel_plane->pipe));
188
189 return ret;
190}
191
192static void
193ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
194{
195 struct drm_device *dev = plane->dev;
196 struct drm_i915_private *dev_priv = dev->dev_private;
197 struct intel_plane *intel_plane;
198 u32 sprctl;
199
200 intel_plane = to_intel_plane(plane);
201
202 key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
203 key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
204 key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
205 key->flags = 0;
206
207 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
208
209 if (sprctl & SPRITE_DEST_KEY)
210 key->flags = I915_SET_COLORKEY_DESTINATION;
211 else if (sprctl & SPRITE_SOURCE_KEY)
212 key->flags = I915_SET_COLORKEY_SOURCE;
213 else
214 key->flags = I915_SET_COLORKEY_NONE;
215}
216
217static void
218ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
219 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
220 unsigned int crtc_w, unsigned int crtc_h,
221 uint32_t x, uint32_t y,
222 uint32_t src_w, uint32_t src_h)
223{
224 struct drm_device *dev = plane->dev;
225 struct drm_i915_private *dev_priv = dev->dev_private;
226 struct intel_plane *intel_plane = to_intel_plane(plane);
227 int pipe = intel_plane->pipe, pixel_size;
228 u32 dvscntr, dvsscale;
229
230 dvscntr = I915_READ(DVSCNTR(pipe));
231
232 /* Mask out pixel format bits in case we change it */
233 dvscntr &= ~DVS_PIXFORMAT_MASK;
234 dvscntr &= ~DVS_RGB_ORDER_XBGR;
235 dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
236
237 switch (fb->pixel_format) {
238 case DRM_FORMAT_XBGR8888:
239 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
240 pixel_size = 4;
241 break;
242 case DRM_FORMAT_XRGB8888:
243 dvscntr |= DVS_FORMAT_RGBX888;
244 pixel_size = 4;
245 break;
246 case DRM_FORMAT_YUYV:
247 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
248 pixel_size = 2;
249 break;
250 case DRM_FORMAT_YVYU:
251 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
252 pixel_size = 2;
253 break;
254 case DRM_FORMAT_UYVY:
255 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
256 pixel_size = 2;
257 break;
258 case DRM_FORMAT_VYUY:
259 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
260 pixel_size = 2;
261 break;
262 default:
263 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
264 dvscntr |= DVS_FORMAT_RGBX888;
265 pixel_size = 4;
266 break;
267 }
268
269 if (obj->tiling_mode != I915_TILING_NONE)
270 dvscntr |= DVS_TILED;
271
272 if (IS_GEN6(dev))
273 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
274 dvscntr |= DVS_ENABLE;
275
276 /* Sizes are 0 based */
277 src_w--;
278 src_h--;
279 crtc_w--;
280 crtc_h--;
281
282 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
283
284 dvsscale = 0;
285 if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)
286 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
287
288 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
289 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
290 if (obj->tiling_mode != I915_TILING_NONE) {
291 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
292 } else {
293 unsigned long offset;
294
295 offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
296 I915_WRITE(DVSLINOFF(pipe), offset);
297 }
298 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
299 I915_WRITE(DVSSCALE(pipe), dvsscale);
300 I915_WRITE(DVSCNTR(pipe), dvscntr);
301 I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset);
302 POSTING_READ(DVSSURF(pipe));
303}
304
305static void
306ilk_disable_plane(struct drm_plane *plane)
307{
308 struct drm_device *dev = plane->dev;
309 struct drm_i915_private *dev_priv = dev->dev_private;
310 struct intel_plane *intel_plane = to_intel_plane(plane);
311 int pipe = intel_plane->pipe;
312
313 I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
314 /* Disable the scaler */
315 I915_WRITE(DVSSCALE(pipe), 0);
316 /* Flush double buffered register updates */
317 I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
318 POSTING_READ(DVSSURF(pipe));
319}
320
321static void
322intel_enable_primary(struct drm_crtc *crtc)
323{
324 struct drm_device *dev = crtc->dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
327 int reg = DSPCNTR(intel_crtc->plane);
328
329 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
330}
331
332static void
333intel_disable_primary(struct drm_crtc *crtc)
334{
335 struct drm_device *dev = crtc->dev;
336 struct drm_i915_private *dev_priv = dev->dev_private;
337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
338 int reg = DSPCNTR(intel_crtc->plane);
339
340 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
341}
342
343static int
344ilk_update_colorkey(struct drm_plane *plane,
345 struct drm_intel_sprite_colorkey *key)
346{
347 struct drm_device *dev = plane->dev;
348 struct drm_i915_private *dev_priv = dev->dev_private;
349 struct intel_plane *intel_plane;
350 u32 dvscntr;
351 int ret = 0;
352
353 intel_plane = to_intel_plane(plane);
354
355 I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
356 I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
357 I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
358
359 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
360 dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
361 if (key->flags & I915_SET_COLORKEY_DESTINATION)
362 dvscntr |= DVS_DEST_KEY;
363 else if (key->flags & I915_SET_COLORKEY_SOURCE)
364 dvscntr |= DVS_SOURCE_KEY;
365 I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
366
367 POSTING_READ(DVSKEYMSK(intel_plane->pipe));
368
369 return ret;
370}
371
372static void
373ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
374{
375 struct drm_device *dev = plane->dev;
376 struct drm_i915_private *dev_priv = dev->dev_private;
377 struct intel_plane *intel_plane;
378 u32 dvscntr;
379
380 intel_plane = to_intel_plane(plane);
381
382 key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
383 key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
384 key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
385 key->flags = 0;
386
387 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
388
389 if (dvscntr & DVS_DEST_KEY)
390 key->flags = I915_SET_COLORKEY_DESTINATION;
391 else if (dvscntr & DVS_SOURCE_KEY)
392 key->flags = I915_SET_COLORKEY_SOURCE;
393 else
394 key->flags = I915_SET_COLORKEY_NONE;
395}
396
397static int
398intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
399 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
400 unsigned int crtc_w, unsigned int crtc_h,
401 uint32_t src_x, uint32_t src_y,
402 uint32_t src_w, uint32_t src_h)
403{
404 struct drm_device *dev = plane->dev;
405 struct drm_i915_private *dev_priv = dev->dev_private;
406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
407 struct intel_plane *intel_plane = to_intel_plane(plane);
408 struct intel_framebuffer *intel_fb;
409 struct drm_i915_gem_object *obj, *old_obj;
410 int pipe = intel_plane->pipe;
411 int ret = 0;
412 int x = src_x >> 16, y = src_y >> 16;
413 int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
414 bool disable_primary = false;
415
416 intel_fb = to_intel_framebuffer(fb);
417 obj = intel_fb->obj;
418
419 old_obj = intel_plane->obj;
420
421 src_w = src_w >> 16;
422 src_h = src_h >> 16;
423
424 /* Pipe must be running... */
425 if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))
426 return -EINVAL;
427
428 if (crtc_x >= primary_w || crtc_y >= primary_h)
429 return -EINVAL;
430
431 /* Don't modify another pipe's plane */
432 if (intel_plane->pipe != intel_crtc->pipe)
433 return -EINVAL;
434
435 /*
436 * Clamp the width & height into the visible area. Note we don't
437 * try to scale the source if part of the visible region is offscreen.
438 * The caller must handle that by adjusting source offset and size.
439 */
440 if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) {
441 crtc_w += crtc_x;
442 crtc_x = 0;
443 }
444 if ((crtc_x + crtc_w) <= 0) /* Nothing to display */
445 goto out;
446 if ((crtc_x + crtc_w) > primary_w)
447 crtc_w = primary_w - crtc_x;
448
449 if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) {
450 crtc_h += crtc_y;
451 crtc_y = 0;
452 }
453 if ((crtc_y + crtc_h) <= 0) /* Nothing to display */
454 goto out;
455 if (crtc_y + crtc_h > primary_h)
456 crtc_h = primary_h - crtc_y;
457
458 if (!crtc_w || !crtc_h) /* Again, nothing to display */
459 goto out;
460
461 /*
462 * We can take a larger source and scale it down, but
463 * only so much... 16x is the max on SNB.
464 */
465 if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale)
466 return -EINVAL;
467
468 /*
469 * If the sprite is completely covering the primary plane,
470 * we can disable the primary and save power.
471 */
472 if ((crtc_x == 0) && (crtc_y == 0) &&
473 (crtc_w == primary_w) && (crtc_h == primary_h))
474 disable_primary = true;
475
476 mutex_lock(&dev->struct_mutex);
477
478 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
479 if (ret)
480 goto out_unlock;
481
482 intel_plane->obj = obj;
483
484 /*
485 * Be sure to re-enable the primary before the sprite is no longer
486 * covering it fully.
487 */
488 if (!disable_primary && intel_plane->primary_disabled) {
489 intel_enable_primary(crtc);
490 intel_plane->primary_disabled = false;
491 }
492
493 intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y,
494 crtc_w, crtc_h, x, y, src_w, src_h);
495
496 if (disable_primary) {
497 intel_disable_primary(crtc);
498 intel_plane->primary_disabled = true;
499 }
500
501 /* Unpin old obj after new one is active to avoid ugliness */
502 if (old_obj) {
503 /*
504 * It's fairly common to simply update the position of
505 * an existing object. In that case, we don't need to
506 * wait for vblank to avoid ugliness, we only need to
507 * do the pin & ref bookkeeping.
508 */
509 if (old_obj != obj) {
510 mutex_unlock(&dev->struct_mutex);
511 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
512 mutex_lock(&dev->struct_mutex);
513 }
514 intel_unpin_fb_obj(old_obj);
515 }
516
517out_unlock:
518 mutex_unlock(&dev->struct_mutex);
519out:
520 return ret;
521}
522
523static int
524intel_disable_plane(struct drm_plane *plane)
525{
526 struct drm_device *dev = plane->dev;
527 struct intel_plane *intel_plane = to_intel_plane(plane);
528 int ret = 0;
529
530 if (intel_plane->primary_disabled) {
531 intel_enable_primary(plane->crtc);
532 intel_plane->primary_disabled = false;
533 }
534
535 intel_plane->disable_plane(plane);
536
537 if (!intel_plane->obj)
538 goto out;
539
540 mutex_lock(&dev->struct_mutex);
541 intel_unpin_fb_obj(intel_plane->obj);
542 intel_plane->obj = NULL;
543 mutex_unlock(&dev->struct_mutex);
544out:
545
546 return ret;
547}
548
549static void intel_destroy_plane(struct drm_plane *plane)
550{
551 struct intel_plane *intel_plane = to_intel_plane(plane);
552 intel_disable_plane(plane);
553 drm_plane_cleanup(plane);
554 kfree(intel_plane);
555}
556
557int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
558 struct drm_file *file_priv)
559{
560 struct drm_intel_sprite_colorkey *set = data;
561 struct drm_mode_object *obj;
562 struct drm_plane *plane;
563 struct intel_plane *intel_plane;
564 int ret = 0;
565
566 if (!drm_core_check_feature(dev, DRIVER_MODESET))
567 return -ENODEV;
568
569 /* Make sure we don't try to enable both src & dest simultaneously */
570 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
571 return -EINVAL;
572
573 mutex_lock(&dev->mode_config.mutex);
574
575 obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
576 if (!obj) {
577 ret = -EINVAL;
578 goto out_unlock;
579 }
580
581 plane = obj_to_plane(obj);
582 intel_plane = to_intel_plane(plane);
583 ret = intel_plane->update_colorkey(plane, set);
584
585out_unlock:
586 mutex_unlock(&dev->mode_config.mutex);
587 return ret;
588}
589
590int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
591 struct drm_file *file_priv)
592{
593 struct drm_intel_sprite_colorkey *get = data;
594 struct drm_mode_object *obj;
595 struct drm_plane *plane;
596 struct intel_plane *intel_plane;
597 int ret = 0;
598
599 if (!drm_core_check_feature(dev, DRIVER_MODESET))
600 return -ENODEV;
601
602 mutex_lock(&dev->mode_config.mutex);
603
604 obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
605 if (!obj) {
606 ret = -EINVAL;
607 goto out_unlock;
608 }
609
610 plane = obj_to_plane(obj);
611 intel_plane = to_intel_plane(plane);
612 intel_plane->get_colorkey(plane, get);
613
614out_unlock:
615 mutex_unlock(&dev->mode_config.mutex);
616 return ret;
617}
618
619static const struct drm_plane_funcs intel_plane_funcs = {
620 .update_plane = intel_update_plane,
621 .disable_plane = intel_disable_plane,
622 .destroy = intel_destroy_plane,
623};
624
625static uint32_t ilk_plane_formats[] = {
626 DRM_FORMAT_XRGB8888,
627 DRM_FORMAT_YUYV,
628 DRM_FORMAT_YVYU,
629 DRM_FORMAT_UYVY,
630 DRM_FORMAT_VYUY,
631};
632
633static uint32_t snb_plane_formats[] = {
634 DRM_FORMAT_XBGR8888,
635 DRM_FORMAT_XRGB8888,
636 DRM_FORMAT_YUYV,
637 DRM_FORMAT_YVYU,
638 DRM_FORMAT_UYVY,
639 DRM_FORMAT_VYUY,
640};
641
642int
643intel_plane_init(struct drm_device *dev, enum pipe pipe)
644{
645 struct intel_plane *intel_plane;
646 unsigned long possible_crtcs;
647 const uint32_t *plane_formats;
648 int num_plane_formats;
649 int ret;
650
651 if (INTEL_INFO(dev)->gen < 5)
652 return -ENODEV;
653
654 intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL);
655 if (!intel_plane)
656 return -ENOMEM;
657
658 switch (INTEL_INFO(dev)->gen) {
659 case 5:
660 case 6:
661 intel_plane->max_downscale = 16;
662 intel_plane->update_plane = ilk_update_plane;
663 intel_plane->disable_plane = ilk_disable_plane;
664 intel_plane->update_colorkey = ilk_update_colorkey;
665 intel_plane->get_colorkey = ilk_get_colorkey;
666
667 if (IS_GEN6(dev)) {
668 plane_formats = snb_plane_formats;
669 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
670 } else {
671 plane_formats = ilk_plane_formats;
672 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
673 }
674 break;
675
676 case 7:
677 intel_plane->max_downscale = 2;
678 intel_plane->update_plane = ivb_update_plane;
679 intel_plane->disable_plane = ivb_disable_plane;
680 intel_plane->update_colorkey = ivb_update_colorkey;
681 intel_plane->get_colorkey = ivb_get_colorkey;
682
683 plane_formats = snb_plane_formats;
684 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
685 break;
686
687 default:
688 return -ENODEV;
689 }
690
691 intel_plane->pipe = pipe;
692 possible_crtcs = (1 << pipe);
693 ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
694 &intel_plane_funcs,
695 plane_formats, num_plane_formats,
696 false);
697 if (ret)
698 kfree(intel_plane);
699
700 return ret;
701}
702