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1/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_fourcc.h>
35#include <drm/drm_rect.h>
36#include <drm/drm_atomic.h>
37#include <drm/drm_plane_helper.h>
38#include "intel_drv.h"
39#include "intel_frontbuffer.h"
40#include <drm/i915_drm.h>
41#include "i915_drv.h"
42
43static bool
44format_is_yuv(uint32_t format)
45{
46 switch (format) {
47 case DRM_FORMAT_YUYV:
48 case DRM_FORMAT_UYVY:
49 case DRM_FORMAT_VYUY:
50 case DRM_FORMAT_YVYU:
51 return true;
52 default:
53 return false;
54 }
55}
56
57int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
58 int usecs)
59{
60 /* paranoia */
61 if (!adjusted_mode->crtc_htotal)
62 return 1;
63
64 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
65 1000 * adjusted_mode->crtc_htotal);
66}
67
68/**
69 * intel_pipe_update_start() - start update of a set of display registers
70 * @crtc: the crtc of which the registers are going to be updated
71 * @start_vbl_count: vblank counter return pointer used for error checking
72 *
73 * Mark the start of an update to pipe registers that should be updated
74 * atomically regarding vblank. If the next vblank will happens within
75 * the next 100 us, this function waits until the vblank passes.
76 *
77 * After a successful call to this function, interrupts will be disabled
78 * until a subsequent call to intel_pipe_update_end(). That is done to
79 * avoid random delays. The value written to @start_vbl_count should be
80 * supplied to intel_pipe_update_end() for error checking.
81 */
82void intel_pipe_update_start(struct intel_crtc *crtc)
83{
84 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
85 long timeout = msecs_to_jiffies_timeout(1);
86 int scanline, min, max, vblank_start;
87 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
88 DEFINE_WAIT(wait);
89
90 vblank_start = adjusted_mode->crtc_vblank_start;
91 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
92 vblank_start = DIV_ROUND_UP(vblank_start, 2);
93
94 /* FIXME needs to be calibrated sensibly */
95 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 100);
96 max = vblank_start - 1;
97
98 local_irq_disable();
99
100 if (min <= 0 || max <= 0)
101 return;
102
103 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
104 return;
105
106 crtc->debug.min_vbl = min;
107 crtc->debug.max_vbl = max;
108 trace_i915_pipe_update_start(crtc);
109
110 for (;;) {
111 /*
112 * prepare_to_wait() has a memory barrier, which guarantees
113 * other CPUs can see the task state update by the time we
114 * read the scanline.
115 */
116 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
117
118 scanline = intel_get_crtc_scanline(crtc);
119 if (scanline < min || scanline > max)
120 break;
121
122 if (timeout <= 0) {
123 DRM_ERROR("Potential atomic update failure on pipe %c\n",
124 pipe_name(crtc->pipe));
125 break;
126 }
127
128 local_irq_enable();
129
130 timeout = schedule_timeout(timeout);
131
132 local_irq_disable();
133 }
134
135 finish_wait(wq, &wait);
136
137 drm_crtc_vblank_put(&crtc->base);
138
139 crtc->debug.scanline_start = scanline;
140 crtc->debug.start_vbl_time = ktime_get();
141 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
142
143 trace_i915_pipe_update_vblank_evaded(crtc);
144}
145
146/**
147 * intel_pipe_update_end() - end update of a set of display registers
148 * @crtc: the crtc of which the registers were updated
149 * @start_vbl_count: start vblank counter (used for error checking)
150 *
151 * Mark the end of an update started with intel_pipe_update_start(). This
152 * re-enables interrupts and verifies the update was actually completed
153 * before a vblank using the value of @start_vbl_count.
154 */
155void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work)
156{
157 enum pipe pipe = crtc->pipe;
158 int scanline_end = intel_get_crtc_scanline(crtc);
159 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
160 ktime_t end_vbl_time = ktime_get();
161
162 if (work) {
163 work->flip_queued_vblank = end_vbl_count;
164 smp_mb__before_atomic();
165 atomic_set(&work->pending, 1);
166 }
167
168 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
169
170 /* We're still in the vblank-evade critical section, this can't race.
171 * Would be slightly nice to just grab the vblank count and arm the
172 * event outside of the critical section - the spinlock might spin for a
173 * while ... */
174 if (crtc->base.state->event) {
175 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
176
177 spin_lock(&crtc->base.dev->event_lock);
178 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
179 spin_unlock(&crtc->base.dev->event_lock);
180
181 crtc->base.state->event = NULL;
182 }
183
184 local_irq_enable();
185
186 if (crtc->debug.start_vbl_count &&
187 crtc->debug.start_vbl_count != end_vbl_count) {
188 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
189 pipe_name(pipe), crtc->debug.start_vbl_count,
190 end_vbl_count,
191 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
192 crtc->debug.min_vbl, crtc->debug.max_vbl,
193 crtc->debug.scanline_start, scanline_end);
194 }
195}
196
197static void
198skl_update_plane(struct drm_plane *drm_plane,
199 const struct intel_crtc_state *crtc_state,
200 const struct intel_plane_state *plane_state)
201{
202 struct drm_device *dev = drm_plane->dev;
203 struct drm_i915_private *dev_priv = to_i915(dev);
204 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
205 struct drm_framebuffer *fb = plane_state->base.fb;
206 const int pipe = intel_plane->pipe;
207 const int plane = intel_plane->plane + 1;
208 u32 plane_ctl;
209 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
210 u32 surf_addr = plane_state->main.offset;
211 unsigned int rotation = plane_state->base.rotation;
212 u32 stride = skl_plane_stride(fb, 0, rotation);
213 int crtc_x = plane_state->base.dst.x1;
214 int crtc_y = plane_state->base.dst.y1;
215 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
216 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
217 uint32_t x = plane_state->main.x;
218 uint32_t y = plane_state->main.y;
219 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
220 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
221
222 plane_ctl = PLANE_CTL_ENABLE |
223 PLANE_CTL_PIPE_GAMMA_ENABLE |
224 PLANE_CTL_PIPE_CSC_ENABLE;
225
226 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
227 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
228
229 plane_ctl |= skl_plane_ctl_rotation(rotation);
230
231 if (key->flags) {
232 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
233 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
234 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
235 }
236
237 if (key->flags & I915_SET_COLORKEY_DESTINATION)
238 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
239 else if (key->flags & I915_SET_COLORKEY_SOURCE)
240 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
241
242 /* Sizes are 0 based */
243 src_w--;
244 src_h--;
245 crtc_w--;
246 crtc_h--;
247
248 I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
249 I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
250 I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w);
251
252 /* program plane scaler */
253 if (plane_state->scaler_id >= 0) {
254 int scaler_id = plane_state->scaler_id;
255 const struct intel_scaler *scaler;
256
257 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
258 PS_PLANE_SEL(plane));
259
260 scaler = &crtc_state->scaler_state.scalers[scaler_id];
261
262 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),
263 PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode);
264 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
265 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
266 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
267 ((crtc_w + 1) << 16)|(crtc_h + 1));
268
269 I915_WRITE(PLANE_POS(pipe, plane), 0);
270 } else {
271 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
272 }
273
274 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
275 I915_WRITE(PLANE_SURF(pipe, plane),
276 intel_plane_ggtt_offset(plane_state) + surf_addr);
277 POSTING_READ(PLANE_SURF(pipe, plane));
278}
279
280static void
281skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
282{
283 struct drm_device *dev = dplane->dev;
284 struct drm_i915_private *dev_priv = to_i915(dev);
285 struct intel_plane *intel_plane = to_intel_plane(dplane);
286 const int pipe = intel_plane->pipe;
287 const int plane = intel_plane->plane + 1;
288
289 I915_WRITE(PLANE_CTL(pipe, plane), 0);
290
291 I915_WRITE(PLANE_SURF(pipe, plane), 0);
292 POSTING_READ(PLANE_SURF(pipe, plane));
293}
294
295static void
296chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
297{
298 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
299 int plane = intel_plane->plane;
300
301 /* Seems RGB data bypasses the CSC always */
302 if (!format_is_yuv(format))
303 return;
304
305 /*
306 * BT.601 limited range YCbCr -> full range RGB
307 *
308 * |r| | 6537 4769 0| |cr |
309 * |g| = |-3330 4769 -1605| x |y-64|
310 * |b| | 0 4769 8263| |cb |
311 *
312 * Cb and Cr apparently come in as signed already, so no
313 * need for any offset. For Y we need to remove the offset.
314 */
315 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
316 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
317 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
318
319 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
320 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
321 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
322 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
323 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
324
325 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
326 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
327 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
328
329 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
330 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
331 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
332}
333
334static void
335vlv_update_plane(struct drm_plane *dplane,
336 const struct intel_crtc_state *crtc_state,
337 const struct intel_plane_state *plane_state)
338{
339 struct drm_device *dev = dplane->dev;
340 struct drm_i915_private *dev_priv = to_i915(dev);
341 struct intel_plane *intel_plane = to_intel_plane(dplane);
342 struct drm_framebuffer *fb = plane_state->base.fb;
343 int pipe = intel_plane->pipe;
344 int plane = intel_plane->plane;
345 u32 sprctl;
346 u32 sprsurf_offset, linear_offset;
347 unsigned int rotation = plane_state->base.rotation;
348 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
349 int crtc_x = plane_state->base.dst.x1;
350 int crtc_y = plane_state->base.dst.y1;
351 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
352 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
353 uint32_t x = plane_state->base.src.x1 >> 16;
354 uint32_t y = plane_state->base.src.y1 >> 16;
355 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
356 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
357
358 sprctl = SP_ENABLE;
359
360 switch (fb->pixel_format) {
361 case DRM_FORMAT_YUYV:
362 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
363 break;
364 case DRM_FORMAT_YVYU:
365 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
366 break;
367 case DRM_FORMAT_UYVY:
368 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
369 break;
370 case DRM_FORMAT_VYUY:
371 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
372 break;
373 case DRM_FORMAT_RGB565:
374 sprctl |= SP_FORMAT_BGR565;
375 break;
376 case DRM_FORMAT_XRGB8888:
377 sprctl |= SP_FORMAT_BGRX8888;
378 break;
379 case DRM_FORMAT_ARGB8888:
380 sprctl |= SP_FORMAT_BGRA8888;
381 break;
382 case DRM_FORMAT_XBGR2101010:
383 sprctl |= SP_FORMAT_RGBX1010102;
384 break;
385 case DRM_FORMAT_ABGR2101010:
386 sprctl |= SP_FORMAT_RGBA1010102;
387 break;
388 case DRM_FORMAT_XBGR8888:
389 sprctl |= SP_FORMAT_RGBX8888;
390 break;
391 case DRM_FORMAT_ABGR8888:
392 sprctl |= SP_FORMAT_RGBA8888;
393 break;
394 default:
395 /*
396 * If we get here one of the upper layers failed to filter
397 * out the unsupported plane formats
398 */
399 BUG();
400 break;
401 }
402
403 /*
404 * Enable gamma to match primary/cursor plane behaviour.
405 * FIXME should be user controllable via propertiesa.
406 */
407 sprctl |= SP_GAMMA_ENABLE;
408
409 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
410 sprctl |= SP_TILED;
411
412 if (rotation & DRM_ROTATE_180)
413 sprctl |= SP_ROTATE_180;
414
415 if (rotation & DRM_REFLECT_X)
416 sprctl |= SP_MIRROR;
417
418 /* Sizes are 0 based */
419 src_w--;
420 src_h--;
421 crtc_w--;
422 crtc_h--;
423
424 intel_add_fb_offsets(&x, &y, plane_state, 0);
425 sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
426
427 if (rotation & DRM_ROTATE_180) {
428 x += src_w;
429 y += src_h;
430 } else if (rotation & DRM_REFLECT_X) {
431 x += src_w;
432 }
433
434 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
435
436 if (key->flags) {
437 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
438 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
439 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
440 }
441
442 if (key->flags & I915_SET_COLORKEY_SOURCE)
443 sprctl |= SP_SOURCE_KEY;
444
445 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
446 chv_update_csc(intel_plane, fb->pixel_format);
447
448 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
449 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
450
451 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
452 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
453 else
454 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
455
456 I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
457
458 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
459 I915_WRITE(SPCNTR(pipe, plane), sprctl);
460 I915_WRITE(SPSURF(pipe, plane),
461 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
462 POSTING_READ(SPSURF(pipe, plane));
463}
464
465static void
466vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
467{
468 struct drm_device *dev = dplane->dev;
469 struct drm_i915_private *dev_priv = to_i915(dev);
470 struct intel_plane *intel_plane = to_intel_plane(dplane);
471 int pipe = intel_plane->pipe;
472 int plane = intel_plane->plane;
473
474 I915_WRITE(SPCNTR(pipe, plane), 0);
475
476 I915_WRITE(SPSURF(pipe, plane), 0);
477 POSTING_READ(SPSURF(pipe, plane));
478}
479
480static void
481ivb_update_plane(struct drm_plane *plane,
482 const struct intel_crtc_state *crtc_state,
483 const struct intel_plane_state *plane_state)
484{
485 struct drm_device *dev = plane->dev;
486 struct drm_i915_private *dev_priv = to_i915(dev);
487 struct intel_plane *intel_plane = to_intel_plane(plane);
488 struct drm_framebuffer *fb = plane_state->base.fb;
489 enum pipe pipe = intel_plane->pipe;
490 u32 sprctl, sprscale = 0;
491 u32 sprsurf_offset, linear_offset;
492 unsigned int rotation = plane_state->base.rotation;
493 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
494 int crtc_x = plane_state->base.dst.x1;
495 int crtc_y = plane_state->base.dst.y1;
496 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
497 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
498 uint32_t x = plane_state->base.src.x1 >> 16;
499 uint32_t y = plane_state->base.src.y1 >> 16;
500 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
501 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
502
503 sprctl = SPRITE_ENABLE;
504
505 switch (fb->pixel_format) {
506 case DRM_FORMAT_XBGR8888:
507 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
508 break;
509 case DRM_FORMAT_XRGB8888:
510 sprctl |= SPRITE_FORMAT_RGBX888;
511 break;
512 case DRM_FORMAT_YUYV:
513 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
514 break;
515 case DRM_FORMAT_YVYU:
516 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
517 break;
518 case DRM_FORMAT_UYVY:
519 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
520 break;
521 case DRM_FORMAT_VYUY:
522 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
523 break;
524 default:
525 BUG();
526 }
527
528 /*
529 * Enable gamma to match primary/cursor plane behaviour.
530 * FIXME should be user controllable via propertiesa.
531 */
532 sprctl |= SPRITE_GAMMA_ENABLE;
533
534 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
535 sprctl |= SPRITE_TILED;
536
537 if (rotation & DRM_ROTATE_180)
538 sprctl |= SPRITE_ROTATE_180;
539
540 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
541 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
542 else
543 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
544
545 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
546 sprctl |= SPRITE_PIPE_CSC_ENABLE;
547
548 /* Sizes are 0 based */
549 src_w--;
550 src_h--;
551 crtc_w--;
552 crtc_h--;
553
554 if (crtc_w != src_w || crtc_h != src_h)
555 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
556
557 intel_add_fb_offsets(&x, &y, plane_state, 0);
558 sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
559
560 /* HSW+ does this automagically in hardware */
561 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
562 rotation & DRM_ROTATE_180) {
563 x += src_w;
564 y += src_h;
565 }
566
567 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
568
569 if (key->flags) {
570 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
571 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
572 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
573 }
574
575 if (key->flags & I915_SET_COLORKEY_DESTINATION)
576 sprctl |= SPRITE_DEST_KEY;
577 else if (key->flags & I915_SET_COLORKEY_SOURCE)
578 sprctl |= SPRITE_SOURCE_KEY;
579
580 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
581 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
582
583 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
584 * register */
585 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
586 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
587 else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
588 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
589 else
590 I915_WRITE(SPRLINOFF(pipe), linear_offset);
591
592 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
593 if (intel_plane->can_scale)
594 I915_WRITE(SPRSCALE(pipe), sprscale);
595 I915_WRITE(SPRCTL(pipe), sprctl);
596 I915_WRITE(SPRSURF(pipe),
597 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
598 POSTING_READ(SPRSURF(pipe));
599}
600
601static void
602ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
603{
604 struct drm_device *dev = plane->dev;
605 struct drm_i915_private *dev_priv = to_i915(dev);
606 struct intel_plane *intel_plane = to_intel_plane(plane);
607 int pipe = intel_plane->pipe;
608
609 I915_WRITE(SPRCTL(pipe), 0);
610 /* Can't leave the scaler enabled... */
611 if (intel_plane->can_scale)
612 I915_WRITE(SPRSCALE(pipe), 0);
613
614 I915_WRITE(SPRSURF(pipe), 0);
615 POSTING_READ(SPRSURF(pipe));
616}
617
618static void
619ilk_update_plane(struct drm_plane *plane,
620 const struct intel_crtc_state *crtc_state,
621 const struct intel_plane_state *plane_state)
622{
623 struct drm_device *dev = plane->dev;
624 struct drm_i915_private *dev_priv = to_i915(dev);
625 struct intel_plane *intel_plane = to_intel_plane(plane);
626 struct drm_framebuffer *fb = plane_state->base.fb;
627 int pipe = intel_plane->pipe;
628 u32 dvscntr, dvsscale;
629 u32 dvssurf_offset, linear_offset;
630 unsigned int rotation = plane_state->base.rotation;
631 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
632 int crtc_x = plane_state->base.dst.x1;
633 int crtc_y = plane_state->base.dst.y1;
634 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
635 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
636 uint32_t x = plane_state->base.src.x1 >> 16;
637 uint32_t y = plane_state->base.src.y1 >> 16;
638 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
639 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
640
641 dvscntr = DVS_ENABLE;
642
643 switch (fb->pixel_format) {
644 case DRM_FORMAT_XBGR8888:
645 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
646 break;
647 case DRM_FORMAT_XRGB8888:
648 dvscntr |= DVS_FORMAT_RGBX888;
649 break;
650 case DRM_FORMAT_YUYV:
651 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
652 break;
653 case DRM_FORMAT_YVYU:
654 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
655 break;
656 case DRM_FORMAT_UYVY:
657 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
658 break;
659 case DRM_FORMAT_VYUY:
660 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
661 break;
662 default:
663 BUG();
664 }
665
666 /*
667 * Enable gamma to match primary/cursor plane behaviour.
668 * FIXME should be user controllable via propertiesa.
669 */
670 dvscntr |= DVS_GAMMA_ENABLE;
671
672 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
673 dvscntr |= DVS_TILED;
674
675 if (rotation & DRM_ROTATE_180)
676 dvscntr |= DVS_ROTATE_180;
677
678 if (IS_GEN6(dev_priv))
679 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
680
681 /* Sizes are 0 based */
682 src_w--;
683 src_h--;
684 crtc_w--;
685 crtc_h--;
686
687 dvsscale = 0;
688 if (crtc_w != src_w || crtc_h != src_h)
689 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
690
691 intel_add_fb_offsets(&x, &y, plane_state, 0);
692 dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
693
694 if (rotation & DRM_ROTATE_180) {
695 x += src_w;
696 y += src_h;
697 }
698
699 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
700
701 if (key->flags) {
702 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
703 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
704 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
705 }
706
707 if (key->flags & I915_SET_COLORKEY_DESTINATION)
708 dvscntr |= DVS_DEST_KEY;
709 else if (key->flags & I915_SET_COLORKEY_SOURCE)
710 dvscntr |= DVS_SOURCE_KEY;
711
712 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
713 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
714
715 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
716 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
717 else
718 I915_WRITE(DVSLINOFF(pipe), linear_offset);
719
720 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
721 I915_WRITE(DVSSCALE(pipe), dvsscale);
722 I915_WRITE(DVSCNTR(pipe), dvscntr);
723 I915_WRITE(DVSSURF(pipe),
724 intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
725 POSTING_READ(DVSSURF(pipe));
726}
727
728static void
729ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
730{
731 struct drm_device *dev = plane->dev;
732 struct drm_i915_private *dev_priv = to_i915(dev);
733 struct intel_plane *intel_plane = to_intel_plane(plane);
734 int pipe = intel_plane->pipe;
735
736 I915_WRITE(DVSCNTR(pipe), 0);
737 /* Disable the scaler */
738 I915_WRITE(DVSSCALE(pipe), 0);
739
740 I915_WRITE(DVSSURF(pipe), 0);
741 POSTING_READ(DVSSURF(pipe));
742}
743
744static int
745intel_check_sprite_plane(struct drm_plane *plane,
746 struct intel_crtc_state *crtc_state,
747 struct intel_plane_state *state)
748{
749 struct drm_i915_private *dev_priv = to_i915(plane->dev);
750 struct drm_crtc *crtc = state->base.crtc;
751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
752 struct intel_plane *intel_plane = to_intel_plane(plane);
753 struct drm_framebuffer *fb = state->base.fb;
754 int crtc_x, crtc_y;
755 unsigned int crtc_w, crtc_h;
756 uint32_t src_x, src_y, src_w, src_h;
757 struct drm_rect *src = &state->base.src;
758 struct drm_rect *dst = &state->base.dst;
759 const struct drm_rect *clip = &state->clip;
760 int hscale, vscale;
761 int max_scale, min_scale;
762 bool can_scale;
763 int ret;
764
765 *src = drm_plane_state_src(&state->base);
766 *dst = drm_plane_state_dest(&state->base);
767
768 if (!fb) {
769 state->base.visible = false;
770 return 0;
771 }
772
773 /* Don't modify another pipe's plane */
774 if (intel_plane->pipe != intel_crtc->pipe) {
775 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
776 return -EINVAL;
777 }
778
779 /* FIXME check all gen limits */
780 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
781 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
782 return -EINVAL;
783 }
784
785 /* setup can_scale, min_scale, max_scale */
786 if (INTEL_GEN(dev_priv) >= 9) {
787 /* use scaler when colorkey is not required */
788 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
789 can_scale = 1;
790 min_scale = 1;
791 max_scale = skl_max_scale(intel_crtc, crtc_state);
792 } else {
793 can_scale = 0;
794 min_scale = DRM_PLANE_HELPER_NO_SCALING;
795 max_scale = DRM_PLANE_HELPER_NO_SCALING;
796 }
797 } else {
798 can_scale = intel_plane->can_scale;
799 max_scale = intel_plane->max_downscale << 16;
800 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
801 }
802
803 /*
804 * FIXME the following code does a bunch of fuzzy adjustments to the
805 * coordinates and sizes. We probably need some way to decide whether
806 * more strict checking should be done instead.
807 */
808 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
809 state->base.rotation);
810
811 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
812 BUG_ON(hscale < 0);
813
814 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
815 BUG_ON(vscale < 0);
816
817 state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
818
819 crtc_x = dst->x1;
820 crtc_y = dst->y1;
821 crtc_w = drm_rect_width(dst);
822 crtc_h = drm_rect_height(dst);
823
824 if (state->base.visible) {
825 /* check again in case clipping clamped the results */
826 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
827 if (hscale < 0) {
828 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
829 drm_rect_debug_print("src: ", src, true);
830 drm_rect_debug_print("dst: ", dst, false);
831
832 return hscale;
833 }
834
835 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
836 if (vscale < 0) {
837 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
838 drm_rect_debug_print("src: ", src, true);
839 drm_rect_debug_print("dst: ", dst, false);
840
841 return vscale;
842 }
843
844 /* Make the source viewport size an exact multiple of the scaling factors. */
845 drm_rect_adjust_size(src,
846 drm_rect_width(dst) * hscale - drm_rect_width(src),
847 drm_rect_height(dst) * vscale - drm_rect_height(src));
848
849 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
850 state->base.rotation);
851
852 /* sanity check to make sure the src viewport wasn't enlarged */
853 WARN_ON(src->x1 < (int) state->base.src_x ||
854 src->y1 < (int) state->base.src_y ||
855 src->x2 > (int) state->base.src_x + state->base.src_w ||
856 src->y2 > (int) state->base.src_y + state->base.src_h);
857
858 /*
859 * Hardware doesn't handle subpixel coordinates.
860 * Adjust to (macro)pixel boundary, but be careful not to
861 * increase the source viewport size, because that could
862 * push the downscaling factor out of bounds.
863 */
864 src_x = src->x1 >> 16;
865 src_w = drm_rect_width(src) >> 16;
866 src_y = src->y1 >> 16;
867 src_h = drm_rect_height(src) >> 16;
868
869 if (format_is_yuv(fb->pixel_format)) {
870 src_x &= ~1;
871 src_w &= ~1;
872
873 /*
874 * Must keep src and dst the
875 * same if we can't scale.
876 */
877 if (!can_scale)
878 crtc_w &= ~1;
879
880 if (crtc_w == 0)
881 state->base.visible = false;
882 }
883 }
884
885 /* Check size restrictions when scaling */
886 if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
887 unsigned int width_bytes;
888 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
889
890 WARN_ON(!can_scale);
891
892 /* FIXME interlacing min height is 6 */
893
894 if (crtc_w < 3 || crtc_h < 3)
895 state->base.visible = false;
896
897 if (src_w < 3 || src_h < 3)
898 state->base.visible = false;
899
900 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
901
902 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
903 width_bytes > 4096 || fb->pitches[0] > 4096)) {
904 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
905 return -EINVAL;
906 }
907 }
908
909 if (state->base.visible) {
910 src->x1 = src_x << 16;
911 src->x2 = (src_x + src_w) << 16;
912 src->y1 = src_y << 16;
913 src->y2 = (src_y + src_h) << 16;
914 }
915
916 dst->x1 = crtc_x;
917 dst->x2 = crtc_x + crtc_w;
918 dst->y1 = crtc_y;
919 dst->y2 = crtc_y + crtc_h;
920
921 if (INTEL_GEN(dev_priv) >= 9) {
922 ret = skl_check_plane_surface(state);
923 if (ret)
924 return ret;
925 }
926
927 return 0;
928}
929
930int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
931 struct drm_file *file_priv)
932{
933 struct drm_i915_private *dev_priv = to_i915(dev);
934 struct drm_intel_sprite_colorkey *set = data;
935 struct drm_plane *plane;
936 struct drm_plane_state *plane_state;
937 struct drm_atomic_state *state;
938 struct drm_modeset_acquire_ctx ctx;
939 int ret = 0;
940
941 /* Make sure we don't try to enable both src & dest simultaneously */
942 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
943 return -EINVAL;
944
945 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
946 set->flags & I915_SET_COLORKEY_DESTINATION)
947 return -EINVAL;
948
949 plane = drm_plane_find(dev, set->plane_id);
950 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
951 return -ENOENT;
952
953 drm_modeset_acquire_init(&ctx, 0);
954
955 state = drm_atomic_state_alloc(plane->dev);
956 if (!state) {
957 ret = -ENOMEM;
958 goto out;
959 }
960 state->acquire_ctx = &ctx;
961
962 while (1) {
963 plane_state = drm_atomic_get_plane_state(state, plane);
964 ret = PTR_ERR_OR_ZERO(plane_state);
965 if (!ret) {
966 to_intel_plane_state(plane_state)->ckey = *set;
967 ret = drm_atomic_commit(state);
968 }
969
970 if (ret != -EDEADLK)
971 break;
972
973 drm_atomic_state_clear(state);
974 drm_modeset_backoff(&ctx);
975 }
976
977 drm_atomic_state_put(state);
978out:
979 drm_modeset_drop_locks(&ctx);
980 drm_modeset_acquire_fini(&ctx);
981 return ret;
982}
983
984static const uint32_t ilk_plane_formats[] = {
985 DRM_FORMAT_XRGB8888,
986 DRM_FORMAT_YUYV,
987 DRM_FORMAT_YVYU,
988 DRM_FORMAT_UYVY,
989 DRM_FORMAT_VYUY,
990};
991
992static const uint32_t snb_plane_formats[] = {
993 DRM_FORMAT_XBGR8888,
994 DRM_FORMAT_XRGB8888,
995 DRM_FORMAT_YUYV,
996 DRM_FORMAT_YVYU,
997 DRM_FORMAT_UYVY,
998 DRM_FORMAT_VYUY,
999};
1000
1001static const uint32_t vlv_plane_formats[] = {
1002 DRM_FORMAT_RGB565,
1003 DRM_FORMAT_ABGR8888,
1004 DRM_FORMAT_ARGB8888,
1005 DRM_FORMAT_XBGR8888,
1006 DRM_FORMAT_XRGB8888,
1007 DRM_FORMAT_XBGR2101010,
1008 DRM_FORMAT_ABGR2101010,
1009 DRM_FORMAT_YUYV,
1010 DRM_FORMAT_YVYU,
1011 DRM_FORMAT_UYVY,
1012 DRM_FORMAT_VYUY,
1013};
1014
1015static uint32_t skl_plane_formats[] = {
1016 DRM_FORMAT_RGB565,
1017 DRM_FORMAT_ABGR8888,
1018 DRM_FORMAT_ARGB8888,
1019 DRM_FORMAT_XBGR8888,
1020 DRM_FORMAT_XRGB8888,
1021 DRM_FORMAT_YUYV,
1022 DRM_FORMAT_YVYU,
1023 DRM_FORMAT_UYVY,
1024 DRM_FORMAT_VYUY,
1025};
1026
1027struct intel_plane *
1028intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1029 enum pipe pipe, int plane)
1030{
1031 struct intel_plane *intel_plane = NULL;
1032 struct intel_plane_state *state = NULL;
1033 unsigned long possible_crtcs;
1034 const uint32_t *plane_formats;
1035 unsigned int supported_rotations;
1036 int num_plane_formats;
1037 int ret;
1038
1039 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1040 if (!intel_plane) {
1041 ret = -ENOMEM;
1042 goto fail;
1043 }
1044
1045 state = intel_create_plane_state(&intel_plane->base);
1046 if (!state) {
1047 ret = -ENOMEM;
1048 goto fail;
1049 }
1050 intel_plane->base.state = &state->base;
1051
1052 if (INTEL_GEN(dev_priv) >= 9) {
1053 intel_plane->can_scale = true;
1054 state->scaler_id = -1;
1055
1056 intel_plane->update_plane = skl_update_plane;
1057 intel_plane->disable_plane = skl_disable_plane;
1058
1059 plane_formats = skl_plane_formats;
1060 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1061 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1062 intel_plane->can_scale = false;
1063 intel_plane->max_downscale = 1;
1064
1065 intel_plane->update_plane = vlv_update_plane;
1066 intel_plane->disable_plane = vlv_disable_plane;
1067
1068 plane_formats = vlv_plane_formats;
1069 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1070 } else if (INTEL_GEN(dev_priv) >= 7) {
1071 if (IS_IVYBRIDGE(dev_priv)) {
1072 intel_plane->can_scale = true;
1073 intel_plane->max_downscale = 2;
1074 } else {
1075 intel_plane->can_scale = false;
1076 intel_plane->max_downscale = 1;
1077 }
1078
1079 intel_plane->update_plane = ivb_update_plane;
1080 intel_plane->disable_plane = ivb_disable_plane;
1081
1082 plane_formats = snb_plane_formats;
1083 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1084 } else {
1085 intel_plane->can_scale = true;
1086 intel_plane->max_downscale = 16;
1087
1088 intel_plane->update_plane = ilk_update_plane;
1089 intel_plane->disable_plane = ilk_disable_plane;
1090
1091 if (IS_GEN6(dev_priv)) {
1092 plane_formats = snb_plane_formats;
1093 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1094 } else {
1095 plane_formats = ilk_plane_formats;
1096 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1097 }
1098 }
1099
1100 if (INTEL_GEN(dev_priv) >= 9) {
1101 supported_rotations =
1102 DRM_ROTATE_0 | DRM_ROTATE_90 |
1103 DRM_ROTATE_180 | DRM_ROTATE_270;
1104 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1105 supported_rotations =
1106 DRM_ROTATE_0 | DRM_ROTATE_180 |
1107 DRM_REFLECT_X;
1108 } else {
1109 supported_rotations =
1110 DRM_ROTATE_0 | DRM_ROTATE_180;
1111 }
1112
1113 intel_plane->pipe = pipe;
1114 intel_plane->plane = plane;
1115 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1116 intel_plane->check_plane = intel_check_sprite_plane;
1117
1118 possible_crtcs = (1 << pipe);
1119
1120 if (INTEL_GEN(dev_priv) >= 9)
1121 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1122 possible_crtcs, &intel_plane_funcs,
1123 plane_formats, num_plane_formats,
1124 DRM_PLANE_TYPE_OVERLAY,
1125 "plane %d%c", plane + 2, pipe_name(pipe));
1126 else
1127 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1128 possible_crtcs, &intel_plane_funcs,
1129 plane_formats, num_plane_formats,
1130 DRM_PLANE_TYPE_OVERLAY,
1131 "sprite %c", sprite_name(pipe, plane));
1132 if (ret)
1133 goto fail;
1134
1135 drm_plane_create_rotation_property(&intel_plane->base,
1136 DRM_ROTATE_0,
1137 supported_rotations);
1138
1139 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1140
1141 return intel_plane;
1142
1143fail:
1144 kfree(state);
1145 kfree(intel_plane);
1146
1147 return ERR_PTR(ret);
1148}