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1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/platform_device.h>
33#include <linux/slab.h>
34#include <linux/spi/spi.h>
35#include <linux/spi/spi_bitbang.h>
36#include <linux/types.h>
37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_gpio.h>
40
41#include <mach/spi.h>
42
43#define DRIVER_NAME "spi_imx"
44
45#define MXC_CSPIRXDATA 0x00
46#define MXC_CSPITXDATA 0x04
47#define MXC_CSPICTRL 0x08
48#define MXC_CSPIINT 0x0c
49#define MXC_RESET 0x1c
50
51/* generic defines to abstract from the different register layouts */
52#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
53#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
54
55struct spi_imx_config {
56 unsigned int speed_hz;
57 unsigned int bpw;
58 unsigned int mode;
59 u8 cs;
60};
61
62enum spi_imx_devtype {
63 IMX1_CSPI,
64 IMX21_CSPI,
65 IMX27_CSPI,
66 IMX31_CSPI,
67 IMX35_CSPI, /* CSPI on all i.mx except above */
68 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
69};
70
71struct spi_imx_data;
72
73struct spi_imx_devtype_data {
74 void (*intctrl)(struct spi_imx_data *, int);
75 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
76 void (*trigger)(struct spi_imx_data *);
77 int (*rx_available)(struct spi_imx_data *);
78 void (*reset)(struct spi_imx_data *);
79 enum spi_imx_devtype devtype;
80};
81
82struct spi_imx_data {
83 struct spi_bitbang bitbang;
84
85 struct completion xfer_done;
86 void *base;
87 int irq;
88 struct clk *clk;
89 unsigned long spi_clk;
90
91 unsigned int count;
92 void (*tx)(struct spi_imx_data *);
93 void (*rx)(struct spi_imx_data *);
94 void *rx_buf;
95 const void *tx_buf;
96 unsigned int txfifo; /* number of words pushed in tx FIFO */
97
98 struct spi_imx_devtype_data *devtype_data;
99 int chipselect[0];
100};
101
102static inline int is_imx27_cspi(struct spi_imx_data *d)
103{
104 return d->devtype_data->devtype == IMX27_CSPI;
105}
106
107static inline int is_imx35_cspi(struct spi_imx_data *d)
108{
109 return d->devtype_data->devtype == IMX35_CSPI;
110}
111
112static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
113{
114 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
115}
116
117#define MXC_SPI_BUF_RX(type) \
118static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
119{ \
120 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
121 \
122 if (spi_imx->rx_buf) { \
123 *(type *)spi_imx->rx_buf = val; \
124 spi_imx->rx_buf += sizeof(type); \
125 } \
126}
127
128#define MXC_SPI_BUF_TX(type) \
129static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
130{ \
131 type val = 0; \
132 \
133 if (spi_imx->tx_buf) { \
134 val = *(type *)spi_imx->tx_buf; \
135 spi_imx->tx_buf += sizeof(type); \
136 } \
137 \
138 spi_imx->count -= sizeof(type); \
139 \
140 writel(val, spi_imx->base + MXC_CSPITXDATA); \
141}
142
143MXC_SPI_BUF_RX(u8)
144MXC_SPI_BUF_TX(u8)
145MXC_SPI_BUF_RX(u16)
146MXC_SPI_BUF_TX(u16)
147MXC_SPI_BUF_RX(u32)
148MXC_SPI_BUF_TX(u32)
149
150/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
151 * (which is currently not the case in this driver)
152 */
153static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
154 256, 384, 512, 768, 1024};
155
156/* MX21, MX27 */
157static unsigned int spi_imx_clkdiv_1(unsigned int fin,
158 unsigned int fspi, unsigned int max)
159{
160 int i;
161
162 for (i = 2; i < max; i++)
163 if (fspi * mxc_clkdivs[i] >= fin)
164 return i;
165
166 return max;
167}
168
169/* MX1, MX31, MX35, MX51 CSPI */
170static unsigned int spi_imx_clkdiv_2(unsigned int fin,
171 unsigned int fspi)
172{
173 int i, div = 4;
174
175 for (i = 0; i < 7; i++) {
176 if (fspi * div >= fin)
177 return i;
178 div <<= 1;
179 }
180
181 return 7;
182}
183
184#define MX51_ECSPI_CTRL 0x08
185#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
186#define MX51_ECSPI_CTRL_XCH (1 << 2)
187#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
188#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
189#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
190#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
191#define MX51_ECSPI_CTRL_BL_OFFSET 20
192
193#define MX51_ECSPI_CONFIG 0x0c
194#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
195#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
196#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
197#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
198
199#define MX51_ECSPI_INT 0x10
200#define MX51_ECSPI_INT_TEEN (1 << 0)
201#define MX51_ECSPI_INT_RREN (1 << 3)
202
203#define MX51_ECSPI_STAT 0x18
204#define MX51_ECSPI_STAT_RR (1 << 3)
205
206/* MX51 eCSPI */
207static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
208{
209 /*
210 * there are two 4-bit dividers, the pre-divider divides by
211 * $pre, the post-divider by 2^$post
212 */
213 unsigned int pre, post;
214
215 if (unlikely(fspi > fin))
216 return 0;
217
218 post = fls(fin) - fls(fspi);
219 if (fin > fspi << post)
220 post++;
221
222 /* now we have: (fin <= fspi << post) with post being minimal */
223
224 post = max(4U, post) - 4;
225 if (unlikely(post > 0xf)) {
226 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
227 __func__, fspi, fin);
228 return 0xff;
229 }
230
231 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
232
233 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
234 __func__, fin, fspi, post, pre);
235 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
236 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
237}
238
239static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
240{
241 unsigned val = 0;
242
243 if (enable & MXC_INT_TE)
244 val |= MX51_ECSPI_INT_TEEN;
245
246 if (enable & MXC_INT_RR)
247 val |= MX51_ECSPI_INT_RREN;
248
249 writel(val, spi_imx->base + MX51_ECSPI_INT);
250}
251
252static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
253{
254 u32 reg;
255
256 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
257 reg |= MX51_ECSPI_CTRL_XCH;
258 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
259}
260
261static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
262 struct spi_imx_config *config)
263{
264 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
265
266 /*
267 * The hardware seems to have a race condition when changing modes. The
268 * current assumption is that the selection of the channel arrives
269 * earlier in the hardware than the mode bits when they are written at
270 * the same time.
271 * So set master mode for all channels as we do not support slave mode.
272 */
273 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
274
275 /* set clock speed */
276 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz);
277
278 /* set chip select to use */
279 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
280
281 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
282
283 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
284
285 if (config->mode & SPI_CPHA)
286 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
287
288 if (config->mode & SPI_CPOL)
289 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
290
291 if (config->mode & SPI_CS_HIGH)
292 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
293
294 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
295 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
296
297 return 0;
298}
299
300static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
301{
302 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
303}
304
305static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
306{
307 /* drain receive buffer */
308 while (mx51_ecspi_rx_available(spi_imx))
309 readl(spi_imx->base + MXC_CSPIRXDATA);
310}
311
312#define MX31_INTREG_TEEN (1 << 0)
313#define MX31_INTREG_RREN (1 << 3)
314
315#define MX31_CSPICTRL_ENABLE (1 << 0)
316#define MX31_CSPICTRL_MASTER (1 << 1)
317#define MX31_CSPICTRL_XCH (1 << 2)
318#define MX31_CSPICTRL_POL (1 << 4)
319#define MX31_CSPICTRL_PHA (1 << 5)
320#define MX31_CSPICTRL_SSCTL (1 << 6)
321#define MX31_CSPICTRL_SSPOL (1 << 7)
322#define MX31_CSPICTRL_BC_SHIFT 8
323#define MX35_CSPICTRL_BL_SHIFT 20
324#define MX31_CSPICTRL_CS_SHIFT 24
325#define MX35_CSPICTRL_CS_SHIFT 12
326#define MX31_CSPICTRL_DR_SHIFT 16
327
328#define MX31_CSPISTATUS 0x14
329#define MX31_STATUS_RR (1 << 3)
330
331/* These functions also work for the i.MX35, but be aware that
332 * the i.MX35 has a slightly different register layout for bits
333 * we do not use here.
334 */
335static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
336{
337 unsigned int val = 0;
338
339 if (enable & MXC_INT_TE)
340 val |= MX31_INTREG_TEEN;
341 if (enable & MXC_INT_RR)
342 val |= MX31_INTREG_RREN;
343
344 writel(val, spi_imx->base + MXC_CSPIINT);
345}
346
347static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
348{
349 unsigned int reg;
350
351 reg = readl(spi_imx->base + MXC_CSPICTRL);
352 reg |= MX31_CSPICTRL_XCH;
353 writel(reg, spi_imx->base + MXC_CSPICTRL);
354}
355
356static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
357 struct spi_imx_config *config)
358{
359 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
360 int cs = spi_imx->chipselect[config->cs];
361
362 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
363 MX31_CSPICTRL_DR_SHIFT;
364
365 if (is_imx35_cspi(spi_imx)) {
366 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
367 reg |= MX31_CSPICTRL_SSCTL;
368 } else {
369 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
370 }
371
372 if (config->mode & SPI_CPHA)
373 reg |= MX31_CSPICTRL_PHA;
374 if (config->mode & SPI_CPOL)
375 reg |= MX31_CSPICTRL_POL;
376 if (config->mode & SPI_CS_HIGH)
377 reg |= MX31_CSPICTRL_SSPOL;
378 if (cs < 0)
379 reg |= (cs + 32) <<
380 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
381 MX31_CSPICTRL_CS_SHIFT);
382
383 writel(reg, spi_imx->base + MXC_CSPICTRL);
384
385 return 0;
386}
387
388static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
389{
390 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
391}
392
393static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
394{
395 /* drain receive buffer */
396 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
397 readl(spi_imx->base + MXC_CSPIRXDATA);
398}
399
400#define MX21_INTREG_RR (1 << 4)
401#define MX21_INTREG_TEEN (1 << 9)
402#define MX21_INTREG_RREN (1 << 13)
403
404#define MX21_CSPICTRL_POL (1 << 5)
405#define MX21_CSPICTRL_PHA (1 << 6)
406#define MX21_CSPICTRL_SSPOL (1 << 8)
407#define MX21_CSPICTRL_XCH (1 << 9)
408#define MX21_CSPICTRL_ENABLE (1 << 10)
409#define MX21_CSPICTRL_MASTER (1 << 11)
410#define MX21_CSPICTRL_DR_SHIFT 14
411#define MX21_CSPICTRL_CS_SHIFT 19
412
413static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
414{
415 unsigned int val = 0;
416
417 if (enable & MXC_INT_TE)
418 val |= MX21_INTREG_TEEN;
419 if (enable & MXC_INT_RR)
420 val |= MX21_INTREG_RREN;
421
422 writel(val, spi_imx->base + MXC_CSPIINT);
423}
424
425static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
426{
427 unsigned int reg;
428
429 reg = readl(spi_imx->base + MXC_CSPICTRL);
430 reg |= MX21_CSPICTRL_XCH;
431 writel(reg, spi_imx->base + MXC_CSPICTRL);
432}
433
434static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
435 struct spi_imx_config *config)
436{
437 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
438 int cs = spi_imx->chipselect[config->cs];
439 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
440
441 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
442 MX21_CSPICTRL_DR_SHIFT;
443 reg |= config->bpw - 1;
444
445 if (config->mode & SPI_CPHA)
446 reg |= MX21_CSPICTRL_PHA;
447 if (config->mode & SPI_CPOL)
448 reg |= MX21_CSPICTRL_POL;
449 if (config->mode & SPI_CS_HIGH)
450 reg |= MX21_CSPICTRL_SSPOL;
451 if (cs < 0)
452 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
453
454 writel(reg, spi_imx->base + MXC_CSPICTRL);
455
456 return 0;
457}
458
459static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
460{
461 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
462}
463
464static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
465{
466 writel(1, spi_imx->base + MXC_RESET);
467}
468
469#define MX1_INTREG_RR (1 << 3)
470#define MX1_INTREG_TEEN (1 << 8)
471#define MX1_INTREG_RREN (1 << 11)
472
473#define MX1_CSPICTRL_POL (1 << 4)
474#define MX1_CSPICTRL_PHA (1 << 5)
475#define MX1_CSPICTRL_XCH (1 << 8)
476#define MX1_CSPICTRL_ENABLE (1 << 9)
477#define MX1_CSPICTRL_MASTER (1 << 10)
478#define MX1_CSPICTRL_DR_SHIFT 13
479
480static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
481{
482 unsigned int val = 0;
483
484 if (enable & MXC_INT_TE)
485 val |= MX1_INTREG_TEEN;
486 if (enable & MXC_INT_RR)
487 val |= MX1_INTREG_RREN;
488
489 writel(val, spi_imx->base + MXC_CSPIINT);
490}
491
492static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
493{
494 unsigned int reg;
495
496 reg = readl(spi_imx->base + MXC_CSPICTRL);
497 reg |= MX1_CSPICTRL_XCH;
498 writel(reg, spi_imx->base + MXC_CSPICTRL);
499}
500
501static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
502 struct spi_imx_config *config)
503{
504 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
505
506 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
507 MX1_CSPICTRL_DR_SHIFT;
508 reg |= config->bpw - 1;
509
510 if (config->mode & SPI_CPHA)
511 reg |= MX1_CSPICTRL_PHA;
512 if (config->mode & SPI_CPOL)
513 reg |= MX1_CSPICTRL_POL;
514
515 writel(reg, spi_imx->base + MXC_CSPICTRL);
516
517 return 0;
518}
519
520static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
521{
522 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
523}
524
525static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
526{
527 writel(1, spi_imx->base + MXC_RESET);
528}
529
530static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
531 .intctrl = mx1_intctrl,
532 .config = mx1_config,
533 .trigger = mx1_trigger,
534 .rx_available = mx1_rx_available,
535 .reset = mx1_reset,
536 .devtype = IMX1_CSPI,
537};
538
539static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
540 .intctrl = mx21_intctrl,
541 .config = mx21_config,
542 .trigger = mx21_trigger,
543 .rx_available = mx21_rx_available,
544 .reset = mx21_reset,
545 .devtype = IMX21_CSPI,
546};
547
548static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
549 /* i.mx27 cspi shares the functions with i.mx21 one */
550 .intctrl = mx21_intctrl,
551 .config = mx21_config,
552 .trigger = mx21_trigger,
553 .rx_available = mx21_rx_available,
554 .reset = mx21_reset,
555 .devtype = IMX27_CSPI,
556};
557
558static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
559 .intctrl = mx31_intctrl,
560 .config = mx31_config,
561 .trigger = mx31_trigger,
562 .rx_available = mx31_rx_available,
563 .reset = mx31_reset,
564 .devtype = IMX31_CSPI,
565};
566
567static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
568 /* i.mx35 and later cspi shares the functions with i.mx31 one */
569 .intctrl = mx31_intctrl,
570 .config = mx31_config,
571 .trigger = mx31_trigger,
572 .rx_available = mx31_rx_available,
573 .reset = mx31_reset,
574 .devtype = IMX35_CSPI,
575};
576
577static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
578 .intctrl = mx51_ecspi_intctrl,
579 .config = mx51_ecspi_config,
580 .trigger = mx51_ecspi_trigger,
581 .rx_available = mx51_ecspi_rx_available,
582 .reset = mx51_ecspi_reset,
583 .devtype = IMX51_ECSPI,
584};
585
586static struct platform_device_id spi_imx_devtype[] = {
587 {
588 .name = "imx1-cspi",
589 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
590 }, {
591 .name = "imx21-cspi",
592 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
593 }, {
594 .name = "imx27-cspi",
595 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
596 }, {
597 .name = "imx31-cspi",
598 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
599 }, {
600 .name = "imx35-cspi",
601 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
602 }, {
603 .name = "imx51-ecspi",
604 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
605 }, {
606 /* sentinel */
607 }
608};
609
610static const struct of_device_id spi_imx_dt_ids[] = {
611 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
612 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
613 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
614 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
615 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
616 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
617 { /* sentinel */ }
618};
619
620static void spi_imx_chipselect(struct spi_device *spi, int is_active)
621{
622 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
623 int gpio = spi_imx->chipselect[spi->chip_select];
624 int active = is_active != BITBANG_CS_INACTIVE;
625 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
626
627 if (gpio < 0)
628 return;
629
630 gpio_set_value(gpio, dev_is_lowactive ^ active);
631}
632
633static void spi_imx_push(struct spi_imx_data *spi_imx)
634{
635 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
636 if (!spi_imx->count)
637 break;
638 spi_imx->tx(spi_imx);
639 spi_imx->txfifo++;
640 }
641
642 spi_imx->devtype_data->trigger(spi_imx);
643}
644
645static irqreturn_t spi_imx_isr(int irq, void *dev_id)
646{
647 struct spi_imx_data *spi_imx = dev_id;
648
649 while (spi_imx->devtype_data->rx_available(spi_imx)) {
650 spi_imx->rx(spi_imx);
651 spi_imx->txfifo--;
652 }
653
654 if (spi_imx->count) {
655 spi_imx_push(spi_imx);
656 return IRQ_HANDLED;
657 }
658
659 if (spi_imx->txfifo) {
660 /* No data left to push, but still waiting for rx data,
661 * enable receive data available interrupt.
662 */
663 spi_imx->devtype_data->intctrl(
664 spi_imx, MXC_INT_RR);
665 return IRQ_HANDLED;
666 }
667
668 spi_imx->devtype_data->intctrl(spi_imx, 0);
669 complete(&spi_imx->xfer_done);
670
671 return IRQ_HANDLED;
672}
673
674static int spi_imx_setupxfer(struct spi_device *spi,
675 struct spi_transfer *t)
676{
677 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
678 struct spi_imx_config config;
679
680 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
681 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
682 config.mode = spi->mode;
683 config.cs = spi->chip_select;
684
685 if (!config.speed_hz)
686 config.speed_hz = spi->max_speed_hz;
687 if (!config.bpw)
688 config.bpw = spi->bits_per_word;
689 if (!config.speed_hz)
690 config.speed_hz = spi->max_speed_hz;
691
692 /* Initialize the functions for transfer */
693 if (config.bpw <= 8) {
694 spi_imx->rx = spi_imx_buf_rx_u8;
695 spi_imx->tx = spi_imx_buf_tx_u8;
696 } else if (config.bpw <= 16) {
697 spi_imx->rx = spi_imx_buf_rx_u16;
698 spi_imx->tx = spi_imx_buf_tx_u16;
699 } else if (config.bpw <= 32) {
700 spi_imx->rx = spi_imx_buf_rx_u32;
701 spi_imx->tx = spi_imx_buf_tx_u32;
702 } else
703 BUG();
704
705 spi_imx->devtype_data->config(spi_imx, &config);
706
707 return 0;
708}
709
710static int spi_imx_transfer(struct spi_device *spi,
711 struct spi_transfer *transfer)
712{
713 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
714
715 spi_imx->tx_buf = transfer->tx_buf;
716 spi_imx->rx_buf = transfer->rx_buf;
717 spi_imx->count = transfer->len;
718 spi_imx->txfifo = 0;
719
720 init_completion(&spi_imx->xfer_done);
721
722 spi_imx_push(spi_imx);
723
724 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
725
726 wait_for_completion(&spi_imx->xfer_done);
727
728 return transfer->len;
729}
730
731static int spi_imx_setup(struct spi_device *spi)
732{
733 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
734 int gpio = spi_imx->chipselect[spi->chip_select];
735
736 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
737 spi->mode, spi->bits_per_word, spi->max_speed_hz);
738
739 if (gpio >= 0)
740 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
741
742 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
743
744 return 0;
745}
746
747static void spi_imx_cleanup(struct spi_device *spi)
748{
749}
750
751static int __devinit spi_imx_probe(struct platform_device *pdev)
752{
753 struct device_node *np = pdev->dev.of_node;
754 const struct of_device_id *of_id =
755 of_match_device(spi_imx_dt_ids, &pdev->dev);
756 struct spi_imx_master *mxc_platform_info =
757 dev_get_platdata(&pdev->dev);
758 struct spi_master *master;
759 struct spi_imx_data *spi_imx;
760 struct resource *res;
761 int i, ret, num_cs;
762
763 if (!np && !mxc_platform_info) {
764 dev_err(&pdev->dev, "can't get the platform data\n");
765 return -EINVAL;
766 }
767
768 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
769 if (ret < 0)
770 num_cs = mxc_platform_info->num_chipselect;
771
772 master = spi_alloc_master(&pdev->dev,
773 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
774 if (!master)
775 return -ENOMEM;
776
777 platform_set_drvdata(pdev, master);
778
779 master->bus_num = pdev->id;
780 master->num_chipselect = num_cs;
781
782 spi_imx = spi_master_get_devdata(master);
783 spi_imx->bitbang.master = spi_master_get(master);
784
785 for (i = 0; i < master->num_chipselect; i++) {
786 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
787 if (cs_gpio < 0)
788 cs_gpio = mxc_platform_info->chipselect[i];
789
790 spi_imx->chipselect[i] = cs_gpio;
791 if (cs_gpio < 0)
792 continue;
793
794 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
795 if (ret) {
796 while (i > 0) {
797 i--;
798 if (spi_imx->chipselect[i] >= 0)
799 gpio_free(spi_imx->chipselect[i]);
800 }
801 dev_err(&pdev->dev, "can't get cs gpios\n");
802 goto out_master_put;
803 }
804 }
805
806 spi_imx->bitbang.chipselect = spi_imx_chipselect;
807 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
808 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
809 spi_imx->bitbang.master->setup = spi_imx_setup;
810 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
811 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
812
813 init_completion(&spi_imx->xfer_done);
814
815 spi_imx->devtype_data = of_id ? of_id->data :
816 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
817
818 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
819 if (!res) {
820 dev_err(&pdev->dev, "can't get platform resource\n");
821 ret = -ENOMEM;
822 goto out_gpio_free;
823 }
824
825 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
826 dev_err(&pdev->dev, "request_mem_region failed\n");
827 ret = -EBUSY;
828 goto out_gpio_free;
829 }
830
831 spi_imx->base = ioremap(res->start, resource_size(res));
832 if (!spi_imx->base) {
833 ret = -EINVAL;
834 goto out_release_mem;
835 }
836
837 spi_imx->irq = platform_get_irq(pdev, 0);
838 if (spi_imx->irq < 0) {
839 ret = -EINVAL;
840 goto out_iounmap;
841 }
842
843 ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
844 if (ret) {
845 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
846 goto out_iounmap;
847 }
848
849 spi_imx->clk = clk_get(&pdev->dev, NULL);
850 if (IS_ERR(spi_imx->clk)) {
851 dev_err(&pdev->dev, "unable to get clock\n");
852 ret = PTR_ERR(spi_imx->clk);
853 goto out_free_irq;
854 }
855
856 clk_enable(spi_imx->clk);
857 spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
858
859 spi_imx->devtype_data->reset(spi_imx);
860
861 spi_imx->devtype_data->intctrl(spi_imx, 0);
862
863 master->dev.of_node = pdev->dev.of_node;
864 ret = spi_bitbang_start(&spi_imx->bitbang);
865 if (ret) {
866 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
867 goto out_clk_put;
868 }
869
870 dev_info(&pdev->dev, "probed\n");
871
872 return ret;
873
874out_clk_put:
875 clk_disable(spi_imx->clk);
876 clk_put(spi_imx->clk);
877out_free_irq:
878 free_irq(spi_imx->irq, spi_imx);
879out_iounmap:
880 iounmap(spi_imx->base);
881out_release_mem:
882 release_mem_region(res->start, resource_size(res));
883out_gpio_free:
884 for (i = 0; i < master->num_chipselect; i++)
885 if (spi_imx->chipselect[i] >= 0)
886 gpio_free(spi_imx->chipselect[i]);
887out_master_put:
888 spi_master_put(master);
889 kfree(master);
890 platform_set_drvdata(pdev, NULL);
891 return ret;
892}
893
894static int __devexit spi_imx_remove(struct platform_device *pdev)
895{
896 struct spi_master *master = platform_get_drvdata(pdev);
897 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
898 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
899 int i;
900
901 spi_bitbang_stop(&spi_imx->bitbang);
902
903 writel(0, spi_imx->base + MXC_CSPICTRL);
904 clk_disable(spi_imx->clk);
905 clk_put(spi_imx->clk);
906 free_irq(spi_imx->irq, spi_imx);
907 iounmap(spi_imx->base);
908
909 for (i = 0; i < master->num_chipselect; i++)
910 if (spi_imx->chipselect[i] >= 0)
911 gpio_free(spi_imx->chipselect[i]);
912
913 spi_master_put(master);
914
915 release_mem_region(res->start, resource_size(res));
916
917 platform_set_drvdata(pdev, NULL);
918
919 return 0;
920}
921
922static struct platform_driver spi_imx_driver = {
923 .driver = {
924 .name = DRIVER_NAME,
925 .owner = THIS_MODULE,
926 .of_match_table = spi_imx_dt_ids,
927 },
928 .id_table = spi_imx_devtype,
929 .probe = spi_imx_probe,
930 .remove = __devexit_p(spi_imx_remove),
931};
932
933static int __init spi_imx_init(void)
934{
935 return platform_driver_register(&spi_imx_driver);
936}
937
938static void __exit spi_imx_exit(void)
939{
940 platform_driver_unregister(&spi_imx_driver);
941}
942
943module_init(spi_imx_init);
944module_exit(spi_imx_exit);
945
946MODULE_DESCRIPTION("SPI Master Controller driver");
947MODULE_AUTHOR("Sascha Hauer, Pengutronix");
948MODULE_LICENSE("GPL");
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/platform_device.h>
33#include <linux/slab.h>
34#include <linux/spi/spi.h>
35#include <linux/spi/spi_bitbang.h>
36#include <linux/types.h>
37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_gpio.h>
40#include <linux/pinctrl/consumer.h>
41
42#include <mach/spi.h>
43
44#define DRIVER_NAME "spi_imx"
45
46#define MXC_CSPIRXDATA 0x00
47#define MXC_CSPITXDATA 0x04
48#define MXC_CSPICTRL 0x08
49#define MXC_CSPIINT 0x0c
50#define MXC_RESET 0x1c
51
52/* generic defines to abstract from the different register layouts */
53#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
54#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
55
56struct spi_imx_config {
57 unsigned int speed_hz;
58 unsigned int bpw;
59 unsigned int mode;
60 u8 cs;
61};
62
63enum spi_imx_devtype {
64 IMX1_CSPI,
65 IMX21_CSPI,
66 IMX27_CSPI,
67 IMX31_CSPI,
68 IMX35_CSPI, /* CSPI on all i.mx except above */
69 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
70};
71
72struct spi_imx_data;
73
74struct spi_imx_devtype_data {
75 void (*intctrl)(struct spi_imx_data *, int);
76 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
77 void (*trigger)(struct spi_imx_data *);
78 int (*rx_available)(struct spi_imx_data *);
79 void (*reset)(struct spi_imx_data *);
80 enum spi_imx_devtype devtype;
81};
82
83struct spi_imx_data {
84 struct spi_bitbang bitbang;
85
86 struct completion xfer_done;
87 void __iomem *base;
88 int irq;
89 struct clk *clk_per;
90 struct clk *clk_ipg;
91 unsigned long spi_clk;
92
93 unsigned int count;
94 void (*tx)(struct spi_imx_data *);
95 void (*rx)(struct spi_imx_data *);
96 void *rx_buf;
97 const void *tx_buf;
98 unsigned int txfifo; /* number of words pushed in tx FIFO */
99
100 struct spi_imx_devtype_data *devtype_data;
101 int chipselect[0];
102};
103
104static inline int is_imx27_cspi(struct spi_imx_data *d)
105{
106 return d->devtype_data->devtype == IMX27_CSPI;
107}
108
109static inline int is_imx35_cspi(struct spi_imx_data *d)
110{
111 return d->devtype_data->devtype == IMX35_CSPI;
112}
113
114static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
115{
116 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
117}
118
119#define MXC_SPI_BUF_RX(type) \
120static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
121{ \
122 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
123 \
124 if (spi_imx->rx_buf) { \
125 *(type *)spi_imx->rx_buf = val; \
126 spi_imx->rx_buf += sizeof(type); \
127 } \
128}
129
130#define MXC_SPI_BUF_TX(type) \
131static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
132{ \
133 type val = 0; \
134 \
135 if (spi_imx->tx_buf) { \
136 val = *(type *)spi_imx->tx_buf; \
137 spi_imx->tx_buf += sizeof(type); \
138 } \
139 \
140 spi_imx->count -= sizeof(type); \
141 \
142 writel(val, spi_imx->base + MXC_CSPITXDATA); \
143}
144
145MXC_SPI_BUF_RX(u8)
146MXC_SPI_BUF_TX(u8)
147MXC_SPI_BUF_RX(u16)
148MXC_SPI_BUF_TX(u16)
149MXC_SPI_BUF_RX(u32)
150MXC_SPI_BUF_TX(u32)
151
152/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
153 * (which is currently not the case in this driver)
154 */
155static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
156 256, 384, 512, 768, 1024};
157
158/* MX21, MX27 */
159static unsigned int spi_imx_clkdiv_1(unsigned int fin,
160 unsigned int fspi, unsigned int max)
161{
162 int i;
163
164 for (i = 2; i < max; i++)
165 if (fspi * mxc_clkdivs[i] >= fin)
166 return i;
167
168 return max;
169}
170
171/* MX1, MX31, MX35, MX51 CSPI */
172static unsigned int spi_imx_clkdiv_2(unsigned int fin,
173 unsigned int fspi)
174{
175 int i, div = 4;
176
177 for (i = 0; i < 7; i++) {
178 if (fspi * div >= fin)
179 return i;
180 div <<= 1;
181 }
182
183 return 7;
184}
185
186#define MX51_ECSPI_CTRL 0x08
187#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
188#define MX51_ECSPI_CTRL_XCH (1 << 2)
189#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
190#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
191#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
192#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
193#define MX51_ECSPI_CTRL_BL_OFFSET 20
194
195#define MX51_ECSPI_CONFIG 0x0c
196#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
197#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
198#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
199#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
200
201#define MX51_ECSPI_INT 0x10
202#define MX51_ECSPI_INT_TEEN (1 << 0)
203#define MX51_ECSPI_INT_RREN (1 << 3)
204
205#define MX51_ECSPI_STAT 0x18
206#define MX51_ECSPI_STAT_RR (1 << 3)
207
208/* MX51 eCSPI */
209static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
210{
211 /*
212 * there are two 4-bit dividers, the pre-divider divides by
213 * $pre, the post-divider by 2^$post
214 */
215 unsigned int pre, post;
216
217 if (unlikely(fspi > fin))
218 return 0;
219
220 post = fls(fin) - fls(fspi);
221 if (fin > fspi << post)
222 post++;
223
224 /* now we have: (fin <= fspi << post) with post being minimal */
225
226 post = max(4U, post) - 4;
227 if (unlikely(post > 0xf)) {
228 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
229 __func__, fspi, fin);
230 return 0xff;
231 }
232
233 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
234
235 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
236 __func__, fin, fspi, post, pre);
237 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
238 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
239}
240
241static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
242{
243 unsigned val = 0;
244
245 if (enable & MXC_INT_TE)
246 val |= MX51_ECSPI_INT_TEEN;
247
248 if (enable & MXC_INT_RR)
249 val |= MX51_ECSPI_INT_RREN;
250
251 writel(val, spi_imx->base + MX51_ECSPI_INT);
252}
253
254static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
255{
256 u32 reg;
257
258 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
259 reg |= MX51_ECSPI_CTRL_XCH;
260 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
261}
262
263static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
264 struct spi_imx_config *config)
265{
266 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
267
268 /*
269 * The hardware seems to have a race condition when changing modes. The
270 * current assumption is that the selection of the channel arrives
271 * earlier in the hardware than the mode bits when they are written at
272 * the same time.
273 * So set master mode for all channels as we do not support slave mode.
274 */
275 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
276
277 /* set clock speed */
278 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz);
279
280 /* set chip select to use */
281 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
282
283 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
284
285 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
286
287 if (config->mode & SPI_CPHA)
288 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
289
290 if (config->mode & SPI_CPOL)
291 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
292
293 if (config->mode & SPI_CS_HIGH)
294 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
295
296 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
297 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
298
299 return 0;
300}
301
302static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
303{
304 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
305}
306
307static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
308{
309 /* drain receive buffer */
310 while (mx51_ecspi_rx_available(spi_imx))
311 readl(spi_imx->base + MXC_CSPIRXDATA);
312}
313
314#define MX31_INTREG_TEEN (1 << 0)
315#define MX31_INTREG_RREN (1 << 3)
316
317#define MX31_CSPICTRL_ENABLE (1 << 0)
318#define MX31_CSPICTRL_MASTER (1 << 1)
319#define MX31_CSPICTRL_XCH (1 << 2)
320#define MX31_CSPICTRL_POL (1 << 4)
321#define MX31_CSPICTRL_PHA (1 << 5)
322#define MX31_CSPICTRL_SSCTL (1 << 6)
323#define MX31_CSPICTRL_SSPOL (1 << 7)
324#define MX31_CSPICTRL_BC_SHIFT 8
325#define MX35_CSPICTRL_BL_SHIFT 20
326#define MX31_CSPICTRL_CS_SHIFT 24
327#define MX35_CSPICTRL_CS_SHIFT 12
328#define MX31_CSPICTRL_DR_SHIFT 16
329
330#define MX31_CSPISTATUS 0x14
331#define MX31_STATUS_RR (1 << 3)
332
333/* These functions also work for the i.MX35, but be aware that
334 * the i.MX35 has a slightly different register layout for bits
335 * we do not use here.
336 */
337static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
338{
339 unsigned int val = 0;
340
341 if (enable & MXC_INT_TE)
342 val |= MX31_INTREG_TEEN;
343 if (enable & MXC_INT_RR)
344 val |= MX31_INTREG_RREN;
345
346 writel(val, spi_imx->base + MXC_CSPIINT);
347}
348
349static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
350{
351 unsigned int reg;
352
353 reg = readl(spi_imx->base + MXC_CSPICTRL);
354 reg |= MX31_CSPICTRL_XCH;
355 writel(reg, spi_imx->base + MXC_CSPICTRL);
356}
357
358static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
359 struct spi_imx_config *config)
360{
361 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
362 int cs = spi_imx->chipselect[config->cs];
363
364 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
365 MX31_CSPICTRL_DR_SHIFT;
366
367 if (is_imx35_cspi(spi_imx)) {
368 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
369 reg |= MX31_CSPICTRL_SSCTL;
370 } else {
371 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
372 }
373
374 if (config->mode & SPI_CPHA)
375 reg |= MX31_CSPICTRL_PHA;
376 if (config->mode & SPI_CPOL)
377 reg |= MX31_CSPICTRL_POL;
378 if (config->mode & SPI_CS_HIGH)
379 reg |= MX31_CSPICTRL_SSPOL;
380 if (cs < 0)
381 reg |= (cs + 32) <<
382 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
383 MX31_CSPICTRL_CS_SHIFT);
384
385 writel(reg, spi_imx->base + MXC_CSPICTRL);
386
387 return 0;
388}
389
390static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
391{
392 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
393}
394
395static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
396{
397 /* drain receive buffer */
398 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
399 readl(spi_imx->base + MXC_CSPIRXDATA);
400}
401
402#define MX21_INTREG_RR (1 << 4)
403#define MX21_INTREG_TEEN (1 << 9)
404#define MX21_INTREG_RREN (1 << 13)
405
406#define MX21_CSPICTRL_POL (1 << 5)
407#define MX21_CSPICTRL_PHA (1 << 6)
408#define MX21_CSPICTRL_SSPOL (1 << 8)
409#define MX21_CSPICTRL_XCH (1 << 9)
410#define MX21_CSPICTRL_ENABLE (1 << 10)
411#define MX21_CSPICTRL_MASTER (1 << 11)
412#define MX21_CSPICTRL_DR_SHIFT 14
413#define MX21_CSPICTRL_CS_SHIFT 19
414
415static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
416{
417 unsigned int val = 0;
418
419 if (enable & MXC_INT_TE)
420 val |= MX21_INTREG_TEEN;
421 if (enable & MXC_INT_RR)
422 val |= MX21_INTREG_RREN;
423
424 writel(val, spi_imx->base + MXC_CSPIINT);
425}
426
427static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
428{
429 unsigned int reg;
430
431 reg = readl(spi_imx->base + MXC_CSPICTRL);
432 reg |= MX21_CSPICTRL_XCH;
433 writel(reg, spi_imx->base + MXC_CSPICTRL);
434}
435
436static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
437 struct spi_imx_config *config)
438{
439 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
440 int cs = spi_imx->chipselect[config->cs];
441 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
442
443 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
444 MX21_CSPICTRL_DR_SHIFT;
445 reg |= config->bpw - 1;
446
447 if (config->mode & SPI_CPHA)
448 reg |= MX21_CSPICTRL_PHA;
449 if (config->mode & SPI_CPOL)
450 reg |= MX21_CSPICTRL_POL;
451 if (config->mode & SPI_CS_HIGH)
452 reg |= MX21_CSPICTRL_SSPOL;
453 if (cs < 0)
454 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
455
456 writel(reg, spi_imx->base + MXC_CSPICTRL);
457
458 return 0;
459}
460
461static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
462{
463 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
464}
465
466static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
467{
468 writel(1, spi_imx->base + MXC_RESET);
469}
470
471#define MX1_INTREG_RR (1 << 3)
472#define MX1_INTREG_TEEN (1 << 8)
473#define MX1_INTREG_RREN (1 << 11)
474
475#define MX1_CSPICTRL_POL (1 << 4)
476#define MX1_CSPICTRL_PHA (1 << 5)
477#define MX1_CSPICTRL_XCH (1 << 8)
478#define MX1_CSPICTRL_ENABLE (1 << 9)
479#define MX1_CSPICTRL_MASTER (1 << 10)
480#define MX1_CSPICTRL_DR_SHIFT 13
481
482static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
483{
484 unsigned int val = 0;
485
486 if (enable & MXC_INT_TE)
487 val |= MX1_INTREG_TEEN;
488 if (enable & MXC_INT_RR)
489 val |= MX1_INTREG_RREN;
490
491 writel(val, spi_imx->base + MXC_CSPIINT);
492}
493
494static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
495{
496 unsigned int reg;
497
498 reg = readl(spi_imx->base + MXC_CSPICTRL);
499 reg |= MX1_CSPICTRL_XCH;
500 writel(reg, spi_imx->base + MXC_CSPICTRL);
501}
502
503static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
504 struct spi_imx_config *config)
505{
506 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
507
508 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
509 MX1_CSPICTRL_DR_SHIFT;
510 reg |= config->bpw - 1;
511
512 if (config->mode & SPI_CPHA)
513 reg |= MX1_CSPICTRL_PHA;
514 if (config->mode & SPI_CPOL)
515 reg |= MX1_CSPICTRL_POL;
516
517 writel(reg, spi_imx->base + MXC_CSPICTRL);
518
519 return 0;
520}
521
522static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
523{
524 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
525}
526
527static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
528{
529 writel(1, spi_imx->base + MXC_RESET);
530}
531
532static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
533 .intctrl = mx1_intctrl,
534 .config = mx1_config,
535 .trigger = mx1_trigger,
536 .rx_available = mx1_rx_available,
537 .reset = mx1_reset,
538 .devtype = IMX1_CSPI,
539};
540
541static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
542 .intctrl = mx21_intctrl,
543 .config = mx21_config,
544 .trigger = mx21_trigger,
545 .rx_available = mx21_rx_available,
546 .reset = mx21_reset,
547 .devtype = IMX21_CSPI,
548};
549
550static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
551 /* i.mx27 cspi shares the functions with i.mx21 one */
552 .intctrl = mx21_intctrl,
553 .config = mx21_config,
554 .trigger = mx21_trigger,
555 .rx_available = mx21_rx_available,
556 .reset = mx21_reset,
557 .devtype = IMX27_CSPI,
558};
559
560static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
561 .intctrl = mx31_intctrl,
562 .config = mx31_config,
563 .trigger = mx31_trigger,
564 .rx_available = mx31_rx_available,
565 .reset = mx31_reset,
566 .devtype = IMX31_CSPI,
567};
568
569static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
570 /* i.mx35 and later cspi shares the functions with i.mx31 one */
571 .intctrl = mx31_intctrl,
572 .config = mx31_config,
573 .trigger = mx31_trigger,
574 .rx_available = mx31_rx_available,
575 .reset = mx31_reset,
576 .devtype = IMX35_CSPI,
577};
578
579static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
580 .intctrl = mx51_ecspi_intctrl,
581 .config = mx51_ecspi_config,
582 .trigger = mx51_ecspi_trigger,
583 .rx_available = mx51_ecspi_rx_available,
584 .reset = mx51_ecspi_reset,
585 .devtype = IMX51_ECSPI,
586};
587
588static struct platform_device_id spi_imx_devtype[] = {
589 {
590 .name = "imx1-cspi",
591 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
592 }, {
593 .name = "imx21-cspi",
594 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
595 }, {
596 .name = "imx27-cspi",
597 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
598 }, {
599 .name = "imx31-cspi",
600 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
601 }, {
602 .name = "imx35-cspi",
603 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
604 }, {
605 .name = "imx51-ecspi",
606 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
607 }, {
608 /* sentinel */
609 }
610};
611
612static const struct of_device_id spi_imx_dt_ids[] = {
613 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
614 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
615 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
616 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
617 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
618 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
619 { /* sentinel */ }
620};
621
622static void spi_imx_chipselect(struct spi_device *spi, int is_active)
623{
624 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
625 int gpio = spi_imx->chipselect[spi->chip_select];
626 int active = is_active != BITBANG_CS_INACTIVE;
627 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
628
629 if (gpio < 0)
630 return;
631
632 gpio_set_value(gpio, dev_is_lowactive ^ active);
633}
634
635static void spi_imx_push(struct spi_imx_data *spi_imx)
636{
637 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
638 if (!spi_imx->count)
639 break;
640 spi_imx->tx(spi_imx);
641 spi_imx->txfifo++;
642 }
643
644 spi_imx->devtype_data->trigger(spi_imx);
645}
646
647static irqreturn_t spi_imx_isr(int irq, void *dev_id)
648{
649 struct spi_imx_data *spi_imx = dev_id;
650
651 while (spi_imx->devtype_data->rx_available(spi_imx)) {
652 spi_imx->rx(spi_imx);
653 spi_imx->txfifo--;
654 }
655
656 if (spi_imx->count) {
657 spi_imx_push(spi_imx);
658 return IRQ_HANDLED;
659 }
660
661 if (spi_imx->txfifo) {
662 /* No data left to push, but still waiting for rx data,
663 * enable receive data available interrupt.
664 */
665 spi_imx->devtype_data->intctrl(
666 spi_imx, MXC_INT_RR);
667 return IRQ_HANDLED;
668 }
669
670 spi_imx->devtype_data->intctrl(spi_imx, 0);
671 complete(&spi_imx->xfer_done);
672
673 return IRQ_HANDLED;
674}
675
676static int spi_imx_setupxfer(struct spi_device *spi,
677 struct spi_transfer *t)
678{
679 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
680 struct spi_imx_config config;
681
682 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
683 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
684 config.mode = spi->mode;
685 config.cs = spi->chip_select;
686
687 if (!config.speed_hz)
688 config.speed_hz = spi->max_speed_hz;
689 if (!config.bpw)
690 config.bpw = spi->bits_per_word;
691 if (!config.speed_hz)
692 config.speed_hz = spi->max_speed_hz;
693
694 /* Initialize the functions for transfer */
695 if (config.bpw <= 8) {
696 spi_imx->rx = spi_imx_buf_rx_u8;
697 spi_imx->tx = spi_imx_buf_tx_u8;
698 } else if (config.bpw <= 16) {
699 spi_imx->rx = spi_imx_buf_rx_u16;
700 spi_imx->tx = spi_imx_buf_tx_u16;
701 } else if (config.bpw <= 32) {
702 spi_imx->rx = spi_imx_buf_rx_u32;
703 spi_imx->tx = spi_imx_buf_tx_u32;
704 } else
705 BUG();
706
707 spi_imx->devtype_data->config(spi_imx, &config);
708
709 return 0;
710}
711
712static int spi_imx_transfer(struct spi_device *spi,
713 struct spi_transfer *transfer)
714{
715 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
716
717 spi_imx->tx_buf = transfer->tx_buf;
718 spi_imx->rx_buf = transfer->rx_buf;
719 spi_imx->count = transfer->len;
720 spi_imx->txfifo = 0;
721
722 init_completion(&spi_imx->xfer_done);
723
724 spi_imx_push(spi_imx);
725
726 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
727
728 wait_for_completion(&spi_imx->xfer_done);
729
730 return transfer->len;
731}
732
733static int spi_imx_setup(struct spi_device *spi)
734{
735 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
736 int gpio = spi_imx->chipselect[spi->chip_select];
737
738 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
739 spi->mode, spi->bits_per_word, spi->max_speed_hz);
740
741 if (gpio >= 0)
742 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
743
744 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
745
746 return 0;
747}
748
749static void spi_imx_cleanup(struct spi_device *spi)
750{
751}
752
753static int __devinit spi_imx_probe(struct platform_device *pdev)
754{
755 struct device_node *np = pdev->dev.of_node;
756 const struct of_device_id *of_id =
757 of_match_device(spi_imx_dt_ids, &pdev->dev);
758 struct spi_imx_master *mxc_platform_info =
759 dev_get_platdata(&pdev->dev);
760 struct spi_master *master;
761 struct spi_imx_data *spi_imx;
762 struct resource *res;
763 struct pinctrl *pinctrl;
764 int i, ret, num_cs;
765
766 if (!np && !mxc_platform_info) {
767 dev_err(&pdev->dev, "can't get the platform data\n");
768 return -EINVAL;
769 }
770
771 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
772 if (ret < 0) {
773 if (mxc_platform_info)
774 num_cs = mxc_platform_info->num_chipselect;
775 else
776 return ret;
777 }
778
779 master = spi_alloc_master(&pdev->dev,
780 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
781 if (!master)
782 return -ENOMEM;
783
784 platform_set_drvdata(pdev, master);
785
786 master->bus_num = pdev->id;
787 master->num_chipselect = num_cs;
788
789 spi_imx = spi_master_get_devdata(master);
790 spi_imx->bitbang.master = spi_master_get(master);
791
792 for (i = 0; i < master->num_chipselect; i++) {
793 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
794 if (cs_gpio < 0 && mxc_platform_info)
795 cs_gpio = mxc_platform_info->chipselect[i];
796
797 spi_imx->chipselect[i] = cs_gpio;
798 if (cs_gpio < 0)
799 continue;
800
801 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
802 if (ret) {
803 dev_err(&pdev->dev, "can't get cs gpios\n");
804 goto out_gpio_free;
805 }
806 }
807
808 spi_imx->bitbang.chipselect = spi_imx_chipselect;
809 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
810 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
811 spi_imx->bitbang.master->setup = spi_imx_setup;
812 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
813 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
814
815 init_completion(&spi_imx->xfer_done);
816
817 spi_imx->devtype_data = of_id ? of_id->data :
818 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
819
820 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
821 if (!res) {
822 dev_err(&pdev->dev, "can't get platform resource\n");
823 ret = -ENOMEM;
824 goto out_gpio_free;
825 }
826
827 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
828 dev_err(&pdev->dev, "request_mem_region failed\n");
829 ret = -EBUSY;
830 goto out_gpio_free;
831 }
832
833 spi_imx->base = ioremap(res->start, resource_size(res));
834 if (!spi_imx->base) {
835 ret = -EINVAL;
836 goto out_release_mem;
837 }
838
839 spi_imx->irq = platform_get_irq(pdev, 0);
840 if (spi_imx->irq < 0) {
841 ret = -EINVAL;
842 goto out_iounmap;
843 }
844
845 ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
846 if (ret) {
847 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
848 goto out_iounmap;
849 }
850
851 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
852 if (IS_ERR(pinctrl)) {
853 ret = PTR_ERR(pinctrl);
854 goto out_free_irq;
855 }
856
857 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
858 if (IS_ERR(spi_imx->clk_ipg)) {
859 ret = PTR_ERR(spi_imx->clk_ipg);
860 goto out_free_irq;
861 }
862
863 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
864 if (IS_ERR(spi_imx->clk_per)) {
865 ret = PTR_ERR(spi_imx->clk_per);
866 goto out_free_irq;
867 }
868
869 clk_prepare_enable(spi_imx->clk_per);
870 clk_prepare_enable(spi_imx->clk_ipg);
871
872 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
873
874 spi_imx->devtype_data->reset(spi_imx);
875
876 spi_imx->devtype_data->intctrl(spi_imx, 0);
877
878 master->dev.of_node = pdev->dev.of_node;
879 ret = spi_bitbang_start(&spi_imx->bitbang);
880 if (ret) {
881 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
882 goto out_clk_put;
883 }
884
885 dev_info(&pdev->dev, "probed\n");
886
887 return ret;
888
889out_clk_put:
890 clk_disable_unprepare(spi_imx->clk_per);
891 clk_disable_unprepare(spi_imx->clk_ipg);
892out_free_irq:
893 free_irq(spi_imx->irq, spi_imx);
894out_iounmap:
895 iounmap(spi_imx->base);
896out_release_mem:
897 release_mem_region(res->start, resource_size(res));
898out_gpio_free:
899 while (--i >= 0) {
900 if (spi_imx->chipselect[i] >= 0)
901 gpio_free(spi_imx->chipselect[i]);
902 }
903 spi_master_put(master);
904 kfree(master);
905 platform_set_drvdata(pdev, NULL);
906 return ret;
907}
908
909static int __devexit spi_imx_remove(struct platform_device *pdev)
910{
911 struct spi_master *master = platform_get_drvdata(pdev);
912 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
913 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
914 int i;
915
916 spi_bitbang_stop(&spi_imx->bitbang);
917
918 writel(0, spi_imx->base + MXC_CSPICTRL);
919 clk_disable_unprepare(spi_imx->clk_per);
920 clk_disable_unprepare(spi_imx->clk_ipg);
921 free_irq(spi_imx->irq, spi_imx);
922 iounmap(spi_imx->base);
923
924 for (i = 0; i < master->num_chipselect; i++)
925 if (spi_imx->chipselect[i] >= 0)
926 gpio_free(spi_imx->chipselect[i]);
927
928 spi_master_put(master);
929
930 release_mem_region(res->start, resource_size(res));
931
932 platform_set_drvdata(pdev, NULL);
933
934 return 0;
935}
936
937static struct platform_driver spi_imx_driver = {
938 .driver = {
939 .name = DRIVER_NAME,
940 .owner = THIS_MODULE,
941 .of_match_table = spi_imx_dt_ids,
942 },
943 .id_table = spi_imx_devtype,
944 .probe = spi_imx_probe,
945 .remove = __devexit_p(spi_imx_remove),
946};
947module_platform_driver(spi_imx_driver);
948
949MODULE_DESCRIPTION("SPI Master Controller driver");
950MODULE_AUTHOR("Sascha Hauer, Pengutronix");
951MODULE_LICENSE("GPL");