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1/*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26#include <linux/swab.h>
27#include <linux/slab.h>
28#include "drmP.h"
29#include "drm.h"
30#include "drm_sarea.h"
31#include "drm_crtc_helper.h"
32#include <linux/vgaarb.h>
33#include <linux/vga_switcheroo.h>
34
35#include "nouveau_drv.h"
36#include "nouveau_drm.h"
37#include "nouveau_fbcon.h"
38#include "nouveau_ramht.h"
39#include "nouveau_pm.h"
40#include "nv50_display.h"
41
42static void nouveau_stub_takedown(struct drm_device *dev) {}
43static int nouveau_stub_init(struct drm_device *dev) { return 0; }
44
45static int nouveau_init_engine_ptrs(struct drm_device *dev)
46{
47 struct drm_nouveau_private *dev_priv = dev->dev_private;
48 struct nouveau_engine *engine = &dev_priv->engine;
49
50 switch (dev_priv->chipset & 0xf0) {
51 case 0x00:
52 engine->instmem.init = nv04_instmem_init;
53 engine->instmem.takedown = nv04_instmem_takedown;
54 engine->instmem.suspend = nv04_instmem_suspend;
55 engine->instmem.resume = nv04_instmem_resume;
56 engine->instmem.get = nv04_instmem_get;
57 engine->instmem.put = nv04_instmem_put;
58 engine->instmem.map = nv04_instmem_map;
59 engine->instmem.unmap = nv04_instmem_unmap;
60 engine->instmem.flush = nv04_instmem_flush;
61 engine->mc.init = nv04_mc_init;
62 engine->mc.takedown = nv04_mc_takedown;
63 engine->timer.init = nv04_timer_init;
64 engine->timer.read = nv04_timer_read;
65 engine->timer.takedown = nv04_timer_takedown;
66 engine->fb.init = nv04_fb_init;
67 engine->fb.takedown = nv04_fb_takedown;
68 engine->fifo.channels = 16;
69 engine->fifo.init = nv04_fifo_init;
70 engine->fifo.takedown = nv04_fifo_fini;
71 engine->fifo.disable = nv04_fifo_disable;
72 engine->fifo.enable = nv04_fifo_enable;
73 engine->fifo.reassign = nv04_fifo_reassign;
74 engine->fifo.cache_pull = nv04_fifo_cache_pull;
75 engine->fifo.channel_id = nv04_fifo_channel_id;
76 engine->fifo.create_context = nv04_fifo_create_context;
77 engine->fifo.destroy_context = nv04_fifo_destroy_context;
78 engine->fifo.load_context = nv04_fifo_load_context;
79 engine->fifo.unload_context = nv04_fifo_unload_context;
80 engine->display.early_init = nv04_display_early_init;
81 engine->display.late_takedown = nv04_display_late_takedown;
82 engine->display.create = nv04_display_create;
83 engine->display.init = nv04_display_init;
84 engine->display.destroy = nv04_display_destroy;
85 engine->gpio.init = nouveau_stub_init;
86 engine->gpio.takedown = nouveau_stub_takedown;
87 engine->gpio.get = NULL;
88 engine->gpio.set = NULL;
89 engine->gpio.irq_enable = NULL;
90 engine->pm.clock_get = nv04_pm_clock_get;
91 engine->pm.clock_pre = nv04_pm_clock_pre;
92 engine->pm.clock_set = nv04_pm_clock_set;
93 engine->vram.init = nouveau_mem_detect;
94 engine->vram.takedown = nouveau_stub_takedown;
95 engine->vram.flags_valid = nouveau_mem_flags_valid;
96 break;
97 case 0x10:
98 engine->instmem.init = nv04_instmem_init;
99 engine->instmem.takedown = nv04_instmem_takedown;
100 engine->instmem.suspend = nv04_instmem_suspend;
101 engine->instmem.resume = nv04_instmem_resume;
102 engine->instmem.get = nv04_instmem_get;
103 engine->instmem.put = nv04_instmem_put;
104 engine->instmem.map = nv04_instmem_map;
105 engine->instmem.unmap = nv04_instmem_unmap;
106 engine->instmem.flush = nv04_instmem_flush;
107 engine->mc.init = nv04_mc_init;
108 engine->mc.takedown = nv04_mc_takedown;
109 engine->timer.init = nv04_timer_init;
110 engine->timer.read = nv04_timer_read;
111 engine->timer.takedown = nv04_timer_takedown;
112 engine->fb.init = nv10_fb_init;
113 engine->fb.takedown = nv10_fb_takedown;
114 engine->fb.init_tile_region = nv10_fb_init_tile_region;
115 engine->fb.set_tile_region = nv10_fb_set_tile_region;
116 engine->fb.free_tile_region = nv10_fb_free_tile_region;
117 engine->fifo.channels = 32;
118 engine->fifo.init = nv10_fifo_init;
119 engine->fifo.takedown = nv04_fifo_fini;
120 engine->fifo.disable = nv04_fifo_disable;
121 engine->fifo.enable = nv04_fifo_enable;
122 engine->fifo.reassign = nv04_fifo_reassign;
123 engine->fifo.cache_pull = nv04_fifo_cache_pull;
124 engine->fifo.channel_id = nv10_fifo_channel_id;
125 engine->fifo.create_context = nv10_fifo_create_context;
126 engine->fifo.destroy_context = nv04_fifo_destroy_context;
127 engine->fifo.load_context = nv10_fifo_load_context;
128 engine->fifo.unload_context = nv10_fifo_unload_context;
129 engine->display.early_init = nv04_display_early_init;
130 engine->display.late_takedown = nv04_display_late_takedown;
131 engine->display.create = nv04_display_create;
132 engine->display.init = nv04_display_init;
133 engine->display.destroy = nv04_display_destroy;
134 engine->gpio.init = nouveau_stub_init;
135 engine->gpio.takedown = nouveau_stub_takedown;
136 engine->gpio.get = nv10_gpio_get;
137 engine->gpio.set = nv10_gpio_set;
138 engine->gpio.irq_enable = NULL;
139 engine->pm.clock_get = nv04_pm_clock_get;
140 engine->pm.clock_pre = nv04_pm_clock_pre;
141 engine->pm.clock_set = nv04_pm_clock_set;
142 engine->vram.init = nouveau_mem_detect;
143 engine->vram.takedown = nouveau_stub_takedown;
144 engine->vram.flags_valid = nouveau_mem_flags_valid;
145 break;
146 case 0x20:
147 engine->instmem.init = nv04_instmem_init;
148 engine->instmem.takedown = nv04_instmem_takedown;
149 engine->instmem.suspend = nv04_instmem_suspend;
150 engine->instmem.resume = nv04_instmem_resume;
151 engine->instmem.get = nv04_instmem_get;
152 engine->instmem.put = nv04_instmem_put;
153 engine->instmem.map = nv04_instmem_map;
154 engine->instmem.unmap = nv04_instmem_unmap;
155 engine->instmem.flush = nv04_instmem_flush;
156 engine->mc.init = nv04_mc_init;
157 engine->mc.takedown = nv04_mc_takedown;
158 engine->timer.init = nv04_timer_init;
159 engine->timer.read = nv04_timer_read;
160 engine->timer.takedown = nv04_timer_takedown;
161 engine->fb.init = nv10_fb_init;
162 engine->fb.takedown = nv10_fb_takedown;
163 engine->fb.init_tile_region = nv10_fb_init_tile_region;
164 engine->fb.set_tile_region = nv10_fb_set_tile_region;
165 engine->fb.free_tile_region = nv10_fb_free_tile_region;
166 engine->fifo.channels = 32;
167 engine->fifo.init = nv10_fifo_init;
168 engine->fifo.takedown = nv04_fifo_fini;
169 engine->fifo.disable = nv04_fifo_disable;
170 engine->fifo.enable = nv04_fifo_enable;
171 engine->fifo.reassign = nv04_fifo_reassign;
172 engine->fifo.cache_pull = nv04_fifo_cache_pull;
173 engine->fifo.channel_id = nv10_fifo_channel_id;
174 engine->fifo.create_context = nv10_fifo_create_context;
175 engine->fifo.destroy_context = nv04_fifo_destroy_context;
176 engine->fifo.load_context = nv10_fifo_load_context;
177 engine->fifo.unload_context = nv10_fifo_unload_context;
178 engine->display.early_init = nv04_display_early_init;
179 engine->display.late_takedown = nv04_display_late_takedown;
180 engine->display.create = nv04_display_create;
181 engine->display.init = nv04_display_init;
182 engine->display.destroy = nv04_display_destroy;
183 engine->gpio.init = nouveau_stub_init;
184 engine->gpio.takedown = nouveau_stub_takedown;
185 engine->gpio.get = nv10_gpio_get;
186 engine->gpio.set = nv10_gpio_set;
187 engine->gpio.irq_enable = NULL;
188 engine->pm.clock_get = nv04_pm_clock_get;
189 engine->pm.clock_pre = nv04_pm_clock_pre;
190 engine->pm.clock_set = nv04_pm_clock_set;
191 engine->vram.init = nouveau_mem_detect;
192 engine->vram.takedown = nouveau_stub_takedown;
193 engine->vram.flags_valid = nouveau_mem_flags_valid;
194 break;
195 case 0x30:
196 engine->instmem.init = nv04_instmem_init;
197 engine->instmem.takedown = nv04_instmem_takedown;
198 engine->instmem.suspend = nv04_instmem_suspend;
199 engine->instmem.resume = nv04_instmem_resume;
200 engine->instmem.get = nv04_instmem_get;
201 engine->instmem.put = nv04_instmem_put;
202 engine->instmem.map = nv04_instmem_map;
203 engine->instmem.unmap = nv04_instmem_unmap;
204 engine->instmem.flush = nv04_instmem_flush;
205 engine->mc.init = nv04_mc_init;
206 engine->mc.takedown = nv04_mc_takedown;
207 engine->timer.init = nv04_timer_init;
208 engine->timer.read = nv04_timer_read;
209 engine->timer.takedown = nv04_timer_takedown;
210 engine->fb.init = nv30_fb_init;
211 engine->fb.takedown = nv30_fb_takedown;
212 engine->fb.init_tile_region = nv30_fb_init_tile_region;
213 engine->fb.set_tile_region = nv10_fb_set_tile_region;
214 engine->fb.free_tile_region = nv30_fb_free_tile_region;
215 engine->fifo.channels = 32;
216 engine->fifo.init = nv10_fifo_init;
217 engine->fifo.takedown = nv04_fifo_fini;
218 engine->fifo.disable = nv04_fifo_disable;
219 engine->fifo.enable = nv04_fifo_enable;
220 engine->fifo.reassign = nv04_fifo_reassign;
221 engine->fifo.cache_pull = nv04_fifo_cache_pull;
222 engine->fifo.channel_id = nv10_fifo_channel_id;
223 engine->fifo.create_context = nv10_fifo_create_context;
224 engine->fifo.destroy_context = nv04_fifo_destroy_context;
225 engine->fifo.load_context = nv10_fifo_load_context;
226 engine->fifo.unload_context = nv10_fifo_unload_context;
227 engine->display.early_init = nv04_display_early_init;
228 engine->display.late_takedown = nv04_display_late_takedown;
229 engine->display.create = nv04_display_create;
230 engine->display.init = nv04_display_init;
231 engine->display.destroy = nv04_display_destroy;
232 engine->gpio.init = nouveau_stub_init;
233 engine->gpio.takedown = nouveau_stub_takedown;
234 engine->gpio.get = nv10_gpio_get;
235 engine->gpio.set = nv10_gpio_set;
236 engine->gpio.irq_enable = NULL;
237 engine->pm.clock_get = nv04_pm_clock_get;
238 engine->pm.clock_pre = nv04_pm_clock_pre;
239 engine->pm.clock_set = nv04_pm_clock_set;
240 engine->pm.voltage_get = nouveau_voltage_gpio_get;
241 engine->pm.voltage_set = nouveau_voltage_gpio_set;
242 engine->vram.init = nouveau_mem_detect;
243 engine->vram.takedown = nouveau_stub_takedown;
244 engine->vram.flags_valid = nouveau_mem_flags_valid;
245 break;
246 case 0x40:
247 case 0x60:
248 engine->instmem.init = nv04_instmem_init;
249 engine->instmem.takedown = nv04_instmem_takedown;
250 engine->instmem.suspend = nv04_instmem_suspend;
251 engine->instmem.resume = nv04_instmem_resume;
252 engine->instmem.get = nv04_instmem_get;
253 engine->instmem.put = nv04_instmem_put;
254 engine->instmem.map = nv04_instmem_map;
255 engine->instmem.unmap = nv04_instmem_unmap;
256 engine->instmem.flush = nv04_instmem_flush;
257 engine->mc.init = nv40_mc_init;
258 engine->mc.takedown = nv40_mc_takedown;
259 engine->timer.init = nv04_timer_init;
260 engine->timer.read = nv04_timer_read;
261 engine->timer.takedown = nv04_timer_takedown;
262 engine->fb.init = nv40_fb_init;
263 engine->fb.takedown = nv40_fb_takedown;
264 engine->fb.init_tile_region = nv30_fb_init_tile_region;
265 engine->fb.set_tile_region = nv40_fb_set_tile_region;
266 engine->fb.free_tile_region = nv30_fb_free_tile_region;
267 engine->fifo.channels = 32;
268 engine->fifo.init = nv40_fifo_init;
269 engine->fifo.takedown = nv04_fifo_fini;
270 engine->fifo.disable = nv04_fifo_disable;
271 engine->fifo.enable = nv04_fifo_enable;
272 engine->fifo.reassign = nv04_fifo_reassign;
273 engine->fifo.cache_pull = nv04_fifo_cache_pull;
274 engine->fifo.channel_id = nv10_fifo_channel_id;
275 engine->fifo.create_context = nv40_fifo_create_context;
276 engine->fifo.destroy_context = nv04_fifo_destroy_context;
277 engine->fifo.load_context = nv40_fifo_load_context;
278 engine->fifo.unload_context = nv40_fifo_unload_context;
279 engine->display.early_init = nv04_display_early_init;
280 engine->display.late_takedown = nv04_display_late_takedown;
281 engine->display.create = nv04_display_create;
282 engine->display.init = nv04_display_init;
283 engine->display.destroy = nv04_display_destroy;
284 engine->gpio.init = nouveau_stub_init;
285 engine->gpio.takedown = nouveau_stub_takedown;
286 engine->gpio.get = nv10_gpio_get;
287 engine->gpio.set = nv10_gpio_set;
288 engine->gpio.irq_enable = NULL;
289 engine->pm.clock_get = nv04_pm_clock_get;
290 engine->pm.clock_pre = nv04_pm_clock_pre;
291 engine->pm.clock_set = nv04_pm_clock_set;
292 engine->pm.voltage_get = nouveau_voltage_gpio_get;
293 engine->pm.voltage_set = nouveau_voltage_gpio_set;
294 engine->pm.temp_get = nv40_temp_get;
295 engine->vram.init = nouveau_mem_detect;
296 engine->vram.takedown = nouveau_stub_takedown;
297 engine->vram.flags_valid = nouveau_mem_flags_valid;
298 break;
299 case 0x50:
300 case 0x80: /* gotta love NVIDIA's consistency.. */
301 case 0x90:
302 case 0xA0:
303 engine->instmem.init = nv50_instmem_init;
304 engine->instmem.takedown = nv50_instmem_takedown;
305 engine->instmem.suspend = nv50_instmem_suspend;
306 engine->instmem.resume = nv50_instmem_resume;
307 engine->instmem.get = nv50_instmem_get;
308 engine->instmem.put = nv50_instmem_put;
309 engine->instmem.map = nv50_instmem_map;
310 engine->instmem.unmap = nv50_instmem_unmap;
311 if (dev_priv->chipset == 0x50)
312 engine->instmem.flush = nv50_instmem_flush;
313 else
314 engine->instmem.flush = nv84_instmem_flush;
315 engine->mc.init = nv50_mc_init;
316 engine->mc.takedown = nv50_mc_takedown;
317 engine->timer.init = nv04_timer_init;
318 engine->timer.read = nv04_timer_read;
319 engine->timer.takedown = nv04_timer_takedown;
320 engine->fb.init = nv50_fb_init;
321 engine->fb.takedown = nv50_fb_takedown;
322 engine->fifo.channels = 128;
323 engine->fifo.init = nv50_fifo_init;
324 engine->fifo.takedown = nv50_fifo_takedown;
325 engine->fifo.disable = nv04_fifo_disable;
326 engine->fifo.enable = nv04_fifo_enable;
327 engine->fifo.reassign = nv04_fifo_reassign;
328 engine->fifo.channel_id = nv50_fifo_channel_id;
329 engine->fifo.create_context = nv50_fifo_create_context;
330 engine->fifo.destroy_context = nv50_fifo_destroy_context;
331 engine->fifo.load_context = nv50_fifo_load_context;
332 engine->fifo.unload_context = nv50_fifo_unload_context;
333 engine->fifo.tlb_flush = nv50_fifo_tlb_flush;
334 engine->display.early_init = nv50_display_early_init;
335 engine->display.late_takedown = nv50_display_late_takedown;
336 engine->display.create = nv50_display_create;
337 engine->display.init = nv50_display_init;
338 engine->display.destroy = nv50_display_destroy;
339 engine->gpio.init = nv50_gpio_init;
340 engine->gpio.takedown = nv50_gpio_fini;
341 engine->gpio.get = nv50_gpio_get;
342 engine->gpio.set = nv50_gpio_set;
343 engine->gpio.irq_register = nv50_gpio_irq_register;
344 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
345 engine->gpio.irq_enable = nv50_gpio_irq_enable;
346 switch (dev_priv->chipset) {
347 case 0x84:
348 case 0x86:
349 case 0x92:
350 case 0x94:
351 case 0x96:
352 case 0x98:
353 case 0xa0:
354 case 0xaa:
355 case 0xac:
356 case 0x50:
357 engine->pm.clock_get = nv50_pm_clock_get;
358 engine->pm.clock_pre = nv50_pm_clock_pre;
359 engine->pm.clock_set = nv50_pm_clock_set;
360 break;
361 default:
362 engine->pm.clock_get = nva3_pm_clock_get;
363 engine->pm.clock_pre = nva3_pm_clock_pre;
364 engine->pm.clock_set = nva3_pm_clock_set;
365 break;
366 }
367 engine->pm.voltage_get = nouveau_voltage_gpio_get;
368 engine->pm.voltage_set = nouveau_voltage_gpio_set;
369 if (dev_priv->chipset >= 0x84)
370 engine->pm.temp_get = nv84_temp_get;
371 else
372 engine->pm.temp_get = nv40_temp_get;
373 engine->vram.init = nv50_vram_init;
374 engine->vram.takedown = nv50_vram_fini;
375 engine->vram.get = nv50_vram_new;
376 engine->vram.put = nv50_vram_del;
377 engine->vram.flags_valid = nv50_vram_flags_valid;
378 break;
379 case 0xC0:
380 engine->instmem.init = nvc0_instmem_init;
381 engine->instmem.takedown = nvc0_instmem_takedown;
382 engine->instmem.suspend = nvc0_instmem_suspend;
383 engine->instmem.resume = nvc0_instmem_resume;
384 engine->instmem.get = nv50_instmem_get;
385 engine->instmem.put = nv50_instmem_put;
386 engine->instmem.map = nv50_instmem_map;
387 engine->instmem.unmap = nv50_instmem_unmap;
388 engine->instmem.flush = nv84_instmem_flush;
389 engine->mc.init = nv50_mc_init;
390 engine->mc.takedown = nv50_mc_takedown;
391 engine->timer.init = nv04_timer_init;
392 engine->timer.read = nv04_timer_read;
393 engine->timer.takedown = nv04_timer_takedown;
394 engine->fb.init = nvc0_fb_init;
395 engine->fb.takedown = nvc0_fb_takedown;
396 engine->fifo.channels = 128;
397 engine->fifo.init = nvc0_fifo_init;
398 engine->fifo.takedown = nvc0_fifo_takedown;
399 engine->fifo.disable = nvc0_fifo_disable;
400 engine->fifo.enable = nvc0_fifo_enable;
401 engine->fifo.reassign = nvc0_fifo_reassign;
402 engine->fifo.channel_id = nvc0_fifo_channel_id;
403 engine->fifo.create_context = nvc0_fifo_create_context;
404 engine->fifo.destroy_context = nvc0_fifo_destroy_context;
405 engine->fifo.load_context = nvc0_fifo_load_context;
406 engine->fifo.unload_context = nvc0_fifo_unload_context;
407 engine->display.early_init = nv50_display_early_init;
408 engine->display.late_takedown = nv50_display_late_takedown;
409 engine->display.create = nv50_display_create;
410 engine->display.init = nv50_display_init;
411 engine->display.destroy = nv50_display_destroy;
412 engine->gpio.init = nv50_gpio_init;
413 engine->gpio.takedown = nouveau_stub_takedown;
414 engine->gpio.get = nv50_gpio_get;
415 engine->gpio.set = nv50_gpio_set;
416 engine->gpio.irq_register = nv50_gpio_irq_register;
417 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
418 engine->gpio.irq_enable = nv50_gpio_irq_enable;
419 engine->vram.init = nvc0_vram_init;
420 engine->vram.takedown = nv50_vram_fini;
421 engine->vram.get = nvc0_vram_new;
422 engine->vram.put = nv50_vram_del;
423 engine->vram.flags_valid = nvc0_vram_flags_valid;
424 engine->pm.temp_get = nv84_temp_get;
425 break;
426 default:
427 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
428 return 1;
429 }
430
431 return 0;
432}
433
434static unsigned int
435nouveau_vga_set_decode(void *priv, bool state)
436{
437 struct drm_device *dev = priv;
438 struct drm_nouveau_private *dev_priv = dev->dev_private;
439
440 if (dev_priv->chipset >= 0x40)
441 nv_wr32(dev, 0x88054, state);
442 else
443 nv_wr32(dev, 0x1854, state);
444
445 if (state)
446 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
447 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
448 else
449 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
450}
451
452static int
453nouveau_card_init_channel(struct drm_device *dev)
454{
455 struct drm_nouveau_private *dev_priv = dev->dev_private;
456 int ret;
457
458 ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL,
459 NvDmaFB, NvDmaTT);
460 if (ret)
461 return ret;
462
463 mutex_unlock(&dev_priv->channel->mutex);
464 return 0;
465}
466
467static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
468 enum vga_switcheroo_state state)
469{
470 struct drm_device *dev = pci_get_drvdata(pdev);
471 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
472 if (state == VGA_SWITCHEROO_ON) {
473 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
474 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
475 nouveau_pci_resume(pdev);
476 drm_kms_helper_poll_enable(dev);
477 dev->switch_power_state = DRM_SWITCH_POWER_ON;
478 } else {
479 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
480 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
481 drm_kms_helper_poll_disable(dev);
482 nouveau_pci_suspend(pdev, pmm);
483 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
484 }
485}
486
487static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
488{
489 struct drm_device *dev = pci_get_drvdata(pdev);
490 nouveau_fbcon_output_poll_changed(dev);
491}
492
493static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
494{
495 struct drm_device *dev = pci_get_drvdata(pdev);
496 bool can_switch;
497
498 spin_lock(&dev->count_lock);
499 can_switch = (dev->open_count == 0);
500 spin_unlock(&dev->count_lock);
501 return can_switch;
502}
503
504int
505nouveau_card_init(struct drm_device *dev)
506{
507 struct drm_nouveau_private *dev_priv = dev->dev_private;
508 struct nouveau_engine *engine;
509 int ret, e = 0;
510
511 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
512 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
513 nouveau_switcheroo_reprobe,
514 nouveau_switcheroo_can_switch);
515
516 /* Initialise internal driver API hooks */
517 ret = nouveau_init_engine_ptrs(dev);
518 if (ret)
519 goto out;
520 engine = &dev_priv->engine;
521 spin_lock_init(&dev_priv->channels.lock);
522 spin_lock_init(&dev_priv->tile.lock);
523 spin_lock_init(&dev_priv->context_switch_lock);
524 spin_lock_init(&dev_priv->vm_lock);
525
526 /* Make the CRTCs and I2C buses accessible */
527 ret = engine->display.early_init(dev);
528 if (ret)
529 goto out;
530
531 /* Parse BIOS tables / Run init tables if card not POSTed */
532 ret = nouveau_bios_init(dev);
533 if (ret)
534 goto out_display_early;
535
536 nouveau_pm_init(dev);
537
538 ret = engine->vram.init(dev);
539 if (ret)
540 goto out_bios;
541
542 ret = nouveau_gpuobj_init(dev);
543 if (ret)
544 goto out_vram;
545
546 ret = engine->instmem.init(dev);
547 if (ret)
548 goto out_gpuobj;
549
550 ret = nouveau_mem_vram_init(dev);
551 if (ret)
552 goto out_instmem;
553
554 ret = nouveau_mem_gart_init(dev);
555 if (ret)
556 goto out_ttmvram;
557
558 /* PMC */
559 ret = engine->mc.init(dev);
560 if (ret)
561 goto out_gart;
562
563 /* PGPIO */
564 ret = engine->gpio.init(dev);
565 if (ret)
566 goto out_mc;
567
568 /* PTIMER */
569 ret = engine->timer.init(dev);
570 if (ret)
571 goto out_gpio;
572
573 /* PFB */
574 ret = engine->fb.init(dev);
575 if (ret)
576 goto out_timer;
577
578 if (!dev_priv->noaccel) {
579 switch (dev_priv->card_type) {
580 case NV_04:
581 nv04_graph_create(dev);
582 break;
583 case NV_10:
584 nv10_graph_create(dev);
585 break;
586 case NV_20:
587 case NV_30:
588 nv20_graph_create(dev);
589 break;
590 case NV_40:
591 nv40_graph_create(dev);
592 break;
593 case NV_50:
594 nv50_graph_create(dev);
595 break;
596 case NV_C0:
597 nvc0_graph_create(dev);
598 break;
599 default:
600 break;
601 }
602
603 switch (dev_priv->chipset) {
604 case 0x84:
605 case 0x86:
606 case 0x92:
607 case 0x94:
608 case 0x96:
609 case 0xa0:
610 nv84_crypt_create(dev);
611 break;
612 }
613
614 switch (dev_priv->card_type) {
615 case NV_50:
616 switch (dev_priv->chipset) {
617 case 0xa3:
618 case 0xa5:
619 case 0xa8:
620 case 0xaf:
621 nva3_copy_create(dev);
622 break;
623 }
624 break;
625 case NV_C0:
626 nvc0_copy_create(dev, 0);
627 nvc0_copy_create(dev, 1);
628 break;
629 default:
630 break;
631 }
632
633 if (dev_priv->card_type == NV_40)
634 nv40_mpeg_create(dev);
635 else
636 if (dev_priv->card_type == NV_50 &&
637 (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
638 nv50_mpeg_create(dev);
639
640 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
641 if (dev_priv->eng[e]) {
642 ret = dev_priv->eng[e]->init(dev, e);
643 if (ret)
644 goto out_engine;
645 }
646 }
647
648 /* PFIFO */
649 ret = engine->fifo.init(dev);
650 if (ret)
651 goto out_engine;
652 }
653
654 ret = engine->display.create(dev);
655 if (ret)
656 goto out_fifo;
657
658 ret = drm_vblank_init(dev, nv_two_heads(dev) ? 2 : 1);
659 if (ret)
660 goto out_vblank;
661
662 ret = nouveau_irq_init(dev);
663 if (ret)
664 goto out_vblank;
665
666 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
667
668 if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
669 ret = nouveau_fence_init(dev);
670 if (ret)
671 goto out_irq;
672
673 ret = nouveau_card_init_channel(dev);
674 if (ret)
675 goto out_fence;
676 }
677
678 nouveau_fbcon_init(dev);
679 drm_kms_helper_poll_init(dev);
680 return 0;
681
682out_fence:
683 nouveau_fence_fini(dev);
684out_irq:
685 nouveau_irq_fini(dev);
686out_vblank:
687 drm_vblank_cleanup(dev);
688 engine->display.destroy(dev);
689out_fifo:
690 if (!dev_priv->noaccel)
691 engine->fifo.takedown(dev);
692out_engine:
693 if (!dev_priv->noaccel) {
694 for (e = e - 1; e >= 0; e--) {
695 if (!dev_priv->eng[e])
696 continue;
697 dev_priv->eng[e]->fini(dev, e, false);
698 dev_priv->eng[e]->destroy(dev,e );
699 }
700 }
701
702 engine->fb.takedown(dev);
703out_timer:
704 engine->timer.takedown(dev);
705out_gpio:
706 engine->gpio.takedown(dev);
707out_mc:
708 engine->mc.takedown(dev);
709out_gart:
710 nouveau_mem_gart_fini(dev);
711out_ttmvram:
712 nouveau_mem_vram_fini(dev);
713out_instmem:
714 engine->instmem.takedown(dev);
715out_gpuobj:
716 nouveau_gpuobj_takedown(dev);
717out_vram:
718 engine->vram.takedown(dev);
719out_bios:
720 nouveau_pm_fini(dev);
721 nouveau_bios_takedown(dev);
722out_display_early:
723 engine->display.late_takedown(dev);
724out:
725 vga_client_register(dev->pdev, NULL, NULL, NULL);
726 return ret;
727}
728
729static void nouveau_card_takedown(struct drm_device *dev)
730{
731 struct drm_nouveau_private *dev_priv = dev->dev_private;
732 struct nouveau_engine *engine = &dev_priv->engine;
733 int e;
734
735 drm_kms_helper_poll_fini(dev);
736 nouveau_fbcon_fini(dev);
737
738 if (dev_priv->channel) {
739 nouveau_channel_put_unlocked(&dev_priv->channel);
740 nouveau_fence_fini(dev);
741 }
742
743 engine->display.destroy(dev);
744
745 if (!dev_priv->noaccel) {
746 engine->fifo.takedown(dev);
747 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
748 if (dev_priv->eng[e]) {
749 dev_priv->eng[e]->fini(dev, e, false);
750 dev_priv->eng[e]->destroy(dev,e );
751 }
752 }
753 }
754 engine->fb.takedown(dev);
755 engine->timer.takedown(dev);
756 engine->gpio.takedown(dev);
757 engine->mc.takedown(dev);
758 engine->display.late_takedown(dev);
759
760 if (dev_priv->vga_ram) {
761 nouveau_bo_unpin(dev_priv->vga_ram);
762 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
763 }
764
765 mutex_lock(&dev->struct_mutex);
766 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
767 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
768 mutex_unlock(&dev->struct_mutex);
769 nouveau_mem_gart_fini(dev);
770 nouveau_mem_vram_fini(dev);
771
772 engine->instmem.takedown(dev);
773 nouveau_gpuobj_takedown(dev);
774 engine->vram.takedown(dev);
775
776 nouveau_irq_fini(dev);
777 drm_vblank_cleanup(dev);
778
779 nouveau_pm_fini(dev);
780 nouveau_bios_takedown(dev);
781
782 vga_client_register(dev->pdev, NULL, NULL, NULL);
783}
784
785int
786nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
787{
788 struct drm_nouveau_private *dev_priv = dev->dev_private;
789 struct nouveau_fpriv *fpriv;
790 int ret;
791
792 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
793 if (unlikely(!fpriv))
794 return -ENOMEM;
795
796 spin_lock_init(&fpriv->lock);
797 INIT_LIST_HEAD(&fpriv->channels);
798
799 if (dev_priv->card_type == NV_50) {
800 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
801 &fpriv->vm);
802 if (ret) {
803 kfree(fpriv);
804 return ret;
805 }
806 } else
807 if (dev_priv->card_type >= NV_C0) {
808 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
809 &fpriv->vm);
810 if (ret) {
811 kfree(fpriv);
812 return ret;
813 }
814 }
815
816 file_priv->driver_priv = fpriv;
817 return 0;
818}
819
820/* here a client dies, release the stuff that was allocated for its
821 * file_priv */
822void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
823{
824 nouveau_channel_cleanup(dev, file_priv);
825}
826
827void
828nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
829{
830 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
831 nouveau_vm_ref(NULL, &fpriv->vm, NULL);
832 kfree(fpriv);
833}
834
835/* first module load, setup the mmio/fb mapping */
836/* KMS: we need mmio at load time, not when the first drm client opens. */
837int nouveau_firstopen(struct drm_device *dev)
838{
839 return 0;
840}
841
842/* if we have an OF card, copy vbios to RAMIN */
843static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
844{
845#if defined(__powerpc__)
846 int size, i;
847 const uint32_t *bios;
848 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
849 if (!dn) {
850 NV_INFO(dev, "Unable to get the OF node\n");
851 return;
852 }
853
854 bios = of_get_property(dn, "NVDA,BMP", &size);
855 if (bios) {
856 for (i = 0; i < size; i += 4)
857 nv_wi32(dev, i, bios[i/4]);
858 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
859 } else {
860 NV_INFO(dev, "Unable to get the OF bios\n");
861 }
862#endif
863}
864
865static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
866{
867 struct pci_dev *pdev = dev->pdev;
868 struct apertures_struct *aper = alloc_apertures(3);
869 if (!aper)
870 return NULL;
871
872 aper->ranges[0].base = pci_resource_start(pdev, 1);
873 aper->ranges[0].size = pci_resource_len(pdev, 1);
874 aper->count = 1;
875
876 if (pci_resource_len(pdev, 2)) {
877 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
878 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
879 aper->count++;
880 }
881
882 if (pci_resource_len(pdev, 3)) {
883 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
884 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
885 aper->count++;
886 }
887
888 return aper;
889}
890
891static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
892{
893 struct drm_nouveau_private *dev_priv = dev->dev_private;
894 bool primary = false;
895 dev_priv->apertures = nouveau_get_apertures(dev);
896 if (!dev_priv->apertures)
897 return -ENOMEM;
898
899#ifdef CONFIG_X86
900 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
901#endif
902
903 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
904 return 0;
905}
906
907int nouveau_load(struct drm_device *dev, unsigned long flags)
908{
909 struct drm_nouveau_private *dev_priv;
910 uint32_t reg0;
911 resource_size_t mmio_start_offs;
912 int ret;
913
914 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
915 if (!dev_priv) {
916 ret = -ENOMEM;
917 goto err_out;
918 }
919 dev->dev_private = dev_priv;
920 dev_priv->dev = dev;
921
922 dev_priv->flags = flags & NOUVEAU_FLAGS;
923
924 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
925 dev->pci_vendor, dev->pci_device, dev->pdev->class);
926
927 /* resource 0 is mmio regs */
928 /* resource 1 is linear FB */
929 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
930 /* resource 6 is bios */
931
932 /* map the mmio regs */
933 mmio_start_offs = pci_resource_start(dev->pdev, 0);
934 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
935 if (!dev_priv->mmio) {
936 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
937 "Please report your setup to " DRIVER_EMAIL "\n");
938 ret = -EINVAL;
939 goto err_priv;
940 }
941 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
942 (unsigned long long)mmio_start_offs);
943
944#ifdef __BIG_ENDIAN
945 /* Put the card in BE mode if it's not */
946 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
947 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
948
949 DRM_MEMORYBARRIER();
950#endif
951
952 /* Time to determine the card architecture */
953 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
954 dev_priv->stepping = 0; /* XXX: add stepping for pre-NV10? */
955
956 /* We're dealing with >=NV10 */
957 if ((reg0 & 0x0f000000) > 0) {
958 /* Bit 27-20 contain the architecture in hex */
959 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
960 dev_priv->stepping = (reg0 & 0xff);
961 /* NV04 or NV05 */
962 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
963 if (reg0 & 0x00f00000)
964 dev_priv->chipset = 0x05;
965 else
966 dev_priv->chipset = 0x04;
967 } else
968 dev_priv->chipset = 0xff;
969
970 switch (dev_priv->chipset & 0xf0) {
971 case 0x00:
972 case 0x10:
973 case 0x20:
974 case 0x30:
975 dev_priv->card_type = dev_priv->chipset & 0xf0;
976 break;
977 case 0x40:
978 case 0x60:
979 dev_priv->card_type = NV_40;
980 break;
981 case 0x50:
982 case 0x80:
983 case 0x90:
984 case 0xa0:
985 dev_priv->card_type = NV_50;
986 break;
987 case 0xc0:
988 dev_priv->card_type = NV_C0;
989 break;
990 default:
991 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
992 ret = -EINVAL;
993 goto err_mmio;
994 }
995
996 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
997 dev_priv->card_type, reg0);
998
999 /* Determine whether we'll attempt acceleration or not, some
1000 * cards are disabled by default here due to them being known
1001 * non-functional, or never been tested due to lack of hw.
1002 */
1003 dev_priv->noaccel = !!nouveau_noaccel;
1004 if (nouveau_noaccel == -1) {
1005 switch (dev_priv->chipset) {
1006 case 0xc1: /* known broken */
1007 case 0xc8: /* never tested */
1008 NV_INFO(dev, "acceleration disabled by default, pass "
1009 "noaccel=0 to force enable\n");
1010 dev_priv->noaccel = true;
1011 break;
1012 default:
1013 dev_priv->noaccel = false;
1014 break;
1015 }
1016 }
1017
1018 ret = nouveau_remove_conflicting_drivers(dev);
1019 if (ret)
1020 goto err_mmio;
1021
1022 /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1023 if (dev_priv->card_type >= NV_40) {
1024 int ramin_bar = 2;
1025 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1026 ramin_bar = 3;
1027
1028 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1029 dev_priv->ramin =
1030 ioremap(pci_resource_start(dev->pdev, ramin_bar),
1031 dev_priv->ramin_size);
1032 if (!dev_priv->ramin) {
1033 NV_ERROR(dev, "Failed to PRAMIN BAR");
1034 ret = -ENOMEM;
1035 goto err_mmio;
1036 }
1037 } else {
1038 dev_priv->ramin_size = 1 * 1024 * 1024;
1039 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
1040 dev_priv->ramin_size);
1041 if (!dev_priv->ramin) {
1042 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1043 ret = -ENOMEM;
1044 goto err_mmio;
1045 }
1046 }
1047
1048 nouveau_OF_copy_vbios_to_ramin(dev);
1049
1050 /* Special flags */
1051 if (dev->pci_device == 0x01a0)
1052 dev_priv->flags |= NV_NFORCE;
1053 else if (dev->pci_device == 0x01f0)
1054 dev_priv->flags |= NV_NFORCE2;
1055
1056 /* For kernel modesetting, init card now and bring up fbcon */
1057 ret = nouveau_card_init(dev);
1058 if (ret)
1059 goto err_ramin;
1060
1061 return 0;
1062
1063err_ramin:
1064 iounmap(dev_priv->ramin);
1065err_mmio:
1066 iounmap(dev_priv->mmio);
1067err_priv:
1068 kfree(dev_priv);
1069 dev->dev_private = NULL;
1070err_out:
1071 return ret;
1072}
1073
1074void nouveau_lastclose(struct drm_device *dev)
1075{
1076 vga_switcheroo_process_delayed_switch();
1077}
1078
1079int nouveau_unload(struct drm_device *dev)
1080{
1081 struct drm_nouveau_private *dev_priv = dev->dev_private;
1082
1083 nouveau_card_takedown(dev);
1084
1085 iounmap(dev_priv->mmio);
1086 iounmap(dev_priv->ramin);
1087
1088 kfree(dev_priv);
1089 dev->dev_private = NULL;
1090 return 0;
1091}
1092
1093int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1094 struct drm_file *file_priv)
1095{
1096 struct drm_nouveau_private *dev_priv = dev->dev_private;
1097 struct drm_nouveau_getparam *getparam = data;
1098
1099 switch (getparam->param) {
1100 case NOUVEAU_GETPARAM_CHIPSET_ID:
1101 getparam->value = dev_priv->chipset;
1102 break;
1103 case NOUVEAU_GETPARAM_PCI_VENDOR:
1104 getparam->value = dev->pci_vendor;
1105 break;
1106 case NOUVEAU_GETPARAM_PCI_DEVICE:
1107 getparam->value = dev->pci_device;
1108 break;
1109 case NOUVEAU_GETPARAM_BUS_TYPE:
1110 if (drm_pci_device_is_agp(dev))
1111 getparam->value = NV_AGP;
1112 else if (pci_is_pcie(dev->pdev))
1113 getparam->value = NV_PCIE;
1114 else
1115 getparam->value = NV_PCI;
1116 break;
1117 case NOUVEAU_GETPARAM_FB_SIZE:
1118 getparam->value = dev_priv->fb_available_size;
1119 break;
1120 case NOUVEAU_GETPARAM_AGP_SIZE:
1121 getparam->value = dev_priv->gart_info.aper_size;
1122 break;
1123 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1124 getparam->value = 0; /* deprecated */
1125 break;
1126 case NOUVEAU_GETPARAM_PTIMER_TIME:
1127 getparam->value = dev_priv->engine.timer.read(dev);
1128 break;
1129 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1130 getparam->value = 1;
1131 break;
1132 case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1133 getparam->value = 1;
1134 break;
1135 case NOUVEAU_GETPARAM_GRAPH_UNITS:
1136 /* NV40 and NV50 versions are quite different, but register
1137 * address is the same. User is supposed to know the card
1138 * family anyway... */
1139 if (dev_priv->chipset >= 0x40) {
1140 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1141 break;
1142 }
1143 /* FALLTHRU */
1144 default:
1145 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1146 return -EINVAL;
1147 }
1148
1149 return 0;
1150}
1151
1152int
1153nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1154 struct drm_file *file_priv)
1155{
1156 struct drm_nouveau_setparam *setparam = data;
1157
1158 switch (setparam->param) {
1159 default:
1160 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1161 return -EINVAL;
1162 }
1163
1164 return 0;
1165}
1166
1167/* Wait until (value(reg) & mask) == val, up until timeout has hit */
1168bool
1169nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1170 uint32_t reg, uint32_t mask, uint32_t val)
1171{
1172 struct drm_nouveau_private *dev_priv = dev->dev_private;
1173 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1174 uint64_t start = ptimer->read(dev);
1175
1176 do {
1177 if ((nv_rd32(dev, reg) & mask) == val)
1178 return true;
1179 } while (ptimer->read(dev) - start < timeout);
1180
1181 return false;
1182}
1183
1184/* Wait until (value(reg) & mask) != val, up until timeout has hit */
1185bool
1186nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1187 uint32_t reg, uint32_t mask, uint32_t val)
1188{
1189 struct drm_nouveau_private *dev_priv = dev->dev_private;
1190 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1191 uint64_t start = ptimer->read(dev);
1192
1193 do {
1194 if ((nv_rd32(dev, reg) & mask) != val)
1195 return true;
1196 } while (ptimer->read(dev) - start < timeout);
1197
1198 return false;
1199}
1200
1201/* Waits for PGRAPH to go completely idle */
1202bool nouveau_wait_for_idle(struct drm_device *dev)
1203{
1204 struct drm_nouveau_private *dev_priv = dev->dev_private;
1205 uint32_t mask = ~0;
1206
1207 if (dev_priv->card_type == NV_40)
1208 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1209
1210 if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1211 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1212 nv_rd32(dev, NV04_PGRAPH_STATUS));
1213 return false;
1214 }
1215
1216 return true;
1217}
1218
1/*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26#include <linux/swab.h>
27#include <linux/slab.h>
28#include "drmP.h"
29#include "drm.h"
30#include "drm_sarea.h"
31#include "drm_crtc_helper.h"
32#include <linux/vgaarb.h>
33#include <linux/vga_switcheroo.h>
34
35#include "nouveau_drv.h"
36#include "nouveau_drm.h"
37#include "nouveau_fbcon.h"
38#include "nouveau_ramht.h"
39#include "nouveau_gpio.h"
40#include "nouveau_pm.h"
41#include "nv50_display.h"
42#include "nouveau_fifo.h"
43#include "nouveau_fence.h"
44#include "nouveau_software.h"
45
46static void nouveau_stub_takedown(struct drm_device *dev) {}
47static int nouveau_stub_init(struct drm_device *dev) { return 0; }
48
49static int nouveau_init_engine_ptrs(struct drm_device *dev)
50{
51 struct drm_nouveau_private *dev_priv = dev->dev_private;
52 struct nouveau_engine *engine = &dev_priv->engine;
53
54 switch (dev_priv->chipset & 0xf0) {
55 case 0x00:
56 engine->instmem.init = nv04_instmem_init;
57 engine->instmem.takedown = nv04_instmem_takedown;
58 engine->instmem.suspend = nv04_instmem_suspend;
59 engine->instmem.resume = nv04_instmem_resume;
60 engine->instmem.get = nv04_instmem_get;
61 engine->instmem.put = nv04_instmem_put;
62 engine->instmem.map = nv04_instmem_map;
63 engine->instmem.unmap = nv04_instmem_unmap;
64 engine->instmem.flush = nv04_instmem_flush;
65 engine->mc.init = nv04_mc_init;
66 engine->mc.takedown = nv04_mc_takedown;
67 engine->timer.init = nv04_timer_init;
68 engine->timer.read = nv04_timer_read;
69 engine->timer.takedown = nv04_timer_takedown;
70 engine->fb.init = nv04_fb_init;
71 engine->fb.takedown = nv04_fb_takedown;
72 engine->display.early_init = nv04_display_early_init;
73 engine->display.late_takedown = nv04_display_late_takedown;
74 engine->display.create = nv04_display_create;
75 engine->display.destroy = nv04_display_destroy;
76 engine->display.init = nv04_display_init;
77 engine->display.fini = nv04_display_fini;
78 engine->pm.clocks_get = nv04_pm_clocks_get;
79 engine->pm.clocks_pre = nv04_pm_clocks_pre;
80 engine->pm.clocks_set = nv04_pm_clocks_set;
81 engine->vram.init = nv04_fb_vram_init;
82 engine->vram.takedown = nouveau_stub_takedown;
83 engine->vram.flags_valid = nouveau_mem_flags_valid;
84 break;
85 case 0x10:
86 engine->instmem.init = nv04_instmem_init;
87 engine->instmem.takedown = nv04_instmem_takedown;
88 engine->instmem.suspend = nv04_instmem_suspend;
89 engine->instmem.resume = nv04_instmem_resume;
90 engine->instmem.get = nv04_instmem_get;
91 engine->instmem.put = nv04_instmem_put;
92 engine->instmem.map = nv04_instmem_map;
93 engine->instmem.unmap = nv04_instmem_unmap;
94 engine->instmem.flush = nv04_instmem_flush;
95 engine->mc.init = nv04_mc_init;
96 engine->mc.takedown = nv04_mc_takedown;
97 engine->timer.init = nv04_timer_init;
98 engine->timer.read = nv04_timer_read;
99 engine->timer.takedown = nv04_timer_takedown;
100 engine->fb.init = nv10_fb_init;
101 engine->fb.takedown = nv10_fb_takedown;
102 engine->fb.init_tile_region = nv10_fb_init_tile_region;
103 engine->fb.set_tile_region = nv10_fb_set_tile_region;
104 engine->fb.free_tile_region = nv10_fb_free_tile_region;
105 engine->display.early_init = nv04_display_early_init;
106 engine->display.late_takedown = nv04_display_late_takedown;
107 engine->display.create = nv04_display_create;
108 engine->display.destroy = nv04_display_destroy;
109 engine->display.init = nv04_display_init;
110 engine->display.fini = nv04_display_fini;
111 engine->gpio.drive = nv10_gpio_drive;
112 engine->gpio.sense = nv10_gpio_sense;
113 engine->pm.clocks_get = nv04_pm_clocks_get;
114 engine->pm.clocks_pre = nv04_pm_clocks_pre;
115 engine->pm.clocks_set = nv04_pm_clocks_set;
116 if (dev_priv->chipset == 0x1a ||
117 dev_priv->chipset == 0x1f)
118 engine->vram.init = nv1a_fb_vram_init;
119 else
120 engine->vram.init = nv10_fb_vram_init;
121 engine->vram.takedown = nouveau_stub_takedown;
122 engine->vram.flags_valid = nouveau_mem_flags_valid;
123 break;
124 case 0x20:
125 engine->instmem.init = nv04_instmem_init;
126 engine->instmem.takedown = nv04_instmem_takedown;
127 engine->instmem.suspend = nv04_instmem_suspend;
128 engine->instmem.resume = nv04_instmem_resume;
129 engine->instmem.get = nv04_instmem_get;
130 engine->instmem.put = nv04_instmem_put;
131 engine->instmem.map = nv04_instmem_map;
132 engine->instmem.unmap = nv04_instmem_unmap;
133 engine->instmem.flush = nv04_instmem_flush;
134 engine->mc.init = nv04_mc_init;
135 engine->mc.takedown = nv04_mc_takedown;
136 engine->timer.init = nv04_timer_init;
137 engine->timer.read = nv04_timer_read;
138 engine->timer.takedown = nv04_timer_takedown;
139 engine->fb.init = nv20_fb_init;
140 engine->fb.takedown = nv20_fb_takedown;
141 engine->fb.init_tile_region = nv20_fb_init_tile_region;
142 engine->fb.set_tile_region = nv20_fb_set_tile_region;
143 engine->fb.free_tile_region = nv20_fb_free_tile_region;
144 engine->display.early_init = nv04_display_early_init;
145 engine->display.late_takedown = nv04_display_late_takedown;
146 engine->display.create = nv04_display_create;
147 engine->display.destroy = nv04_display_destroy;
148 engine->display.init = nv04_display_init;
149 engine->display.fini = nv04_display_fini;
150 engine->gpio.drive = nv10_gpio_drive;
151 engine->gpio.sense = nv10_gpio_sense;
152 engine->pm.clocks_get = nv04_pm_clocks_get;
153 engine->pm.clocks_pre = nv04_pm_clocks_pre;
154 engine->pm.clocks_set = nv04_pm_clocks_set;
155 engine->vram.init = nv20_fb_vram_init;
156 engine->vram.takedown = nouveau_stub_takedown;
157 engine->vram.flags_valid = nouveau_mem_flags_valid;
158 break;
159 case 0x30:
160 engine->instmem.init = nv04_instmem_init;
161 engine->instmem.takedown = nv04_instmem_takedown;
162 engine->instmem.suspend = nv04_instmem_suspend;
163 engine->instmem.resume = nv04_instmem_resume;
164 engine->instmem.get = nv04_instmem_get;
165 engine->instmem.put = nv04_instmem_put;
166 engine->instmem.map = nv04_instmem_map;
167 engine->instmem.unmap = nv04_instmem_unmap;
168 engine->instmem.flush = nv04_instmem_flush;
169 engine->mc.init = nv04_mc_init;
170 engine->mc.takedown = nv04_mc_takedown;
171 engine->timer.init = nv04_timer_init;
172 engine->timer.read = nv04_timer_read;
173 engine->timer.takedown = nv04_timer_takedown;
174 engine->fb.init = nv30_fb_init;
175 engine->fb.takedown = nv30_fb_takedown;
176 engine->fb.init_tile_region = nv30_fb_init_tile_region;
177 engine->fb.set_tile_region = nv10_fb_set_tile_region;
178 engine->fb.free_tile_region = nv30_fb_free_tile_region;
179 engine->display.early_init = nv04_display_early_init;
180 engine->display.late_takedown = nv04_display_late_takedown;
181 engine->display.create = nv04_display_create;
182 engine->display.destroy = nv04_display_destroy;
183 engine->display.init = nv04_display_init;
184 engine->display.fini = nv04_display_fini;
185 engine->gpio.drive = nv10_gpio_drive;
186 engine->gpio.sense = nv10_gpio_sense;
187 engine->pm.clocks_get = nv04_pm_clocks_get;
188 engine->pm.clocks_pre = nv04_pm_clocks_pre;
189 engine->pm.clocks_set = nv04_pm_clocks_set;
190 engine->pm.voltage_get = nouveau_voltage_gpio_get;
191 engine->pm.voltage_set = nouveau_voltage_gpio_set;
192 engine->vram.init = nv20_fb_vram_init;
193 engine->vram.takedown = nouveau_stub_takedown;
194 engine->vram.flags_valid = nouveau_mem_flags_valid;
195 break;
196 case 0x40:
197 case 0x60:
198 engine->instmem.init = nv04_instmem_init;
199 engine->instmem.takedown = nv04_instmem_takedown;
200 engine->instmem.suspend = nv04_instmem_suspend;
201 engine->instmem.resume = nv04_instmem_resume;
202 engine->instmem.get = nv04_instmem_get;
203 engine->instmem.put = nv04_instmem_put;
204 engine->instmem.map = nv04_instmem_map;
205 engine->instmem.unmap = nv04_instmem_unmap;
206 engine->instmem.flush = nv04_instmem_flush;
207 engine->mc.init = nv40_mc_init;
208 engine->mc.takedown = nv40_mc_takedown;
209 engine->timer.init = nv04_timer_init;
210 engine->timer.read = nv04_timer_read;
211 engine->timer.takedown = nv04_timer_takedown;
212 engine->fb.init = nv40_fb_init;
213 engine->fb.takedown = nv40_fb_takedown;
214 engine->fb.init_tile_region = nv30_fb_init_tile_region;
215 engine->fb.set_tile_region = nv40_fb_set_tile_region;
216 engine->fb.free_tile_region = nv30_fb_free_tile_region;
217 engine->display.early_init = nv04_display_early_init;
218 engine->display.late_takedown = nv04_display_late_takedown;
219 engine->display.create = nv04_display_create;
220 engine->display.destroy = nv04_display_destroy;
221 engine->display.init = nv04_display_init;
222 engine->display.fini = nv04_display_fini;
223 engine->gpio.init = nv10_gpio_init;
224 engine->gpio.fini = nv10_gpio_fini;
225 engine->gpio.drive = nv10_gpio_drive;
226 engine->gpio.sense = nv10_gpio_sense;
227 engine->gpio.irq_enable = nv10_gpio_irq_enable;
228 engine->pm.clocks_get = nv40_pm_clocks_get;
229 engine->pm.clocks_pre = nv40_pm_clocks_pre;
230 engine->pm.clocks_set = nv40_pm_clocks_set;
231 engine->pm.voltage_get = nouveau_voltage_gpio_get;
232 engine->pm.voltage_set = nouveau_voltage_gpio_set;
233 engine->pm.temp_get = nv40_temp_get;
234 engine->pm.pwm_get = nv40_pm_pwm_get;
235 engine->pm.pwm_set = nv40_pm_pwm_set;
236 engine->vram.init = nv40_fb_vram_init;
237 engine->vram.takedown = nouveau_stub_takedown;
238 engine->vram.flags_valid = nouveau_mem_flags_valid;
239 break;
240 case 0x50:
241 case 0x80: /* gotta love NVIDIA's consistency.. */
242 case 0x90:
243 case 0xa0:
244 engine->instmem.init = nv50_instmem_init;
245 engine->instmem.takedown = nv50_instmem_takedown;
246 engine->instmem.suspend = nv50_instmem_suspend;
247 engine->instmem.resume = nv50_instmem_resume;
248 engine->instmem.get = nv50_instmem_get;
249 engine->instmem.put = nv50_instmem_put;
250 engine->instmem.map = nv50_instmem_map;
251 engine->instmem.unmap = nv50_instmem_unmap;
252 if (dev_priv->chipset == 0x50)
253 engine->instmem.flush = nv50_instmem_flush;
254 else
255 engine->instmem.flush = nv84_instmem_flush;
256 engine->mc.init = nv50_mc_init;
257 engine->mc.takedown = nv50_mc_takedown;
258 engine->timer.init = nv04_timer_init;
259 engine->timer.read = nv04_timer_read;
260 engine->timer.takedown = nv04_timer_takedown;
261 engine->fb.init = nv50_fb_init;
262 engine->fb.takedown = nv50_fb_takedown;
263 engine->display.early_init = nv50_display_early_init;
264 engine->display.late_takedown = nv50_display_late_takedown;
265 engine->display.create = nv50_display_create;
266 engine->display.destroy = nv50_display_destroy;
267 engine->display.init = nv50_display_init;
268 engine->display.fini = nv50_display_fini;
269 engine->gpio.init = nv50_gpio_init;
270 engine->gpio.fini = nv50_gpio_fini;
271 engine->gpio.drive = nv50_gpio_drive;
272 engine->gpio.sense = nv50_gpio_sense;
273 engine->gpio.irq_enable = nv50_gpio_irq_enable;
274 switch (dev_priv->chipset) {
275 case 0x84:
276 case 0x86:
277 case 0x92:
278 case 0x94:
279 case 0x96:
280 case 0x98:
281 case 0xa0:
282 case 0xaa:
283 case 0xac:
284 case 0x50:
285 engine->pm.clocks_get = nv50_pm_clocks_get;
286 engine->pm.clocks_pre = nv50_pm_clocks_pre;
287 engine->pm.clocks_set = nv50_pm_clocks_set;
288 break;
289 default:
290 engine->pm.clocks_get = nva3_pm_clocks_get;
291 engine->pm.clocks_pre = nva3_pm_clocks_pre;
292 engine->pm.clocks_set = nva3_pm_clocks_set;
293 break;
294 }
295 engine->pm.voltage_get = nouveau_voltage_gpio_get;
296 engine->pm.voltage_set = nouveau_voltage_gpio_set;
297 if (dev_priv->chipset >= 0x84)
298 engine->pm.temp_get = nv84_temp_get;
299 else
300 engine->pm.temp_get = nv40_temp_get;
301 engine->pm.pwm_get = nv50_pm_pwm_get;
302 engine->pm.pwm_set = nv50_pm_pwm_set;
303 engine->vram.init = nv50_vram_init;
304 engine->vram.takedown = nv50_vram_fini;
305 engine->vram.get = nv50_vram_new;
306 engine->vram.put = nv50_vram_del;
307 engine->vram.flags_valid = nv50_vram_flags_valid;
308 break;
309 case 0xc0:
310 engine->instmem.init = nvc0_instmem_init;
311 engine->instmem.takedown = nvc0_instmem_takedown;
312 engine->instmem.suspend = nvc0_instmem_suspend;
313 engine->instmem.resume = nvc0_instmem_resume;
314 engine->instmem.get = nv50_instmem_get;
315 engine->instmem.put = nv50_instmem_put;
316 engine->instmem.map = nv50_instmem_map;
317 engine->instmem.unmap = nv50_instmem_unmap;
318 engine->instmem.flush = nv84_instmem_flush;
319 engine->mc.init = nv50_mc_init;
320 engine->mc.takedown = nv50_mc_takedown;
321 engine->timer.init = nv04_timer_init;
322 engine->timer.read = nv04_timer_read;
323 engine->timer.takedown = nv04_timer_takedown;
324 engine->fb.init = nvc0_fb_init;
325 engine->fb.takedown = nvc0_fb_takedown;
326 engine->display.early_init = nv50_display_early_init;
327 engine->display.late_takedown = nv50_display_late_takedown;
328 engine->display.create = nv50_display_create;
329 engine->display.destroy = nv50_display_destroy;
330 engine->display.init = nv50_display_init;
331 engine->display.fini = nv50_display_fini;
332 engine->gpio.init = nv50_gpio_init;
333 engine->gpio.fini = nv50_gpio_fini;
334 engine->gpio.drive = nv50_gpio_drive;
335 engine->gpio.sense = nv50_gpio_sense;
336 engine->gpio.irq_enable = nv50_gpio_irq_enable;
337 engine->vram.init = nvc0_vram_init;
338 engine->vram.takedown = nv50_vram_fini;
339 engine->vram.get = nvc0_vram_new;
340 engine->vram.put = nv50_vram_del;
341 engine->vram.flags_valid = nvc0_vram_flags_valid;
342 engine->pm.temp_get = nv84_temp_get;
343 engine->pm.clocks_get = nvc0_pm_clocks_get;
344 engine->pm.clocks_pre = nvc0_pm_clocks_pre;
345 engine->pm.clocks_set = nvc0_pm_clocks_set;
346 engine->pm.voltage_get = nouveau_voltage_gpio_get;
347 engine->pm.voltage_set = nouveau_voltage_gpio_set;
348 engine->pm.pwm_get = nv50_pm_pwm_get;
349 engine->pm.pwm_set = nv50_pm_pwm_set;
350 break;
351 case 0xd0:
352 engine->instmem.init = nvc0_instmem_init;
353 engine->instmem.takedown = nvc0_instmem_takedown;
354 engine->instmem.suspend = nvc0_instmem_suspend;
355 engine->instmem.resume = nvc0_instmem_resume;
356 engine->instmem.get = nv50_instmem_get;
357 engine->instmem.put = nv50_instmem_put;
358 engine->instmem.map = nv50_instmem_map;
359 engine->instmem.unmap = nv50_instmem_unmap;
360 engine->instmem.flush = nv84_instmem_flush;
361 engine->mc.init = nv50_mc_init;
362 engine->mc.takedown = nv50_mc_takedown;
363 engine->timer.init = nv04_timer_init;
364 engine->timer.read = nv04_timer_read;
365 engine->timer.takedown = nv04_timer_takedown;
366 engine->fb.init = nvc0_fb_init;
367 engine->fb.takedown = nvc0_fb_takedown;
368 engine->display.early_init = nouveau_stub_init;
369 engine->display.late_takedown = nouveau_stub_takedown;
370 engine->display.create = nvd0_display_create;
371 engine->display.destroy = nvd0_display_destroy;
372 engine->display.init = nvd0_display_init;
373 engine->display.fini = nvd0_display_fini;
374 engine->gpio.init = nv50_gpio_init;
375 engine->gpio.fini = nv50_gpio_fini;
376 engine->gpio.drive = nvd0_gpio_drive;
377 engine->gpio.sense = nvd0_gpio_sense;
378 engine->gpio.irq_enable = nv50_gpio_irq_enable;
379 engine->vram.init = nvc0_vram_init;
380 engine->vram.takedown = nv50_vram_fini;
381 engine->vram.get = nvc0_vram_new;
382 engine->vram.put = nv50_vram_del;
383 engine->vram.flags_valid = nvc0_vram_flags_valid;
384 engine->pm.temp_get = nv84_temp_get;
385 engine->pm.clocks_get = nvc0_pm_clocks_get;
386 engine->pm.clocks_pre = nvc0_pm_clocks_pre;
387 engine->pm.clocks_set = nvc0_pm_clocks_set;
388 engine->pm.voltage_get = nouveau_voltage_gpio_get;
389 engine->pm.voltage_set = nouveau_voltage_gpio_set;
390 break;
391 case 0xe0:
392 engine->instmem.init = nvc0_instmem_init;
393 engine->instmem.takedown = nvc0_instmem_takedown;
394 engine->instmem.suspend = nvc0_instmem_suspend;
395 engine->instmem.resume = nvc0_instmem_resume;
396 engine->instmem.get = nv50_instmem_get;
397 engine->instmem.put = nv50_instmem_put;
398 engine->instmem.map = nv50_instmem_map;
399 engine->instmem.unmap = nv50_instmem_unmap;
400 engine->instmem.flush = nv84_instmem_flush;
401 engine->mc.init = nv50_mc_init;
402 engine->mc.takedown = nv50_mc_takedown;
403 engine->timer.init = nv04_timer_init;
404 engine->timer.read = nv04_timer_read;
405 engine->timer.takedown = nv04_timer_takedown;
406 engine->fb.init = nvc0_fb_init;
407 engine->fb.takedown = nvc0_fb_takedown;
408 engine->display.early_init = nouveau_stub_init;
409 engine->display.late_takedown = nouveau_stub_takedown;
410 engine->display.create = nvd0_display_create;
411 engine->display.destroy = nvd0_display_destroy;
412 engine->display.init = nvd0_display_init;
413 engine->display.fini = nvd0_display_fini;
414 engine->gpio.init = nv50_gpio_init;
415 engine->gpio.fini = nv50_gpio_fini;
416 engine->gpio.drive = nvd0_gpio_drive;
417 engine->gpio.sense = nvd0_gpio_sense;
418 engine->gpio.irq_enable = nv50_gpio_irq_enable;
419 engine->vram.init = nvc0_vram_init;
420 engine->vram.takedown = nv50_vram_fini;
421 engine->vram.get = nvc0_vram_new;
422 engine->vram.put = nv50_vram_del;
423 engine->vram.flags_valid = nvc0_vram_flags_valid;
424 break;
425 default:
426 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
427 return 1;
428 }
429
430 /* headless mode */
431 if (nouveau_modeset == 2) {
432 engine->display.early_init = nouveau_stub_init;
433 engine->display.late_takedown = nouveau_stub_takedown;
434 engine->display.create = nouveau_stub_init;
435 engine->display.init = nouveau_stub_init;
436 engine->display.destroy = nouveau_stub_takedown;
437 }
438
439 return 0;
440}
441
442static unsigned int
443nouveau_vga_set_decode(void *priv, bool state)
444{
445 struct drm_device *dev = priv;
446 struct drm_nouveau_private *dev_priv = dev->dev_private;
447
448 if (dev_priv->chipset >= 0x40)
449 nv_wr32(dev, 0x88054, state);
450 else
451 nv_wr32(dev, 0x1854, state);
452
453 if (state)
454 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
455 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
456 else
457 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
458}
459
460static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
461 enum vga_switcheroo_state state)
462{
463 struct drm_device *dev = pci_get_drvdata(pdev);
464 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
465 if (state == VGA_SWITCHEROO_ON) {
466 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
467 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
468 nouveau_pci_resume(pdev);
469 drm_kms_helper_poll_enable(dev);
470 dev->switch_power_state = DRM_SWITCH_POWER_ON;
471 } else {
472 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
473 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
474 drm_kms_helper_poll_disable(dev);
475 nouveau_switcheroo_optimus_dsm();
476 nouveau_pci_suspend(pdev, pmm);
477 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
478 }
479}
480
481static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
482{
483 struct drm_device *dev = pci_get_drvdata(pdev);
484 nouveau_fbcon_output_poll_changed(dev);
485}
486
487static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
488{
489 struct drm_device *dev = pci_get_drvdata(pdev);
490 bool can_switch;
491
492 spin_lock(&dev->count_lock);
493 can_switch = (dev->open_count == 0);
494 spin_unlock(&dev->count_lock);
495 return can_switch;
496}
497
498static void
499nouveau_card_channel_fini(struct drm_device *dev)
500{
501 struct drm_nouveau_private *dev_priv = dev->dev_private;
502
503 if (dev_priv->channel)
504 nouveau_channel_put_unlocked(&dev_priv->channel);
505}
506
507static int
508nouveau_card_channel_init(struct drm_device *dev)
509{
510 struct drm_nouveau_private *dev_priv = dev->dev_private;
511 struct nouveau_channel *chan;
512 int ret;
513
514 ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT);
515 dev_priv->channel = chan;
516 if (ret)
517 return ret;
518 mutex_unlock(&dev_priv->channel->mutex);
519
520 nouveau_bo_move_init(chan);
521 return 0;
522}
523
524static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = {
525 .set_gpu_state = nouveau_switcheroo_set_state,
526 .reprobe = nouveau_switcheroo_reprobe,
527 .can_switch = nouveau_switcheroo_can_switch,
528};
529
530int
531nouveau_card_init(struct drm_device *dev)
532{
533 struct drm_nouveau_private *dev_priv = dev->dev_private;
534 struct nouveau_engine *engine;
535 int ret, e = 0;
536
537 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
538 vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
539
540 /* Initialise internal driver API hooks */
541 ret = nouveau_init_engine_ptrs(dev);
542 if (ret)
543 goto out;
544 engine = &dev_priv->engine;
545 spin_lock_init(&dev_priv->channels.lock);
546 spin_lock_init(&dev_priv->tile.lock);
547 spin_lock_init(&dev_priv->context_switch_lock);
548 spin_lock_init(&dev_priv->vm_lock);
549
550 /* Make the CRTCs and I2C buses accessible */
551 ret = engine->display.early_init(dev);
552 if (ret)
553 goto out;
554
555 /* Parse BIOS tables / Run init tables if card not POSTed */
556 ret = nouveau_bios_init(dev);
557 if (ret)
558 goto out_display_early;
559
560 /* workaround an odd issue on nvc1 by disabling the device's
561 * nosnoop capability. hopefully won't cause issues until a
562 * better fix is found - assuming there is one...
563 */
564 if (dev_priv->chipset == 0xc1) {
565 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
566 }
567
568 /* PMC */
569 ret = engine->mc.init(dev);
570 if (ret)
571 goto out_bios;
572
573 /* PTIMER */
574 ret = engine->timer.init(dev);
575 if (ret)
576 goto out_mc;
577
578 /* PFB */
579 ret = engine->fb.init(dev);
580 if (ret)
581 goto out_timer;
582
583 ret = engine->vram.init(dev);
584 if (ret)
585 goto out_fb;
586
587 /* PGPIO */
588 ret = nouveau_gpio_create(dev);
589 if (ret)
590 goto out_vram;
591
592 ret = nouveau_gpuobj_init(dev);
593 if (ret)
594 goto out_gpio;
595
596 ret = engine->instmem.init(dev);
597 if (ret)
598 goto out_gpuobj;
599
600 ret = nouveau_mem_vram_init(dev);
601 if (ret)
602 goto out_instmem;
603
604 ret = nouveau_mem_gart_init(dev);
605 if (ret)
606 goto out_ttmvram;
607
608 if (!dev_priv->noaccel) {
609 switch (dev_priv->card_type) {
610 case NV_04:
611 nv04_fifo_create(dev);
612 break;
613 case NV_10:
614 case NV_20:
615 case NV_30:
616 if (dev_priv->chipset < 0x17)
617 nv10_fifo_create(dev);
618 else
619 nv17_fifo_create(dev);
620 break;
621 case NV_40:
622 nv40_fifo_create(dev);
623 break;
624 case NV_50:
625 if (dev_priv->chipset == 0x50)
626 nv50_fifo_create(dev);
627 else
628 nv84_fifo_create(dev);
629 break;
630 case NV_C0:
631 case NV_D0:
632 nvc0_fifo_create(dev);
633 break;
634 case NV_E0:
635 nve0_fifo_create(dev);
636 break;
637 default:
638 break;
639 }
640
641 switch (dev_priv->card_type) {
642 case NV_04:
643 nv04_fence_create(dev);
644 break;
645 case NV_10:
646 case NV_20:
647 case NV_30:
648 case NV_40:
649 case NV_50:
650 if (dev_priv->chipset < 0x84)
651 nv10_fence_create(dev);
652 else
653 nv84_fence_create(dev);
654 break;
655 case NV_C0:
656 case NV_D0:
657 case NV_E0:
658 nvc0_fence_create(dev);
659 break;
660 default:
661 break;
662 }
663
664 switch (dev_priv->card_type) {
665 case NV_04:
666 case NV_10:
667 case NV_20:
668 case NV_30:
669 case NV_40:
670 nv04_software_create(dev);
671 break;
672 case NV_50:
673 nv50_software_create(dev);
674 break;
675 case NV_C0:
676 case NV_D0:
677 case NV_E0:
678 nvc0_software_create(dev);
679 break;
680 default:
681 break;
682 }
683
684 switch (dev_priv->card_type) {
685 case NV_04:
686 nv04_graph_create(dev);
687 break;
688 case NV_10:
689 nv10_graph_create(dev);
690 break;
691 case NV_20:
692 case NV_30:
693 nv20_graph_create(dev);
694 break;
695 case NV_40:
696 nv40_graph_create(dev);
697 break;
698 case NV_50:
699 nv50_graph_create(dev);
700 break;
701 case NV_C0:
702 case NV_D0:
703 nvc0_graph_create(dev);
704 break;
705 case NV_E0:
706 nve0_graph_create(dev);
707 break;
708 default:
709 break;
710 }
711
712 switch (dev_priv->chipset) {
713 case 0x84:
714 case 0x86:
715 case 0x92:
716 case 0x94:
717 case 0x96:
718 case 0xa0:
719 nv84_crypt_create(dev);
720 break;
721 case 0x98:
722 case 0xaa:
723 case 0xac:
724 nv98_crypt_create(dev);
725 break;
726 }
727
728 switch (dev_priv->card_type) {
729 case NV_50:
730 switch (dev_priv->chipset) {
731 case 0xa3:
732 case 0xa5:
733 case 0xa8:
734 case 0xaf:
735 nva3_copy_create(dev);
736 break;
737 }
738 break;
739 case NV_C0:
740 if (!(nv_rd32(dev, 0x022500) & 0x00000200))
741 nvc0_copy_create(dev, 1);
742 case NV_D0:
743 if (!(nv_rd32(dev, 0x022500) & 0x00000100))
744 nvc0_copy_create(dev, 0);
745 break;
746 default:
747 break;
748 }
749
750 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
751 nv84_bsp_create(dev);
752 nv84_vp_create(dev);
753 nv98_ppp_create(dev);
754 } else
755 if (dev_priv->chipset >= 0x84) {
756 nv50_mpeg_create(dev);
757 nv84_bsp_create(dev);
758 nv84_vp_create(dev);
759 } else
760 if (dev_priv->chipset >= 0x50) {
761 nv50_mpeg_create(dev);
762 } else
763 if (dev_priv->card_type == NV_40 ||
764 dev_priv->chipset == 0x31 ||
765 dev_priv->chipset == 0x34 ||
766 dev_priv->chipset == 0x36) {
767 nv31_mpeg_create(dev);
768 }
769
770 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
771 if (dev_priv->eng[e]) {
772 ret = dev_priv->eng[e]->init(dev, e);
773 if (ret)
774 goto out_engine;
775 }
776 }
777 }
778
779 ret = nouveau_irq_init(dev);
780 if (ret)
781 goto out_engine;
782
783 ret = nouveau_display_create(dev);
784 if (ret)
785 goto out_irq;
786
787 nouveau_backlight_init(dev);
788 nouveau_pm_init(dev);
789
790 if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
791 ret = nouveau_card_channel_init(dev);
792 if (ret)
793 goto out_pm;
794 }
795
796 if (dev->mode_config.num_crtc) {
797 ret = nouveau_display_init(dev);
798 if (ret)
799 goto out_chan;
800
801 nouveau_fbcon_init(dev);
802 }
803
804 return 0;
805
806out_chan:
807 nouveau_card_channel_fini(dev);
808out_pm:
809 nouveau_pm_fini(dev);
810 nouveau_backlight_exit(dev);
811 nouveau_display_destroy(dev);
812out_irq:
813 nouveau_irq_fini(dev);
814out_engine:
815 if (!dev_priv->noaccel) {
816 for (e = e - 1; e >= 0; e--) {
817 if (!dev_priv->eng[e])
818 continue;
819 dev_priv->eng[e]->fini(dev, e, false);
820 dev_priv->eng[e]->destroy(dev,e );
821 }
822 }
823 nouveau_mem_gart_fini(dev);
824out_ttmvram:
825 nouveau_mem_vram_fini(dev);
826out_instmem:
827 engine->instmem.takedown(dev);
828out_gpuobj:
829 nouveau_gpuobj_takedown(dev);
830out_gpio:
831 nouveau_gpio_destroy(dev);
832out_vram:
833 engine->vram.takedown(dev);
834out_fb:
835 engine->fb.takedown(dev);
836out_timer:
837 engine->timer.takedown(dev);
838out_mc:
839 engine->mc.takedown(dev);
840out_bios:
841 nouveau_bios_takedown(dev);
842out_display_early:
843 engine->display.late_takedown(dev);
844out:
845 vga_switcheroo_unregister_client(dev->pdev);
846 vga_client_register(dev->pdev, NULL, NULL, NULL);
847 return ret;
848}
849
850static void nouveau_card_takedown(struct drm_device *dev)
851{
852 struct drm_nouveau_private *dev_priv = dev->dev_private;
853 struct nouveau_engine *engine = &dev_priv->engine;
854 int e;
855
856 if (dev->mode_config.num_crtc) {
857 nouveau_fbcon_fini(dev);
858 nouveau_display_fini(dev);
859 }
860
861 nouveau_card_channel_fini(dev);
862 nouveau_pm_fini(dev);
863 nouveau_backlight_exit(dev);
864 nouveau_display_destroy(dev);
865
866 if (!dev_priv->noaccel) {
867 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
868 if (dev_priv->eng[e]) {
869 dev_priv->eng[e]->fini(dev, e, false);
870 dev_priv->eng[e]->destroy(dev,e );
871 }
872 }
873 }
874
875 if (dev_priv->vga_ram) {
876 nouveau_bo_unpin(dev_priv->vga_ram);
877 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
878 }
879
880 mutex_lock(&dev->struct_mutex);
881 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
882 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
883 mutex_unlock(&dev->struct_mutex);
884 nouveau_mem_gart_fini(dev);
885 nouveau_mem_vram_fini(dev);
886
887 engine->instmem.takedown(dev);
888 nouveau_gpuobj_takedown(dev);
889
890 nouveau_gpio_destroy(dev);
891 engine->vram.takedown(dev);
892 engine->fb.takedown(dev);
893 engine->timer.takedown(dev);
894 engine->mc.takedown(dev);
895
896 nouveau_bios_takedown(dev);
897 engine->display.late_takedown(dev);
898
899 nouveau_irq_fini(dev);
900
901 vga_switcheroo_unregister_client(dev->pdev);
902 vga_client_register(dev->pdev, NULL, NULL, NULL);
903}
904
905int
906nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
907{
908 struct drm_nouveau_private *dev_priv = dev->dev_private;
909 struct nouveau_fpriv *fpriv;
910 int ret;
911
912 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
913 if (unlikely(!fpriv))
914 return -ENOMEM;
915
916 spin_lock_init(&fpriv->lock);
917 INIT_LIST_HEAD(&fpriv->channels);
918
919 if (dev_priv->card_type == NV_50) {
920 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
921 &fpriv->vm);
922 if (ret) {
923 kfree(fpriv);
924 return ret;
925 }
926 } else
927 if (dev_priv->card_type >= NV_C0) {
928 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
929 &fpriv->vm);
930 if (ret) {
931 kfree(fpriv);
932 return ret;
933 }
934 }
935
936 file_priv->driver_priv = fpriv;
937 return 0;
938}
939
940/* here a client dies, release the stuff that was allocated for its
941 * file_priv */
942void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
943{
944 nouveau_channel_cleanup(dev, file_priv);
945}
946
947void
948nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
949{
950 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
951 nouveau_vm_ref(NULL, &fpriv->vm, NULL);
952 kfree(fpriv);
953}
954
955/* first module load, setup the mmio/fb mapping */
956/* KMS: we need mmio at load time, not when the first drm client opens. */
957int nouveau_firstopen(struct drm_device *dev)
958{
959 return 0;
960}
961
962/* if we have an OF card, copy vbios to RAMIN */
963static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
964{
965#if defined(__powerpc__)
966 int size, i;
967 const uint32_t *bios;
968 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
969 if (!dn) {
970 NV_INFO(dev, "Unable to get the OF node\n");
971 return;
972 }
973
974 bios = of_get_property(dn, "NVDA,BMP", &size);
975 if (bios) {
976 for (i = 0; i < size; i += 4)
977 nv_wi32(dev, i, bios[i/4]);
978 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
979 } else {
980 NV_INFO(dev, "Unable to get the OF bios\n");
981 }
982#endif
983}
984
985static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
986{
987 struct pci_dev *pdev = dev->pdev;
988 struct apertures_struct *aper = alloc_apertures(3);
989 if (!aper)
990 return NULL;
991
992 aper->ranges[0].base = pci_resource_start(pdev, 1);
993 aper->ranges[0].size = pci_resource_len(pdev, 1);
994 aper->count = 1;
995
996 if (pci_resource_len(pdev, 2)) {
997 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
998 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
999 aper->count++;
1000 }
1001
1002 if (pci_resource_len(pdev, 3)) {
1003 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
1004 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
1005 aper->count++;
1006 }
1007
1008 return aper;
1009}
1010
1011static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
1012{
1013 struct drm_nouveau_private *dev_priv = dev->dev_private;
1014 bool primary = false;
1015 dev_priv->apertures = nouveau_get_apertures(dev);
1016 if (!dev_priv->apertures)
1017 return -ENOMEM;
1018
1019#ifdef CONFIG_X86
1020 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1021#endif
1022
1023 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
1024 return 0;
1025}
1026
1027int nouveau_load(struct drm_device *dev, unsigned long flags)
1028{
1029 struct drm_nouveau_private *dev_priv;
1030 unsigned long long offset, length;
1031 uint32_t reg0 = ~0, strap;
1032 int ret;
1033
1034 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1035 if (!dev_priv) {
1036 ret = -ENOMEM;
1037 goto err_out;
1038 }
1039 dev->dev_private = dev_priv;
1040 dev_priv->dev = dev;
1041
1042 pci_set_master(dev->pdev);
1043
1044 dev_priv->flags = flags & NOUVEAU_FLAGS;
1045
1046 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1047 dev->pci_vendor, dev->pci_device, dev->pdev->class);
1048
1049 /* first up, map the start of mmio and determine the chipset */
1050 dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE);
1051 if (dev_priv->mmio) {
1052#ifdef __BIG_ENDIAN
1053 /* put the card into big-endian mode if it's not */
1054 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1055 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1056 DRM_MEMORYBARRIER();
1057#endif
1058
1059 /* determine chipset and derive architecture from it */
1060 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1061 if ((reg0 & 0x0f000000) > 0) {
1062 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1063 switch (dev_priv->chipset & 0xf0) {
1064 case 0x10:
1065 case 0x20:
1066 case 0x30:
1067 dev_priv->card_type = dev_priv->chipset & 0xf0;
1068 break;
1069 case 0x40:
1070 case 0x60:
1071 dev_priv->card_type = NV_40;
1072 break;
1073 case 0x50:
1074 case 0x80:
1075 case 0x90:
1076 case 0xa0:
1077 dev_priv->card_type = NV_50;
1078 break;
1079 case 0xc0:
1080 dev_priv->card_type = NV_C0;
1081 break;
1082 case 0xd0:
1083 dev_priv->card_type = NV_D0;
1084 break;
1085 case 0xe0:
1086 dev_priv->card_type = NV_E0;
1087 break;
1088 default:
1089 break;
1090 }
1091 } else
1092 if ((reg0 & 0xff00fff0) == 0x20004000) {
1093 if (reg0 & 0x00f00000)
1094 dev_priv->chipset = 0x05;
1095 else
1096 dev_priv->chipset = 0x04;
1097 dev_priv->card_type = NV_04;
1098 }
1099
1100 iounmap(dev_priv->mmio);
1101 }
1102
1103 if (!dev_priv->card_type) {
1104 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1105 ret = -EINVAL;
1106 goto err_priv;
1107 }
1108
1109 NV_INFO(dev, "Detected an NV%02x generation card (0x%08x)\n",
1110 dev_priv->card_type, reg0);
1111
1112 /* map the mmio regs, limiting the amount to preserve vmap space */
1113 offset = pci_resource_start(dev->pdev, 0);
1114 length = pci_resource_len(dev->pdev, 0);
1115 if (dev_priv->card_type < NV_E0)
1116 length = min(length, (unsigned long long)0x00800000);
1117
1118 dev_priv->mmio = ioremap(offset, length);
1119 if (!dev_priv->mmio) {
1120 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1121 "Please report your setup to " DRIVER_EMAIL "\n");
1122 ret = -EINVAL;
1123 goto err_priv;
1124 }
1125 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", offset);
1126
1127 /* determine frequency of timing crystal */
1128 strap = nv_rd32(dev, 0x101000);
1129 if ( dev_priv->chipset < 0x17 ||
1130 (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1131 strap &= 0x00000040;
1132 else
1133 strap &= 0x00400040;
1134
1135 switch (strap) {
1136 case 0x00000000: dev_priv->crystal = 13500; break;
1137 case 0x00000040: dev_priv->crystal = 14318; break;
1138 case 0x00400000: dev_priv->crystal = 27000; break;
1139 case 0x00400040: dev_priv->crystal = 25000; break;
1140 }
1141
1142 NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1143
1144 /* Determine whether we'll attempt acceleration or not, some
1145 * cards are disabled by default here due to them being known
1146 * non-functional, or never been tested due to lack of hw.
1147 */
1148 dev_priv->noaccel = !!nouveau_noaccel;
1149 if (nouveau_noaccel == -1) {
1150 switch (dev_priv->chipset) {
1151 case 0xd9: /* known broken */
1152 case 0xe4: /* needs binary driver firmware */
1153 case 0xe7: /* needs binary driver firmware */
1154 NV_INFO(dev, "acceleration disabled by default, pass "
1155 "noaccel=0 to force enable\n");
1156 dev_priv->noaccel = true;
1157 break;
1158 default:
1159 dev_priv->noaccel = false;
1160 break;
1161 }
1162 }
1163
1164 ret = nouveau_remove_conflicting_drivers(dev);
1165 if (ret)
1166 goto err_mmio;
1167
1168 /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1169 if (dev_priv->card_type >= NV_40) {
1170 int ramin_bar = 2;
1171 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1172 ramin_bar = 3;
1173
1174 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1175 dev_priv->ramin =
1176 ioremap(pci_resource_start(dev->pdev, ramin_bar),
1177 dev_priv->ramin_size);
1178 if (!dev_priv->ramin) {
1179 NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1180 ret = -ENOMEM;
1181 goto err_mmio;
1182 }
1183 } else {
1184 dev_priv->ramin_size = 1 * 1024 * 1024;
1185 dev_priv->ramin = ioremap(offset + NV_RAMIN,
1186 dev_priv->ramin_size);
1187 if (!dev_priv->ramin) {
1188 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1189 ret = -ENOMEM;
1190 goto err_mmio;
1191 }
1192 }
1193
1194 nouveau_OF_copy_vbios_to_ramin(dev);
1195
1196 /* Special flags */
1197 if (dev->pci_device == 0x01a0)
1198 dev_priv->flags |= NV_NFORCE;
1199 else if (dev->pci_device == 0x01f0)
1200 dev_priv->flags |= NV_NFORCE2;
1201
1202 /* For kernel modesetting, init card now and bring up fbcon */
1203 ret = nouveau_card_init(dev);
1204 if (ret)
1205 goto err_ramin;
1206
1207 return 0;
1208
1209err_ramin:
1210 iounmap(dev_priv->ramin);
1211err_mmio:
1212 iounmap(dev_priv->mmio);
1213err_priv:
1214 kfree(dev_priv);
1215 dev->dev_private = NULL;
1216err_out:
1217 return ret;
1218}
1219
1220void nouveau_lastclose(struct drm_device *dev)
1221{
1222 vga_switcheroo_process_delayed_switch();
1223}
1224
1225int nouveau_unload(struct drm_device *dev)
1226{
1227 struct drm_nouveau_private *dev_priv = dev->dev_private;
1228
1229 nouveau_card_takedown(dev);
1230
1231 iounmap(dev_priv->mmio);
1232 iounmap(dev_priv->ramin);
1233
1234 kfree(dev_priv);
1235 dev->dev_private = NULL;
1236 return 0;
1237}
1238
1239int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1240 struct drm_file *file_priv)
1241{
1242 struct drm_nouveau_private *dev_priv = dev->dev_private;
1243 struct drm_nouveau_getparam *getparam = data;
1244
1245 switch (getparam->param) {
1246 case NOUVEAU_GETPARAM_CHIPSET_ID:
1247 getparam->value = dev_priv->chipset;
1248 break;
1249 case NOUVEAU_GETPARAM_PCI_VENDOR:
1250 getparam->value = dev->pci_vendor;
1251 break;
1252 case NOUVEAU_GETPARAM_PCI_DEVICE:
1253 getparam->value = dev->pci_device;
1254 break;
1255 case NOUVEAU_GETPARAM_BUS_TYPE:
1256 if (drm_pci_device_is_agp(dev))
1257 getparam->value = NV_AGP;
1258 else if (pci_is_pcie(dev->pdev))
1259 getparam->value = NV_PCIE;
1260 else
1261 getparam->value = NV_PCI;
1262 break;
1263 case NOUVEAU_GETPARAM_FB_SIZE:
1264 getparam->value = dev_priv->fb_available_size;
1265 break;
1266 case NOUVEAU_GETPARAM_AGP_SIZE:
1267 getparam->value = dev_priv->gart_info.aper_size;
1268 break;
1269 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1270 getparam->value = 0; /* deprecated */
1271 break;
1272 case NOUVEAU_GETPARAM_PTIMER_TIME:
1273 getparam->value = dev_priv->engine.timer.read(dev);
1274 break;
1275 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1276 getparam->value = 1;
1277 break;
1278 case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1279 getparam->value = 1;
1280 break;
1281 case NOUVEAU_GETPARAM_GRAPH_UNITS:
1282 /* NV40 and NV50 versions are quite different, but register
1283 * address is the same. User is supposed to know the card
1284 * family anyway... */
1285 if (dev_priv->chipset >= 0x40) {
1286 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1287 break;
1288 }
1289 /* FALLTHRU */
1290 default:
1291 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1292 return -EINVAL;
1293 }
1294
1295 return 0;
1296}
1297
1298int
1299nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1300 struct drm_file *file_priv)
1301{
1302 struct drm_nouveau_setparam *setparam = data;
1303
1304 switch (setparam->param) {
1305 default:
1306 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1307 return -EINVAL;
1308 }
1309
1310 return 0;
1311}
1312
1313/* Wait until (value(reg) & mask) == val, up until timeout has hit */
1314bool
1315nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1316 uint32_t reg, uint32_t mask, uint32_t val)
1317{
1318 struct drm_nouveau_private *dev_priv = dev->dev_private;
1319 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1320 uint64_t start = ptimer->read(dev);
1321
1322 do {
1323 if ((nv_rd32(dev, reg) & mask) == val)
1324 return true;
1325 } while (ptimer->read(dev) - start < timeout);
1326
1327 return false;
1328}
1329
1330/* Wait until (value(reg) & mask) != val, up until timeout has hit */
1331bool
1332nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1333 uint32_t reg, uint32_t mask, uint32_t val)
1334{
1335 struct drm_nouveau_private *dev_priv = dev->dev_private;
1336 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1337 uint64_t start = ptimer->read(dev);
1338
1339 do {
1340 if ((nv_rd32(dev, reg) & mask) != val)
1341 return true;
1342 } while (ptimer->read(dev) - start < timeout);
1343
1344 return false;
1345}
1346
1347/* Wait until cond(data) == true, up until timeout has hit */
1348bool
1349nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1350 bool (*cond)(void *), void *data)
1351{
1352 struct drm_nouveau_private *dev_priv = dev->dev_private;
1353 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1354 u64 start = ptimer->read(dev);
1355
1356 do {
1357 if (cond(data) == true)
1358 return true;
1359 } while (ptimer->read(dev) - start < timeout);
1360
1361 return false;
1362}
1363
1364/* Waits for PGRAPH to go completely idle */
1365bool nouveau_wait_for_idle(struct drm_device *dev)
1366{
1367 struct drm_nouveau_private *dev_priv = dev->dev_private;
1368 uint32_t mask = ~0;
1369
1370 if (dev_priv->card_type == NV_40)
1371 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1372
1373 if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1374 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1375 nv_rd32(dev, NV04_PGRAPH_STATUS));
1376 return false;
1377 }
1378
1379 return true;
1380}
1381