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1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
29 *
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
41 *
42 * Cycle bit rules:
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
47 *
48 * Producer rules:
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
52 * cycle state).
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
56 *
57 * Consumer rules:
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
65 */
66
67#include <linux/scatterlist.h>
68#include <linux/slab.h>
69#include "xhci.h"
70
71static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
74
75/*
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
77 * address of the TRB.
78 */
79dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
80 union xhci_trb *trb)
81{
82 unsigned long segment_offset;
83
84 if (!seg || !trb || trb < seg->trbs)
85 return 0;
86 /* offset in TRBs */
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
89 return 0;
90 return seg->dma + (segment_offset * sizeof(*trb));
91}
92
93/* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
95 */
96static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
98{
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
102 else
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
104}
105
106/* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
108 * event seg?
109 */
110static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
112{
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
115 else
116 return TRB_TYPE_LINK_LE32(trb->link.control);
117}
118
119static int enqueue_is_link_trb(struct xhci_ring *ring)
120{
121 struct xhci_link_trb *link = &ring->enqueue->link;
122 return TRB_TYPE_LINK_LE32(link->control);
123}
124
125/* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
128 */
129static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
133{
134 if (last_trb(xhci, ring, *seg, *trb)) {
135 *seg = (*seg)->next;
136 *trb = ((*seg)->trbs);
137 } else {
138 (*trb)++;
139 }
140}
141
142/*
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
145 */
146static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
147{
148 union xhci_trb *next = ++(ring->dequeue);
149 unsigned long long addr;
150
151 ring->deq_updates++;
152 /* Update the dequeue pointer further if that was a link TRB or we're at
153 * the end of an event ring segment (which doesn't have link TRBS)
154 */
155 while (last_trb(xhci, ring, ring->deq_seg, next)) {
156 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
157 ring->cycle_state = (ring->cycle_state ? 0 : 1);
158 if (!in_interrupt())
159 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
160 ring,
161 (unsigned int) ring->cycle_state);
162 }
163 ring->deq_seg = ring->deq_seg->next;
164 ring->dequeue = ring->deq_seg->trbs;
165 next = ring->dequeue;
166 }
167 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
168}
169
170/*
171 * See Cycle bit rules. SW is the consumer for the event ring only.
172 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
173 *
174 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
175 * chain bit is set), then set the chain bit in all the following link TRBs.
176 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
177 * have their chain bit cleared (so that each Link TRB is a separate TD).
178 *
179 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
180 * set, but other sections talk about dealing with the chain bit set. This was
181 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
182 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
183 *
184 * @more_trbs_coming: Will you enqueue more TRBs before calling
185 * prepare_transfer()?
186 */
187static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
188 bool consumer, bool more_trbs_coming)
189{
190 u32 chain;
191 union xhci_trb *next;
192 unsigned long long addr;
193
194 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
195 next = ++(ring->enqueue);
196
197 ring->enq_updates++;
198 /* Update the dequeue pointer further if that was a link TRB or we're at
199 * the end of an event ring segment (which doesn't have link TRBS)
200 */
201 while (last_trb(xhci, ring, ring->enq_seg, next)) {
202 if (!consumer) {
203 if (ring != xhci->event_ring) {
204 /*
205 * If the caller doesn't plan on enqueueing more
206 * TDs before ringing the doorbell, then we
207 * don't want to give the link TRB to the
208 * hardware just yet. We'll give the link TRB
209 * back in prepare_ring() just before we enqueue
210 * the TD at the top of the ring.
211 */
212 if (!chain && !more_trbs_coming)
213 break;
214
215 /* If we're not dealing with 0.95 hardware,
216 * carry over the chain bit of the previous TRB
217 * (which may mean the chain bit is cleared).
218 */
219 if (!xhci_link_trb_quirk(xhci)) {
220 next->link.control &=
221 cpu_to_le32(~TRB_CHAIN);
222 next->link.control |=
223 cpu_to_le32(chain);
224 }
225 /* Give this link TRB to the hardware */
226 wmb();
227 next->link.control ^= cpu_to_le32(TRB_CYCLE);
228 }
229 /* Toggle the cycle bit after the last ring segment. */
230 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
231 ring->cycle_state = (ring->cycle_state ? 0 : 1);
232 if (!in_interrupt())
233 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
234 ring,
235 (unsigned int) ring->cycle_state);
236 }
237 }
238 ring->enq_seg = ring->enq_seg->next;
239 ring->enqueue = ring->enq_seg->trbs;
240 next = ring->enqueue;
241 }
242 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
243}
244
245/*
246 * Check to see if there's room to enqueue num_trbs on the ring. See rules
247 * above.
248 * FIXME: this would be simpler and faster if we just kept track of the number
249 * of free TRBs in a ring.
250 */
251static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
252 unsigned int num_trbs)
253{
254 int i;
255 union xhci_trb *enq = ring->enqueue;
256 struct xhci_segment *enq_seg = ring->enq_seg;
257 struct xhci_segment *cur_seg;
258 unsigned int left_on_ring;
259
260 /* If we are currently pointing to a link TRB, advance the
261 * enqueue pointer before checking for space */
262 while (last_trb(xhci, ring, enq_seg, enq)) {
263 enq_seg = enq_seg->next;
264 enq = enq_seg->trbs;
265 }
266
267 /* Check if ring is empty */
268 if (enq == ring->dequeue) {
269 /* Can't use link trbs */
270 left_on_ring = TRBS_PER_SEGMENT - 1;
271 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
272 cur_seg = cur_seg->next)
273 left_on_ring += TRBS_PER_SEGMENT - 1;
274
275 /* Always need one TRB free in the ring. */
276 left_on_ring -= 1;
277 if (num_trbs > left_on_ring) {
278 xhci_warn(xhci, "Not enough room on ring; "
279 "need %u TRBs, %u TRBs left\n",
280 num_trbs, left_on_ring);
281 return 0;
282 }
283 return 1;
284 }
285 /* Make sure there's an extra empty TRB available */
286 for (i = 0; i <= num_trbs; ++i) {
287 if (enq == ring->dequeue)
288 return 0;
289 enq++;
290 while (last_trb(xhci, ring, enq_seg, enq)) {
291 enq_seg = enq_seg->next;
292 enq = enq_seg->trbs;
293 }
294 }
295 return 1;
296}
297
298/* Ring the host controller doorbell after placing a command on the ring */
299void xhci_ring_cmd_db(struct xhci_hcd *xhci)
300{
301 xhci_dbg(xhci, "// Ding dong!\n");
302 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
303 /* Flush PCI posted writes */
304 xhci_readl(xhci, &xhci->dba->doorbell[0]);
305}
306
307void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
308 unsigned int slot_id,
309 unsigned int ep_index,
310 unsigned int stream_id)
311{
312 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
313 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
314 unsigned int ep_state = ep->ep_state;
315
316 /* Don't ring the doorbell for this endpoint if there are pending
317 * cancellations because we don't want to interrupt processing.
318 * We don't want to restart any stream rings if there's a set dequeue
319 * pointer command pending because the device can choose to start any
320 * stream once the endpoint is on the HW schedule.
321 * FIXME - check all the stream rings for pending cancellations.
322 */
323 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
324 (ep_state & EP_HALTED))
325 return;
326 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
327 /* The CPU has better things to do at this point than wait for a
328 * write-posting flush. It'll get there soon enough.
329 */
330}
331
332/* Ring the doorbell for any rings with pending URBs */
333static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
334 unsigned int slot_id,
335 unsigned int ep_index)
336{
337 unsigned int stream_id;
338 struct xhci_virt_ep *ep;
339
340 ep = &xhci->devs[slot_id]->eps[ep_index];
341
342 /* A ring has pending URBs if its TD list is not empty */
343 if (!(ep->ep_state & EP_HAS_STREAMS)) {
344 if (!(list_empty(&ep->ring->td_list)))
345 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
346 return;
347 }
348
349 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
350 stream_id++) {
351 struct xhci_stream_info *stream_info = ep->stream_info;
352 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
353 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
354 stream_id);
355 }
356}
357
358/*
359 * Find the segment that trb is in. Start searching in start_seg.
360 * If we must move past a segment that has a link TRB with a toggle cycle state
361 * bit set, then we will toggle the value pointed at by cycle_state.
362 */
363static struct xhci_segment *find_trb_seg(
364 struct xhci_segment *start_seg,
365 union xhci_trb *trb, int *cycle_state)
366{
367 struct xhci_segment *cur_seg = start_seg;
368 struct xhci_generic_trb *generic_trb;
369
370 while (cur_seg->trbs > trb ||
371 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
372 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
373 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
374 *cycle_state ^= 0x1;
375 cur_seg = cur_seg->next;
376 if (cur_seg == start_seg)
377 /* Looped over the entire list. Oops! */
378 return NULL;
379 }
380 return cur_seg;
381}
382
383
384static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
385 unsigned int slot_id, unsigned int ep_index,
386 unsigned int stream_id)
387{
388 struct xhci_virt_ep *ep;
389
390 ep = &xhci->devs[slot_id]->eps[ep_index];
391 /* Common case: no streams */
392 if (!(ep->ep_state & EP_HAS_STREAMS))
393 return ep->ring;
394
395 if (stream_id == 0) {
396 xhci_warn(xhci,
397 "WARN: Slot ID %u, ep index %u has streams, "
398 "but URB has no stream ID.\n",
399 slot_id, ep_index);
400 return NULL;
401 }
402
403 if (stream_id < ep->stream_info->num_streams)
404 return ep->stream_info->stream_rings[stream_id];
405
406 xhci_warn(xhci,
407 "WARN: Slot ID %u, ep index %u has "
408 "stream IDs 1 to %u allocated, "
409 "but stream ID %u is requested.\n",
410 slot_id, ep_index,
411 ep->stream_info->num_streams - 1,
412 stream_id);
413 return NULL;
414}
415
416/* Get the right ring for the given URB.
417 * If the endpoint supports streams, boundary check the URB's stream ID.
418 * If the endpoint doesn't support streams, return the singular endpoint ring.
419 */
420static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
421 struct urb *urb)
422{
423 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
424 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
425}
426
427/*
428 * Move the xHC's endpoint ring dequeue pointer past cur_td.
429 * Record the new state of the xHC's endpoint ring dequeue segment,
430 * dequeue pointer, and new consumer cycle state in state.
431 * Update our internal representation of the ring's dequeue pointer.
432 *
433 * We do this in three jumps:
434 * - First we update our new ring state to be the same as when the xHC stopped.
435 * - Then we traverse the ring to find the segment that contains
436 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
437 * any link TRBs with the toggle cycle bit set.
438 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
439 * if we've moved it past a link TRB with the toggle cycle bit set.
440 *
441 * Some of the uses of xhci_generic_trb are grotty, but if they're done
442 * with correct __le32 accesses they should work fine. Only users of this are
443 * in here.
444 */
445void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
446 unsigned int slot_id, unsigned int ep_index,
447 unsigned int stream_id, struct xhci_td *cur_td,
448 struct xhci_dequeue_state *state)
449{
450 struct xhci_virt_device *dev = xhci->devs[slot_id];
451 struct xhci_ring *ep_ring;
452 struct xhci_generic_trb *trb;
453 struct xhci_ep_ctx *ep_ctx;
454 dma_addr_t addr;
455
456 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
457 ep_index, stream_id);
458 if (!ep_ring) {
459 xhci_warn(xhci, "WARN can't find new dequeue state "
460 "for invalid stream ID %u.\n",
461 stream_id);
462 return;
463 }
464 state->new_cycle_state = 0;
465 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
466 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
467 dev->eps[ep_index].stopped_trb,
468 &state->new_cycle_state);
469 if (!state->new_deq_seg) {
470 WARN_ON(1);
471 return;
472 }
473
474 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
475 xhci_dbg(xhci, "Finding endpoint context\n");
476 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
477 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
478
479 state->new_deq_ptr = cur_td->last_trb;
480 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
481 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
482 state->new_deq_ptr,
483 &state->new_cycle_state);
484 if (!state->new_deq_seg) {
485 WARN_ON(1);
486 return;
487 }
488
489 trb = &state->new_deq_ptr->generic;
490 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
491 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
492 state->new_cycle_state ^= 0x1;
493 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
494
495 /*
496 * If there is only one segment in a ring, find_trb_seg()'s while loop
497 * will not run, and it will return before it has a chance to see if it
498 * needs to toggle the cycle bit. It can't tell if the stalled transfer
499 * ended just before the link TRB on a one-segment ring, or if the TD
500 * wrapped around the top of the ring, because it doesn't have the TD in
501 * question. Look for the one-segment case where stalled TRB's address
502 * is greater than the new dequeue pointer address.
503 */
504 if (ep_ring->first_seg == ep_ring->first_seg->next &&
505 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
506 state->new_cycle_state ^= 0x1;
507 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
508
509 /* Don't update the ring cycle state for the producer (us). */
510 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
511 state->new_deq_seg);
512 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
513 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
514 (unsigned long long) addr);
515}
516
517/* flip_cycle means flip the cycle bit of all but the first and last TRB.
518 * (The last TRB actually points to the ring enqueue pointer, which is not part
519 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
520 */
521static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
522 struct xhci_td *cur_td, bool flip_cycle)
523{
524 struct xhci_segment *cur_seg;
525 union xhci_trb *cur_trb;
526
527 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
528 true;
529 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
530 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
531 /* Unchain any chained Link TRBs, but
532 * leave the pointers intact.
533 */
534 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
535 /* Flip the cycle bit (link TRBs can't be the first
536 * or last TRB).
537 */
538 if (flip_cycle)
539 cur_trb->generic.field[3] ^=
540 cpu_to_le32(TRB_CYCLE);
541 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
542 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
543 "in seg %p (0x%llx dma)\n",
544 cur_trb,
545 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
546 cur_seg,
547 (unsigned long long)cur_seg->dma);
548 } else {
549 cur_trb->generic.field[0] = 0;
550 cur_trb->generic.field[1] = 0;
551 cur_trb->generic.field[2] = 0;
552 /* Preserve only the cycle bit of this TRB */
553 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
554 /* Flip the cycle bit except on the first or last TRB */
555 if (flip_cycle && cur_trb != cur_td->first_trb &&
556 cur_trb != cur_td->last_trb)
557 cur_trb->generic.field[3] ^=
558 cpu_to_le32(TRB_CYCLE);
559 cur_trb->generic.field[3] |= cpu_to_le32(
560 TRB_TYPE(TRB_TR_NOOP));
561 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
562 "in seg %p (0x%llx dma)\n",
563 cur_trb,
564 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
565 cur_seg,
566 (unsigned long long)cur_seg->dma);
567 }
568 if (cur_trb == cur_td->last_trb)
569 break;
570 }
571}
572
573static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
574 unsigned int ep_index, unsigned int stream_id,
575 struct xhci_segment *deq_seg,
576 union xhci_trb *deq_ptr, u32 cycle_state);
577
578void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
579 unsigned int slot_id, unsigned int ep_index,
580 unsigned int stream_id,
581 struct xhci_dequeue_state *deq_state)
582{
583 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
584
585 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
586 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
587 deq_state->new_deq_seg,
588 (unsigned long long)deq_state->new_deq_seg->dma,
589 deq_state->new_deq_ptr,
590 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
591 deq_state->new_cycle_state);
592 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
593 deq_state->new_deq_seg,
594 deq_state->new_deq_ptr,
595 (u32) deq_state->new_cycle_state);
596 /* Stop the TD queueing code from ringing the doorbell until
597 * this command completes. The HC won't set the dequeue pointer
598 * if the ring is running, and ringing the doorbell starts the
599 * ring running.
600 */
601 ep->ep_state |= SET_DEQ_PENDING;
602}
603
604static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
605 struct xhci_virt_ep *ep)
606{
607 ep->ep_state &= ~EP_HALT_PENDING;
608 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
609 * timer is running on another CPU, we don't decrement stop_cmds_pending
610 * (since we didn't successfully stop the watchdog timer).
611 */
612 if (del_timer(&ep->stop_cmd_timer))
613 ep->stop_cmds_pending--;
614}
615
616/* Must be called with xhci->lock held in interrupt context */
617static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
618 struct xhci_td *cur_td, int status, char *adjective)
619{
620 struct usb_hcd *hcd;
621 struct urb *urb;
622 struct urb_priv *urb_priv;
623
624 urb = cur_td->urb;
625 urb_priv = urb->hcpriv;
626 urb_priv->td_cnt++;
627 hcd = bus_to_hcd(urb->dev->bus);
628
629 /* Only giveback urb when this is the last td in urb */
630 if (urb_priv->td_cnt == urb_priv->length) {
631 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
632 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
633 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
634 if (xhci->quirks & XHCI_AMD_PLL_FIX)
635 usb_amd_quirk_pll_enable();
636 }
637 }
638 usb_hcd_unlink_urb_from_ep(hcd, urb);
639
640 spin_unlock(&xhci->lock);
641 usb_hcd_giveback_urb(hcd, urb, status);
642 xhci_urb_free_priv(xhci, urb_priv);
643 spin_lock(&xhci->lock);
644 }
645}
646
647/*
648 * When we get a command completion for a Stop Endpoint Command, we need to
649 * unlink any cancelled TDs from the ring. There are two ways to do that:
650 *
651 * 1. If the HW was in the middle of processing the TD that needs to be
652 * cancelled, then we must move the ring's dequeue pointer past the last TRB
653 * in the TD with a Set Dequeue Pointer Command.
654 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
655 * bit cleared) so that the HW will skip over them.
656 */
657static void handle_stopped_endpoint(struct xhci_hcd *xhci,
658 union xhci_trb *trb, struct xhci_event_cmd *event)
659{
660 unsigned int slot_id;
661 unsigned int ep_index;
662 struct xhci_virt_device *virt_dev;
663 struct xhci_ring *ep_ring;
664 struct xhci_virt_ep *ep;
665 struct list_head *entry;
666 struct xhci_td *cur_td = NULL;
667 struct xhci_td *last_unlinked_td;
668
669 struct xhci_dequeue_state deq_state;
670
671 if (unlikely(TRB_TO_SUSPEND_PORT(
672 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
673 slot_id = TRB_TO_SLOT_ID(
674 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
675 virt_dev = xhci->devs[slot_id];
676 if (virt_dev)
677 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
678 event);
679 else
680 xhci_warn(xhci, "Stop endpoint command "
681 "completion for disabled slot %u\n",
682 slot_id);
683 return;
684 }
685
686 memset(&deq_state, 0, sizeof(deq_state));
687 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
688 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
689 ep = &xhci->devs[slot_id]->eps[ep_index];
690
691 if (list_empty(&ep->cancelled_td_list)) {
692 xhci_stop_watchdog_timer_in_irq(xhci, ep);
693 ep->stopped_td = NULL;
694 ep->stopped_trb = NULL;
695 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
696 return;
697 }
698
699 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
700 * We have the xHCI lock, so nothing can modify this list until we drop
701 * it. We're also in the event handler, so we can't get re-interrupted
702 * if another Stop Endpoint command completes
703 */
704 list_for_each(entry, &ep->cancelled_td_list) {
705 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
706 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
707 cur_td->first_trb,
708 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
709 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
710 if (!ep_ring) {
711 /* This shouldn't happen unless a driver is mucking
712 * with the stream ID after submission. This will
713 * leave the TD on the hardware ring, and the hardware
714 * will try to execute it, and may access a buffer
715 * that has already been freed. In the best case, the
716 * hardware will execute it, and the event handler will
717 * ignore the completion event for that TD, since it was
718 * removed from the td_list for that endpoint. In
719 * short, don't muck with the stream ID after
720 * submission.
721 */
722 xhci_warn(xhci, "WARN Cancelled URB %p "
723 "has invalid stream ID %u.\n",
724 cur_td->urb,
725 cur_td->urb->stream_id);
726 goto remove_finished_td;
727 }
728 /*
729 * If we stopped on the TD we need to cancel, then we have to
730 * move the xHC endpoint ring dequeue pointer past this TD.
731 */
732 if (cur_td == ep->stopped_td)
733 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
734 cur_td->urb->stream_id,
735 cur_td, &deq_state);
736 else
737 td_to_noop(xhci, ep_ring, cur_td, false);
738remove_finished_td:
739 /*
740 * The event handler won't see a completion for this TD anymore,
741 * so remove it from the endpoint ring's TD list. Keep it in
742 * the cancelled TD list for URB completion later.
743 */
744 list_del_init(&cur_td->td_list);
745 }
746 last_unlinked_td = cur_td;
747 xhci_stop_watchdog_timer_in_irq(xhci, ep);
748
749 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
750 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
751 xhci_queue_new_dequeue_state(xhci,
752 slot_id, ep_index,
753 ep->stopped_td->urb->stream_id,
754 &deq_state);
755 xhci_ring_cmd_db(xhci);
756 } else {
757 /* Otherwise ring the doorbell(s) to restart queued transfers */
758 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
759 }
760 ep->stopped_td = NULL;
761 ep->stopped_trb = NULL;
762
763 /*
764 * Drop the lock and complete the URBs in the cancelled TD list.
765 * New TDs to be cancelled might be added to the end of the list before
766 * we can complete all the URBs for the TDs we already unlinked.
767 * So stop when we've completed the URB for the last TD we unlinked.
768 */
769 do {
770 cur_td = list_entry(ep->cancelled_td_list.next,
771 struct xhci_td, cancelled_td_list);
772 list_del_init(&cur_td->cancelled_td_list);
773
774 /* Clean up the cancelled URB */
775 /* Doesn't matter what we pass for status, since the core will
776 * just overwrite it (because the URB has been unlinked).
777 */
778 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
779
780 /* Stop processing the cancelled list if the watchdog timer is
781 * running.
782 */
783 if (xhci->xhc_state & XHCI_STATE_DYING)
784 return;
785 } while (cur_td != last_unlinked_td);
786
787 /* Return to the event handler with xhci->lock re-acquired */
788}
789
790/* Watchdog timer function for when a stop endpoint command fails to complete.
791 * In this case, we assume the host controller is broken or dying or dead. The
792 * host may still be completing some other events, so we have to be careful to
793 * let the event ring handler and the URB dequeueing/enqueueing functions know
794 * through xhci->state.
795 *
796 * The timer may also fire if the host takes a very long time to respond to the
797 * command, and the stop endpoint command completion handler cannot delete the
798 * timer before the timer function is called. Another endpoint cancellation may
799 * sneak in before the timer function can grab the lock, and that may queue
800 * another stop endpoint command and add the timer back. So we cannot use a
801 * simple flag to say whether there is a pending stop endpoint command for a
802 * particular endpoint.
803 *
804 * Instead we use a combination of that flag and a counter for the number of
805 * pending stop endpoint commands. If the timer is the tail end of the last
806 * stop endpoint command, and the endpoint's command is still pending, we assume
807 * the host is dying.
808 */
809void xhci_stop_endpoint_command_watchdog(unsigned long arg)
810{
811 struct xhci_hcd *xhci;
812 struct xhci_virt_ep *ep;
813 struct xhci_virt_ep *temp_ep;
814 struct xhci_ring *ring;
815 struct xhci_td *cur_td;
816 int ret, i, j;
817
818 ep = (struct xhci_virt_ep *) arg;
819 xhci = ep->xhci;
820
821 spin_lock(&xhci->lock);
822
823 ep->stop_cmds_pending--;
824 if (xhci->xhc_state & XHCI_STATE_DYING) {
825 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
826 "xHCI as DYING, exiting.\n");
827 spin_unlock(&xhci->lock);
828 return;
829 }
830 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
831 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
832 "exiting.\n");
833 spin_unlock(&xhci->lock);
834 return;
835 }
836
837 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
838 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
839 /* Oops, HC is dead or dying or at least not responding to the stop
840 * endpoint command.
841 */
842 xhci->xhc_state |= XHCI_STATE_DYING;
843 /* Disable interrupts from the host controller and start halting it */
844 xhci_quiesce(xhci);
845 spin_unlock(&xhci->lock);
846
847 ret = xhci_halt(xhci);
848
849 spin_lock(&xhci->lock);
850 if (ret < 0) {
851 /* This is bad; the host is not responding to commands and it's
852 * not allowing itself to be halted. At least interrupts are
853 * disabled. If we call usb_hc_died(), it will attempt to
854 * disconnect all device drivers under this host. Those
855 * disconnect() methods will wait for all URBs to be unlinked,
856 * so we must complete them.
857 */
858 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
859 xhci_warn(xhci, "Completing active URBs anyway.\n");
860 /* We could turn all TDs on the rings to no-ops. This won't
861 * help if the host has cached part of the ring, and is slow if
862 * we want to preserve the cycle bit. Skip it and hope the host
863 * doesn't touch the memory.
864 */
865 }
866 for (i = 0; i < MAX_HC_SLOTS; i++) {
867 if (!xhci->devs[i])
868 continue;
869 for (j = 0; j < 31; j++) {
870 temp_ep = &xhci->devs[i]->eps[j];
871 ring = temp_ep->ring;
872 if (!ring)
873 continue;
874 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
875 "ep index %u\n", i, j);
876 while (!list_empty(&ring->td_list)) {
877 cur_td = list_first_entry(&ring->td_list,
878 struct xhci_td,
879 td_list);
880 list_del_init(&cur_td->td_list);
881 if (!list_empty(&cur_td->cancelled_td_list))
882 list_del_init(&cur_td->cancelled_td_list);
883 xhci_giveback_urb_in_irq(xhci, cur_td,
884 -ESHUTDOWN, "killed");
885 }
886 while (!list_empty(&temp_ep->cancelled_td_list)) {
887 cur_td = list_first_entry(
888 &temp_ep->cancelled_td_list,
889 struct xhci_td,
890 cancelled_td_list);
891 list_del_init(&cur_td->cancelled_td_list);
892 xhci_giveback_urb_in_irq(xhci, cur_td,
893 -ESHUTDOWN, "killed");
894 }
895 }
896 }
897 spin_unlock(&xhci->lock);
898 xhci_dbg(xhci, "Calling usb_hc_died()\n");
899 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
900 xhci_dbg(xhci, "xHCI host controller is dead.\n");
901}
902
903/*
904 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
905 * we need to clear the set deq pending flag in the endpoint ring state, so that
906 * the TD queueing code can ring the doorbell again. We also need to ring the
907 * endpoint doorbell to restart the ring, but only if there aren't more
908 * cancellations pending.
909 */
910static void handle_set_deq_completion(struct xhci_hcd *xhci,
911 struct xhci_event_cmd *event,
912 union xhci_trb *trb)
913{
914 unsigned int slot_id;
915 unsigned int ep_index;
916 unsigned int stream_id;
917 struct xhci_ring *ep_ring;
918 struct xhci_virt_device *dev;
919 struct xhci_ep_ctx *ep_ctx;
920 struct xhci_slot_ctx *slot_ctx;
921
922 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
923 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
924 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
925 dev = xhci->devs[slot_id];
926
927 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
928 if (!ep_ring) {
929 xhci_warn(xhci, "WARN Set TR deq ptr command for "
930 "freed stream ID %u\n",
931 stream_id);
932 /* XXX: Harmless??? */
933 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
934 return;
935 }
936
937 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
938 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
939
940 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
941 unsigned int ep_state;
942 unsigned int slot_state;
943
944 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
945 case COMP_TRB_ERR:
946 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
947 "of stream ID configuration\n");
948 break;
949 case COMP_CTX_STATE:
950 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
951 "to incorrect slot or ep state.\n");
952 ep_state = le32_to_cpu(ep_ctx->ep_info);
953 ep_state &= EP_STATE_MASK;
954 slot_state = le32_to_cpu(slot_ctx->dev_state);
955 slot_state = GET_SLOT_STATE(slot_state);
956 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
957 slot_state, ep_state);
958 break;
959 case COMP_EBADSLT:
960 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
961 "slot %u was not enabled.\n", slot_id);
962 break;
963 default:
964 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
965 "completion code of %u.\n",
966 GET_COMP_CODE(le32_to_cpu(event->status)));
967 break;
968 }
969 /* OK what do we do now? The endpoint state is hosed, and we
970 * should never get to this point if the synchronization between
971 * queueing, and endpoint state are correct. This might happen
972 * if the device gets disconnected after we've finished
973 * cancelling URBs, which might not be an error...
974 */
975 } else {
976 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
977 le64_to_cpu(ep_ctx->deq));
978 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
979 dev->eps[ep_index].queued_deq_ptr) ==
980 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
981 /* Update the ring's dequeue segment and dequeue pointer
982 * to reflect the new position.
983 */
984 ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
985 ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
986 } else {
987 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
988 "Ptr command & xHCI internal state.\n");
989 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
990 dev->eps[ep_index].queued_deq_seg,
991 dev->eps[ep_index].queued_deq_ptr);
992 }
993 }
994
995 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
996 dev->eps[ep_index].queued_deq_seg = NULL;
997 dev->eps[ep_index].queued_deq_ptr = NULL;
998 /* Restart any rings with pending URBs */
999 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1000}
1001
1002static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1003 struct xhci_event_cmd *event,
1004 union xhci_trb *trb)
1005{
1006 int slot_id;
1007 unsigned int ep_index;
1008
1009 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1010 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1011 /* This command will only fail if the endpoint wasn't halted,
1012 * but we don't care.
1013 */
1014 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1015 GET_COMP_CODE(le32_to_cpu(event->status)));
1016
1017 /* HW with the reset endpoint quirk needs to have a configure endpoint
1018 * command complete before the endpoint can be used. Queue that here
1019 * because the HW can't handle two commands being queued in a row.
1020 */
1021 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1022 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1023 xhci_queue_configure_endpoint(xhci,
1024 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1025 false);
1026 xhci_ring_cmd_db(xhci);
1027 } else {
1028 /* Clear our internal halted state and restart the ring(s) */
1029 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1030 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1031 }
1032}
1033
1034/* Check to see if a command in the device's command queue matches this one.
1035 * Signal the completion or free the command, and return 1. Return 0 if the
1036 * completed command isn't at the head of the command list.
1037 */
1038static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1039 struct xhci_virt_device *virt_dev,
1040 struct xhci_event_cmd *event)
1041{
1042 struct xhci_command *command;
1043
1044 if (list_empty(&virt_dev->cmd_list))
1045 return 0;
1046
1047 command = list_entry(virt_dev->cmd_list.next,
1048 struct xhci_command, cmd_list);
1049 if (xhci->cmd_ring->dequeue != command->command_trb)
1050 return 0;
1051
1052 command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1053 list_del(&command->cmd_list);
1054 if (command->completion)
1055 complete(command->completion);
1056 else
1057 xhci_free_command(xhci, command);
1058 return 1;
1059}
1060
1061static void handle_cmd_completion(struct xhci_hcd *xhci,
1062 struct xhci_event_cmd *event)
1063{
1064 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1065 u64 cmd_dma;
1066 dma_addr_t cmd_dequeue_dma;
1067 struct xhci_input_control_ctx *ctrl_ctx;
1068 struct xhci_virt_device *virt_dev;
1069 unsigned int ep_index;
1070 struct xhci_ring *ep_ring;
1071 unsigned int ep_state;
1072
1073 cmd_dma = le64_to_cpu(event->cmd_trb);
1074 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1075 xhci->cmd_ring->dequeue);
1076 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1077 if (cmd_dequeue_dma == 0) {
1078 xhci->error_bitmask |= 1 << 4;
1079 return;
1080 }
1081 /* Does the DMA address match our internal dequeue pointer address? */
1082 if (cmd_dma != (u64) cmd_dequeue_dma) {
1083 xhci->error_bitmask |= 1 << 5;
1084 return;
1085 }
1086 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1087 & TRB_TYPE_BITMASK) {
1088 case TRB_TYPE(TRB_ENABLE_SLOT):
1089 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1090 xhci->slot_id = slot_id;
1091 else
1092 xhci->slot_id = 0;
1093 complete(&xhci->addr_dev);
1094 break;
1095 case TRB_TYPE(TRB_DISABLE_SLOT):
1096 if (xhci->devs[slot_id]) {
1097 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1098 /* Delete default control endpoint resources */
1099 xhci_free_device_endpoint_resources(xhci,
1100 xhci->devs[slot_id], true);
1101 xhci_free_virt_device(xhci, slot_id);
1102 }
1103 break;
1104 case TRB_TYPE(TRB_CONFIG_EP):
1105 virt_dev = xhci->devs[slot_id];
1106 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1107 break;
1108 /*
1109 * Configure endpoint commands can come from the USB core
1110 * configuration or alt setting changes, or because the HW
1111 * needed an extra configure endpoint command after a reset
1112 * endpoint command or streams were being configured.
1113 * If the command was for a halted endpoint, the xHCI driver
1114 * is not waiting on the configure endpoint command.
1115 */
1116 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1117 virt_dev->in_ctx);
1118 /* Input ctx add_flags are the endpoint index plus one */
1119 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1120 /* A usb_set_interface() call directly after clearing a halted
1121 * condition may race on this quirky hardware. Not worth
1122 * worrying about, since this is prototype hardware. Not sure
1123 * if this will work for streams, but streams support was
1124 * untested on this prototype.
1125 */
1126 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1127 ep_index != (unsigned int) -1 &&
1128 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1129 le32_to_cpu(ctrl_ctx->drop_flags)) {
1130 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1131 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1132 if (!(ep_state & EP_HALTED))
1133 goto bandwidth_change;
1134 xhci_dbg(xhci, "Completed config ep cmd - "
1135 "last ep index = %d, state = %d\n",
1136 ep_index, ep_state);
1137 /* Clear internal halted state and restart ring(s) */
1138 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1139 ~EP_HALTED;
1140 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1141 break;
1142 }
1143bandwidth_change:
1144 xhci_dbg(xhci, "Completed config ep cmd\n");
1145 xhci->devs[slot_id]->cmd_status =
1146 GET_COMP_CODE(le32_to_cpu(event->status));
1147 complete(&xhci->devs[slot_id]->cmd_completion);
1148 break;
1149 case TRB_TYPE(TRB_EVAL_CONTEXT):
1150 virt_dev = xhci->devs[slot_id];
1151 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1152 break;
1153 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1154 complete(&xhci->devs[slot_id]->cmd_completion);
1155 break;
1156 case TRB_TYPE(TRB_ADDR_DEV):
1157 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1158 complete(&xhci->addr_dev);
1159 break;
1160 case TRB_TYPE(TRB_STOP_RING):
1161 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1162 break;
1163 case TRB_TYPE(TRB_SET_DEQ):
1164 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1165 break;
1166 case TRB_TYPE(TRB_CMD_NOOP):
1167 break;
1168 case TRB_TYPE(TRB_RESET_EP):
1169 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1170 break;
1171 case TRB_TYPE(TRB_RESET_DEV):
1172 xhci_dbg(xhci, "Completed reset device command.\n");
1173 slot_id = TRB_TO_SLOT_ID(
1174 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1175 virt_dev = xhci->devs[slot_id];
1176 if (virt_dev)
1177 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1178 else
1179 xhci_warn(xhci, "Reset device command completion "
1180 "for disabled slot %u\n", slot_id);
1181 break;
1182 case TRB_TYPE(TRB_NEC_GET_FW):
1183 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1184 xhci->error_bitmask |= 1 << 6;
1185 break;
1186 }
1187 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1188 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1189 NEC_FW_MINOR(le32_to_cpu(event->status)));
1190 break;
1191 default:
1192 /* Skip over unknown commands on the event ring */
1193 xhci->error_bitmask |= 1 << 6;
1194 break;
1195 }
1196 inc_deq(xhci, xhci->cmd_ring, false);
1197}
1198
1199static void handle_vendor_event(struct xhci_hcd *xhci,
1200 union xhci_trb *event)
1201{
1202 u32 trb_type;
1203
1204 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1205 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1206 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1207 handle_cmd_completion(xhci, &event->event_cmd);
1208}
1209
1210/* @port_id: the one-based port ID from the hardware (indexed from array of all
1211 * port registers -- USB 3.0 and USB 2.0).
1212 *
1213 * Returns a zero-based port number, which is suitable for indexing into each of
1214 * the split roothubs' port arrays and bus state arrays.
1215 */
1216static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1217 struct xhci_hcd *xhci, u32 port_id)
1218{
1219 unsigned int i;
1220 unsigned int num_similar_speed_ports = 0;
1221
1222 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1223 * and usb2_ports are 0-based indexes. Count the number of similar
1224 * speed ports, up to 1 port before this port.
1225 */
1226 for (i = 0; i < (port_id - 1); i++) {
1227 u8 port_speed = xhci->port_array[i];
1228
1229 /*
1230 * Skip ports that don't have known speeds, or have duplicate
1231 * Extended Capabilities port speed entries.
1232 */
1233 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1234 continue;
1235
1236 /*
1237 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1238 * 1.1 ports are under the USB 2.0 hub. If the port speed
1239 * matches the device speed, it's a similar speed port.
1240 */
1241 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1242 num_similar_speed_ports++;
1243 }
1244 return num_similar_speed_ports;
1245}
1246
1247static void handle_port_status(struct xhci_hcd *xhci,
1248 union xhci_trb *event)
1249{
1250 struct usb_hcd *hcd;
1251 u32 port_id;
1252 u32 temp, temp1;
1253 int max_ports;
1254 int slot_id;
1255 unsigned int faked_port_index;
1256 u8 major_revision;
1257 struct xhci_bus_state *bus_state;
1258 __le32 __iomem **port_array;
1259 bool bogus_port_status = false;
1260
1261 /* Port status change events always have a successful completion code */
1262 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1263 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1264 xhci->error_bitmask |= 1 << 8;
1265 }
1266 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1267 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1268
1269 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1270 if ((port_id <= 0) || (port_id > max_ports)) {
1271 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1272 bogus_port_status = true;
1273 goto cleanup;
1274 }
1275
1276 /* Figure out which usb_hcd this port is attached to:
1277 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1278 */
1279 major_revision = xhci->port_array[port_id - 1];
1280 if (major_revision == 0) {
1281 xhci_warn(xhci, "Event for port %u not in "
1282 "Extended Capabilities, ignoring.\n",
1283 port_id);
1284 bogus_port_status = true;
1285 goto cleanup;
1286 }
1287 if (major_revision == DUPLICATE_ENTRY) {
1288 xhci_warn(xhci, "Event for port %u duplicated in"
1289 "Extended Capabilities, ignoring.\n",
1290 port_id);
1291 bogus_port_status = true;
1292 goto cleanup;
1293 }
1294
1295 /*
1296 * Hardware port IDs reported by a Port Status Change Event include USB
1297 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1298 * resume event, but we first need to translate the hardware port ID
1299 * into the index into the ports on the correct split roothub, and the
1300 * correct bus_state structure.
1301 */
1302 /* Find the right roothub. */
1303 hcd = xhci_to_hcd(xhci);
1304 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1305 hcd = xhci->shared_hcd;
1306 bus_state = &xhci->bus_state[hcd_index(hcd)];
1307 if (hcd->speed == HCD_USB3)
1308 port_array = xhci->usb3_ports;
1309 else
1310 port_array = xhci->usb2_ports;
1311 /* Find the faked port hub number */
1312 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1313 port_id);
1314
1315 temp = xhci_readl(xhci, port_array[faked_port_index]);
1316 if (hcd->state == HC_STATE_SUSPENDED) {
1317 xhci_dbg(xhci, "resume root hub\n");
1318 usb_hcd_resume_root_hub(hcd);
1319 }
1320
1321 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1322 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1323
1324 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1325 if (!(temp1 & CMD_RUN)) {
1326 xhci_warn(xhci, "xHC is not running.\n");
1327 goto cleanup;
1328 }
1329
1330 if (DEV_SUPERSPEED(temp)) {
1331 xhci_dbg(xhci, "resume SS port %d\n", port_id);
1332 temp = xhci_port_state_to_neutral(temp);
1333 temp &= ~PORT_PLS_MASK;
1334 temp |= PORT_LINK_STROBE | XDEV_U0;
1335 xhci_writel(xhci, temp, port_array[faked_port_index]);
1336 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1337 faked_port_index);
1338 if (!slot_id) {
1339 xhci_dbg(xhci, "slot_id is zero\n");
1340 goto cleanup;
1341 }
1342 xhci_ring_device(xhci, slot_id);
1343 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1344 /* Clear PORT_PLC */
1345 temp = xhci_readl(xhci, port_array[faked_port_index]);
1346 temp = xhci_port_state_to_neutral(temp);
1347 temp |= PORT_PLC;
1348 xhci_writel(xhci, temp, port_array[faked_port_index]);
1349 } else {
1350 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1351 bus_state->resume_done[faked_port_index] = jiffies +
1352 msecs_to_jiffies(20);
1353 mod_timer(&hcd->rh_timer,
1354 bus_state->resume_done[faked_port_index]);
1355 /* Do the rest in GetPortStatus */
1356 }
1357 }
1358
1359cleanup:
1360 /* Update event ring dequeue pointer before dropping the lock */
1361 inc_deq(xhci, xhci->event_ring, true);
1362
1363 /* Don't make the USB core poll the roothub if we got a bad port status
1364 * change event. Besides, at that point we can't tell which roothub
1365 * (USB 2.0 or USB 3.0) to kick.
1366 */
1367 if (bogus_port_status)
1368 return;
1369
1370 spin_unlock(&xhci->lock);
1371 /* Pass this up to the core */
1372 usb_hcd_poll_rh_status(hcd);
1373 spin_lock(&xhci->lock);
1374}
1375
1376/*
1377 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1378 * at end_trb, which may be in another segment. If the suspect DMA address is a
1379 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1380 * returns 0.
1381 */
1382struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1383 union xhci_trb *start_trb,
1384 union xhci_trb *end_trb,
1385 dma_addr_t suspect_dma)
1386{
1387 dma_addr_t start_dma;
1388 dma_addr_t end_seg_dma;
1389 dma_addr_t end_trb_dma;
1390 struct xhci_segment *cur_seg;
1391
1392 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1393 cur_seg = start_seg;
1394
1395 do {
1396 if (start_dma == 0)
1397 return NULL;
1398 /* We may get an event for a Link TRB in the middle of a TD */
1399 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1400 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1401 /* If the end TRB isn't in this segment, this is set to 0 */
1402 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1403
1404 if (end_trb_dma > 0) {
1405 /* The end TRB is in this segment, so suspect should be here */
1406 if (start_dma <= end_trb_dma) {
1407 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1408 return cur_seg;
1409 } else {
1410 /* Case for one segment with
1411 * a TD wrapped around to the top
1412 */
1413 if ((suspect_dma >= start_dma &&
1414 suspect_dma <= end_seg_dma) ||
1415 (suspect_dma >= cur_seg->dma &&
1416 suspect_dma <= end_trb_dma))
1417 return cur_seg;
1418 }
1419 return NULL;
1420 } else {
1421 /* Might still be somewhere in this segment */
1422 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1423 return cur_seg;
1424 }
1425 cur_seg = cur_seg->next;
1426 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1427 } while (cur_seg != start_seg);
1428
1429 return NULL;
1430}
1431
1432static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1433 unsigned int slot_id, unsigned int ep_index,
1434 unsigned int stream_id,
1435 struct xhci_td *td, union xhci_trb *event_trb)
1436{
1437 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1438 ep->ep_state |= EP_HALTED;
1439 ep->stopped_td = td;
1440 ep->stopped_trb = event_trb;
1441 ep->stopped_stream = stream_id;
1442
1443 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1444 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1445
1446 ep->stopped_td = NULL;
1447 ep->stopped_trb = NULL;
1448 ep->stopped_stream = 0;
1449
1450 xhci_ring_cmd_db(xhci);
1451}
1452
1453/* Check if an error has halted the endpoint ring. The class driver will
1454 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1455 * However, a babble and other errors also halt the endpoint ring, and the class
1456 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1457 * Ring Dequeue Pointer command manually.
1458 */
1459static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1460 struct xhci_ep_ctx *ep_ctx,
1461 unsigned int trb_comp_code)
1462{
1463 /* TRB completion codes that may require a manual halt cleanup */
1464 if (trb_comp_code == COMP_TX_ERR ||
1465 trb_comp_code == COMP_BABBLE ||
1466 trb_comp_code == COMP_SPLIT_ERR)
1467 /* The 0.96 spec says a babbling control endpoint
1468 * is not halted. The 0.96 spec says it is. Some HW
1469 * claims to be 0.95 compliant, but it halts the control
1470 * endpoint anyway. Check if a babble halted the
1471 * endpoint.
1472 */
1473 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1474 cpu_to_le32(EP_STATE_HALTED))
1475 return 1;
1476
1477 return 0;
1478}
1479
1480int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1481{
1482 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1483 /* Vendor defined "informational" completion code,
1484 * treat as not-an-error.
1485 */
1486 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1487 trb_comp_code);
1488 xhci_dbg(xhci, "Treating code as success.\n");
1489 return 1;
1490 }
1491 return 0;
1492}
1493
1494/*
1495 * Finish the td processing, remove the td from td list;
1496 * Return 1 if the urb can be given back.
1497 */
1498static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1499 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1500 struct xhci_virt_ep *ep, int *status, bool skip)
1501{
1502 struct xhci_virt_device *xdev;
1503 struct xhci_ring *ep_ring;
1504 unsigned int slot_id;
1505 int ep_index;
1506 struct urb *urb = NULL;
1507 struct xhci_ep_ctx *ep_ctx;
1508 int ret = 0;
1509 struct urb_priv *urb_priv;
1510 u32 trb_comp_code;
1511
1512 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1513 xdev = xhci->devs[slot_id];
1514 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1515 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1516 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1517 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1518
1519 if (skip)
1520 goto td_cleanup;
1521
1522 if (trb_comp_code == COMP_STOP_INVAL ||
1523 trb_comp_code == COMP_STOP) {
1524 /* The Endpoint Stop Command completion will take care of any
1525 * stopped TDs. A stopped TD may be restarted, so don't update
1526 * the ring dequeue pointer or take this TD off any lists yet.
1527 */
1528 ep->stopped_td = td;
1529 ep->stopped_trb = event_trb;
1530 return 0;
1531 } else {
1532 if (trb_comp_code == COMP_STALL) {
1533 /* The transfer is completed from the driver's
1534 * perspective, but we need to issue a set dequeue
1535 * command for this stalled endpoint to move the dequeue
1536 * pointer past the TD. We can't do that here because
1537 * the halt condition must be cleared first. Let the
1538 * USB class driver clear the stall later.
1539 */
1540 ep->stopped_td = td;
1541 ep->stopped_trb = event_trb;
1542 ep->stopped_stream = ep_ring->stream_id;
1543 } else if (xhci_requires_manual_halt_cleanup(xhci,
1544 ep_ctx, trb_comp_code)) {
1545 /* Other types of errors halt the endpoint, but the
1546 * class driver doesn't call usb_reset_endpoint() unless
1547 * the error is -EPIPE. Clear the halted status in the
1548 * xHCI hardware manually.
1549 */
1550 xhci_cleanup_halted_endpoint(xhci,
1551 slot_id, ep_index, ep_ring->stream_id,
1552 td, event_trb);
1553 } else {
1554 /* Update ring dequeue pointer */
1555 while (ep_ring->dequeue != td->last_trb)
1556 inc_deq(xhci, ep_ring, false);
1557 inc_deq(xhci, ep_ring, false);
1558 }
1559
1560td_cleanup:
1561 /* Clean up the endpoint's TD list */
1562 urb = td->urb;
1563 urb_priv = urb->hcpriv;
1564
1565 /* Do one last check of the actual transfer length.
1566 * If the host controller said we transferred more data than
1567 * the buffer length, urb->actual_length will be a very big
1568 * number (since it's unsigned). Play it safe and say we didn't
1569 * transfer anything.
1570 */
1571 if (urb->actual_length > urb->transfer_buffer_length) {
1572 xhci_warn(xhci, "URB transfer length is wrong, "
1573 "xHC issue? req. len = %u, "
1574 "act. len = %u\n",
1575 urb->transfer_buffer_length,
1576 urb->actual_length);
1577 urb->actual_length = 0;
1578 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1579 *status = -EREMOTEIO;
1580 else
1581 *status = 0;
1582 }
1583 list_del_init(&td->td_list);
1584 /* Was this TD slated to be cancelled but completed anyway? */
1585 if (!list_empty(&td->cancelled_td_list))
1586 list_del_init(&td->cancelled_td_list);
1587
1588 urb_priv->td_cnt++;
1589 /* Giveback the urb when all the tds are completed */
1590 if (urb_priv->td_cnt == urb_priv->length) {
1591 ret = 1;
1592 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1593 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1594 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1595 == 0) {
1596 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1597 usb_amd_quirk_pll_enable();
1598 }
1599 }
1600 }
1601 }
1602
1603 return ret;
1604}
1605
1606/*
1607 * Process control tds, update urb status and actual_length.
1608 */
1609static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1610 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1611 struct xhci_virt_ep *ep, int *status)
1612{
1613 struct xhci_virt_device *xdev;
1614 struct xhci_ring *ep_ring;
1615 unsigned int slot_id;
1616 int ep_index;
1617 struct xhci_ep_ctx *ep_ctx;
1618 u32 trb_comp_code;
1619
1620 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1621 xdev = xhci->devs[slot_id];
1622 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1623 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1624 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1625 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1626
1627 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1628 switch (trb_comp_code) {
1629 case COMP_SUCCESS:
1630 if (event_trb == ep_ring->dequeue) {
1631 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1632 "without IOC set??\n");
1633 *status = -ESHUTDOWN;
1634 } else if (event_trb != td->last_trb) {
1635 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1636 "without IOC set??\n");
1637 *status = -ESHUTDOWN;
1638 } else {
1639 *status = 0;
1640 }
1641 break;
1642 case COMP_SHORT_TX:
1643 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1644 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1645 *status = -EREMOTEIO;
1646 else
1647 *status = 0;
1648 break;
1649 case COMP_STOP_INVAL:
1650 case COMP_STOP:
1651 return finish_td(xhci, td, event_trb, event, ep, status, false);
1652 default:
1653 if (!xhci_requires_manual_halt_cleanup(xhci,
1654 ep_ctx, trb_comp_code))
1655 break;
1656 xhci_dbg(xhci, "TRB error code %u, "
1657 "halted endpoint index = %u\n",
1658 trb_comp_code, ep_index);
1659 /* else fall through */
1660 case COMP_STALL:
1661 /* Did we transfer part of the data (middle) phase? */
1662 if (event_trb != ep_ring->dequeue &&
1663 event_trb != td->last_trb)
1664 td->urb->actual_length =
1665 td->urb->transfer_buffer_length
1666 - TRB_LEN(le32_to_cpu(event->transfer_len));
1667 else
1668 td->urb->actual_length = 0;
1669
1670 xhci_cleanup_halted_endpoint(xhci,
1671 slot_id, ep_index, 0, td, event_trb);
1672 return finish_td(xhci, td, event_trb, event, ep, status, true);
1673 }
1674 /*
1675 * Did we transfer any data, despite the errors that might have
1676 * happened? I.e. did we get past the setup stage?
1677 */
1678 if (event_trb != ep_ring->dequeue) {
1679 /* The event was for the status stage */
1680 if (event_trb == td->last_trb) {
1681 if (td->urb->actual_length != 0) {
1682 /* Don't overwrite a previously set error code
1683 */
1684 if ((*status == -EINPROGRESS || *status == 0) &&
1685 (td->urb->transfer_flags
1686 & URB_SHORT_NOT_OK))
1687 /* Did we already see a short data
1688 * stage? */
1689 *status = -EREMOTEIO;
1690 } else {
1691 td->urb->actual_length =
1692 td->urb->transfer_buffer_length;
1693 }
1694 } else {
1695 /* Maybe the event was for the data stage? */
1696 td->urb->actual_length =
1697 td->urb->transfer_buffer_length -
1698 TRB_LEN(le32_to_cpu(event->transfer_len));
1699 xhci_dbg(xhci, "Waiting for status "
1700 "stage event\n");
1701 return 0;
1702 }
1703 }
1704
1705 return finish_td(xhci, td, event_trb, event, ep, status, false);
1706}
1707
1708/*
1709 * Process isochronous tds, update urb packet status and actual_length.
1710 */
1711static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1712 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1713 struct xhci_virt_ep *ep, int *status)
1714{
1715 struct xhci_ring *ep_ring;
1716 struct urb_priv *urb_priv;
1717 int idx;
1718 int len = 0;
1719 union xhci_trb *cur_trb;
1720 struct xhci_segment *cur_seg;
1721 struct usb_iso_packet_descriptor *frame;
1722 u32 trb_comp_code;
1723 bool skip_td = false;
1724
1725 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1726 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1727 urb_priv = td->urb->hcpriv;
1728 idx = urb_priv->td_cnt;
1729 frame = &td->urb->iso_frame_desc[idx];
1730
1731 /* handle completion code */
1732 switch (trb_comp_code) {
1733 case COMP_SUCCESS:
1734 frame->status = 0;
1735 break;
1736 case COMP_SHORT_TX:
1737 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1738 -EREMOTEIO : 0;
1739 break;
1740 case COMP_BW_OVER:
1741 frame->status = -ECOMM;
1742 skip_td = true;
1743 break;
1744 case COMP_BUFF_OVER:
1745 case COMP_BABBLE:
1746 frame->status = -EOVERFLOW;
1747 skip_td = true;
1748 break;
1749 case COMP_DEV_ERR:
1750 case COMP_STALL:
1751 frame->status = -EPROTO;
1752 skip_td = true;
1753 break;
1754 case COMP_STOP:
1755 case COMP_STOP_INVAL:
1756 break;
1757 default:
1758 frame->status = -1;
1759 break;
1760 }
1761
1762 if (trb_comp_code == COMP_SUCCESS || skip_td) {
1763 frame->actual_length = frame->length;
1764 td->urb->actual_length += frame->length;
1765 } else {
1766 for (cur_trb = ep_ring->dequeue,
1767 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1768 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1769 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1770 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1771 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1772 }
1773 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1774 TRB_LEN(le32_to_cpu(event->transfer_len));
1775
1776 if (trb_comp_code != COMP_STOP_INVAL) {
1777 frame->actual_length = len;
1778 td->urb->actual_length += len;
1779 }
1780 }
1781
1782 return finish_td(xhci, td, event_trb, event, ep, status, false);
1783}
1784
1785static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1786 struct xhci_transfer_event *event,
1787 struct xhci_virt_ep *ep, int *status)
1788{
1789 struct xhci_ring *ep_ring;
1790 struct urb_priv *urb_priv;
1791 struct usb_iso_packet_descriptor *frame;
1792 int idx;
1793
1794 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1795 urb_priv = td->urb->hcpriv;
1796 idx = urb_priv->td_cnt;
1797 frame = &td->urb->iso_frame_desc[idx];
1798
1799 /* The transfer is partly done. */
1800 frame->status = -EXDEV;
1801
1802 /* calc actual length */
1803 frame->actual_length = 0;
1804
1805 /* Update ring dequeue pointer */
1806 while (ep_ring->dequeue != td->last_trb)
1807 inc_deq(xhci, ep_ring, false);
1808 inc_deq(xhci, ep_ring, false);
1809
1810 return finish_td(xhci, td, NULL, event, ep, status, true);
1811}
1812
1813/*
1814 * Process bulk and interrupt tds, update urb status and actual_length.
1815 */
1816static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1817 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1818 struct xhci_virt_ep *ep, int *status)
1819{
1820 struct xhci_ring *ep_ring;
1821 union xhci_trb *cur_trb;
1822 struct xhci_segment *cur_seg;
1823 u32 trb_comp_code;
1824
1825 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1826 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1827
1828 switch (trb_comp_code) {
1829 case COMP_SUCCESS:
1830 /* Double check that the HW transferred everything. */
1831 if (event_trb != td->last_trb) {
1832 xhci_warn(xhci, "WARN Successful completion "
1833 "on short TX\n");
1834 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1835 *status = -EREMOTEIO;
1836 else
1837 *status = 0;
1838 } else {
1839 *status = 0;
1840 }
1841 break;
1842 case COMP_SHORT_TX:
1843 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1844 *status = -EREMOTEIO;
1845 else
1846 *status = 0;
1847 break;
1848 default:
1849 /* Others already handled above */
1850 break;
1851 }
1852 if (trb_comp_code == COMP_SHORT_TX)
1853 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1854 "%d bytes untransferred\n",
1855 td->urb->ep->desc.bEndpointAddress,
1856 td->urb->transfer_buffer_length,
1857 TRB_LEN(le32_to_cpu(event->transfer_len)));
1858 /* Fast path - was this the last TRB in the TD for this URB? */
1859 if (event_trb == td->last_trb) {
1860 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1861 td->urb->actual_length =
1862 td->urb->transfer_buffer_length -
1863 TRB_LEN(le32_to_cpu(event->transfer_len));
1864 if (td->urb->transfer_buffer_length <
1865 td->urb->actual_length) {
1866 xhci_warn(xhci, "HC gave bad length "
1867 "of %d bytes left\n",
1868 TRB_LEN(le32_to_cpu(event->transfer_len)));
1869 td->urb->actual_length = 0;
1870 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1871 *status = -EREMOTEIO;
1872 else
1873 *status = 0;
1874 }
1875 /* Don't overwrite a previously set error code */
1876 if (*status == -EINPROGRESS) {
1877 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1878 *status = -EREMOTEIO;
1879 else
1880 *status = 0;
1881 }
1882 } else {
1883 td->urb->actual_length =
1884 td->urb->transfer_buffer_length;
1885 /* Ignore a short packet completion if the
1886 * untransferred length was zero.
1887 */
1888 if (*status == -EREMOTEIO)
1889 *status = 0;
1890 }
1891 } else {
1892 /* Slow path - walk the list, starting from the dequeue
1893 * pointer, to get the actual length transferred.
1894 */
1895 td->urb->actual_length = 0;
1896 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1897 cur_trb != event_trb;
1898 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1899 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1900 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1901 td->urb->actual_length +=
1902 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1903 }
1904 /* If the ring didn't stop on a Link or No-op TRB, add
1905 * in the actual bytes transferred from the Normal TRB
1906 */
1907 if (trb_comp_code != COMP_STOP_INVAL)
1908 td->urb->actual_length +=
1909 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1910 TRB_LEN(le32_to_cpu(event->transfer_len));
1911 }
1912
1913 return finish_td(xhci, td, event_trb, event, ep, status, false);
1914}
1915
1916/*
1917 * If this function returns an error condition, it means it got a Transfer
1918 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1919 * At this point, the host controller is probably hosed and should be reset.
1920 */
1921static int handle_tx_event(struct xhci_hcd *xhci,
1922 struct xhci_transfer_event *event)
1923{
1924 struct xhci_virt_device *xdev;
1925 struct xhci_virt_ep *ep;
1926 struct xhci_ring *ep_ring;
1927 unsigned int slot_id;
1928 int ep_index;
1929 struct xhci_td *td = NULL;
1930 dma_addr_t event_dma;
1931 struct xhci_segment *event_seg;
1932 union xhci_trb *event_trb;
1933 struct urb *urb = NULL;
1934 int status = -EINPROGRESS;
1935 struct urb_priv *urb_priv;
1936 struct xhci_ep_ctx *ep_ctx;
1937 struct list_head *tmp;
1938 u32 trb_comp_code;
1939 int ret = 0;
1940 int td_num = 0;
1941
1942 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1943 xdev = xhci->devs[slot_id];
1944 if (!xdev) {
1945 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1946 return -ENODEV;
1947 }
1948
1949 /* Endpoint ID is 1 based, our index is zero based */
1950 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1951 ep = &xdev->eps[ep_index];
1952 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1953 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1954 if (!ep_ring ||
1955 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
1956 EP_STATE_DISABLED) {
1957 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1958 "or incorrect stream ring\n");
1959 return -ENODEV;
1960 }
1961
1962 /* Count current td numbers if ep->skip is set */
1963 if (ep->skip) {
1964 list_for_each(tmp, &ep_ring->td_list)
1965 td_num++;
1966 }
1967
1968 event_dma = le64_to_cpu(event->buffer);
1969 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1970 /* Look for common error cases */
1971 switch (trb_comp_code) {
1972 /* Skip codes that require special handling depending on
1973 * transfer type
1974 */
1975 case COMP_SUCCESS:
1976 case COMP_SHORT_TX:
1977 break;
1978 case COMP_STOP:
1979 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1980 break;
1981 case COMP_STOP_INVAL:
1982 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1983 break;
1984 case COMP_STALL:
1985 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1986 ep->ep_state |= EP_HALTED;
1987 status = -EPIPE;
1988 break;
1989 case COMP_TRB_ERR:
1990 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1991 status = -EILSEQ;
1992 break;
1993 case COMP_SPLIT_ERR:
1994 case COMP_TX_ERR:
1995 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1996 status = -EPROTO;
1997 break;
1998 case COMP_BABBLE:
1999 xhci_warn(xhci, "WARN: babble error on endpoint\n");
2000 status = -EOVERFLOW;
2001 break;
2002 case COMP_DB_ERR:
2003 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2004 status = -ENOSR;
2005 break;
2006 case COMP_BW_OVER:
2007 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2008 break;
2009 case COMP_BUFF_OVER:
2010 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2011 break;
2012 case COMP_UNDERRUN:
2013 /*
2014 * When the Isoch ring is empty, the xHC will generate
2015 * a Ring Overrun Event for IN Isoch endpoint or Ring
2016 * Underrun Event for OUT Isoch endpoint.
2017 */
2018 xhci_dbg(xhci, "underrun event on endpoint\n");
2019 if (!list_empty(&ep_ring->td_list))
2020 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2021 "still with TDs queued?\n",
2022 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2023 ep_index);
2024 goto cleanup;
2025 case COMP_OVERRUN:
2026 xhci_dbg(xhci, "overrun event on endpoint\n");
2027 if (!list_empty(&ep_ring->td_list))
2028 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2029 "still with TDs queued?\n",
2030 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2031 ep_index);
2032 goto cleanup;
2033 case COMP_DEV_ERR:
2034 xhci_warn(xhci, "WARN: detect an incompatible device");
2035 status = -EPROTO;
2036 break;
2037 case COMP_MISSED_INT:
2038 /*
2039 * When encounter missed service error, one or more isoc tds
2040 * may be missed by xHC.
2041 * Set skip flag of the ep_ring; Complete the missed tds as
2042 * short transfer when process the ep_ring next time.
2043 */
2044 ep->skip = true;
2045 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2046 goto cleanup;
2047 default:
2048 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2049 status = 0;
2050 break;
2051 }
2052 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2053 "busted\n");
2054 goto cleanup;
2055 }
2056
2057 do {
2058 /* This TRB should be in the TD at the head of this ring's
2059 * TD list.
2060 */
2061 if (list_empty(&ep_ring->td_list)) {
2062 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2063 "with no TDs queued?\n",
2064 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2065 ep_index);
2066 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2067 (le32_to_cpu(event->flags) &
2068 TRB_TYPE_BITMASK)>>10);
2069 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2070 if (ep->skip) {
2071 ep->skip = false;
2072 xhci_dbg(xhci, "td_list is empty while skip "
2073 "flag set. Clear skip flag.\n");
2074 }
2075 ret = 0;
2076 goto cleanup;
2077 }
2078
2079 /* We've skipped all the TDs on the ep ring when ep->skip set */
2080 if (ep->skip && td_num == 0) {
2081 ep->skip = false;
2082 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2083 "Clear skip flag.\n");
2084 ret = 0;
2085 goto cleanup;
2086 }
2087
2088 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2089 if (ep->skip)
2090 td_num--;
2091
2092 /* Is this a TRB in the currently executing TD? */
2093 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2094 td->last_trb, event_dma);
2095
2096 /*
2097 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2098 * is not in the current TD pointed by ep_ring->dequeue because
2099 * that the hardware dequeue pointer still at the previous TRB
2100 * of the current TD. The previous TRB maybe a Link TD or the
2101 * last TRB of the previous TD. The command completion handle
2102 * will take care the rest.
2103 */
2104 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2105 ret = 0;
2106 goto cleanup;
2107 }
2108
2109 if (!event_seg) {
2110 if (!ep->skip ||
2111 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2112 /* Some host controllers give a spurious
2113 * successful event after a short transfer.
2114 * Ignore it.
2115 */
2116 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2117 ep_ring->last_td_was_short) {
2118 ep_ring->last_td_was_short = false;
2119 ret = 0;
2120 goto cleanup;
2121 }
2122 /* HC is busted, give up! */
2123 xhci_err(xhci,
2124 "ERROR Transfer event TRB DMA ptr not "
2125 "part of current TD\n");
2126 return -ESHUTDOWN;
2127 }
2128
2129 ret = skip_isoc_td(xhci, td, event, ep, &status);
2130 goto cleanup;
2131 }
2132 if (trb_comp_code == COMP_SHORT_TX)
2133 ep_ring->last_td_was_short = true;
2134 else
2135 ep_ring->last_td_was_short = false;
2136
2137 if (ep->skip) {
2138 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2139 ep->skip = false;
2140 }
2141
2142 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2143 sizeof(*event_trb)];
2144 /*
2145 * No-op TRB should not trigger interrupts.
2146 * If event_trb is a no-op TRB, it means the
2147 * corresponding TD has been cancelled. Just ignore
2148 * the TD.
2149 */
2150 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2151 xhci_dbg(xhci,
2152 "event_trb is a no-op TRB. Skip it\n");
2153 goto cleanup;
2154 }
2155
2156 /* Now update the urb's actual_length and give back to
2157 * the core
2158 */
2159 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2160 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2161 &status);
2162 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2163 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2164 &status);
2165 else
2166 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2167 ep, &status);
2168
2169cleanup:
2170 /*
2171 * Do not update event ring dequeue pointer if ep->skip is set.
2172 * Will roll back to continue process missed tds.
2173 */
2174 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2175 inc_deq(xhci, xhci->event_ring, true);
2176 }
2177
2178 if (ret) {
2179 urb = td->urb;
2180 urb_priv = urb->hcpriv;
2181 /* Leave the TD around for the reset endpoint function
2182 * to use(but only if it's not a control endpoint,
2183 * since we already queued the Set TR dequeue pointer
2184 * command for stalled control endpoints).
2185 */
2186 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2187 (trb_comp_code != COMP_STALL &&
2188 trb_comp_code != COMP_BABBLE))
2189 xhci_urb_free_priv(xhci, urb_priv);
2190
2191 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2192 if ((urb->actual_length != urb->transfer_buffer_length &&
2193 (urb->transfer_flags &
2194 URB_SHORT_NOT_OK)) ||
2195 status != 0)
2196 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2197 "expected = %x, status = %d\n",
2198 urb, urb->actual_length,
2199 urb->transfer_buffer_length,
2200 status);
2201 spin_unlock(&xhci->lock);
2202 /* EHCI, UHCI, and OHCI always unconditionally set the
2203 * urb->status of an isochronous endpoint to 0.
2204 */
2205 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2206 status = 0;
2207 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2208 spin_lock(&xhci->lock);
2209 }
2210
2211 /*
2212 * If ep->skip is set, it means there are missed tds on the
2213 * endpoint ring need to take care of.
2214 * Process them as short transfer until reach the td pointed by
2215 * the event.
2216 */
2217 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2218
2219 return 0;
2220}
2221
2222/*
2223 * This function handles all OS-owned events on the event ring. It may drop
2224 * xhci->lock between event processing (e.g. to pass up port status changes).
2225 * Returns >0 for "possibly more events to process" (caller should call again),
2226 * otherwise 0 if done. In future, <0 returns should indicate error code.
2227 */
2228static int xhci_handle_event(struct xhci_hcd *xhci)
2229{
2230 union xhci_trb *event;
2231 int update_ptrs = 1;
2232 int ret;
2233
2234 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2235 xhci->error_bitmask |= 1 << 1;
2236 return 0;
2237 }
2238
2239 event = xhci->event_ring->dequeue;
2240 /* Does the HC or OS own the TRB? */
2241 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2242 xhci->event_ring->cycle_state) {
2243 xhci->error_bitmask |= 1 << 2;
2244 return 0;
2245 }
2246
2247 /*
2248 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2249 * speculative reads of the event's flags/data below.
2250 */
2251 rmb();
2252 /* FIXME: Handle more event types. */
2253 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2254 case TRB_TYPE(TRB_COMPLETION):
2255 handle_cmd_completion(xhci, &event->event_cmd);
2256 break;
2257 case TRB_TYPE(TRB_PORT_STATUS):
2258 handle_port_status(xhci, event);
2259 update_ptrs = 0;
2260 break;
2261 case TRB_TYPE(TRB_TRANSFER):
2262 ret = handle_tx_event(xhci, &event->trans_event);
2263 if (ret < 0)
2264 xhci->error_bitmask |= 1 << 9;
2265 else
2266 update_ptrs = 0;
2267 break;
2268 default:
2269 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2270 TRB_TYPE(48))
2271 handle_vendor_event(xhci, event);
2272 else
2273 xhci->error_bitmask |= 1 << 3;
2274 }
2275 /* Any of the above functions may drop and re-acquire the lock, so check
2276 * to make sure a watchdog timer didn't mark the host as non-responsive.
2277 */
2278 if (xhci->xhc_state & XHCI_STATE_DYING) {
2279 xhci_dbg(xhci, "xHCI host dying, returning from "
2280 "event handler.\n");
2281 return 0;
2282 }
2283
2284 if (update_ptrs)
2285 /* Update SW event ring dequeue pointer */
2286 inc_deq(xhci, xhci->event_ring, true);
2287
2288 /* Are there more items on the event ring? Caller will call us again to
2289 * check.
2290 */
2291 return 1;
2292}
2293
2294/*
2295 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2296 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2297 * indicators of an event TRB error, but we check the status *first* to be safe.
2298 */
2299irqreturn_t xhci_irq(struct usb_hcd *hcd)
2300{
2301 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2302 u32 status;
2303 union xhci_trb *trb;
2304 u64 temp_64;
2305 union xhci_trb *event_ring_deq;
2306 dma_addr_t deq;
2307
2308 spin_lock(&xhci->lock);
2309 trb = xhci->event_ring->dequeue;
2310 /* Check if the xHC generated the interrupt, or the irq is shared */
2311 status = xhci_readl(xhci, &xhci->op_regs->status);
2312 if (status == 0xffffffff)
2313 goto hw_died;
2314
2315 if (!(status & STS_EINT)) {
2316 spin_unlock(&xhci->lock);
2317 return IRQ_NONE;
2318 }
2319 if (status & STS_FATAL) {
2320 xhci_warn(xhci, "WARNING: Host System Error\n");
2321 xhci_halt(xhci);
2322hw_died:
2323 spin_unlock(&xhci->lock);
2324 return -ESHUTDOWN;
2325 }
2326
2327 /*
2328 * Clear the op reg interrupt status first,
2329 * so we can receive interrupts from other MSI-X interrupters.
2330 * Write 1 to clear the interrupt status.
2331 */
2332 status |= STS_EINT;
2333 xhci_writel(xhci, status, &xhci->op_regs->status);
2334 /* FIXME when MSI-X is supported and there are multiple vectors */
2335 /* Clear the MSI-X event interrupt status */
2336
2337 if (hcd->irq != -1) {
2338 u32 irq_pending;
2339 /* Acknowledge the PCI interrupt */
2340 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2341 irq_pending |= 0x3;
2342 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2343 }
2344
2345 if (xhci->xhc_state & XHCI_STATE_DYING) {
2346 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2347 "Shouldn't IRQs be disabled?\n");
2348 /* Clear the event handler busy flag (RW1C);
2349 * the event ring should be empty.
2350 */
2351 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2352 xhci_write_64(xhci, temp_64 | ERST_EHB,
2353 &xhci->ir_set->erst_dequeue);
2354 spin_unlock(&xhci->lock);
2355
2356 return IRQ_HANDLED;
2357 }
2358
2359 event_ring_deq = xhci->event_ring->dequeue;
2360 /* FIXME this should be a delayed service routine
2361 * that clears the EHB.
2362 */
2363 while (xhci_handle_event(xhci) > 0) {}
2364
2365 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2366 /* If necessary, update the HW's version of the event ring deq ptr. */
2367 if (event_ring_deq != xhci->event_ring->dequeue) {
2368 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2369 xhci->event_ring->dequeue);
2370 if (deq == 0)
2371 xhci_warn(xhci, "WARN something wrong with SW event "
2372 "ring dequeue ptr.\n");
2373 /* Update HC event ring dequeue pointer */
2374 temp_64 &= ERST_PTR_MASK;
2375 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2376 }
2377
2378 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2379 temp_64 |= ERST_EHB;
2380 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2381
2382 spin_unlock(&xhci->lock);
2383
2384 return IRQ_HANDLED;
2385}
2386
2387irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2388{
2389 irqreturn_t ret;
2390 struct xhci_hcd *xhci;
2391
2392 xhci = hcd_to_xhci(hcd);
2393 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2394 if (xhci->shared_hcd)
2395 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2396
2397 ret = xhci_irq(hcd);
2398
2399 return ret;
2400}
2401
2402/**** Endpoint Ring Operations ****/
2403
2404/*
2405 * Generic function for queueing a TRB on a ring.
2406 * The caller must have checked to make sure there's room on the ring.
2407 *
2408 * @more_trbs_coming: Will you enqueue more TRBs before calling
2409 * prepare_transfer()?
2410 */
2411static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2412 bool consumer, bool more_trbs_coming,
2413 u32 field1, u32 field2, u32 field3, u32 field4)
2414{
2415 struct xhci_generic_trb *trb;
2416
2417 trb = &ring->enqueue->generic;
2418 trb->field[0] = cpu_to_le32(field1);
2419 trb->field[1] = cpu_to_le32(field2);
2420 trb->field[2] = cpu_to_le32(field3);
2421 trb->field[3] = cpu_to_le32(field4);
2422 inc_enq(xhci, ring, consumer, more_trbs_coming);
2423}
2424
2425/*
2426 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2427 * FIXME allocate segments if the ring is full.
2428 */
2429static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2430 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2431{
2432 /* Make sure the endpoint has been added to xHC schedule */
2433 switch (ep_state) {
2434 case EP_STATE_DISABLED:
2435 /*
2436 * USB core changed config/interfaces without notifying us,
2437 * or hardware is reporting the wrong state.
2438 */
2439 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2440 return -ENOENT;
2441 case EP_STATE_ERROR:
2442 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2443 /* FIXME event handling code for error needs to clear it */
2444 /* XXX not sure if this should be -ENOENT or not */
2445 return -EINVAL;
2446 case EP_STATE_HALTED:
2447 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2448 case EP_STATE_STOPPED:
2449 case EP_STATE_RUNNING:
2450 break;
2451 default:
2452 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2453 /*
2454 * FIXME issue Configure Endpoint command to try to get the HC
2455 * back into a known state.
2456 */
2457 return -EINVAL;
2458 }
2459 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2460 /* FIXME allocate more room */
2461 xhci_err(xhci, "ERROR no room on ep ring\n");
2462 return -ENOMEM;
2463 }
2464
2465 if (enqueue_is_link_trb(ep_ring)) {
2466 struct xhci_ring *ring = ep_ring;
2467 union xhci_trb *next;
2468
2469 next = ring->enqueue;
2470
2471 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2472 /* If we're not dealing with 0.95 hardware,
2473 * clear the chain bit.
2474 */
2475 if (!xhci_link_trb_quirk(xhci))
2476 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2477 else
2478 next->link.control |= cpu_to_le32(TRB_CHAIN);
2479
2480 wmb();
2481 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2482
2483 /* Toggle the cycle bit after the last ring segment. */
2484 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2485 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2486 if (!in_interrupt()) {
2487 xhci_dbg(xhci, "queue_trb: Toggle cycle "
2488 "state for ring %p = %i\n",
2489 ring, (unsigned int)ring->cycle_state);
2490 }
2491 }
2492 ring->enq_seg = ring->enq_seg->next;
2493 ring->enqueue = ring->enq_seg->trbs;
2494 next = ring->enqueue;
2495 }
2496 }
2497
2498 return 0;
2499}
2500
2501static int prepare_transfer(struct xhci_hcd *xhci,
2502 struct xhci_virt_device *xdev,
2503 unsigned int ep_index,
2504 unsigned int stream_id,
2505 unsigned int num_trbs,
2506 struct urb *urb,
2507 unsigned int td_index,
2508 gfp_t mem_flags)
2509{
2510 int ret;
2511 struct urb_priv *urb_priv;
2512 struct xhci_td *td;
2513 struct xhci_ring *ep_ring;
2514 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2515
2516 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2517 if (!ep_ring) {
2518 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2519 stream_id);
2520 return -EINVAL;
2521 }
2522
2523 ret = prepare_ring(xhci, ep_ring,
2524 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2525 num_trbs, mem_flags);
2526 if (ret)
2527 return ret;
2528
2529 urb_priv = urb->hcpriv;
2530 td = urb_priv->td[td_index];
2531
2532 INIT_LIST_HEAD(&td->td_list);
2533 INIT_LIST_HEAD(&td->cancelled_td_list);
2534
2535 if (td_index == 0) {
2536 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2537 if (unlikely(ret))
2538 return ret;
2539 }
2540
2541 td->urb = urb;
2542 /* Add this TD to the tail of the endpoint ring's TD list */
2543 list_add_tail(&td->td_list, &ep_ring->td_list);
2544 td->start_seg = ep_ring->enq_seg;
2545 td->first_trb = ep_ring->enqueue;
2546
2547 urb_priv->td[td_index] = td;
2548
2549 return 0;
2550}
2551
2552static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2553{
2554 int num_sgs, num_trbs, running_total, temp, i;
2555 struct scatterlist *sg;
2556
2557 sg = NULL;
2558 num_sgs = urb->num_sgs;
2559 temp = urb->transfer_buffer_length;
2560
2561 xhci_dbg(xhci, "count sg list trbs: \n");
2562 num_trbs = 0;
2563 for_each_sg(urb->sg, sg, num_sgs, i) {
2564 unsigned int previous_total_trbs = num_trbs;
2565 unsigned int len = sg_dma_len(sg);
2566
2567 /* Scatter gather list entries may cross 64KB boundaries */
2568 running_total = TRB_MAX_BUFF_SIZE -
2569 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2570 running_total &= TRB_MAX_BUFF_SIZE - 1;
2571 if (running_total != 0)
2572 num_trbs++;
2573
2574 /* How many more 64KB chunks to transfer, how many more TRBs? */
2575 while (running_total < sg_dma_len(sg) && running_total < temp) {
2576 num_trbs++;
2577 running_total += TRB_MAX_BUFF_SIZE;
2578 }
2579 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2580 i, (unsigned long long)sg_dma_address(sg),
2581 len, len, num_trbs - previous_total_trbs);
2582
2583 len = min_t(int, len, temp);
2584 temp -= len;
2585 if (temp == 0)
2586 break;
2587 }
2588 xhci_dbg(xhci, "\n");
2589 if (!in_interrupt())
2590 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2591 "num_trbs = %d\n",
2592 urb->ep->desc.bEndpointAddress,
2593 urb->transfer_buffer_length,
2594 num_trbs);
2595 return num_trbs;
2596}
2597
2598static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2599{
2600 if (num_trbs != 0)
2601 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2602 "TRBs, %d left\n", __func__,
2603 urb->ep->desc.bEndpointAddress, num_trbs);
2604 if (running_total != urb->transfer_buffer_length)
2605 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2606 "queued %#x (%d), asked for %#x (%d)\n",
2607 __func__,
2608 urb->ep->desc.bEndpointAddress,
2609 running_total, running_total,
2610 urb->transfer_buffer_length,
2611 urb->transfer_buffer_length);
2612}
2613
2614static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2615 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2616 struct xhci_generic_trb *start_trb)
2617{
2618 /*
2619 * Pass all the TRBs to the hardware at once and make sure this write
2620 * isn't reordered.
2621 */
2622 wmb();
2623 if (start_cycle)
2624 start_trb->field[3] |= cpu_to_le32(start_cycle);
2625 else
2626 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2627 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2628}
2629
2630/*
2631 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2632 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2633 * (comprised of sg list entries) can take several service intervals to
2634 * transmit.
2635 */
2636int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2637 struct urb *urb, int slot_id, unsigned int ep_index)
2638{
2639 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2640 xhci->devs[slot_id]->out_ctx, ep_index);
2641 int xhci_interval;
2642 int ep_interval;
2643
2644 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2645 ep_interval = urb->interval;
2646 /* Convert to microframes */
2647 if (urb->dev->speed == USB_SPEED_LOW ||
2648 urb->dev->speed == USB_SPEED_FULL)
2649 ep_interval *= 8;
2650 /* FIXME change this to a warning and a suggestion to use the new API
2651 * to set the polling interval (once the API is added).
2652 */
2653 if (xhci_interval != ep_interval) {
2654 if (printk_ratelimit())
2655 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2656 " (%d microframe%s) than xHCI "
2657 "(%d microframe%s)\n",
2658 ep_interval,
2659 ep_interval == 1 ? "" : "s",
2660 xhci_interval,
2661 xhci_interval == 1 ? "" : "s");
2662 urb->interval = xhci_interval;
2663 /* Convert back to frames for LS/FS devices */
2664 if (urb->dev->speed == USB_SPEED_LOW ||
2665 urb->dev->speed == USB_SPEED_FULL)
2666 urb->interval /= 8;
2667 }
2668 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2669}
2670
2671/*
2672 * The TD size is the number of bytes remaining in the TD (including this TRB),
2673 * right shifted by 10.
2674 * It must fit in bits 21:17, so it can't be bigger than 31.
2675 */
2676static u32 xhci_td_remainder(unsigned int remainder)
2677{
2678 u32 max = (1 << (21 - 17 + 1)) - 1;
2679
2680 if ((remainder >> 10) >= max)
2681 return max << 17;
2682 else
2683 return (remainder >> 10) << 17;
2684}
2685
2686/*
2687 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2688 * the TD (*not* including this TRB).
2689 *
2690 * Total TD packet count = total_packet_count =
2691 * roundup(TD size in bytes / wMaxPacketSize)
2692 *
2693 * Packets transferred up to and including this TRB = packets_transferred =
2694 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2695 *
2696 * TD size = total_packet_count - packets_transferred
2697 *
2698 * It must fit in bits 21:17, so it can't be bigger than 31.
2699 */
2700
2701static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2702 unsigned int total_packet_count, struct urb *urb)
2703{
2704 int packets_transferred;
2705
2706 /* One TRB with a zero-length data packet. */
2707 if (running_total == 0 && trb_buff_len == 0)
2708 return 0;
2709
2710 /* All the TRB queueing functions don't count the current TRB in
2711 * running_total.
2712 */
2713 packets_transferred = (running_total + trb_buff_len) /
2714 le16_to_cpu(urb->ep->desc.wMaxPacketSize);
2715
2716 return xhci_td_remainder(total_packet_count - packets_transferred);
2717}
2718
2719static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2720 struct urb *urb, int slot_id, unsigned int ep_index)
2721{
2722 struct xhci_ring *ep_ring;
2723 unsigned int num_trbs;
2724 struct urb_priv *urb_priv;
2725 struct xhci_td *td;
2726 struct scatterlist *sg;
2727 int num_sgs;
2728 int trb_buff_len, this_sg_len, running_total;
2729 unsigned int total_packet_count;
2730 bool first_trb;
2731 u64 addr;
2732 bool more_trbs_coming;
2733
2734 struct xhci_generic_trb *start_trb;
2735 int start_cycle;
2736
2737 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2738 if (!ep_ring)
2739 return -EINVAL;
2740
2741 num_trbs = count_sg_trbs_needed(xhci, urb);
2742 num_sgs = urb->num_sgs;
2743 total_packet_count = roundup(urb->transfer_buffer_length,
2744 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
2745
2746 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2747 ep_index, urb->stream_id,
2748 num_trbs, urb, 0, mem_flags);
2749 if (trb_buff_len < 0)
2750 return trb_buff_len;
2751
2752 urb_priv = urb->hcpriv;
2753 td = urb_priv->td[0];
2754
2755 /*
2756 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2757 * until we've finished creating all the other TRBs. The ring's cycle
2758 * state may change as we enqueue the other TRBs, so save it too.
2759 */
2760 start_trb = &ep_ring->enqueue->generic;
2761 start_cycle = ep_ring->cycle_state;
2762
2763 running_total = 0;
2764 /*
2765 * How much data is in the first TRB?
2766 *
2767 * There are three forces at work for TRB buffer pointers and lengths:
2768 * 1. We don't want to walk off the end of this sg-list entry buffer.
2769 * 2. The transfer length that the driver requested may be smaller than
2770 * the amount of memory allocated for this scatter-gather list.
2771 * 3. TRBs buffers can't cross 64KB boundaries.
2772 */
2773 sg = urb->sg;
2774 addr = (u64) sg_dma_address(sg);
2775 this_sg_len = sg_dma_len(sg);
2776 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2777 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2778 if (trb_buff_len > urb->transfer_buffer_length)
2779 trb_buff_len = urb->transfer_buffer_length;
2780 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2781 trb_buff_len);
2782
2783 first_trb = true;
2784 /* Queue the first TRB, even if it's zero-length */
2785 do {
2786 u32 field = 0;
2787 u32 length_field = 0;
2788 u32 remainder = 0;
2789
2790 /* Don't change the cycle bit of the first TRB until later */
2791 if (first_trb) {
2792 first_trb = false;
2793 if (start_cycle == 0)
2794 field |= 0x1;
2795 } else
2796 field |= ep_ring->cycle_state;
2797
2798 /* Chain all the TRBs together; clear the chain bit in the last
2799 * TRB to indicate it's the last TRB in the chain.
2800 */
2801 if (num_trbs > 1) {
2802 field |= TRB_CHAIN;
2803 } else {
2804 /* FIXME - add check for ZERO_PACKET flag before this */
2805 td->last_trb = ep_ring->enqueue;
2806 field |= TRB_IOC;
2807 }
2808
2809 /* Only set interrupt on short packet for IN endpoints */
2810 if (usb_urb_dir_in(urb))
2811 field |= TRB_ISP;
2812
2813 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2814 "64KB boundary at %#x, end dma = %#x\n",
2815 (unsigned int) addr, trb_buff_len, trb_buff_len,
2816 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2817 (unsigned int) addr + trb_buff_len);
2818 if (TRB_MAX_BUFF_SIZE -
2819 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2820 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2821 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2822 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2823 (unsigned int) addr + trb_buff_len);
2824 }
2825
2826 /* Set the TRB length, TD size, and interrupter fields. */
2827 if (xhci->hci_version < 0x100) {
2828 remainder = xhci_td_remainder(
2829 urb->transfer_buffer_length -
2830 running_total);
2831 } else {
2832 remainder = xhci_v1_0_td_remainder(running_total,
2833 trb_buff_len, total_packet_count, urb);
2834 }
2835 length_field = TRB_LEN(trb_buff_len) |
2836 remainder |
2837 TRB_INTR_TARGET(0);
2838
2839 if (num_trbs > 1)
2840 more_trbs_coming = true;
2841 else
2842 more_trbs_coming = false;
2843 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2844 lower_32_bits(addr),
2845 upper_32_bits(addr),
2846 length_field,
2847 field | TRB_TYPE(TRB_NORMAL));
2848 --num_trbs;
2849 running_total += trb_buff_len;
2850
2851 /* Calculate length for next transfer --
2852 * Are we done queueing all the TRBs for this sg entry?
2853 */
2854 this_sg_len -= trb_buff_len;
2855 if (this_sg_len == 0) {
2856 --num_sgs;
2857 if (num_sgs == 0)
2858 break;
2859 sg = sg_next(sg);
2860 addr = (u64) sg_dma_address(sg);
2861 this_sg_len = sg_dma_len(sg);
2862 } else {
2863 addr += trb_buff_len;
2864 }
2865
2866 trb_buff_len = TRB_MAX_BUFF_SIZE -
2867 (addr & (TRB_MAX_BUFF_SIZE - 1));
2868 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2869 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2870 trb_buff_len =
2871 urb->transfer_buffer_length - running_total;
2872 } while (running_total < urb->transfer_buffer_length);
2873
2874 check_trb_math(urb, num_trbs, running_total);
2875 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2876 start_cycle, start_trb);
2877 return 0;
2878}
2879
2880/* This is very similar to what ehci-q.c qtd_fill() does */
2881int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2882 struct urb *urb, int slot_id, unsigned int ep_index)
2883{
2884 struct xhci_ring *ep_ring;
2885 struct urb_priv *urb_priv;
2886 struct xhci_td *td;
2887 int num_trbs;
2888 struct xhci_generic_trb *start_trb;
2889 bool first_trb;
2890 bool more_trbs_coming;
2891 int start_cycle;
2892 u32 field, length_field;
2893
2894 int running_total, trb_buff_len, ret;
2895 unsigned int total_packet_count;
2896 u64 addr;
2897
2898 if (urb->num_sgs)
2899 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2900
2901 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2902 if (!ep_ring)
2903 return -EINVAL;
2904
2905 num_trbs = 0;
2906 /* How much data is (potentially) left before the 64KB boundary? */
2907 running_total = TRB_MAX_BUFF_SIZE -
2908 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2909 running_total &= TRB_MAX_BUFF_SIZE - 1;
2910
2911 /* If there's some data on this 64KB chunk, or we have to send a
2912 * zero-length transfer, we need at least one TRB
2913 */
2914 if (running_total != 0 || urb->transfer_buffer_length == 0)
2915 num_trbs++;
2916 /* How many more 64KB chunks to transfer, how many more TRBs? */
2917 while (running_total < urb->transfer_buffer_length) {
2918 num_trbs++;
2919 running_total += TRB_MAX_BUFF_SIZE;
2920 }
2921 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2922
2923 if (!in_interrupt())
2924 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2925 "addr = %#llx, num_trbs = %d\n",
2926 urb->ep->desc.bEndpointAddress,
2927 urb->transfer_buffer_length,
2928 urb->transfer_buffer_length,
2929 (unsigned long long)urb->transfer_dma,
2930 num_trbs);
2931
2932 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2933 ep_index, urb->stream_id,
2934 num_trbs, urb, 0, mem_flags);
2935 if (ret < 0)
2936 return ret;
2937
2938 urb_priv = urb->hcpriv;
2939 td = urb_priv->td[0];
2940
2941 /*
2942 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2943 * until we've finished creating all the other TRBs. The ring's cycle
2944 * state may change as we enqueue the other TRBs, so save it too.
2945 */
2946 start_trb = &ep_ring->enqueue->generic;
2947 start_cycle = ep_ring->cycle_state;
2948
2949 running_total = 0;
2950 total_packet_count = roundup(urb->transfer_buffer_length,
2951 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
2952 /* How much data is in the first TRB? */
2953 addr = (u64) urb->transfer_dma;
2954 trb_buff_len = TRB_MAX_BUFF_SIZE -
2955 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2956 if (trb_buff_len > urb->transfer_buffer_length)
2957 trb_buff_len = urb->transfer_buffer_length;
2958
2959 first_trb = true;
2960
2961 /* Queue the first TRB, even if it's zero-length */
2962 do {
2963 u32 remainder = 0;
2964 field = 0;
2965
2966 /* Don't change the cycle bit of the first TRB until later */
2967 if (first_trb) {
2968 first_trb = false;
2969 if (start_cycle == 0)
2970 field |= 0x1;
2971 } else
2972 field |= ep_ring->cycle_state;
2973
2974 /* Chain all the TRBs together; clear the chain bit in the last
2975 * TRB to indicate it's the last TRB in the chain.
2976 */
2977 if (num_trbs > 1) {
2978 field |= TRB_CHAIN;
2979 } else {
2980 /* FIXME - add check for ZERO_PACKET flag before this */
2981 td->last_trb = ep_ring->enqueue;
2982 field |= TRB_IOC;
2983 }
2984
2985 /* Only set interrupt on short packet for IN endpoints */
2986 if (usb_urb_dir_in(urb))
2987 field |= TRB_ISP;
2988
2989 /* Set the TRB length, TD size, and interrupter fields. */
2990 if (xhci->hci_version < 0x100) {
2991 remainder = xhci_td_remainder(
2992 urb->transfer_buffer_length -
2993 running_total);
2994 } else {
2995 remainder = xhci_v1_0_td_remainder(running_total,
2996 trb_buff_len, total_packet_count, urb);
2997 }
2998 length_field = TRB_LEN(trb_buff_len) |
2999 remainder |
3000 TRB_INTR_TARGET(0);
3001
3002 if (num_trbs > 1)
3003 more_trbs_coming = true;
3004 else
3005 more_trbs_coming = false;
3006 queue_trb(xhci, ep_ring, false, more_trbs_coming,
3007 lower_32_bits(addr),
3008 upper_32_bits(addr),
3009 length_field,
3010 field | TRB_TYPE(TRB_NORMAL));
3011 --num_trbs;
3012 running_total += trb_buff_len;
3013
3014 /* Calculate length for next transfer */
3015 addr += trb_buff_len;
3016 trb_buff_len = urb->transfer_buffer_length - running_total;
3017 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3018 trb_buff_len = TRB_MAX_BUFF_SIZE;
3019 } while (running_total < urb->transfer_buffer_length);
3020
3021 check_trb_math(urb, num_trbs, running_total);
3022 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3023 start_cycle, start_trb);
3024 return 0;
3025}
3026
3027/* Caller must have locked xhci->lock */
3028int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3029 struct urb *urb, int slot_id, unsigned int ep_index)
3030{
3031 struct xhci_ring *ep_ring;
3032 int num_trbs;
3033 int ret;
3034 struct usb_ctrlrequest *setup;
3035 struct xhci_generic_trb *start_trb;
3036 int start_cycle;
3037 u32 field, length_field;
3038 struct urb_priv *urb_priv;
3039 struct xhci_td *td;
3040
3041 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3042 if (!ep_ring)
3043 return -EINVAL;
3044
3045 /*
3046 * Need to copy setup packet into setup TRB, so we can't use the setup
3047 * DMA address.
3048 */
3049 if (!urb->setup_packet)
3050 return -EINVAL;
3051
3052 if (!in_interrupt())
3053 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3054 slot_id, ep_index);
3055 /* 1 TRB for setup, 1 for status */
3056 num_trbs = 2;
3057 /*
3058 * Don't need to check if we need additional event data and normal TRBs,
3059 * since data in control transfers will never get bigger than 16MB
3060 * XXX: can we get a buffer that crosses 64KB boundaries?
3061 */
3062 if (urb->transfer_buffer_length > 0)
3063 num_trbs++;
3064 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3065 ep_index, urb->stream_id,
3066 num_trbs, urb, 0, mem_flags);
3067 if (ret < 0)
3068 return ret;
3069
3070 urb_priv = urb->hcpriv;
3071 td = urb_priv->td[0];
3072
3073 /*
3074 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3075 * until we've finished creating all the other TRBs. The ring's cycle
3076 * state may change as we enqueue the other TRBs, so save it too.
3077 */
3078 start_trb = &ep_ring->enqueue->generic;
3079 start_cycle = ep_ring->cycle_state;
3080
3081 /* Queue setup TRB - see section 6.4.1.2.1 */
3082 /* FIXME better way to translate setup_packet into two u32 fields? */
3083 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3084 field = 0;
3085 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3086 if (start_cycle == 0)
3087 field |= 0x1;
3088
3089 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3090 if (xhci->hci_version == 0x100) {
3091 if (urb->transfer_buffer_length > 0) {
3092 if (setup->bRequestType & USB_DIR_IN)
3093 field |= TRB_TX_TYPE(TRB_DATA_IN);
3094 else
3095 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3096 }
3097 }
3098
3099 queue_trb(xhci, ep_ring, false, true,
3100 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3101 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3102 TRB_LEN(8) | TRB_INTR_TARGET(0),
3103 /* Immediate data in pointer */
3104 field);
3105
3106 /* If there's data, queue data TRBs */
3107 /* Only set interrupt on short packet for IN endpoints */
3108 if (usb_urb_dir_in(urb))
3109 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3110 else
3111 field = TRB_TYPE(TRB_DATA);
3112
3113 length_field = TRB_LEN(urb->transfer_buffer_length) |
3114 xhci_td_remainder(urb->transfer_buffer_length) |
3115 TRB_INTR_TARGET(0);
3116 if (urb->transfer_buffer_length > 0) {
3117 if (setup->bRequestType & USB_DIR_IN)
3118 field |= TRB_DIR_IN;
3119 queue_trb(xhci, ep_ring, false, true,
3120 lower_32_bits(urb->transfer_dma),
3121 upper_32_bits(urb->transfer_dma),
3122 length_field,
3123 field | ep_ring->cycle_state);
3124 }
3125
3126 /* Save the DMA address of the last TRB in the TD */
3127 td->last_trb = ep_ring->enqueue;
3128
3129 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3130 /* If the device sent data, the status stage is an OUT transfer */
3131 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3132 field = 0;
3133 else
3134 field = TRB_DIR_IN;
3135 queue_trb(xhci, ep_ring, false, false,
3136 0,
3137 0,
3138 TRB_INTR_TARGET(0),
3139 /* Event on completion */
3140 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3141
3142 giveback_first_trb(xhci, slot_id, ep_index, 0,
3143 start_cycle, start_trb);
3144 return 0;
3145}
3146
3147static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3148 struct urb *urb, int i)
3149{
3150 int num_trbs = 0;
3151 u64 addr, td_len;
3152
3153 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3154 td_len = urb->iso_frame_desc[i].length;
3155
3156 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3157 TRB_MAX_BUFF_SIZE);
3158 if (num_trbs == 0)
3159 num_trbs++;
3160
3161 return num_trbs;
3162}
3163
3164/*
3165 * The transfer burst count field of the isochronous TRB defines the number of
3166 * bursts that are required to move all packets in this TD. Only SuperSpeed
3167 * devices can burst up to bMaxBurst number of packets per service interval.
3168 * This field is zero based, meaning a value of zero in the field means one
3169 * burst. Basically, for everything but SuperSpeed devices, this field will be
3170 * zero. Only xHCI 1.0 host controllers support this field.
3171 */
3172static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3173 struct usb_device *udev,
3174 struct urb *urb, unsigned int total_packet_count)
3175{
3176 unsigned int max_burst;
3177
3178 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3179 return 0;
3180
3181 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3182 return roundup(total_packet_count, max_burst + 1) - 1;
3183}
3184
3185/*
3186 * Returns the number of packets in the last "burst" of packets. This field is
3187 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3188 * the last burst packet count is equal to the total number of packets in the
3189 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3190 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3191 * contain 1 to (bMaxBurst + 1) packets.
3192 */
3193static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3194 struct usb_device *udev,
3195 struct urb *urb, unsigned int total_packet_count)
3196{
3197 unsigned int max_burst;
3198 unsigned int residue;
3199
3200 if (xhci->hci_version < 0x100)
3201 return 0;
3202
3203 switch (udev->speed) {
3204 case USB_SPEED_SUPER:
3205 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3206 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3207 residue = total_packet_count % (max_burst + 1);
3208 /* If residue is zero, the last burst contains (max_burst + 1)
3209 * number of packets, but the TLBPC field is zero-based.
3210 */
3211 if (residue == 0)
3212 return max_burst;
3213 return residue - 1;
3214 default:
3215 if (total_packet_count == 0)
3216 return 0;
3217 return total_packet_count - 1;
3218 }
3219}
3220
3221/* This is for isoc transfer */
3222static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3223 struct urb *urb, int slot_id, unsigned int ep_index)
3224{
3225 struct xhci_ring *ep_ring;
3226 struct urb_priv *urb_priv;
3227 struct xhci_td *td;
3228 int num_tds, trbs_per_td;
3229 struct xhci_generic_trb *start_trb;
3230 bool first_trb;
3231 int start_cycle;
3232 u32 field, length_field;
3233 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3234 u64 start_addr, addr;
3235 int i, j;
3236 bool more_trbs_coming;
3237
3238 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3239
3240 num_tds = urb->number_of_packets;
3241 if (num_tds < 1) {
3242 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3243 return -EINVAL;
3244 }
3245
3246 if (!in_interrupt())
3247 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3248 " addr = %#llx, num_tds = %d\n",
3249 urb->ep->desc.bEndpointAddress,
3250 urb->transfer_buffer_length,
3251 urb->transfer_buffer_length,
3252 (unsigned long long)urb->transfer_dma,
3253 num_tds);
3254
3255 start_addr = (u64) urb->transfer_dma;
3256 start_trb = &ep_ring->enqueue->generic;
3257 start_cycle = ep_ring->cycle_state;
3258
3259 urb_priv = urb->hcpriv;
3260 /* Queue the first TRB, even if it's zero-length */
3261 for (i = 0; i < num_tds; i++) {
3262 unsigned int total_packet_count;
3263 unsigned int burst_count;
3264 unsigned int residue;
3265
3266 first_trb = true;
3267 running_total = 0;
3268 addr = start_addr + urb->iso_frame_desc[i].offset;
3269 td_len = urb->iso_frame_desc[i].length;
3270 td_remain_len = td_len;
3271 total_packet_count = roundup(td_len,
3272 le16_to_cpu(urb->ep->desc.wMaxPacketSize));
3273 /* A zero-length transfer still involves at least one packet. */
3274 if (total_packet_count == 0)
3275 total_packet_count++;
3276 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3277 total_packet_count);
3278 residue = xhci_get_last_burst_packet_count(xhci,
3279 urb->dev, urb, total_packet_count);
3280
3281 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3282
3283 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3284 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3285 if (ret < 0) {
3286 if (i == 0)
3287 return ret;
3288 goto cleanup;
3289 }
3290
3291 td = urb_priv->td[i];
3292 for (j = 0; j < trbs_per_td; j++) {
3293 u32 remainder = 0;
3294 field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3295
3296 if (first_trb) {
3297 /* Queue the isoc TRB */
3298 field |= TRB_TYPE(TRB_ISOC);
3299 /* Assume URB_ISO_ASAP is set */
3300 field |= TRB_SIA;
3301 if (i == 0) {
3302 if (start_cycle == 0)
3303 field |= 0x1;
3304 } else
3305 field |= ep_ring->cycle_state;
3306 first_trb = false;
3307 } else {
3308 /* Queue other normal TRBs */
3309 field |= TRB_TYPE(TRB_NORMAL);
3310 field |= ep_ring->cycle_state;
3311 }
3312
3313 /* Only set interrupt on short packet for IN EPs */
3314 if (usb_urb_dir_in(urb))
3315 field |= TRB_ISP;
3316
3317 /* Chain all the TRBs together; clear the chain bit in
3318 * the last TRB to indicate it's the last TRB in the
3319 * chain.
3320 */
3321 if (j < trbs_per_td - 1) {
3322 field |= TRB_CHAIN;
3323 more_trbs_coming = true;
3324 } else {
3325 td->last_trb = ep_ring->enqueue;
3326 field |= TRB_IOC;
3327 if (xhci->hci_version == 0x100) {
3328 /* Set BEI bit except for the last td */
3329 if (i < num_tds - 1)
3330 field |= TRB_BEI;
3331 }
3332 more_trbs_coming = false;
3333 }
3334
3335 /* Calculate TRB length */
3336 trb_buff_len = TRB_MAX_BUFF_SIZE -
3337 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3338 if (trb_buff_len > td_remain_len)
3339 trb_buff_len = td_remain_len;
3340
3341 /* Set the TRB length, TD size, & interrupter fields. */
3342 if (xhci->hci_version < 0x100) {
3343 remainder = xhci_td_remainder(
3344 td_len - running_total);
3345 } else {
3346 remainder = xhci_v1_0_td_remainder(
3347 running_total, trb_buff_len,
3348 total_packet_count, urb);
3349 }
3350 length_field = TRB_LEN(trb_buff_len) |
3351 remainder |
3352 TRB_INTR_TARGET(0);
3353
3354 queue_trb(xhci, ep_ring, false, more_trbs_coming,
3355 lower_32_bits(addr),
3356 upper_32_bits(addr),
3357 length_field,
3358 field);
3359 running_total += trb_buff_len;
3360
3361 addr += trb_buff_len;
3362 td_remain_len -= trb_buff_len;
3363 }
3364
3365 /* Check TD length */
3366 if (running_total != td_len) {
3367 xhci_err(xhci, "ISOC TD length unmatch\n");
3368 return -EINVAL;
3369 }
3370 }
3371
3372 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3373 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3374 usb_amd_quirk_pll_disable();
3375 }
3376 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3377
3378 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3379 start_cycle, start_trb);
3380 return 0;
3381cleanup:
3382 /* Clean up a partially enqueued isoc transfer. */
3383
3384 for (i--; i >= 0; i--)
3385 list_del_init(&urb_priv->td[i]->td_list);
3386
3387 /* Use the first TD as a temporary variable to turn the TDs we've queued
3388 * into No-ops with a software-owned cycle bit. That way the hardware
3389 * won't accidentally start executing bogus TDs when we partially
3390 * overwrite them. td->first_trb and td->start_seg are already set.
3391 */
3392 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3393 /* Every TRB except the first & last will have its cycle bit flipped. */
3394 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3395
3396 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3397 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3398 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3399 ep_ring->cycle_state = start_cycle;
3400 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3401 return ret;
3402}
3403
3404/*
3405 * Check transfer ring to guarantee there is enough room for the urb.
3406 * Update ISO URB start_frame and interval.
3407 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3408 * update the urb->start_frame by now.
3409 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3410 */
3411int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3412 struct urb *urb, int slot_id, unsigned int ep_index)
3413{
3414 struct xhci_virt_device *xdev;
3415 struct xhci_ring *ep_ring;
3416 struct xhci_ep_ctx *ep_ctx;
3417 int start_frame;
3418 int xhci_interval;
3419 int ep_interval;
3420 int num_tds, num_trbs, i;
3421 int ret;
3422
3423 xdev = xhci->devs[slot_id];
3424 ep_ring = xdev->eps[ep_index].ring;
3425 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3426
3427 num_trbs = 0;
3428 num_tds = urb->number_of_packets;
3429 for (i = 0; i < num_tds; i++)
3430 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3431
3432 /* Check the ring to guarantee there is enough room for the whole urb.
3433 * Do not insert any td of the urb to the ring if the check failed.
3434 */
3435 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3436 num_trbs, mem_flags);
3437 if (ret)
3438 return ret;
3439
3440 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3441 start_frame &= 0x3fff;
3442
3443 urb->start_frame = start_frame;
3444 if (urb->dev->speed == USB_SPEED_LOW ||
3445 urb->dev->speed == USB_SPEED_FULL)
3446 urb->start_frame >>= 3;
3447
3448 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3449 ep_interval = urb->interval;
3450 /* Convert to microframes */
3451 if (urb->dev->speed == USB_SPEED_LOW ||
3452 urb->dev->speed == USB_SPEED_FULL)
3453 ep_interval *= 8;
3454 /* FIXME change this to a warning and a suggestion to use the new API
3455 * to set the polling interval (once the API is added).
3456 */
3457 if (xhci_interval != ep_interval) {
3458 if (printk_ratelimit())
3459 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3460 " (%d microframe%s) than xHCI "
3461 "(%d microframe%s)\n",
3462 ep_interval,
3463 ep_interval == 1 ? "" : "s",
3464 xhci_interval,
3465 xhci_interval == 1 ? "" : "s");
3466 urb->interval = xhci_interval;
3467 /* Convert back to frames for LS/FS devices */
3468 if (urb->dev->speed == USB_SPEED_LOW ||
3469 urb->dev->speed == USB_SPEED_FULL)
3470 urb->interval /= 8;
3471 }
3472 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3473}
3474
3475/**** Command Ring Operations ****/
3476
3477/* Generic function for queueing a command TRB on the command ring.
3478 * Check to make sure there's room on the command ring for one command TRB.
3479 * Also check that there's room reserved for commands that must not fail.
3480 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3481 * then only check for the number of reserved spots.
3482 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3483 * because the command event handler may want to resubmit a failed command.
3484 */
3485static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3486 u32 field3, u32 field4, bool command_must_succeed)
3487{
3488 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3489 int ret;
3490
3491 if (!command_must_succeed)
3492 reserved_trbs++;
3493
3494 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3495 reserved_trbs, GFP_ATOMIC);
3496 if (ret < 0) {
3497 xhci_err(xhci, "ERR: No room for command on command ring\n");
3498 if (command_must_succeed)
3499 xhci_err(xhci, "ERR: Reserved TRB counting for "
3500 "unfailable commands failed.\n");
3501 return ret;
3502 }
3503 queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
3504 field4 | xhci->cmd_ring->cycle_state);
3505 return 0;
3506}
3507
3508/* Queue a slot enable or disable request on the command ring */
3509int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3510{
3511 return queue_command(xhci, 0, 0, 0,
3512 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3513}
3514
3515/* Queue an address device command TRB */
3516int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3517 u32 slot_id)
3518{
3519 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3520 upper_32_bits(in_ctx_ptr), 0,
3521 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3522 false);
3523}
3524
3525int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3526 u32 field1, u32 field2, u32 field3, u32 field4)
3527{
3528 return queue_command(xhci, field1, field2, field3, field4, false);
3529}
3530
3531/* Queue a reset device command TRB */
3532int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3533{
3534 return queue_command(xhci, 0, 0, 0,
3535 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3536 false);
3537}
3538
3539/* Queue a configure endpoint command TRB */
3540int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3541 u32 slot_id, bool command_must_succeed)
3542{
3543 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3544 upper_32_bits(in_ctx_ptr), 0,
3545 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3546 command_must_succeed);
3547}
3548
3549/* Queue an evaluate context command TRB */
3550int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3551 u32 slot_id)
3552{
3553 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3554 upper_32_bits(in_ctx_ptr), 0,
3555 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3556 false);
3557}
3558
3559/*
3560 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3561 * activity on an endpoint that is about to be suspended.
3562 */
3563int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3564 unsigned int ep_index, int suspend)
3565{
3566 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3567 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3568 u32 type = TRB_TYPE(TRB_STOP_RING);
3569 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3570
3571 return queue_command(xhci, 0, 0, 0,
3572 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3573}
3574
3575/* Set Transfer Ring Dequeue Pointer command.
3576 * This should not be used for endpoints that have streams enabled.
3577 */
3578static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3579 unsigned int ep_index, unsigned int stream_id,
3580 struct xhci_segment *deq_seg,
3581 union xhci_trb *deq_ptr, u32 cycle_state)
3582{
3583 dma_addr_t addr;
3584 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3585 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3586 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3587 u32 type = TRB_TYPE(TRB_SET_DEQ);
3588 struct xhci_virt_ep *ep;
3589
3590 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3591 if (addr == 0) {
3592 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3593 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3594 deq_seg, deq_ptr);
3595 return 0;
3596 }
3597 ep = &xhci->devs[slot_id]->eps[ep_index];
3598 if ((ep->ep_state & SET_DEQ_PENDING)) {
3599 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3600 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3601 return 0;
3602 }
3603 ep->queued_deq_seg = deq_seg;
3604 ep->queued_deq_ptr = deq_ptr;
3605 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3606 upper_32_bits(addr), trb_stream_id,
3607 trb_slot_id | trb_ep_index | type, false);
3608}
3609
3610int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3611 unsigned int ep_index)
3612{
3613 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3614 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3615 u32 type = TRB_TYPE(TRB_RESET_EP);
3616
3617 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3618 false);
3619}
1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
29 *
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
41 *
42 * Cycle bit rules:
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
47 *
48 * Producer rules:
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
52 * cycle state).
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
56 *
57 * Consumer rules:
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
65 */
66
67#include <linux/scatterlist.h>
68#include <linux/slab.h>
69#include "xhci.h"
70#include "xhci-trace.h"
71
72static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
73 struct xhci_virt_device *virt_dev,
74 struct xhci_event_cmd *event);
75
76/*
77 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
78 * address of the TRB.
79 */
80dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
81 union xhci_trb *trb)
82{
83 unsigned long segment_offset;
84
85 if (!seg || !trb || trb < seg->trbs)
86 return 0;
87 /* offset in TRBs */
88 segment_offset = trb - seg->trbs;
89 if (segment_offset > TRBS_PER_SEGMENT)
90 return 0;
91 return seg->dma + (segment_offset * sizeof(*trb));
92}
93
94/* Does this link TRB point to the first segment in a ring,
95 * or was the previous TRB the last TRB on the last segment in the ERST?
96 */
97static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
98 struct xhci_segment *seg, union xhci_trb *trb)
99{
100 if (ring == xhci->event_ring)
101 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
102 (seg->next == xhci->event_ring->first_seg);
103 else
104 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
105}
106
107/* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
108 * segment? I.e. would the updated event TRB pointer step off the end of the
109 * event seg?
110 */
111static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
112 struct xhci_segment *seg, union xhci_trb *trb)
113{
114 if (ring == xhci->event_ring)
115 return trb == &seg->trbs[TRBS_PER_SEGMENT];
116 else
117 return TRB_TYPE_LINK_LE32(trb->link.control);
118}
119
120static int enqueue_is_link_trb(struct xhci_ring *ring)
121{
122 struct xhci_link_trb *link = &ring->enqueue->link;
123 return TRB_TYPE_LINK_LE32(link->control);
124}
125
126union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring)
127{
128 /* Enqueue pointer can be left pointing to the link TRB,
129 * we must handle that
130 */
131 if (TRB_TYPE_LINK_LE32(ring->enqueue->link.control))
132 return ring->enq_seg->next->trbs;
133 return ring->enqueue;
134}
135
136/* Updates trb to point to the next TRB in the ring, and updates seg if the next
137 * TRB is in a new segment. This does not skip over link TRBs, and it does not
138 * effect the ring dequeue or enqueue pointers.
139 */
140static void next_trb(struct xhci_hcd *xhci,
141 struct xhci_ring *ring,
142 struct xhci_segment **seg,
143 union xhci_trb **trb)
144{
145 if (last_trb(xhci, ring, *seg, *trb)) {
146 *seg = (*seg)->next;
147 *trb = ((*seg)->trbs);
148 } else {
149 (*trb)++;
150 }
151}
152
153/*
154 * See Cycle bit rules. SW is the consumer for the event ring only.
155 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
156 */
157static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
158{
159 ring->deq_updates++;
160
161 /*
162 * If this is not event ring, and the dequeue pointer
163 * is not on a link TRB, there is one more usable TRB
164 */
165 if (ring->type != TYPE_EVENT &&
166 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
167 ring->num_trbs_free++;
168
169 do {
170 /*
171 * Update the dequeue pointer further if that was a link TRB or
172 * we're at the end of an event ring segment (which doesn't have
173 * link TRBS)
174 */
175 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
176 if (ring->type == TYPE_EVENT &&
177 last_trb_on_last_seg(xhci, ring,
178 ring->deq_seg, ring->dequeue)) {
179 ring->cycle_state ^= 1;
180 }
181 ring->deq_seg = ring->deq_seg->next;
182 ring->dequeue = ring->deq_seg->trbs;
183 } else {
184 ring->dequeue++;
185 }
186 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
187}
188
189/*
190 * See Cycle bit rules. SW is the consumer for the event ring only.
191 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
192 *
193 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
194 * chain bit is set), then set the chain bit in all the following link TRBs.
195 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
196 * have their chain bit cleared (so that each Link TRB is a separate TD).
197 *
198 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
199 * set, but other sections talk about dealing with the chain bit set. This was
200 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
201 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
202 *
203 * @more_trbs_coming: Will you enqueue more TRBs before calling
204 * prepare_transfer()?
205 */
206static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
207 bool more_trbs_coming)
208{
209 u32 chain;
210 union xhci_trb *next;
211
212 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
213 /* If this is not event ring, there is one less usable TRB */
214 if (ring->type != TYPE_EVENT &&
215 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
216 ring->num_trbs_free--;
217 next = ++(ring->enqueue);
218
219 ring->enq_updates++;
220 /* Update the dequeue pointer further if that was a link TRB or we're at
221 * the end of an event ring segment (which doesn't have link TRBS)
222 */
223 while (last_trb(xhci, ring, ring->enq_seg, next)) {
224 if (ring->type != TYPE_EVENT) {
225 /*
226 * If the caller doesn't plan on enqueueing more
227 * TDs before ringing the doorbell, then we
228 * don't want to give the link TRB to the
229 * hardware just yet. We'll give the link TRB
230 * back in prepare_ring() just before we enqueue
231 * the TD at the top of the ring.
232 */
233 if (!chain && !more_trbs_coming)
234 break;
235
236 /* If we're not dealing with 0.95 hardware or
237 * isoc rings on AMD 0.96 host,
238 * carry over the chain bit of the previous TRB
239 * (which may mean the chain bit is cleared).
240 */
241 if (!(ring->type == TYPE_ISOC &&
242 (xhci->quirks & XHCI_AMD_0x96_HOST))
243 && !xhci_link_trb_quirk(xhci)) {
244 next->link.control &=
245 cpu_to_le32(~TRB_CHAIN);
246 next->link.control |=
247 cpu_to_le32(chain);
248 }
249 /* Give this link TRB to the hardware */
250 wmb();
251 next->link.control ^= cpu_to_le32(TRB_CYCLE);
252
253 /* Toggle the cycle bit after the last ring segment. */
254 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
255 ring->cycle_state = (ring->cycle_state ? 0 : 1);
256 }
257 }
258 ring->enq_seg = ring->enq_seg->next;
259 ring->enqueue = ring->enq_seg->trbs;
260 next = ring->enqueue;
261 }
262}
263
264/*
265 * Check to see if there's room to enqueue num_trbs on the ring and make sure
266 * enqueue pointer will not advance into dequeue segment. See rules above.
267 */
268static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
269 unsigned int num_trbs)
270{
271 int num_trbs_in_deq_seg;
272
273 if (ring->num_trbs_free < num_trbs)
274 return 0;
275
276 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
277 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
278 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
279 return 0;
280 }
281
282 return 1;
283}
284
285/* Ring the host controller doorbell after placing a command on the ring */
286void xhci_ring_cmd_db(struct xhci_hcd *xhci)
287{
288 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
289 return;
290
291 xhci_dbg(xhci, "// Ding dong!\n");
292 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
293 /* Flush PCI posted writes */
294 readl(&xhci->dba->doorbell[0]);
295}
296
297static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
298{
299 u64 temp_64;
300 int ret;
301
302 xhci_dbg(xhci, "Abort command ring\n");
303
304 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
305 xhci_dbg(xhci, "The command ring isn't running, "
306 "Have the command ring been stopped?\n");
307 return 0;
308 }
309
310 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
311 if (!(temp_64 & CMD_RING_RUNNING)) {
312 xhci_dbg(xhci, "Command ring had been stopped\n");
313 return 0;
314 }
315 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
316 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
317 &xhci->op_regs->cmd_ring);
318
319 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
320 * time the completion od all xHCI commands, including
321 * the Command Abort operation. If software doesn't see
322 * CRR negated in a timely manner (e.g. longer than 5
323 * seconds), then it should assume that the there are
324 * larger problems with the xHC and assert HCRST.
325 */
326 ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
327 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
328 if (ret < 0) {
329 xhci_err(xhci, "Stopped the command ring failed, "
330 "maybe the host is dead\n");
331 xhci->xhc_state |= XHCI_STATE_DYING;
332 xhci_quiesce(xhci);
333 xhci_halt(xhci);
334 return -ESHUTDOWN;
335 }
336
337 return 0;
338}
339
340static int xhci_queue_cd(struct xhci_hcd *xhci,
341 struct xhci_command *command,
342 union xhci_trb *cmd_trb)
343{
344 struct xhci_cd *cd;
345 cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
346 if (!cd)
347 return -ENOMEM;
348 INIT_LIST_HEAD(&cd->cancel_cmd_list);
349
350 cd->command = command;
351 cd->cmd_trb = cmd_trb;
352 list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
353
354 return 0;
355}
356
357/*
358 * Cancel the command which has issue.
359 *
360 * Some commands may hang due to waiting for acknowledgement from
361 * usb device. It is outside of the xHC's ability to control and
362 * will cause the command ring is blocked. When it occurs software
363 * should intervene to recover the command ring.
364 * See Section 4.6.1.1 and 4.6.1.2
365 */
366int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
367 union xhci_trb *cmd_trb)
368{
369 int retval = 0;
370 unsigned long flags;
371
372 spin_lock_irqsave(&xhci->lock, flags);
373
374 if (xhci->xhc_state & XHCI_STATE_DYING) {
375 xhci_warn(xhci, "Abort the command ring,"
376 " but the xHCI is dead.\n");
377 retval = -ESHUTDOWN;
378 goto fail;
379 }
380
381 /* queue the cmd desriptor to cancel_cmd_list */
382 retval = xhci_queue_cd(xhci, command, cmd_trb);
383 if (retval) {
384 xhci_warn(xhci, "Queuing command descriptor failed.\n");
385 goto fail;
386 }
387
388 /* abort command ring */
389 retval = xhci_abort_cmd_ring(xhci);
390 if (retval) {
391 xhci_err(xhci, "Abort command ring failed\n");
392 if (unlikely(retval == -ESHUTDOWN)) {
393 spin_unlock_irqrestore(&xhci->lock, flags);
394 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
395 xhci_dbg(xhci, "xHCI host controller is dead.\n");
396 return retval;
397 }
398 }
399
400fail:
401 spin_unlock_irqrestore(&xhci->lock, flags);
402 return retval;
403}
404
405void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
406 unsigned int slot_id,
407 unsigned int ep_index,
408 unsigned int stream_id)
409{
410 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
411 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
412 unsigned int ep_state = ep->ep_state;
413
414 /* Don't ring the doorbell for this endpoint if there are pending
415 * cancellations because we don't want to interrupt processing.
416 * We don't want to restart any stream rings if there's a set dequeue
417 * pointer command pending because the device can choose to start any
418 * stream once the endpoint is on the HW schedule.
419 * FIXME - check all the stream rings for pending cancellations.
420 */
421 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
422 (ep_state & EP_HALTED))
423 return;
424 writel(DB_VALUE(ep_index, stream_id), db_addr);
425 /* The CPU has better things to do at this point than wait for a
426 * write-posting flush. It'll get there soon enough.
427 */
428}
429
430/* Ring the doorbell for any rings with pending URBs */
431static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
432 unsigned int slot_id,
433 unsigned int ep_index)
434{
435 unsigned int stream_id;
436 struct xhci_virt_ep *ep;
437
438 ep = &xhci->devs[slot_id]->eps[ep_index];
439
440 /* A ring has pending URBs if its TD list is not empty */
441 if (!(ep->ep_state & EP_HAS_STREAMS)) {
442 if (ep->ring && !(list_empty(&ep->ring->td_list)))
443 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
444 return;
445 }
446
447 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
448 stream_id++) {
449 struct xhci_stream_info *stream_info = ep->stream_info;
450 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
451 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
452 stream_id);
453 }
454}
455
456/*
457 * Find the segment that trb is in. Start searching in start_seg.
458 * If we must move past a segment that has a link TRB with a toggle cycle state
459 * bit set, then we will toggle the value pointed at by cycle_state.
460 */
461static struct xhci_segment *find_trb_seg(
462 struct xhci_segment *start_seg,
463 union xhci_trb *trb, int *cycle_state)
464{
465 struct xhci_segment *cur_seg = start_seg;
466 struct xhci_generic_trb *generic_trb;
467
468 while (cur_seg->trbs > trb ||
469 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
470 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
471 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
472 *cycle_state ^= 0x1;
473 cur_seg = cur_seg->next;
474 if (cur_seg == start_seg)
475 /* Looped over the entire list. Oops! */
476 return NULL;
477 }
478 return cur_seg;
479}
480
481
482static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
483 unsigned int slot_id, unsigned int ep_index,
484 unsigned int stream_id)
485{
486 struct xhci_virt_ep *ep;
487
488 ep = &xhci->devs[slot_id]->eps[ep_index];
489 /* Common case: no streams */
490 if (!(ep->ep_state & EP_HAS_STREAMS))
491 return ep->ring;
492
493 if (stream_id == 0) {
494 xhci_warn(xhci,
495 "WARN: Slot ID %u, ep index %u has streams, "
496 "but URB has no stream ID.\n",
497 slot_id, ep_index);
498 return NULL;
499 }
500
501 if (stream_id < ep->stream_info->num_streams)
502 return ep->stream_info->stream_rings[stream_id];
503
504 xhci_warn(xhci,
505 "WARN: Slot ID %u, ep index %u has "
506 "stream IDs 1 to %u allocated, "
507 "but stream ID %u is requested.\n",
508 slot_id, ep_index,
509 ep->stream_info->num_streams - 1,
510 stream_id);
511 return NULL;
512}
513
514/* Get the right ring for the given URB.
515 * If the endpoint supports streams, boundary check the URB's stream ID.
516 * If the endpoint doesn't support streams, return the singular endpoint ring.
517 */
518static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
519 struct urb *urb)
520{
521 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
522 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
523}
524
525/*
526 * Move the xHC's endpoint ring dequeue pointer past cur_td.
527 * Record the new state of the xHC's endpoint ring dequeue segment,
528 * dequeue pointer, and new consumer cycle state in state.
529 * Update our internal representation of the ring's dequeue pointer.
530 *
531 * We do this in three jumps:
532 * - First we update our new ring state to be the same as when the xHC stopped.
533 * - Then we traverse the ring to find the segment that contains
534 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
535 * any link TRBs with the toggle cycle bit set.
536 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
537 * if we've moved it past a link TRB with the toggle cycle bit set.
538 *
539 * Some of the uses of xhci_generic_trb are grotty, but if they're done
540 * with correct __le32 accesses they should work fine. Only users of this are
541 * in here.
542 */
543void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
544 unsigned int slot_id, unsigned int ep_index,
545 unsigned int stream_id, struct xhci_td *cur_td,
546 struct xhci_dequeue_state *state)
547{
548 struct xhci_virt_device *dev = xhci->devs[slot_id];
549 struct xhci_virt_ep *ep = &dev->eps[ep_index];
550 struct xhci_ring *ep_ring;
551 struct xhci_generic_trb *trb;
552 dma_addr_t addr;
553 u64 hw_dequeue;
554
555 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
556 ep_index, stream_id);
557 if (!ep_ring) {
558 xhci_warn(xhci, "WARN can't find new dequeue state "
559 "for invalid stream ID %u.\n",
560 stream_id);
561 return;
562 }
563
564 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
565 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
566 "Finding endpoint context");
567 /* 4.6.9 the css flag is written to the stream context for streams */
568 if (ep->ep_state & EP_HAS_STREAMS) {
569 struct xhci_stream_ctx *ctx =
570 &ep->stream_info->stream_ctx_array[stream_id];
571 hw_dequeue = le64_to_cpu(ctx->stream_ring);
572 } else {
573 struct xhci_ep_ctx *ep_ctx
574 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
575 hw_dequeue = le64_to_cpu(ep_ctx->deq);
576 }
577
578 /* Find virtual address and segment of hardware dequeue pointer */
579 state->new_deq_seg = ep_ring->deq_seg;
580 state->new_deq_ptr = ep_ring->dequeue;
581 while (xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr)
582 != (dma_addr_t)(hw_dequeue & ~0xf)) {
583 next_trb(xhci, ep_ring, &state->new_deq_seg,
584 &state->new_deq_ptr);
585 if (state->new_deq_ptr == ep_ring->dequeue) {
586 WARN_ON(1);
587 return;
588 }
589 }
590 /*
591 * Find cycle state for last_trb, starting at old cycle state of
592 * hw_dequeue. If there is only one segment ring, find_trb_seg() will
593 * return immediately and cannot toggle the cycle state if this search
594 * wraps around, so add one more toggle manually in that case.
595 */
596 state->new_cycle_state = hw_dequeue & 0x1;
597 if (ep_ring->first_seg == ep_ring->first_seg->next &&
598 cur_td->last_trb < state->new_deq_ptr)
599 state->new_cycle_state ^= 0x1;
600
601 state->new_deq_ptr = cur_td->last_trb;
602 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
603 "Finding segment containing last TRB in TD.");
604 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
605 state->new_deq_ptr, &state->new_cycle_state);
606 if (!state->new_deq_seg) {
607 WARN_ON(1);
608 return;
609 }
610
611 /* Increment to find next TRB after last_trb. Cycle if appropriate. */
612 trb = &state->new_deq_ptr->generic;
613 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
614 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
615 state->new_cycle_state ^= 0x1;
616 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
617
618 /* Don't update the ring cycle state for the producer (us). */
619 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
620 "Cycle state = 0x%x", state->new_cycle_state);
621
622 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
623 "New dequeue segment = %p (virtual)",
624 state->new_deq_seg);
625 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
626 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
627 "New dequeue pointer = 0x%llx (DMA)",
628 (unsigned long long) addr);
629}
630
631/* flip_cycle means flip the cycle bit of all but the first and last TRB.
632 * (The last TRB actually points to the ring enqueue pointer, which is not part
633 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
634 */
635static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
636 struct xhci_td *cur_td, bool flip_cycle)
637{
638 struct xhci_segment *cur_seg;
639 union xhci_trb *cur_trb;
640
641 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
642 true;
643 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
644 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
645 /* Unchain any chained Link TRBs, but
646 * leave the pointers intact.
647 */
648 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
649 /* Flip the cycle bit (link TRBs can't be the first
650 * or last TRB).
651 */
652 if (flip_cycle)
653 cur_trb->generic.field[3] ^=
654 cpu_to_le32(TRB_CYCLE);
655 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
656 "Cancel (unchain) link TRB");
657 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
658 "Address = %p (0x%llx dma); "
659 "in seg %p (0x%llx dma)",
660 cur_trb,
661 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
662 cur_seg,
663 (unsigned long long)cur_seg->dma);
664 } else {
665 cur_trb->generic.field[0] = 0;
666 cur_trb->generic.field[1] = 0;
667 cur_trb->generic.field[2] = 0;
668 /* Preserve only the cycle bit of this TRB */
669 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
670 /* Flip the cycle bit except on the first or last TRB */
671 if (flip_cycle && cur_trb != cur_td->first_trb &&
672 cur_trb != cur_td->last_trb)
673 cur_trb->generic.field[3] ^=
674 cpu_to_le32(TRB_CYCLE);
675 cur_trb->generic.field[3] |= cpu_to_le32(
676 TRB_TYPE(TRB_TR_NOOP));
677 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
678 "TRB to noop at offset 0x%llx",
679 (unsigned long long)
680 xhci_trb_virt_to_dma(cur_seg, cur_trb));
681 }
682 if (cur_trb == cur_td->last_trb)
683 break;
684 }
685}
686
687static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
688 unsigned int ep_index, unsigned int stream_id,
689 struct xhci_segment *deq_seg,
690 union xhci_trb *deq_ptr, u32 cycle_state);
691
692void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
693 unsigned int slot_id, unsigned int ep_index,
694 unsigned int stream_id,
695 struct xhci_dequeue_state *deq_state)
696{
697 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
698
699 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
700 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
701 "new deq ptr = %p (0x%llx dma), new cycle = %u",
702 deq_state->new_deq_seg,
703 (unsigned long long)deq_state->new_deq_seg->dma,
704 deq_state->new_deq_ptr,
705 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
706 deq_state->new_cycle_state);
707 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
708 deq_state->new_deq_seg,
709 deq_state->new_deq_ptr,
710 (u32) deq_state->new_cycle_state);
711 /* Stop the TD queueing code from ringing the doorbell until
712 * this command completes. The HC won't set the dequeue pointer
713 * if the ring is running, and ringing the doorbell starts the
714 * ring running.
715 */
716 ep->ep_state |= SET_DEQ_PENDING;
717}
718
719static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
720 struct xhci_virt_ep *ep)
721{
722 ep->ep_state &= ~EP_HALT_PENDING;
723 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
724 * timer is running on another CPU, we don't decrement stop_cmds_pending
725 * (since we didn't successfully stop the watchdog timer).
726 */
727 if (del_timer(&ep->stop_cmd_timer))
728 ep->stop_cmds_pending--;
729}
730
731/* Must be called with xhci->lock held in interrupt context */
732static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
733 struct xhci_td *cur_td, int status)
734{
735 struct usb_hcd *hcd;
736 struct urb *urb;
737 struct urb_priv *urb_priv;
738
739 urb = cur_td->urb;
740 urb_priv = urb->hcpriv;
741 urb_priv->td_cnt++;
742 hcd = bus_to_hcd(urb->dev->bus);
743
744 /* Only giveback urb when this is the last td in urb */
745 if (urb_priv->td_cnt == urb_priv->length) {
746 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
747 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
748 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
749 if (xhci->quirks & XHCI_AMD_PLL_FIX)
750 usb_amd_quirk_pll_enable();
751 }
752 }
753 usb_hcd_unlink_urb_from_ep(hcd, urb);
754
755 spin_unlock(&xhci->lock);
756 usb_hcd_giveback_urb(hcd, urb, status);
757 xhci_urb_free_priv(xhci, urb_priv);
758 spin_lock(&xhci->lock);
759 }
760}
761
762/*
763 * When we get a command completion for a Stop Endpoint Command, we need to
764 * unlink any cancelled TDs from the ring. There are two ways to do that:
765 *
766 * 1. If the HW was in the middle of processing the TD that needs to be
767 * cancelled, then we must move the ring's dequeue pointer past the last TRB
768 * in the TD with a Set Dequeue Pointer Command.
769 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
770 * bit cleared) so that the HW will skip over them.
771 */
772static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
773 union xhci_trb *trb, struct xhci_event_cmd *event)
774{
775 unsigned int ep_index;
776 struct xhci_virt_device *virt_dev;
777 struct xhci_ring *ep_ring;
778 struct xhci_virt_ep *ep;
779 struct list_head *entry;
780 struct xhci_td *cur_td = NULL;
781 struct xhci_td *last_unlinked_td;
782
783 struct xhci_dequeue_state deq_state;
784
785 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
786 virt_dev = xhci->devs[slot_id];
787 if (virt_dev)
788 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
789 event);
790 else
791 xhci_warn(xhci, "Stop endpoint command "
792 "completion for disabled slot %u\n",
793 slot_id);
794 return;
795 }
796
797 memset(&deq_state, 0, sizeof(deq_state));
798 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
799 ep = &xhci->devs[slot_id]->eps[ep_index];
800
801 if (list_empty(&ep->cancelled_td_list)) {
802 xhci_stop_watchdog_timer_in_irq(xhci, ep);
803 ep->stopped_td = NULL;
804 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
805 return;
806 }
807
808 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
809 * We have the xHCI lock, so nothing can modify this list until we drop
810 * it. We're also in the event handler, so we can't get re-interrupted
811 * if another Stop Endpoint command completes
812 */
813 list_for_each(entry, &ep->cancelled_td_list) {
814 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
815 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
816 "Removing canceled TD starting at 0x%llx (dma).",
817 (unsigned long long)xhci_trb_virt_to_dma(
818 cur_td->start_seg, cur_td->first_trb));
819 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
820 if (!ep_ring) {
821 /* This shouldn't happen unless a driver is mucking
822 * with the stream ID after submission. This will
823 * leave the TD on the hardware ring, and the hardware
824 * will try to execute it, and may access a buffer
825 * that has already been freed. In the best case, the
826 * hardware will execute it, and the event handler will
827 * ignore the completion event for that TD, since it was
828 * removed from the td_list for that endpoint. In
829 * short, don't muck with the stream ID after
830 * submission.
831 */
832 xhci_warn(xhci, "WARN Cancelled URB %p "
833 "has invalid stream ID %u.\n",
834 cur_td->urb,
835 cur_td->urb->stream_id);
836 goto remove_finished_td;
837 }
838 /*
839 * If we stopped on the TD we need to cancel, then we have to
840 * move the xHC endpoint ring dequeue pointer past this TD.
841 */
842 if (cur_td == ep->stopped_td)
843 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
844 cur_td->urb->stream_id,
845 cur_td, &deq_state);
846 else
847 td_to_noop(xhci, ep_ring, cur_td, false);
848remove_finished_td:
849 /*
850 * The event handler won't see a completion for this TD anymore,
851 * so remove it from the endpoint ring's TD list. Keep it in
852 * the cancelled TD list for URB completion later.
853 */
854 list_del_init(&cur_td->td_list);
855 }
856 last_unlinked_td = cur_td;
857 xhci_stop_watchdog_timer_in_irq(xhci, ep);
858
859 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
860 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
861 xhci_queue_new_dequeue_state(xhci,
862 slot_id, ep_index,
863 ep->stopped_td->urb->stream_id,
864 &deq_state);
865 xhci_ring_cmd_db(xhci);
866 } else {
867 /* Otherwise ring the doorbell(s) to restart queued transfers */
868 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
869 }
870
871 /* Clear stopped_td if endpoint is not halted */
872 if (!(ep->ep_state & EP_HALTED))
873 ep->stopped_td = NULL;
874
875 /*
876 * Drop the lock and complete the URBs in the cancelled TD list.
877 * New TDs to be cancelled might be added to the end of the list before
878 * we can complete all the URBs for the TDs we already unlinked.
879 * So stop when we've completed the URB for the last TD we unlinked.
880 */
881 do {
882 cur_td = list_entry(ep->cancelled_td_list.next,
883 struct xhci_td, cancelled_td_list);
884 list_del_init(&cur_td->cancelled_td_list);
885
886 /* Clean up the cancelled URB */
887 /* Doesn't matter what we pass for status, since the core will
888 * just overwrite it (because the URB has been unlinked).
889 */
890 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
891
892 /* Stop processing the cancelled list if the watchdog timer is
893 * running.
894 */
895 if (xhci->xhc_state & XHCI_STATE_DYING)
896 return;
897 } while (cur_td != last_unlinked_td);
898
899 /* Return to the event handler with xhci->lock re-acquired */
900}
901
902static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
903{
904 struct xhci_td *cur_td;
905
906 while (!list_empty(&ring->td_list)) {
907 cur_td = list_first_entry(&ring->td_list,
908 struct xhci_td, td_list);
909 list_del_init(&cur_td->td_list);
910 if (!list_empty(&cur_td->cancelled_td_list))
911 list_del_init(&cur_td->cancelled_td_list);
912 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
913 }
914}
915
916static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
917 int slot_id, int ep_index)
918{
919 struct xhci_td *cur_td;
920 struct xhci_virt_ep *ep;
921 struct xhci_ring *ring;
922
923 ep = &xhci->devs[slot_id]->eps[ep_index];
924 if ((ep->ep_state & EP_HAS_STREAMS) ||
925 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
926 int stream_id;
927
928 for (stream_id = 0; stream_id < ep->stream_info->num_streams;
929 stream_id++) {
930 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
931 "Killing URBs for slot ID %u, ep index %u, stream %u",
932 slot_id, ep_index, stream_id + 1);
933 xhci_kill_ring_urbs(xhci,
934 ep->stream_info->stream_rings[stream_id]);
935 }
936 } else {
937 ring = ep->ring;
938 if (!ring)
939 return;
940 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
941 "Killing URBs for slot ID %u, ep index %u",
942 slot_id, ep_index);
943 xhci_kill_ring_urbs(xhci, ring);
944 }
945 while (!list_empty(&ep->cancelled_td_list)) {
946 cur_td = list_first_entry(&ep->cancelled_td_list,
947 struct xhci_td, cancelled_td_list);
948 list_del_init(&cur_td->cancelled_td_list);
949 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
950 }
951}
952
953/* Watchdog timer function for when a stop endpoint command fails to complete.
954 * In this case, we assume the host controller is broken or dying or dead. The
955 * host may still be completing some other events, so we have to be careful to
956 * let the event ring handler and the URB dequeueing/enqueueing functions know
957 * through xhci->state.
958 *
959 * The timer may also fire if the host takes a very long time to respond to the
960 * command, and the stop endpoint command completion handler cannot delete the
961 * timer before the timer function is called. Another endpoint cancellation may
962 * sneak in before the timer function can grab the lock, and that may queue
963 * another stop endpoint command and add the timer back. So we cannot use a
964 * simple flag to say whether there is a pending stop endpoint command for a
965 * particular endpoint.
966 *
967 * Instead we use a combination of that flag and a counter for the number of
968 * pending stop endpoint commands. If the timer is the tail end of the last
969 * stop endpoint command, and the endpoint's command is still pending, we assume
970 * the host is dying.
971 */
972void xhci_stop_endpoint_command_watchdog(unsigned long arg)
973{
974 struct xhci_hcd *xhci;
975 struct xhci_virt_ep *ep;
976 int ret, i, j;
977 unsigned long flags;
978
979 ep = (struct xhci_virt_ep *) arg;
980 xhci = ep->xhci;
981
982 spin_lock_irqsave(&xhci->lock, flags);
983
984 ep->stop_cmds_pending--;
985 if (xhci->xhc_state & XHCI_STATE_DYING) {
986 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
987 "Stop EP timer ran, but another timer marked "
988 "xHCI as DYING, exiting.");
989 spin_unlock_irqrestore(&xhci->lock, flags);
990 return;
991 }
992 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
993 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
994 "Stop EP timer ran, but no command pending, "
995 "exiting.");
996 spin_unlock_irqrestore(&xhci->lock, flags);
997 return;
998 }
999
1000 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
1001 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
1002 /* Oops, HC is dead or dying or at least not responding to the stop
1003 * endpoint command.
1004 */
1005 xhci->xhc_state |= XHCI_STATE_DYING;
1006 /* Disable interrupts from the host controller and start halting it */
1007 xhci_quiesce(xhci);
1008 spin_unlock_irqrestore(&xhci->lock, flags);
1009
1010 ret = xhci_halt(xhci);
1011
1012 spin_lock_irqsave(&xhci->lock, flags);
1013 if (ret < 0) {
1014 /* This is bad; the host is not responding to commands and it's
1015 * not allowing itself to be halted. At least interrupts are
1016 * disabled. If we call usb_hc_died(), it will attempt to
1017 * disconnect all device drivers under this host. Those
1018 * disconnect() methods will wait for all URBs to be unlinked,
1019 * so we must complete them.
1020 */
1021 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
1022 xhci_warn(xhci, "Completing active URBs anyway.\n");
1023 /* We could turn all TDs on the rings to no-ops. This won't
1024 * help if the host has cached part of the ring, and is slow if
1025 * we want to preserve the cycle bit. Skip it and hope the host
1026 * doesn't touch the memory.
1027 */
1028 }
1029 for (i = 0; i < MAX_HC_SLOTS; i++) {
1030 if (!xhci->devs[i])
1031 continue;
1032 for (j = 0; j < 31; j++)
1033 xhci_kill_endpoint_urbs(xhci, i, j);
1034 }
1035 spin_unlock_irqrestore(&xhci->lock, flags);
1036 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1037 "Calling usb_hc_died()");
1038 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1039 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1040 "xHCI host controller is dead.");
1041}
1042
1043
1044static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1045 struct xhci_virt_device *dev,
1046 struct xhci_ring *ep_ring,
1047 unsigned int ep_index)
1048{
1049 union xhci_trb *dequeue_temp;
1050 int num_trbs_free_temp;
1051 bool revert = false;
1052
1053 num_trbs_free_temp = ep_ring->num_trbs_free;
1054 dequeue_temp = ep_ring->dequeue;
1055
1056 /* If we get two back-to-back stalls, and the first stalled transfer
1057 * ends just before a link TRB, the dequeue pointer will be left on
1058 * the link TRB by the code in the while loop. So we have to update
1059 * the dequeue pointer one segment further, or we'll jump off
1060 * the segment into la-la-land.
1061 */
1062 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1063 ep_ring->deq_seg = ep_ring->deq_seg->next;
1064 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1065 }
1066
1067 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1068 /* We have more usable TRBs */
1069 ep_ring->num_trbs_free++;
1070 ep_ring->dequeue++;
1071 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1072 ep_ring->dequeue)) {
1073 if (ep_ring->dequeue ==
1074 dev->eps[ep_index].queued_deq_ptr)
1075 break;
1076 ep_ring->deq_seg = ep_ring->deq_seg->next;
1077 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1078 }
1079 if (ep_ring->dequeue == dequeue_temp) {
1080 revert = true;
1081 break;
1082 }
1083 }
1084
1085 if (revert) {
1086 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1087 ep_ring->num_trbs_free = num_trbs_free_temp;
1088 }
1089}
1090
1091/*
1092 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1093 * we need to clear the set deq pending flag in the endpoint ring state, so that
1094 * the TD queueing code can ring the doorbell again. We also need to ring the
1095 * endpoint doorbell to restart the ring, but only if there aren't more
1096 * cancellations pending.
1097 */
1098static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1099 union xhci_trb *trb, u32 cmd_comp_code)
1100{
1101 unsigned int ep_index;
1102 unsigned int stream_id;
1103 struct xhci_ring *ep_ring;
1104 struct xhci_virt_device *dev;
1105 struct xhci_virt_ep *ep;
1106 struct xhci_ep_ctx *ep_ctx;
1107 struct xhci_slot_ctx *slot_ctx;
1108
1109 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1110 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1111 dev = xhci->devs[slot_id];
1112 ep = &dev->eps[ep_index];
1113
1114 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1115 if (!ep_ring) {
1116 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1117 stream_id);
1118 /* XXX: Harmless??? */
1119 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1120 return;
1121 }
1122
1123 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1124 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1125
1126 if (cmd_comp_code != COMP_SUCCESS) {
1127 unsigned int ep_state;
1128 unsigned int slot_state;
1129
1130 switch (cmd_comp_code) {
1131 case COMP_TRB_ERR:
1132 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1133 break;
1134 case COMP_CTX_STATE:
1135 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1136 ep_state = le32_to_cpu(ep_ctx->ep_info);
1137 ep_state &= EP_STATE_MASK;
1138 slot_state = le32_to_cpu(slot_ctx->dev_state);
1139 slot_state = GET_SLOT_STATE(slot_state);
1140 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1141 "Slot state = %u, EP state = %u",
1142 slot_state, ep_state);
1143 break;
1144 case COMP_EBADSLT:
1145 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1146 slot_id);
1147 break;
1148 default:
1149 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1150 cmd_comp_code);
1151 break;
1152 }
1153 /* OK what do we do now? The endpoint state is hosed, and we
1154 * should never get to this point if the synchronization between
1155 * queueing, and endpoint state are correct. This might happen
1156 * if the device gets disconnected after we've finished
1157 * cancelling URBs, which might not be an error...
1158 */
1159 } else {
1160 u64 deq;
1161 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1162 if (ep->ep_state & EP_HAS_STREAMS) {
1163 struct xhci_stream_ctx *ctx =
1164 &ep->stream_info->stream_ctx_array[stream_id];
1165 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1166 } else {
1167 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1168 }
1169 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1170 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1171 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1172 ep->queued_deq_ptr) == deq) {
1173 /* Update the ring's dequeue segment and dequeue pointer
1174 * to reflect the new position.
1175 */
1176 update_ring_for_set_deq_completion(xhci, dev,
1177 ep_ring, ep_index);
1178 } else {
1179 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1180 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1181 ep->queued_deq_seg, ep->queued_deq_ptr);
1182 }
1183 }
1184
1185 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1186 dev->eps[ep_index].queued_deq_seg = NULL;
1187 dev->eps[ep_index].queued_deq_ptr = NULL;
1188 /* Restart any rings with pending URBs */
1189 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1190}
1191
1192static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1193 union xhci_trb *trb, u32 cmd_comp_code)
1194{
1195 unsigned int ep_index;
1196
1197 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1198 /* This command will only fail if the endpoint wasn't halted,
1199 * but we don't care.
1200 */
1201 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1202 "Ignoring reset ep completion code of %u", cmd_comp_code);
1203
1204 /* HW with the reset endpoint quirk needs to have a configure endpoint
1205 * command complete before the endpoint can be used. Queue that here
1206 * because the HW can't handle two commands being queued in a row.
1207 */
1208 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1209 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1210 "Queueing configure endpoint command");
1211 xhci_queue_configure_endpoint(xhci,
1212 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1213 false);
1214 xhci_ring_cmd_db(xhci);
1215 } else {
1216 /* Clear our internal halted state and restart the ring(s) */
1217 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1218 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1219 }
1220}
1221
1222/* Complete the command and detele it from the devcie's command queue.
1223 */
1224static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1225 struct xhci_command *command, u32 status)
1226{
1227 command->status = status;
1228 list_del(&command->cmd_list);
1229 if (command->completion)
1230 complete(command->completion);
1231 else
1232 xhci_free_command(xhci, command);
1233}
1234
1235
1236/* Check to see if a command in the device's command queue matches this one.
1237 * Signal the completion or free the command, and return 1. Return 0 if the
1238 * completed command isn't at the head of the command list.
1239 */
1240static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1241 struct xhci_virt_device *virt_dev,
1242 struct xhci_event_cmd *event)
1243{
1244 struct xhci_command *command;
1245
1246 if (list_empty(&virt_dev->cmd_list))
1247 return 0;
1248
1249 command = list_entry(virt_dev->cmd_list.next,
1250 struct xhci_command, cmd_list);
1251 if (xhci->cmd_ring->dequeue != command->command_trb)
1252 return 0;
1253
1254 xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1255 GET_COMP_CODE(le32_to_cpu(event->status)));
1256 return 1;
1257}
1258
1259/*
1260 * Finding the command trb need to be cancelled and modifying it to
1261 * NO OP command. And if the command is in device's command wait
1262 * list, finishing and freeing it.
1263 *
1264 * If we can't find the command trb, we think it had already been
1265 * executed.
1266 */
1267static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1268{
1269 struct xhci_segment *cur_seg;
1270 union xhci_trb *cmd_trb;
1271 u32 cycle_state;
1272
1273 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1274 return;
1275
1276 /* find the current segment of command ring */
1277 cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1278 xhci->cmd_ring->dequeue, &cycle_state);
1279
1280 if (!cur_seg) {
1281 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1282 xhci->cmd_ring->dequeue,
1283 (unsigned long long)
1284 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1285 xhci->cmd_ring->dequeue));
1286 xhci_debug_ring(xhci, xhci->cmd_ring);
1287 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1288 return;
1289 }
1290
1291 /* find the command trb matched by cd from command ring */
1292 for (cmd_trb = xhci->cmd_ring->dequeue;
1293 cmd_trb != xhci->cmd_ring->enqueue;
1294 next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1295 /* If the trb is link trb, continue */
1296 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1297 continue;
1298
1299 if (cur_cd->cmd_trb == cmd_trb) {
1300
1301 /* If the command in device's command list, we should
1302 * finish it and free the command structure.
1303 */
1304 if (cur_cd->command)
1305 xhci_complete_cmd_in_cmd_wait_list(xhci,
1306 cur_cd->command, COMP_CMD_STOP);
1307
1308 /* get cycle state from the origin command trb */
1309 cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1310 & TRB_CYCLE;
1311
1312 /* modify the command trb to NO OP command */
1313 cmd_trb->generic.field[0] = 0;
1314 cmd_trb->generic.field[1] = 0;
1315 cmd_trb->generic.field[2] = 0;
1316 cmd_trb->generic.field[3] = cpu_to_le32(
1317 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1318 break;
1319 }
1320 }
1321}
1322
1323static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1324{
1325 struct xhci_cd *cur_cd, *next_cd;
1326
1327 if (list_empty(&xhci->cancel_cmd_list))
1328 return;
1329
1330 list_for_each_entry_safe(cur_cd, next_cd,
1331 &xhci->cancel_cmd_list, cancel_cmd_list) {
1332 xhci_cmd_to_noop(xhci, cur_cd);
1333 list_del(&cur_cd->cancel_cmd_list);
1334 kfree(cur_cd);
1335 }
1336}
1337
1338/*
1339 * traversing the cancel_cmd_list. If the command descriptor according
1340 * to cmd_trb is found, the function free it and return 1, otherwise
1341 * return 0.
1342 */
1343static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1344 union xhci_trb *cmd_trb)
1345{
1346 struct xhci_cd *cur_cd, *next_cd;
1347
1348 if (list_empty(&xhci->cancel_cmd_list))
1349 return 0;
1350
1351 list_for_each_entry_safe(cur_cd, next_cd,
1352 &xhci->cancel_cmd_list, cancel_cmd_list) {
1353 if (cur_cd->cmd_trb == cmd_trb) {
1354 if (cur_cd->command)
1355 xhci_complete_cmd_in_cmd_wait_list(xhci,
1356 cur_cd->command, COMP_CMD_STOP);
1357 list_del(&cur_cd->cancel_cmd_list);
1358 kfree(cur_cd);
1359 return 1;
1360 }
1361 }
1362
1363 return 0;
1364}
1365
1366/*
1367 * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1368 * trb pointed by the command ring dequeue pointer is the trb we want to
1369 * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1370 * traverse the cancel_cmd_list to trun the all of the commands according
1371 * to command descriptor to NO-OP trb.
1372 */
1373static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1374 int cmd_trb_comp_code)
1375{
1376 int cur_trb_is_good = 0;
1377
1378 /* Searching the cmd trb pointed by the command ring dequeue
1379 * pointer in command descriptor list. If it is found, free it.
1380 */
1381 cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1382 xhci->cmd_ring->dequeue);
1383
1384 if (cmd_trb_comp_code == COMP_CMD_ABORT)
1385 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1386 else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1387 /* traversing the cancel_cmd_list and canceling
1388 * the command according to command descriptor
1389 */
1390 xhci_cancel_cmd_in_cd_list(xhci);
1391
1392 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1393 /*
1394 * ring command ring doorbell again to restart the
1395 * command ring
1396 */
1397 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1398 xhci_ring_cmd_db(xhci);
1399 }
1400 return cur_trb_is_good;
1401}
1402
1403static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1404 u32 cmd_comp_code)
1405{
1406 if (cmd_comp_code == COMP_SUCCESS)
1407 xhci->slot_id = slot_id;
1408 else
1409 xhci->slot_id = 0;
1410 complete(&xhci->addr_dev);
1411}
1412
1413static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1414{
1415 struct xhci_virt_device *virt_dev;
1416
1417 virt_dev = xhci->devs[slot_id];
1418 if (!virt_dev)
1419 return;
1420 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1421 /* Delete default control endpoint resources */
1422 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1423 xhci_free_virt_device(xhci, slot_id);
1424}
1425
1426static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1427 struct xhci_event_cmd *event, u32 cmd_comp_code)
1428{
1429 struct xhci_virt_device *virt_dev;
1430 struct xhci_input_control_ctx *ctrl_ctx;
1431 unsigned int ep_index;
1432 unsigned int ep_state;
1433 u32 add_flags, drop_flags;
1434
1435 virt_dev = xhci->devs[slot_id];
1436 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1437 return;
1438 /*
1439 * Configure endpoint commands can come from the USB core
1440 * configuration or alt setting changes, or because the HW
1441 * needed an extra configure endpoint command after a reset
1442 * endpoint command or streams were being configured.
1443 * If the command was for a halted endpoint, the xHCI driver
1444 * is not waiting on the configure endpoint command.
1445 */
1446 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1447 if (!ctrl_ctx) {
1448 xhci_warn(xhci, "Could not get input context, bad type.\n");
1449 return;
1450 }
1451
1452 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1453 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1454 /* Input ctx add_flags are the endpoint index plus one */
1455 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1456
1457 /* A usb_set_interface() call directly after clearing a halted
1458 * condition may race on this quirky hardware. Not worth
1459 * worrying about, since this is prototype hardware. Not sure
1460 * if this will work for streams, but streams support was
1461 * untested on this prototype.
1462 */
1463 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1464 ep_index != (unsigned int) -1 &&
1465 add_flags - SLOT_FLAG == drop_flags) {
1466 ep_state = virt_dev->eps[ep_index].ep_state;
1467 if (!(ep_state & EP_HALTED))
1468 goto bandwidth_change;
1469 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1470 "Completed config ep cmd - "
1471 "last ep index = %d, state = %d",
1472 ep_index, ep_state);
1473 /* Clear internal halted state and restart ring(s) */
1474 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1475 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1476 return;
1477 }
1478bandwidth_change:
1479 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1480 "Completed config ep cmd");
1481 virt_dev->cmd_status = cmd_comp_code;
1482 complete(&virt_dev->cmd_completion);
1483 return;
1484}
1485
1486static void xhci_handle_cmd_eval_ctx(struct xhci_hcd *xhci, int slot_id,
1487 struct xhci_event_cmd *event, u32 cmd_comp_code)
1488{
1489 struct xhci_virt_device *virt_dev;
1490
1491 virt_dev = xhci->devs[slot_id];
1492 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1493 return;
1494 virt_dev->cmd_status = cmd_comp_code;
1495 complete(&virt_dev->cmd_completion);
1496}
1497
1498static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id,
1499 u32 cmd_comp_code)
1500{
1501 xhci->devs[slot_id]->cmd_status = cmd_comp_code;
1502 complete(&xhci->addr_dev);
1503}
1504
1505static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1506 struct xhci_event_cmd *event)
1507{
1508 struct xhci_virt_device *virt_dev;
1509
1510 xhci_dbg(xhci, "Completed reset device command.\n");
1511 virt_dev = xhci->devs[slot_id];
1512 if (virt_dev)
1513 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1514 else
1515 xhci_warn(xhci, "Reset device command completion "
1516 "for disabled slot %u\n", slot_id);
1517}
1518
1519static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1520 struct xhci_event_cmd *event)
1521{
1522 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1523 xhci->error_bitmask |= 1 << 6;
1524 return;
1525 }
1526 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1527 "NEC firmware version %2x.%02x",
1528 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1529 NEC_FW_MINOR(le32_to_cpu(event->status)));
1530}
1531
1532static void handle_cmd_completion(struct xhci_hcd *xhci,
1533 struct xhci_event_cmd *event)
1534{
1535 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1536 u64 cmd_dma;
1537 dma_addr_t cmd_dequeue_dma;
1538 u32 cmd_comp_code;
1539 union xhci_trb *cmd_trb;
1540 u32 cmd_type;
1541
1542 cmd_dma = le64_to_cpu(event->cmd_trb);
1543 cmd_trb = xhci->cmd_ring->dequeue;
1544 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1545 cmd_trb);
1546 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1547 if (cmd_dequeue_dma == 0) {
1548 xhci->error_bitmask |= 1 << 4;
1549 return;
1550 }
1551 /* Does the DMA address match our internal dequeue pointer address? */
1552 if (cmd_dma != (u64) cmd_dequeue_dma) {
1553 xhci->error_bitmask |= 1 << 5;
1554 return;
1555 }
1556
1557 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1558
1559 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1560 if (cmd_comp_code == COMP_CMD_ABORT || cmd_comp_code == COMP_CMD_STOP) {
1561 /* If the return value is 0, we think the trb pointed by
1562 * command ring dequeue pointer is a good trb. The good
1563 * trb means we don't want to cancel the trb, but it have
1564 * been stopped by host. So we should handle it normally.
1565 * Otherwise, driver should invoke inc_deq() and return.
1566 */
1567 if (handle_stopped_cmd_ring(xhci, cmd_comp_code)) {
1568 inc_deq(xhci, xhci->cmd_ring);
1569 return;
1570 }
1571 /* There is no command to handle if we get a stop event when the
1572 * command ring is empty, event->cmd_trb points to the next
1573 * unset command
1574 */
1575 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1576 return;
1577 }
1578
1579 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1580 switch (cmd_type) {
1581 case TRB_ENABLE_SLOT:
1582 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1583 break;
1584 case TRB_DISABLE_SLOT:
1585 xhci_handle_cmd_disable_slot(xhci, slot_id);
1586 break;
1587 case TRB_CONFIG_EP:
1588 xhci_handle_cmd_config_ep(xhci, slot_id, event, cmd_comp_code);
1589 break;
1590 case TRB_EVAL_CONTEXT:
1591 xhci_handle_cmd_eval_ctx(xhci, slot_id, event, cmd_comp_code);
1592 break;
1593 case TRB_ADDR_DEV:
1594 xhci_handle_cmd_addr_dev(xhci, slot_id, cmd_comp_code);
1595 break;
1596 case TRB_STOP_RING:
1597 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1598 le32_to_cpu(cmd_trb->generic.field[3])));
1599 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1600 break;
1601 case TRB_SET_DEQ:
1602 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1603 le32_to_cpu(cmd_trb->generic.field[3])));
1604 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1605 break;
1606 case TRB_CMD_NOOP:
1607 break;
1608 case TRB_RESET_EP:
1609 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1610 le32_to_cpu(cmd_trb->generic.field[3])));
1611 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1612 break;
1613 case TRB_RESET_DEV:
1614 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1615 le32_to_cpu(cmd_trb->generic.field[3])));
1616 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1617 break;
1618 case TRB_NEC_GET_FW:
1619 xhci_handle_cmd_nec_get_fw(xhci, event);
1620 break;
1621 default:
1622 /* Skip over unknown commands on the event ring */
1623 xhci->error_bitmask |= 1 << 6;
1624 break;
1625 }
1626 inc_deq(xhci, xhci->cmd_ring);
1627}
1628
1629static void handle_vendor_event(struct xhci_hcd *xhci,
1630 union xhci_trb *event)
1631{
1632 u32 trb_type;
1633
1634 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1635 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1636 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1637 handle_cmd_completion(xhci, &event->event_cmd);
1638}
1639
1640/* @port_id: the one-based port ID from the hardware (indexed from array of all
1641 * port registers -- USB 3.0 and USB 2.0).
1642 *
1643 * Returns a zero-based port number, which is suitable for indexing into each of
1644 * the split roothubs' port arrays and bus state arrays.
1645 * Add one to it in order to call xhci_find_slot_id_by_port.
1646 */
1647static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1648 struct xhci_hcd *xhci, u32 port_id)
1649{
1650 unsigned int i;
1651 unsigned int num_similar_speed_ports = 0;
1652
1653 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1654 * and usb2_ports are 0-based indexes. Count the number of similar
1655 * speed ports, up to 1 port before this port.
1656 */
1657 for (i = 0; i < (port_id - 1); i++) {
1658 u8 port_speed = xhci->port_array[i];
1659
1660 /*
1661 * Skip ports that don't have known speeds, or have duplicate
1662 * Extended Capabilities port speed entries.
1663 */
1664 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1665 continue;
1666
1667 /*
1668 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1669 * 1.1 ports are under the USB 2.0 hub. If the port speed
1670 * matches the device speed, it's a similar speed port.
1671 */
1672 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1673 num_similar_speed_ports++;
1674 }
1675 return num_similar_speed_ports;
1676}
1677
1678static void handle_device_notification(struct xhci_hcd *xhci,
1679 union xhci_trb *event)
1680{
1681 u32 slot_id;
1682 struct usb_device *udev;
1683
1684 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1685 if (!xhci->devs[slot_id]) {
1686 xhci_warn(xhci, "Device Notification event for "
1687 "unused slot %u\n", slot_id);
1688 return;
1689 }
1690
1691 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1692 slot_id);
1693 udev = xhci->devs[slot_id]->udev;
1694 if (udev && udev->parent)
1695 usb_wakeup_notification(udev->parent, udev->portnum);
1696}
1697
1698static void handle_port_status(struct xhci_hcd *xhci,
1699 union xhci_trb *event)
1700{
1701 struct usb_hcd *hcd;
1702 u32 port_id;
1703 u32 temp, temp1;
1704 int max_ports;
1705 int slot_id;
1706 unsigned int faked_port_index;
1707 u8 major_revision;
1708 struct xhci_bus_state *bus_state;
1709 __le32 __iomem **port_array;
1710 bool bogus_port_status = false;
1711
1712 /* Port status change events always have a successful completion code */
1713 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1714 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1715 xhci->error_bitmask |= 1 << 8;
1716 }
1717 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1718 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1719
1720 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1721 if ((port_id <= 0) || (port_id > max_ports)) {
1722 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1723 inc_deq(xhci, xhci->event_ring);
1724 return;
1725 }
1726
1727 /* Figure out which usb_hcd this port is attached to:
1728 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1729 */
1730 major_revision = xhci->port_array[port_id - 1];
1731
1732 /* Find the right roothub. */
1733 hcd = xhci_to_hcd(xhci);
1734 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1735 hcd = xhci->shared_hcd;
1736
1737 if (major_revision == 0) {
1738 xhci_warn(xhci, "Event for port %u not in "
1739 "Extended Capabilities, ignoring.\n",
1740 port_id);
1741 bogus_port_status = true;
1742 goto cleanup;
1743 }
1744 if (major_revision == DUPLICATE_ENTRY) {
1745 xhci_warn(xhci, "Event for port %u duplicated in"
1746 "Extended Capabilities, ignoring.\n",
1747 port_id);
1748 bogus_port_status = true;
1749 goto cleanup;
1750 }
1751
1752 /*
1753 * Hardware port IDs reported by a Port Status Change Event include USB
1754 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1755 * resume event, but we first need to translate the hardware port ID
1756 * into the index into the ports on the correct split roothub, and the
1757 * correct bus_state structure.
1758 */
1759 bus_state = &xhci->bus_state[hcd_index(hcd)];
1760 if (hcd->speed == HCD_USB3)
1761 port_array = xhci->usb3_ports;
1762 else
1763 port_array = xhci->usb2_ports;
1764 /* Find the faked port hub number */
1765 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1766 port_id);
1767
1768 temp = readl(port_array[faked_port_index]);
1769 if (hcd->state == HC_STATE_SUSPENDED) {
1770 xhci_dbg(xhci, "resume root hub\n");
1771 usb_hcd_resume_root_hub(hcd);
1772 }
1773
1774 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1775 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1776
1777 temp1 = readl(&xhci->op_regs->command);
1778 if (!(temp1 & CMD_RUN)) {
1779 xhci_warn(xhci, "xHC is not running.\n");
1780 goto cleanup;
1781 }
1782
1783 if (DEV_SUPERSPEED(temp)) {
1784 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1785 /* Set a flag to say the port signaled remote wakeup,
1786 * so we can tell the difference between the end of
1787 * device and host initiated resume.
1788 */
1789 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1790 xhci_test_and_clear_bit(xhci, port_array,
1791 faked_port_index, PORT_PLC);
1792 xhci_set_link_state(xhci, port_array, faked_port_index,
1793 XDEV_U0);
1794 /* Need to wait until the next link state change
1795 * indicates the device is actually in U0.
1796 */
1797 bogus_port_status = true;
1798 goto cleanup;
1799 } else {
1800 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1801 bus_state->resume_done[faked_port_index] = jiffies +
1802 msecs_to_jiffies(20);
1803 set_bit(faked_port_index, &bus_state->resuming_ports);
1804 mod_timer(&hcd->rh_timer,
1805 bus_state->resume_done[faked_port_index]);
1806 /* Do the rest in GetPortStatus */
1807 }
1808 }
1809
1810 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1811 DEV_SUPERSPEED(temp)) {
1812 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1813 /* We've just brought the device into U0 through either the
1814 * Resume state after a device remote wakeup, or through the
1815 * U3Exit state after a host-initiated resume. If it's a device
1816 * initiated remote wake, don't pass up the link state change,
1817 * so the roothub behavior is consistent with external
1818 * USB 3.0 hub behavior.
1819 */
1820 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1821 faked_port_index + 1);
1822 if (slot_id && xhci->devs[slot_id])
1823 xhci_ring_device(xhci, slot_id);
1824 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1825 bus_state->port_remote_wakeup &=
1826 ~(1 << faked_port_index);
1827 xhci_test_and_clear_bit(xhci, port_array,
1828 faked_port_index, PORT_PLC);
1829 usb_wakeup_notification(hcd->self.root_hub,
1830 faked_port_index + 1);
1831 bogus_port_status = true;
1832 goto cleanup;
1833 }
1834 }
1835
1836 /*
1837 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1838 * RExit to a disconnect state). If so, let the the driver know it's
1839 * out of the RExit state.
1840 */
1841 if (!DEV_SUPERSPEED(temp) &&
1842 test_and_clear_bit(faked_port_index,
1843 &bus_state->rexit_ports)) {
1844 complete(&bus_state->rexit_done[faked_port_index]);
1845 bogus_port_status = true;
1846 goto cleanup;
1847 }
1848
1849 if (hcd->speed != HCD_USB3)
1850 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1851 PORT_PLC);
1852
1853cleanup:
1854 /* Update event ring dequeue pointer before dropping the lock */
1855 inc_deq(xhci, xhci->event_ring);
1856
1857 /* Don't make the USB core poll the roothub if we got a bad port status
1858 * change event. Besides, at that point we can't tell which roothub
1859 * (USB 2.0 or USB 3.0) to kick.
1860 */
1861 if (bogus_port_status)
1862 return;
1863
1864 /*
1865 * xHCI port-status-change events occur when the "or" of all the
1866 * status-change bits in the portsc register changes from 0 to 1.
1867 * New status changes won't cause an event if any other change
1868 * bits are still set. When an event occurs, switch over to
1869 * polling to avoid losing status changes.
1870 */
1871 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1872 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1873 spin_unlock(&xhci->lock);
1874 /* Pass this up to the core */
1875 usb_hcd_poll_rh_status(hcd);
1876 spin_lock(&xhci->lock);
1877}
1878
1879/*
1880 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1881 * at end_trb, which may be in another segment. If the suspect DMA address is a
1882 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1883 * returns 0.
1884 */
1885struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1886 union xhci_trb *start_trb,
1887 union xhci_trb *end_trb,
1888 dma_addr_t suspect_dma)
1889{
1890 dma_addr_t start_dma;
1891 dma_addr_t end_seg_dma;
1892 dma_addr_t end_trb_dma;
1893 struct xhci_segment *cur_seg;
1894
1895 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1896 cur_seg = start_seg;
1897
1898 do {
1899 if (start_dma == 0)
1900 return NULL;
1901 /* We may get an event for a Link TRB in the middle of a TD */
1902 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1903 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1904 /* If the end TRB isn't in this segment, this is set to 0 */
1905 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1906
1907 if (end_trb_dma > 0) {
1908 /* The end TRB is in this segment, so suspect should be here */
1909 if (start_dma <= end_trb_dma) {
1910 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1911 return cur_seg;
1912 } else {
1913 /* Case for one segment with
1914 * a TD wrapped around to the top
1915 */
1916 if ((suspect_dma >= start_dma &&
1917 suspect_dma <= end_seg_dma) ||
1918 (suspect_dma >= cur_seg->dma &&
1919 suspect_dma <= end_trb_dma))
1920 return cur_seg;
1921 }
1922 return NULL;
1923 } else {
1924 /* Might still be somewhere in this segment */
1925 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1926 return cur_seg;
1927 }
1928 cur_seg = cur_seg->next;
1929 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1930 } while (cur_seg != start_seg);
1931
1932 return NULL;
1933}
1934
1935static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1936 unsigned int slot_id, unsigned int ep_index,
1937 unsigned int stream_id,
1938 struct xhci_td *td, union xhci_trb *event_trb)
1939{
1940 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1941 ep->ep_state |= EP_HALTED;
1942 ep->stopped_td = td;
1943 ep->stopped_stream = stream_id;
1944
1945 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1946 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1947
1948 ep->stopped_td = NULL;
1949 ep->stopped_stream = 0;
1950
1951 xhci_ring_cmd_db(xhci);
1952}
1953
1954/* Check if an error has halted the endpoint ring. The class driver will
1955 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1956 * However, a babble and other errors also halt the endpoint ring, and the class
1957 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1958 * Ring Dequeue Pointer command manually.
1959 */
1960static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1961 struct xhci_ep_ctx *ep_ctx,
1962 unsigned int trb_comp_code)
1963{
1964 /* TRB completion codes that may require a manual halt cleanup */
1965 if (trb_comp_code == COMP_TX_ERR ||
1966 trb_comp_code == COMP_BABBLE ||
1967 trb_comp_code == COMP_SPLIT_ERR)
1968 /* The 0.96 spec says a babbling control endpoint
1969 * is not halted. The 0.96 spec says it is. Some HW
1970 * claims to be 0.95 compliant, but it halts the control
1971 * endpoint anyway. Check if a babble halted the
1972 * endpoint.
1973 */
1974 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1975 cpu_to_le32(EP_STATE_HALTED))
1976 return 1;
1977
1978 return 0;
1979}
1980
1981int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1982{
1983 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1984 /* Vendor defined "informational" completion code,
1985 * treat as not-an-error.
1986 */
1987 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1988 trb_comp_code);
1989 xhci_dbg(xhci, "Treating code as success.\n");
1990 return 1;
1991 }
1992 return 0;
1993}
1994
1995/*
1996 * Finish the td processing, remove the td from td list;
1997 * Return 1 if the urb can be given back.
1998 */
1999static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
2000 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2001 struct xhci_virt_ep *ep, int *status, bool skip)
2002{
2003 struct xhci_virt_device *xdev;
2004 struct xhci_ring *ep_ring;
2005 unsigned int slot_id;
2006 int ep_index;
2007 struct urb *urb = NULL;
2008 struct xhci_ep_ctx *ep_ctx;
2009 int ret = 0;
2010 struct urb_priv *urb_priv;
2011 u32 trb_comp_code;
2012
2013 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2014 xdev = xhci->devs[slot_id];
2015 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2016 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2017 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2018 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2019
2020 if (skip)
2021 goto td_cleanup;
2022
2023 if (trb_comp_code == COMP_STOP_INVAL ||
2024 trb_comp_code == COMP_STOP) {
2025 /* The Endpoint Stop Command completion will take care of any
2026 * stopped TDs. A stopped TD may be restarted, so don't update
2027 * the ring dequeue pointer or take this TD off any lists yet.
2028 */
2029 ep->stopped_td = td;
2030 return 0;
2031 } else {
2032 if (trb_comp_code == COMP_STALL) {
2033 /* The transfer is completed from the driver's
2034 * perspective, but we need to issue a set dequeue
2035 * command for this stalled endpoint to move the dequeue
2036 * pointer past the TD. We can't do that here because
2037 * the halt condition must be cleared first. Let the
2038 * USB class driver clear the stall later.
2039 */
2040 ep->stopped_td = td;
2041 ep->stopped_stream = ep_ring->stream_id;
2042 } else if (xhci_requires_manual_halt_cleanup(xhci,
2043 ep_ctx, trb_comp_code)) {
2044 /* Other types of errors halt the endpoint, but the
2045 * class driver doesn't call usb_reset_endpoint() unless
2046 * the error is -EPIPE. Clear the halted status in the
2047 * xHCI hardware manually.
2048 */
2049 xhci_cleanup_halted_endpoint(xhci,
2050 slot_id, ep_index, ep_ring->stream_id,
2051 td, event_trb);
2052 } else {
2053 /* Update ring dequeue pointer */
2054 while (ep_ring->dequeue != td->last_trb)
2055 inc_deq(xhci, ep_ring);
2056 inc_deq(xhci, ep_ring);
2057 }
2058
2059td_cleanup:
2060 /* Clean up the endpoint's TD list */
2061 urb = td->urb;
2062 urb_priv = urb->hcpriv;
2063
2064 /* Do one last check of the actual transfer length.
2065 * If the host controller said we transferred more data than
2066 * the buffer length, urb->actual_length will be a very big
2067 * number (since it's unsigned). Play it safe and say we didn't
2068 * transfer anything.
2069 */
2070 if (urb->actual_length > urb->transfer_buffer_length) {
2071 xhci_warn(xhci, "URB transfer length is wrong, "
2072 "xHC issue? req. len = %u, "
2073 "act. len = %u\n",
2074 urb->transfer_buffer_length,
2075 urb->actual_length);
2076 urb->actual_length = 0;
2077 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2078 *status = -EREMOTEIO;
2079 else
2080 *status = 0;
2081 }
2082 list_del_init(&td->td_list);
2083 /* Was this TD slated to be cancelled but completed anyway? */
2084 if (!list_empty(&td->cancelled_td_list))
2085 list_del_init(&td->cancelled_td_list);
2086
2087 urb_priv->td_cnt++;
2088 /* Giveback the urb when all the tds are completed */
2089 if (urb_priv->td_cnt == urb_priv->length) {
2090 ret = 1;
2091 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2092 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
2093 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
2094 == 0) {
2095 if (xhci->quirks & XHCI_AMD_PLL_FIX)
2096 usb_amd_quirk_pll_enable();
2097 }
2098 }
2099 }
2100 }
2101
2102 return ret;
2103}
2104
2105/*
2106 * Process control tds, update urb status and actual_length.
2107 */
2108static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2109 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2110 struct xhci_virt_ep *ep, int *status)
2111{
2112 struct xhci_virt_device *xdev;
2113 struct xhci_ring *ep_ring;
2114 unsigned int slot_id;
2115 int ep_index;
2116 struct xhci_ep_ctx *ep_ctx;
2117 u32 trb_comp_code;
2118
2119 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2120 xdev = xhci->devs[slot_id];
2121 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2122 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2123 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2124 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2125
2126 switch (trb_comp_code) {
2127 case COMP_SUCCESS:
2128 if (event_trb == ep_ring->dequeue) {
2129 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2130 "without IOC set??\n");
2131 *status = -ESHUTDOWN;
2132 } else if (event_trb != td->last_trb) {
2133 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2134 "without IOC set??\n");
2135 *status = -ESHUTDOWN;
2136 } else {
2137 *status = 0;
2138 }
2139 break;
2140 case COMP_SHORT_TX:
2141 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2142 *status = -EREMOTEIO;
2143 else
2144 *status = 0;
2145 break;
2146 case COMP_STOP_INVAL:
2147 case COMP_STOP:
2148 return finish_td(xhci, td, event_trb, event, ep, status, false);
2149 default:
2150 if (!xhci_requires_manual_halt_cleanup(xhci,
2151 ep_ctx, trb_comp_code))
2152 break;
2153 xhci_dbg(xhci, "TRB error code %u, "
2154 "halted endpoint index = %u\n",
2155 trb_comp_code, ep_index);
2156 /* else fall through */
2157 case COMP_STALL:
2158 /* Did we transfer part of the data (middle) phase? */
2159 if (event_trb != ep_ring->dequeue &&
2160 event_trb != td->last_trb)
2161 td->urb->actual_length =
2162 td->urb->transfer_buffer_length -
2163 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2164 else
2165 td->urb->actual_length = 0;
2166
2167 xhci_cleanup_halted_endpoint(xhci,
2168 slot_id, ep_index, 0, td, event_trb);
2169 return finish_td(xhci, td, event_trb, event, ep, status, true);
2170 }
2171 /*
2172 * Did we transfer any data, despite the errors that might have
2173 * happened? I.e. did we get past the setup stage?
2174 */
2175 if (event_trb != ep_ring->dequeue) {
2176 /* The event was for the status stage */
2177 if (event_trb == td->last_trb) {
2178 if (td->urb->actual_length != 0) {
2179 /* Don't overwrite a previously set error code
2180 */
2181 if ((*status == -EINPROGRESS || *status == 0) &&
2182 (td->urb->transfer_flags
2183 & URB_SHORT_NOT_OK))
2184 /* Did we already see a short data
2185 * stage? */
2186 *status = -EREMOTEIO;
2187 } else {
2188 td->urb->actual_length =
2189 td->urb->transfer_buffer_length;
2190 }
2191 } else {
2192 /* Maybe the event was for the data stage? */
2193 td->urb->actual_length =
2194 td->urb->transfer_buffer_length -
2195 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2196 xhci_dbg(xhci, "Waiting for status "
2197 "stage event\n");
2198 return 0;
2199 }
2200 }
2201
2202 return finish_td(xhci, td, event_trb, event, ep, status, false);
2203}
2204
2205/*
2206 * Process isochronous tds, update urb packet status and actual_length.
2207 */
2208static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2209 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2210 struct xhci_virt_ep *ep, int *status)
2211{
2212 struct xhci_ring *ep_ring;
2213 struct urb_priv *urb_priv;
2214 int idx;
2215 int len = 0;
2216 union xhci_trb *cur_trb;
2217 struct xhci_segment *cur_seg;
2218 struct usb_iso_packet_descriptor *frame;
2219 u32 trb_comp_code;
2220 bool skip_td = false;
2221
2222 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2223 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2224 urb_priv = td->urb->hcpriv;
2225 idx = urb_priv->td_cnt;
2226 frame = &td->urb->iso_frame_desc[idx];
2227
2228 /* handle completion code */
2229 switch (trb_comp_code) {
2230 case COMP_SUCCESS:
2231 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2232 frame->status = 0;
2233 break;
2234 }
2235 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2236 trb_comp_code = COMP_SHORT_TX;
2237 case COMP_SHORT_TX:
2238 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2239 -EREMOTEIO : 0;
2240 break;
2241 case COMP_BW_OVER:
2242 frame->status = -ECOMM;
2243 skip_td = true;
2244 break;
2245 case COMP_BUFF_OVER:
2246 case COMP_BABBLE:
2247 frame->status = -EOVERFLOW;
2248 skip_td = true;
2249 break;
2250 case COMP_DEV_ERR:
2251 case COMP_STALL:
2252 case COMP_TX_ERR:
2253 frame->status = -EPROTO;
2254 skip_td = true;
2255 break;
2256 case COMP_STOP:
2257 case COMP_STOP_INVAL:
2258 break;
2259 default:
2260 frame->status = -1;
2261 break;
2262 }
2263
2264 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2265 frame->actual_length = frame->length;
2266 td->urb->actual_length += frame->length;
2267 } else {
2268 for (cur_trb = ep_ring->dequeue,
2269 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2270 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2271 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2272 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2273 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2274 }
2275 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2276 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2277
2278 if (trb_comp_code != COMP_STOP_INVAL) {
2279 frame->actual_length = len;
2280 td->urb->actual_length += len;
2281 }
2282 }
2283
2284 return finish_td(xhci, td, event_trb, event, ep, status, false);
2285}
2286
2287static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2288 struct xhci_transfer_event *event,
2289 struct xhci_virt_ep *ep, int *status)
2290{
2291 struct xhci_ring *ep_ring;
2292 struct urb_priv *urb_priv;
2293 struct usb_iso_packet_descriptor *frame;
2294 int idx;
2295
2296 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2297 urb_priv = td->urb->hcpriv;
2298 idx = urb_priv->td_cnt;
2299 frame = &td->urb->iso_frame_desc[idx];
2300
2301 /* The transfer is partly done. */
2302 frame->status = -EXDEV;
2303
2304 /* calc actual length */
2305 frame->actual_length = 0;
2306
2307 /* Update ring dequeue pointer */
2308 while (ep_ring->dequeue != td->last_trb)
2309 inc_deq(xhci, ep_ring);
2310 inc_deq(xhci, ep_ring);
2311
2312 return finish_td(xhci, td, NULL, event, ep, status, true);
2313}
2314
2315/*
2316 * Process bulk and interrupt tds, update urb status and actual_length.
2317 */
2318static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2319 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2320 struct xhci_virt_ep *ep, int *status)
2321{
2322 struct xhci_ring *ep_ring;
2323 union xhci_trb *cur_trb;
2324 struct xhci_segment *cur_seg;
2325 u32 trb_comp_code;
2326
2327 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2328 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2329
2330 switch (trb_comp_code) {
2331 case COMP_SUCCESS:
2332 /* Double check that the HW transferred everything. */
2333 if (event_trb != td->last_trb ||
2334 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2335 xhci_warn(xhci, "WARN Successful completion "
2336 "on short TX\n");
2337 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2338 *status = -EREMOTEIO;
2339 else
2340 *status = 0;
2341 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2342 trb_comp_code = COMP_SHORT_TX;
2343 } else {
2344 *status = 0;
2345 }
2346 break;
2347 case COMP_SHORT_TX:
2348 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2349 *status = -EREMOTEIO;
2350 else
2351 *status = 0;
2352 break;
2353 default:
2354 /* Others already handled above */
2355 break;
2356 }
2357 if (trb_comp_code == COMP_SHORT_TX)
2358 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2359 "%d bytes untransferred\n",
2360 td->urb->ep->desc.bEndpointAddress,
2361 td->urb->transfer_buffer_length,
2362 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2363 /* Fast path - was this the last TRB in the TD for this URB? */
2364 if (event_trb == td->last_trb) {
2365 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2366 td->urb->actual_length =
2367 td->urb->transfer_buffer_length -
2368 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2369 if (td->urb->transfer_buffer_length <
2370 td->urb->actual_length) {
2371 xhci_warn(xhci, "HC gave bad length "
2372 "of %d bytes left\n",
2373 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2374 td->urb->actual_length = 0;
2375 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2376 *status = -EREMOTEIO;
2377 else
2378 *status = 0;
2379 }
2380 /* Don't overwrite a previously set error code */
2381 if (*status == -EINPROGRESS) {
2382 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2383 *status = -EREMOTEIO;
2384 else
2385 *status = 0;
2386 }
2387 } else {
2388 td->urb->actual_length =
2389 td->urb->transfer_buffer_length;
2390 /* Ignore a short packet completion if the
2391 * untransferred length was zero.
2392 */
2393 if (*status == -EREMOTEIO)
2394 *status = 0;
2395 }
2396 } else {
2397 /* Slow path - walk the list, starting from the dequeue
2398 * pointer, to get the actual length transferred.
2399 */
2400 td->urb->actual_length = 0;
2401 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2402 cur_trb != event_trb;
2403 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2404 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2405 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2406 td->urb->actual_length +=
2407 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2408 }
2409 /* If the ring didn't stop on a Link or No-op TRB, add
2410 * in the actual bytes transferred from the Normal TRB
2411 */
2412 if (trb_comp_code != COMP_STOP_INVAL)
2413 td->urb->actual_length +=
2414 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2415 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2416 }
2417
2418 return finish_td(xhci, td, event_trb, event, ep, status, false);
2419}
2420
2421/*
2422 * If this function returns an error condition, it means it got a Transfer
2423 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2424 * At this point, the host controller is probably hosed and should be reset.
2425 */
2426static int handle_tx_event(struct xhci_hcd *xhci,
2427 struct xhci_transfer_event *event)
2428 __releases(&xhci->lock)
2429 __acquires(&xhci->lock)
2430{
2431 struct xhci_virt_device *xdev;
2432 struct xhci_virt_ep *ep;
2433 struct xhci_ring *ep_ring;
2434 unsigned int slot_id;
2435 int ep_index;
2436 struct xhci_td *td = NULL;
2437 dma_addr_t event_dma;
2438 struct xhci_segment *event_seg;
2439 union xhci_trb *event_trb;
2440 struct urb *urb = NULL;
2441 int status = -EINPROGRESS;
2442 struct urb_priv *urb_priv;
2443 struct xhci_ep_ctx *ep_ctx;
2444 struct list_head *tmp;
2445 u32 trb_comp_code;
2446 int ret = 0;
2447 int td_num = 0;
2448
2449 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2450 xdev = xhci->devs[slot_id];
2451 if (!xdev) {
2452 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2453 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2454 (unsigned long long) xhci_trb_virt_to_dma(
2455 xhci->event_ring->deq_seg,
2456 xhci->event_ring->dequeue),
2457 lower_32_bits(le64_to_cpu(event->buffer)),
2458 upper_32_bits(le64_to_cpu(event->buffer)),
2459 le32_to_cpu(event->transfer_len),
2460 le32_to_cpu(event->flags));
2461 xhci_dbg(xhci, "Event ring:\n");
2462 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2463 return -ENODEV;
2464 }
2465
2466 /* Endpoint ID is 1 based, our index is zero based */
2467 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2468 ep = &xdev->eps[ep_index];
2469 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2470 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2471 if (!ep_ring ||
2472 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2473 EP_STATE_DISABLED) {
2474 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2475 "or incorrect stream ring\n");
2476 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2477 (unsigned long long) xhci_trb_virt_to_dma(
2478 xhci->event_ring->deq_seg,
2479 xhci->event_ring->dequeue),
2480 lower_32_bits(le64_to_cpu(event->buffer)),
2481 upper_32_bits(le64_to_cpu(event->buffer)),
2482 le32_to_cpu(event->transfer_len),
2483 le32_to_cpu(event->flags));
2484 xhci_dbg(xhci, "Event ring:\n");
2485 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2486 return -ENODEV;
2487 }
2488
2489 /* Count current td numbers if ep->skip is set */
2490 if (ep->skip) {
2491 list_for_each(tmp, &ep_ring->td_list)
2492 td_num++;
2493 }
2494
2495 event_dma = le64_to_cpu(event->buffer);
2496 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2497 /* Look for common error cases */
2498 switch (trb_comp_code) {
2499 /* Skip codes that require special handling depending on
2500 * transfer type
2501 */
2502 case COMP_SUCCESS:
2503 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2504 break;
2505 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2506 trb_comp_code = COMP_SHORT_TX;
2507 else
2508 xhci_warn_ratelimited(xhci,
2509 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2510 case COMP_SHORT_TX:
2511 break;
2512 case COMP_STOP:
2513 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2514 break;
2515 case COMP_STOP_INVAL:
2516 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2517 break;
2518 case COMP_STALL:
2519 xhci_dbg(xhci, "Stalled endpoint\n");
2520 ep->ep_state |= EP_HALTED;
2521 status = -EPIPE;
2522 break;
2523 case COMP_TRB_ERR:
2524 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2525 status = -EILSEQ;
2526 break;
2527 case COMP_SPLIT_ERR:
2528 case COMP_TX_ERR:
2529 xhci_dbg(xhci, "Transfer error on endpoint\n");
2530 status = -EPROTO;
2531 break;
2532 case COMP_BABBLE:
2533 xhci_dbg(xhci, "Babble error on endpoint\n");
2534 status = -EOVERFLOW;
2535 break;
2536 case COMP_DB_ERR:
2537 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2538 status = -ENOSR;
2539 break;
2540 case COMP_BW_OVER:
2541 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2542 break;
2543 case COMP_BUFF_OVER:
2544 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2545 break;
2546 case COMP_UNDERRUN:
2547 /*
2548 * When the Isoch ring is empty, the xHC will generate
2549 * a Ring Overrun Event for IN Isoch endpoint or Ring
2550 * Underrun Event for OUT Isoch endpoint.
2551 */
2552 xhci_dbg(xhci, "underrun event on endpoint\n");
2553 if (!list_empty(&ep_ring->td_list))
2554 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2555 "still with TDs queued?\n",
2556 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2557 ep_index);
2558 goto cleanup;
2559 case COMP_OVERRUN:
2560 xhci_dbg(xhci, "overrun event on endpoint\n");
2561 if (!list_empty(&ep_ring->td_list))
2562 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2563 "still with TDs queued?\n",
2564 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2565 ep_index);
2566 goto cleanup;
2567 case COMP_DEV_ERR:
2568 xhci_warn(xhci, "WARN: detect an incompatible device");
2569 status = -EPROTO;
2570 break;
2571 case COMP_MISSED_INT:
2572 /*
2573 * When encounter missed service error, one or more isoc tds
2574 * may be missed by xHC.
2575 * Set skip flag of the ep_ring; Complete the missed tds as
2576 * short transfer when process the ep_ring next time.
2577 */
2578 ep->skip = true;
2579 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2580 goto cleanup;
2581 default:
2582 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2583 status = 0;
2584 break;
2585 }
2586 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2587 "busted\n");
2588 goto cleanup;
2589 }
2590
2591 do {
2592 /* This TRB should be in the TD at the head of this ring's
2593 * TD list.
2594 */
2595 if (list_empty(&ep_ring->td_list)) {
2596 /*
2597 * A stopped endpoint may generate an extra completion
2598 * event if the device was suspended. Don't print
2599 * warnings.
2600 */
2601 if (!(trb_comp_code == COMP_STOP ||
2602 trb_comp_code == COMP_STOP_INVAL)) {
2603 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2604 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2605 ep_index);
2606 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2607 (le32_to_cpu(event->flags) &
2608 TRB_TYPE_BITMASK)>>10);
2609 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2610 }
2611 if (ep->skip) {
2612 ep->skip = false;
2613 xhci_dbg(xhci, "td_list is empty while skip "
2614 "flag set. Clear skip flag.\n");
2615 }
2616 ret = 0;
2617 goto cleanup;
2618 }
2619
2620 /* We've skipped all the TDs on the ep ring when ep->skip set */
2621 if (ep->skip && td_num == 0) {
2622 ep->skip = false;
2623 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2624 "Clear skip flag.\n");
2625 ret = 0;
2626 goto cleanup;
2627 }
2628
2629 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2630 if (ep->skip)
2631 td_num--;
2632
2633 /* Is this a TRB in the currently executing TD? */
2634 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2635 td->last_trb, event_dma);
2636
2637 /*
2638 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2639 * is not in the current TD pointed by ep_ring->dequeue because
2640 * that the hardware dequeue pointer still at the previous TRB
2641 * of the current TD. The previous TRB maybe a Link TD or the
2642 * last TRB of the previous TD. The command completion handle
2643 * will take care the rest.
2644 */
2645 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2646 ret = 0;
2647 goto cleanup;
2648 }
2649
2650 if (!event_seg) {
2651 if (!ep->skip ||
2652 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2653 /* Some host controllers give a spurious
2654 * successful event after a short transfer.
2655 * Ignore it.
2656 */
2657 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2658 ep_ring->last_td_was_short) {
2659 ep_ring->last_td_was_short = false;
2660 ret = 0;
2661 goto cleanup;
2662 }
2663 /* HC is busted, give up! */
2664 xhci_err(xhci,
2665 "ERROR Transfer event TRB DMA ptr not "
2666 "part of current TD\n");
2667 return -ESHUTDOWN;
2668 }
2669
2670 ret = skip_isoc_td(xhci, td, event, ep, &status);
2671 goto cleanup;
2672 }
2673 if (trb_comp_code == COMP_SHORT_TX)
2674 ep_ring->last_td_was_short = true;
2675 else
2676 ep_ring->last_td_was_short = false;
2677
2678 if (ep->skip) {
2679 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2680 ep->skip = false;
2681 }
2682
2683 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2684 sizeof(*event_trb)];
2685 /*
2686 * No-op TRB should not trigger interrupts.
2687 * If event_trb is a no-op TRB, it means the
2688 * corresponding TD has been cancelled. Just ignore
2689 * the TD.
2690 */
2691 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2692 xhci_dbg(xhci,
2693 "event_trb is a no-op TRB. Skip it\n");
2694 goto cleanup;
2695 }
2696
2697 /* Now update the urb's actual_length and give back to
2698 * the core
2699 */
2700 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2701 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2702 &status);
2703 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2704 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2705 &status);
2706 else
2707 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2708 ep, &status);
2709
2710cleanup:
2711 /*
2712 * Do not update event ring dequeue pointer if ep->skip is set.
2713 * Will roll back to continue process missed tds.
2714 */
2715 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2716 inc_deq(xhci, xhci->event_ring);
2717 }
2718
2719 if (ret) {
2720 urb = td->urb;
2721 urb_priv = urb->hcpriv;
2722 /* Leave the TD around for the reset endpoint function
2723 * to use(but only if it's not a control endpoint,
2724 * since we already queued the Set TR dequeue pointer
2725 * command for stalled control endpoints).
2726 */
2727 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2728 (trb_comp_code != COMP_STALL &&
2729 trb_comp_code != COMP_BABBLE))
2730 xhci_urb_free_priv(xhci, urb_priv);
2731 else
2732 kfree(urb_priv);
2733
2734 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2735 if ((urb->actual_length != urb->transfer_buffer_length &&
2736 (urb->transfer_flags &
2737 URB_SHORT_NOT_OK)) ||
2738 (status != 0 &&
2739 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2740 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2741 "expected = %d, status = %d\n",
2742 urb, urb->actual_length,
2743 urb->transfer_buffer_length,
2744 status);
2745 spin_unlock(&xhci->lock);
2746 /* EHCI, UHCI, and OHCI always unconditionally set the
2747 * urb->status of an isochronous endpoint to 0.
2748 */
2749 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2750 status = 0;
2751 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2752 spin_lock(&xhci->lock);
2753 }
2754
2755 /*
2756 * If ep->skip is set, it means there are missed tds on the
2757 * endpoint ring need to take care of.
2758 * Process them as short transfer until reach the td pointed by
2759 * the event.
2760 */
2761 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2762
2763 return 0;
2764}
2765
2766/*
2767 * This function handles all OS-owned events on the event ring. It may drop
2768 * xhci->lock between event processing (e.g. to pass up port status changes).
2769 * Returns >0 for "possibly more events to process" (caller should call again),
2770 * otherwise 0 if done. In future, <0 returns should indicate error code.
2771 */
2772static int xhci_handle_event(struct xhci_hcd *xhci)
2773{
2774 union xhci_trb *event;
2775 int update_ptrs = 1;
2776 int ret;
2777
2778 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2779 xhci->error_bitmask |= 1 << 1;
2780 return 0;
2781 }
2782
2783 event = xhci->event_ring->dequeue;
2784 /* Does the HC or OS own the TRB? */
2785 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2786 xhci->event_ring->cycle_state) {
2787 xhci->error_bitmask |= 1 << 2;
2788 return 0;
2789 }
2790
2791 /*
2792 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2793 * speculative reads of the event's flags/data below.
2794 */
2795 rmb();
2796 /* FIXME: Handle more event types. */
2797 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2798 case TRB_TYPE(TRB_COMPLETION):
2799 handle_cmd_completion(xhci, &event->event_cmd);
2800 break;
2801 case TRB_TYPE(TRB_PORT_STATUS):
2802 handle_port_status(xhci, event);
2803 update_ptrs = 0;
2804 break;
2805 case TRB_TYPE(TRB_TRANSFER):
2806 ret = handle_tx_event(xhci, &event->trans_event);
2807 if (ret < 0)
2808 xhci->error_bitmask |= 1 << 9;
2809 else
2810 update_ptrs = 0;
2811 break;
2812 case TRB_TYPE(TRB_DEV_NOTE):
2813 handle_device_notification(xhci, event);
2814 break;
2815 default:
2816 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2817 TRB_TYPE(48))
2818 handle_vendor_event(xhci, event);
2819 else
2820 xhci->error_bitmask |= 1 << 3;
2821 }
2822 /* Any of the above functions may drop and re-acquire the lock, so check
2823 * to make sure a watchdog timer didn't mark the host as non-responsive.
2824 */
2825 if (xhci->xhc_state & XHCI_STATE_DYING) {
2826 xhci_dbg(xhci, "xHCI host dying, returning from "
2827 "event handler.\n");
2828 return 0;
2829 }
2830
2831 if (update_ptrs)
2832 /* Update SW event ring dequeue pointer */
2833 inc_deq(xhci, xhci->event_ring);
2834
2835 /* Are there more items on the event ring? Caller will call us again to
2836 * check.
2837 */
2838 return 1;
2839}
2840
2841/*
2842 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2843 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2844 * indicators of an event TRB error, but we check the status *first* to be safe.
2845 */
2846irqreturn_t xhci_irq(struct usb_hcd *hcd)
2847{
2848 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2849 u32 status;
2850 u64 temp_64;
2851 union xhci_trb *event_ring_deq;
2852 dma_addr_t deq;
2853
2854 spin_lock(&xhci->lock);
2855 /* Check if the xHC generated the interrupt, or the irq is shared */
2856 status = readl(&xhci->op_regs->status);
2857 if (status == 0xffffffff)
2858 goto hw_died;
2859
2860 if (!(status & STS_EINT)) {
2861 spin_unlock(&xhci->lock);
2862 return IRQ_NONE;
2863 }
2864 if (status & STS_FATAL) {
2865 xhci_warn(xhci, "WARNING: Host System Error\n");
2866 xhci_halt(xhci);
2867hw_died:
2868 spin_unlock(&xhci->lock);
2869 return -ESHUTDOWN;
2870 }
2871
2872 /*
2873 * Clear the op reg interrupt status first,
2874 * so we can receive interrupts from other MSI-X interrupters.
2875 * Write 1 to clear the interrupt status.
2876 */
2877 status |= STS_EINT;
2878 writel(status, &xhci->op_regs->status);
2879 /* FIXME when MSI-X is supported and there are multiple vectors */
2880 /* Clear the MSI-X event interrupt status */
2881
2882 if (hcd->irq) {
2883 u32 irq_pending;
2884 /* Acknowledge the PCI interrupt */
2885 irq_pending = readl(&xhci->ir_set->irq_pending);
2886 irq_pending |= IMAN_IP;
2887 writel(irq_pending, &xhci->ir_set->irq_pending);
2888 }
2889
2890 if (xhci->xhc_state & XHCI_STATE_DYING) {
2891 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2892 "Shouldn't IRQs be disabled?\n");
2893 /* Clear the event handler busy flag (RW1C);
2894 * the event ring should be empty.
2895 */
2896 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2897 xhci_write_64(xhci, temp_64 | ERST_EHB,
2898 &xhci->ir_set->erst_dequeue);
2899 spin_unlock(&xhci->lock);
2900
2901 return IRQ_HANDLED;
2902 }
2903
2904 event_ring_deq = xhci->event_ring->dequeue;
2905 /* FIXME this should be a delayed service routine
2906 * that clears the EHB.
2907 */
2908 while (xhci_handle_event(xhci) > 0) {}
2909
2910 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2911 /* If necessary, update the HW's version of the event ring deq ptr. */
2912 if (event_ring_deq != xhci->event_ring->dequeue) {
2913 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2914 xhci->event_ring->dequeue);
2915 if (deq == 0)
2916 xhci_warn(xhci, "WARN something wrong with SW event "
2917 "ring dequeue ptr.\n");
2918 /* Update HC event ring dequeue pointer */
2919 temp_64 &= ERST_PTR_MASK;
2920 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2921 }
2922
2923 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2924 temp_64 |= ERST_EHB;
2925 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2926
2927 spin_unlock(&xhci->lock);
2928
2929 return IRQ_HANDLED;
2930}
2931
2932irqreturn_t xhci_msi_irq(int irq, void *hcd)
2933{
2934 return xhci_irq(hcd);
2935}
2936
2937/**** Endpoint Ring Operations ****/
2938
2939/*
2940 * Generic function for queueing a TRB on a ring.
2941 * The caller must have checked to make sure there's room on the ring.
2942 *
2943 * @more_trbs_coming: Will you enqueue more TRBs before calling
2944 * prepare_transfer()?
2945 */
2946static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2947 bool more_trbs_coming,
2948 u32 field1, u32 field2, u32 field3, u32 field4)
2949{
2950 struct xhci_generic_trb *trb;
2951
2952 trb = &ring->enqueue->generic;
2953 trb->field[0] = cpu_to_le32(field1);
2954 trb->field[1] = cpu_to_le32(field2);
2955 trb->field[2] = cpu_to_le32(field3);
2956 trb->field[3] = cpu_to_le32(field4);
2957 inc_enq(xhci, ring, more_trbs_coming);
2958}
2959
2960/*
2961 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2962 * FIXME allocate segments if the ring is full.
2963 */
2964static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2965 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2966{
2967 unsigned int num_trbs_needed;
2968
2969 /* Make sure the endpoint has been added to xHC schedule */
2970 switch (ep_state) {
2971 case EP_STATE_DISABLED:
2972 /*
2973 * USB core changed config/interfaces without notifying us,
2974 * or hardware is reporting the wrong state.
2975 */
2976 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2977 return -ENOENT;
2978 case EP_STATE_ERROR:
2979 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2980 /* FIXME event handling code for error needs to clear it */
2981 /* XXX not sure if this should be -ENOENT or not */
2982 return -EINVAL;
2983 case EP_STATE_HALTED:
2984 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2985 case EP_STATE_STOPPED:
2986 case EP_STATE_RUNNING:
2987 break;
2988 default:
2989 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2990 /*
2991 * FIXME issue Configure Endpoint command to try to get the HC
2992 * back into a known state.
2993 */
2994 return -EINVAL;
2995 }
2996
2997 while (1) {
2998 if (room_on_ring(xhci, ep_ring, num_trbs))
2999 break;
3000
3001 if (ep_ring == xhci->cmd_ring) {
3002 xhci_err(xhci, "Do not support expand command ring\n");
3003 return -ENOMEM;
3004 }
3005
3006 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3007 "ERROR no room on ep ring, try ring expansion");
3008 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3009 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3010 mem_flags)) {
3011 xhci_err(xhci, "Ring expansion failed\n");
3012 return -ENOMEM;
3013 }
3014 }
3015
3016 if (enqueue_is_link_trb(ep_ring)) {
3017 struct xhci_ring *ring = ep_ring;
3018 union xhci_trb *next;
3019
3020 next = ring->enqueue;
3021
3022 while (last_trb(xhci, ring, ring->enq_seg, next)) {
3023 /* If we're not dealing with 0.95 hardware or isoc rings
3024 * on AMD 0.96 host, clear the chain bit.
3025 */
3026 if (!xhci_link_trb_quirk(xhci) &&
3027 !(ring->type == TYPE_ISOC &&
3028 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3029 next->link.control &= cpu_to_le32(~TRB_CHAIN);
3030 else
3031 next->link.control |= cpu_to_le32(TRB_CHAIN);
3032
3033 wmb();
3034 next->link.control ^= cpu_to_le32(TRB_CYCLE);
3035
3036 /* Toggle the cycle bit after the last ring segment. */
3037 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
3038 ring->cycle_state = (ring->cycle_state ? 0 : 1);
3039 }
3040 ring->enq_seg = ring->enq_seg->next;
3041 ring->enqueue = ring->enq_seg->trbs;
3042 next = ring->enqueue;
3043 }
3044 }
3045
3046 return 0;
3047}
3048
3049static int prepare_transfer(struct xhci_hcd *xhci,
3050 struct xhci_virt_device *xdev,
3051 unsigned int ep_index,
3052 unsigned int stream_id,
3053 unsigned int num_trbs,
3054 struct urb *urb,
3055 unsigned int td_index,
3056 gfp_t mem_flags)
3057{
3058 int ret;
3059 struct urb_priv *urb_priv;
3060 struct xhci_td *td;
3061 struct xhci_ring *ep_ring;
3062 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3063
3064 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
3065 if (!ep_ring) {
3066 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3067 stream_id);
3068 return -EINVAL;
3069 }
3070
3071 ret = prepare_ring(xhci, ep_ring,
3072 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3073 num_trbs, mem_flags);
3074 if (ret)
3075 return ret;
3076
3077 urb_priv = urb->hcpriv;
3078 td = urb_priv->td[td_index];
3079
3080 INIT_LIST_HEAD(&td->td_list);
3081 INIT_LIST_HEAD(&td->cancelled_td_list);
3082
3083 if (td_index == 0) {
3084 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3085 if (unlikely(ret))
3086 return ret;
3087 }
3088
3089 td->urb = urb;
3090 /* Add this TD to the tail of the endpoint ring's TD list */
3091 list_add_tail(&td->td_list, &ep_ring->td_list);
3092 td->start_seg = ep_ring->enq_seg;
3093 td->first_trb = ep_ring->enqueue;
3094
3095 urb_priv->td[td_index] = td;
3096
3097 return 0;
3098}
3099
3100static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
3101{
3102 int num_sgs, num_trbs, running_total, temp, i;
3103 struct scatterlist *sg;
3104
3105 sg = NULL;
3106 num_sgs = urb->num_mapped_sgs;
3107 temp = urb->transfer_buffer_length;
3108
3109 num_trbs = 0;
3110 for_each_sg(urb->sg, sg, num_sgs, i) {
3111 unsigned int len = sg_dma_len(sg);
3112
3113 /* Scatter gather list entries may cross 64KB boundaries */
3114 running_total = TRB_MAX_BUFF_SIZE -
3115 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3116 running_total &= TRB_MAX_BUFF_SIZE - 1;
3117 if (running_total != 0)
3118 num_trbs++;
3119
3120 /* How many more 64KB chunks to transfer, how many more TRBs? */
3121 while (running_total < sg_dma_len(sg) && running_total < temp) {
3122 num_trbs++;
3123 running_total += TRB_MAX_BUFF_SIZE;
3124 }
3125 len = min_t(int, len, temp);
3126 temp -= len;
3127 if (temp == 0)
3128 break;
3129 }
3130 return num_trbs;
3131}
3132
3133static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3134{
3135 if (num_trbs != 0)
3136 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3137 "TRBs, %d left\n", __func__,
3138 urb->ep->desc.bEndpointAddress, num_trbs);
3139 if (running_total != urb->transfer_buffer_length)
3140 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3141 "queued %#x (%d), asked for %#x (%d)\n",
3142 __func__,
3143 urb->ep->desc.bEndpointAddress,
3144 running_total, running_total,
3145 urb->transfer_buffer_length,
3146 urb->transfer_buffer_length);
3147}
3148
3149static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3150 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3151 struct xhci_generic_trb *start_trb)
3152{
3153 /*
3154 * Pass all the TRBs to the hardware at once and make sure this write
3155 * isn't reordered.
3156 */
3157 wmb();
3158 if (start_cycle)
3159 start_trb->field[3] |= cpu_to_le32(start_cycle);
3160 else
3161 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3162 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3163}
3164
3165/*
3166 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3167 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3168 * (comprised of sg list entries) can take several service intervals to
3169 * transmit.
3170 */
3171int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3172 struct urb *urb, int slot_id, unsigned int ep_index)
3173{
3174 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3175 xhci->devs[slot_id]->out_ctx, ep_index);
3176 int xhci_interval;
3177 int ep_interval;
3178
3179 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3180 ep_interval = urb->interval;
3181 /* Convert to microframes */
3182 if (urb->dev->speed == USB_SPEED_LOW ||
3183 urb->dev->speed == USB_SPEED_FULL)
3184 ep_interval *= 8;
3185 /* FIXME change this to a warning and a suggestion to use the new API
3186 * to set the polling interval (once the API is added).
3187 */
3188 if (xhci_interval != ep_interval) {
3189 dev_dbg_ratelimited(&urb->dev->dev,
3190 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3191 ep_interval, ep_interval == 1 ? "" : "s",
3192 xhci_interval, xhci_interval == 1 ? "" : "s");
3193 urb->interval = xhci_interval;
3194 /* Convert back to frames for LS/FS devices */
3195 if (urb->dev->speed == USB_SPEED_LOW ||
3196 urb->dev->speed == USB_SPEED_FULL)
3197 urb->interval /= 8;
3198 }
3199 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3200}
3201
3202/*
3203 * The TD size is the number of bytes remaining in the TD (including this TRB),
3204 * right shifted by 10.
3205 * It must fit in bits 21:17, so it can't be bigger than 31.
3206 */
3207static u32 xhci_td_remainder(unsigned int remainder)
3208{
3209 u32 max = (1 << (21 - 17 + 1)) - 1;
3210
3211 if ((remainder >> 10) >= max)
3212 return max << 17;
3213 else
3214 return (remainder >> 10) << 17;
3215}
3216
3217/*
3218 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3219 * packets remaining in the TD (*not* including this TRB).
3220 *
3221 * Total TD packet count = total_packet_count =
3222 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3223 *
3224 * Packets transferred up to and including this TRB = packets_transferred =
3225 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3226 *
3227 * TD size = total_packet_count - packets_transferred
3228 *
3229 * It must fit in bits 21:17, so it can't be bigger than 31.
3230 * The last TRB in a TD must have the TD size set to zero.
3231 */
3232static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3233 unsigned int total_packet_count, struct urb *urb,
3234 unsigned int num_trbs_left)
3235{
3236 int packets_transferred;
3237
3238 /* One TRB with a zero-length data packet. */
3239 if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3240 return 0;
3241
3242 /* All the TRB queueing functions don't count the current TRB in
3243 * running_total.
3244 */
3245 packets_transferred = (running_total + trb_buff_len) /
3246 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3247
3248 if ((total_packet_count - packets_transferred) > 31)
3249 return 31 << 17;
3250 return (total_packet_count - packets_transferred) << 17;
3251}
3252
3253static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3254 struct urb *urb, int slot_id, unsigned int ep_index)
3255{
3256 struct xhci_ring *ep_ring;
3257 unsigned int num_trbs;
3258 struct urb_priv *urb_priv;
3259 struct xhci_td *td;
3260 struct scatterlist *sg;
3261 int num_sgs;
3262 int trb_buff_len, this_sg_len, running_total;
3263 unsigned int total_packet_count;
3264 bool first_trb;
3265 u64 addr;
3266 bool more_trbs_coming;
3267
3268 struct xhci_generic_trb *start_trb;
3269 int start_cycle;
3270
3271 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3272 if (!ep_ring)
3273 return -EINVAL;
3274
3275 num_trbs = count_sg_trbs_needed(xhci, urb);
3276 num_sgs = urb->num_mapped_sgs;
3277 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3278 usb_endpoint_maxp(&urb->ep->desc));
3279
3280 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3281 ep_index, urb->stream_id,
3282 num_trbs, urb, 0, mem_flags);
3283 if (trb_buff_len < 0)
3284 return trb_buff_len;
3285
3286 urb_priv = urb->hcpriv;
3287 td = urb_priv->td[0];
3288
3289 /*
3290 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3291 * until we've finished creating all the other TRBs. The ring's cycle
3292 * state may change as we enqueue the other TRBs, so save it too.
3293 */
3294 start_trb = &ep_ring->enqueue->generic;
3295 start_cycle = ep_ring->cycle_state;
3296
3297 running_total = 0;
3298 /*
3299 * How much data is in the first TRB?
3300 *
3301 * There are three forces at work for TRB buffer pointers and lengths:
3302 * 1. We don't want to walk off the end of this sg-list entry buffer.
3303 * 2. The transfer length that the driver requested may be smaller than
3304 * the amount of memory allocated for this scatter-gather list.
3305 * 3. TRBs buffers can't cross 64KB boundaries.
3306 */
3307 sg = urb->sg;
3308 addr = (u64) sg_dma_address(sg);
3309 this_sg_len = sg_dma_len(sg);
3310 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3311 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3312 if (trb_buff_len > urb->transfer_buffer_length)
3313 trb_buff_len = urb->transfer_buffer_length;
3314
3315 first_trb = true;
3316 /* Queue the first TRB, even if it's zero-length */
3317 do {
3318 u32 field = 0;
3319 u32 length_field = 0;
3320 u32 remainder = 0;
3321
3322 /* Don't change the cycle bit of the first TRB until later */
3323 if (first_trb) {
3324 first_trb = false;
3325 if (start_cycle == 0)
3326 field |= 0x1;
3327 } else
3328 field |= ep_ring->cycle_state;
3329
3330 /* Chain all the TRBs together; clear the chain bit in the last
3331 * TRB to indicate it's the last TRB in the chain.
3332 */
3333 if (num_trbs > 1) {
3334 field |= TRB_CHAIN;
3335 } else {
3336 /* FIXME - add check for ZERO_PACKET flag before this */
3337 td->last_trb = ep_ring->enqueue;
3338 field |= TRB_IOC;
3339 }
3340
3341 /* Only set interrupt on short packet for IN endpoints */
3342 if (usb_urb_dir_in(urb))
3343 field |= TRB_ISP;
3344
3345 if (TRB_MAX_BUFF_SIZE -
3346 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3347 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3348 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3349 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3350 (unsigned int) addr + trb_buff_len);
3351 }
3352
3353 /* Set the TRB length, TD size, and interrupter fields. */
3354 if (xhci->hci_version < 0x100) {
3355 remainder = xhci_td_remainder(
3356 urb->transfer_buffer_length -
3357 running_total);
3358 } else {
3359 remainder = xhci_v1_0_td_remainder(running_total,
3360 trb_buff_len, total_packet_count, urb,
3361 num_trbs - 1);
3362 }
3363 length_field = TRB_LEN(trb_buff_len) |
3364 remainder |
3365 TRB_INTR_TARGET(0);
3366
3367 if (num_trbs > 1)
3368 more_trbs_coming = true;
3369 else
3370 more_trbs_coming = false;
3371 queue_trb(xhci, ep_ring, more_trbs_coming,
3372 lower_32_bits(addr),
3373 upper_32_bits(addr),
3374 length_field,
3375 field | TRB_TYPE(TRB_NORMAL));
3376 --num_trbs;
3377 running_total += trb_buff_len;
3378
3379 /* Calculate length for next transfer --
3380 * Are we done queueing all the TRBs for this sg entry?
3381 */
3382 this_sg_len -= trb_buff_len;
3383 if (this_sg_len == 0) {
3384 --num_sgs;
3385 if (num_sgs == 0)
3386 break;
3387 sg = sg_next(sg);
3388 addr = (u64) sg_dma_address(sg);
3389 this_sg_len = sg_dma_len(sg);
3390 } else {
3391 addr += trb_buff_len;
3392 }
3393
3394 trb_buff_len = TRB_MAX_BUFF_SIZE -
3395 (addr & (TRB_MAX_BUFF_SIZE - 1));
3396 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3397 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3398 trb_buff_len =
3399 urb->transfer_buffer_length - running_total;
3400 } while (running_total < urb->transfer_buffer_length);
3401
3402 check_trb_math(urb, num_trbs, running_total);
3403 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3404 start_cycle, start_trb);
3405 return 0;
3406}
3407
3408/* This is very similar to what ehci-q.c qtd_fill() does */
3409int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3410 struct urb *urb, int slot_id, unsigned int ep_index)
3411{
3412 struct xhci_ring *ep_ring;
3413 struct urb_priv *urb_priv;
3414 struct xhci_td *td;
3415 int num_trbs;
3416 struct xhci_generic_trb *start_trb;
3417 bool first_trb;
3418 bool more_trbs_coming;
3419 int start_cycle;
3420 u32 field, length_field;
3421
3422 int running_total, trb_buff_len, ret;
3423 unsigned int total_packet_count;
3424 u64 addr;
3425
3426 if (urb->num_sgs)
3427 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3428
3429 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3430 if (!ep_ring)
3431 return -EINVAL;
3432
3433 num_trbs = 0;
3434 /* How much data is (potentially) left before the 64KB boundary? */
3435 running_total = TRB_MAX_BUFF_SIZE -
3436 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3437 running_total &= TRB_MAX_BUFF_SIZE - 1;
3438
3439 /* If there's some data on this 64KB chunk, or we have to send a
3440 * zero-length transfer, we need at least one TRB
3441 */
3442 if (running_total != 0 || urb->transfer_buffer_length == 0)
3443 num_trbs++;
3444 /* How many more 64KB chunks to transfer, how many more TRBs? */
3445 while (running_total < urb->transfer_buffer_length) {
3446 num_trbs++;
3447 running_total += TRB_MAX_BUFF_SIZE;
3448 }
3449 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3450
3451 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3452 ep_index, urb->stream_id,
3453 num_trbs, urb, 0, mem_flags);
3454 if (ret < 0)
3455 return ret;
3456
3457 urb_priv = urb->hcpriv;
3458 td = urb_priv->td[0];
3459
3460 /*
3461 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3462 * until we've finished creating all the other TRBs. The ring's cycle
3463 * state may change as we enqueue the other TRBs, so save it too.
3464 */
3465 start_trb = &ep_ring->enqueue->generic;
3466 start_cycle = ep_ring->cycle_state;
3467
3468 running_total = 0;
3469 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3470 usb_endpoint_maxp(&urb->ep->desc));
3471 /* How much data is in the first TRB? */
3472 addr = (u64) urb->transfer_dma;
3473 trb_buff_len = TRB_MAX_BUFF_SIZE -
3474 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3475 if (trb_buff_len > urb->transfer_buffer_length)
3476 trb_buff_len = urb->transfer_buffer_length;
3477
3478 first_trb = true;
3479
3480 /* Queue the first TRB, even if it's zero-length */
3481 do {
3482 u32 remainder = 0;
3483 field = 0;
3484
3485 /* Don't change the cycle bit of the first TRB until later */
3486 if (first_trb) {
3487 first_trb = false;
3488 if (start_cycle == 0)
3489 field |= 0x1;
3490 } else
3491 field |= ep_ring->cycle_state;
3492
3493 /* Chain all the TRBs together; clear the chain bit in the last
3494 * TRB to indicate it's the last TRB in the chain.
3495 */
3496 if (num_trbs > 1) {
3497 field |= TRB_CHAIN;
3498 } else {
3499 /* FIXME - add check for ZERO_PACKET flag before this */
3500 td->last_trb = ep_ring->enqueue;
3501 field |= TRB_IOC;
3502 }
3503
3504 /* Only set interrupt on short packet for IN endpoints */
3505 if (usb_urb_dir_in(urb))
3506 field |= TRB_ISP;
3507
3508 /* Set the TRB length, TD size, and interrupter fields. */
3509 if (xhci->hci_version < 0x100) {
3510 remainder = xhci_td_remainder(
3511 urb->transfer_buffer_length -
3512 running_total);
3513 } else {
3514 remainder = xhci_v1_0_td_remainder(running_total,
3515 trb_buff_len, total_packet_count, urb,
3516 num_trbs - 1);
3517 }
3518 length_field = TRB_LEN(trb_buff_len) |
3519 remainder |
3520 TRB_INTR_TARGET(0);
3521
3522 if (num_trbs > 1)
3523 more_trbs_coming = true;
3524 else
3525 more_trbs_coming = false;
3526 queue_trb(xhci, ep_ring, more_trbs_coming,
3527 lower_32_bits(addr),
3528 upper_32_bits(addr),
3529 length_field,
3530 field | TRB_TYPE(TRB_NORMAL));
3531 --num_trbs;
3532 running_total += trb_buff_len;
3533
3534 /* Calculate length for next transfer */
3535 addr += trb_buff_len;
3536 trb_buff_len = urb->transfer_buffer_length - running_total;
3537 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3538 trb_buff_len = TRB_MAX_BUFF_SIZE;
3539 } while (running_total < urb->transfer_buffer_length);
3540
3541 check_trb_math(urb, num_trbs, running_total);
3542 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3543 start_cycle, start_trb);
3544 return 0;
3545}
3546
3547/* Caller must have locked xhci->lock */
3548int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3549 struct urb *urb, int slot_id, unsigned int ep_index)
3550{
3551 struct xhci_ring *ep_ring;
3552 int num_trbs;
3553 int ret;
3554 struct usb_ctrlrequest *setup;
3555 struct xhci_generic_trb *start_trb;
3556 int start_cycle;
3557 u32 field, length_field;
3558 struct urb_priv *urb_priv;
3559 struct xhci_td *td;
3560
3561 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3562 if (!ep_ring)
3563 return -EINVAL;
3564
3565 /*
3566 * Need to copy setup packet into setup TRB, so we can't use the setup
3567 * DMA address.
3568 */
3569 if (!urb->setup_packet)
3570 return -EINVAL;
3571
3572 /* 1 TRB for setup, 1 for status */
3573 num_trbs = 2;
3574 /*
3575 * Don't need to check if we need additional event data and normal TRBs,
3576 * since data in control transfers will never get bigger than 16MB
3577 * XXX: can we get a buffer that crosses 64KB boundaries?
3578 */
3579 if (urb->transfer_buffer_length > 0)
3580 num_trbs++;
3581 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3582 ep_index, urb->stream_id,
3583 num_trbs, urb, 0, mem_flags);
3584 if (ret < 0)
3585 return ret;
3586
3587 urb_priv = urb->hcpriv;
3588 td = urb_priv->td[0];
3589
3590 /*
3591 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3592 * until we've finished creating all the other TRBs. The ring's cycle
3593 * state may change as we enqueue the other TRBs, so save it too.
3594 */
3595 start_trb = &ep_ring->enqueue->generic;
3596 start_cycle = ep_ring->cycle_state;
3597
3598 /* Queue setup TRB - see section 6.4.1.2.1 */
3599 /* FIXME better way to translate setup_packet into two u32 fields? */
3600 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3601 field = 0;
3602 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3603 if (start_cycle == 0)
3604 field |= 0x1;
3605
3606 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3607 if (xhci->hci_version == 0x100) {
3608 if (urb->transfer_buffer_length > 0) {
3609 if (setup->bRequestType & USB_DIR_IN)
3610 field |= TRB_TX_TYPE(TRB_DATA_IN);
3611 else
3612 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3613 }
3614 }
3615
3616 queue_trb(xhci, ep_ring, true,
3617 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3618 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3619 TRB_LEN(8) | TRB_INTR_TARGET(0),
3620 /* Immediate data in pointer */
3621 field);
3622
3623 /* If there's data, queue data TRBs */
3624 /* Only set interrupt on short packet for IN endpoints */
3625 if (usb_urb_dir_in(urb))
3626 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3627 else
3628 field = TRB_TYPE(TRB_DATA);
3629
3630 length_field = TRB_LEN(urb->transfer_buffer_length) |
3631 xhci_td_remainder(urb->transfer_buffer_length) |
3632 TRB_INTR_TARGET(0);
3633 if (urb->transfer_buffer_length > 0) {
3634 if (setup->bRequestType & USB_DIR_IN)
3635 field |= TRB_DIR_IN;
3636 queue_trb(xhci, ep_ring, true,
3637 lower_32_bits(urb->transfer_dma),
3638 upper_32_bits(urb->transfer_dma),
3639 length_field,
3640 field | ep_ring->cycle_state);
3641 }
3642
3643 /* Save the DMA address of the last TRB in the TD */
3644 td->last_trb = ep_ring->enqueue;
3645
3646 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3647 /* If the device sent data, the status stage is an OUT transfer */
3648 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3649 field = 0;
3650 else
3651 field = TRB_DIR_IN;
3652 queue_trb(xhci, ep_ring, false,
3653 0,
3654 0,
3655 TRB_INTR_TARGET(0),
3656 /* Event on completion */
3657 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3658
3659 giveback_first_trb(xhci, slot_id, ep_index, 0,
3660 start_cycle, start_trb);
3661 return 0;
3662}
3663
3664static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3665 struct urb *urb, int i)
3666{
3667 int num_trbs = 0;
3668 u64 addr, td_len;
3669
3670 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3671 td_len = urb->iso_frame_desc[i].length;
3672
3673 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3674 TRB_MAX_BUFF_SIZE);
3675 if (num_trbs == 0)
3676 num_trbs++;
3677
3678 return num_trbs;
3679}
3680
3681/*
3682 * The transfer burst count field of the isochronous TRB defines the number of
3683 * bursts that are required to move all packets in this TD. Only SuperSpeed
3684 * devices can burst up to bMaxBurst number of packets per service interval.
3685 * This field is zero based, meaning a value of zero in the field means one
3686 * burst. Basically, for everything but SuperSpeed devices, this field will be
3687 * zero. Only xHCI 1.0 host controllers support this field.
3688 */
3689static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3690 struct usb_device *udev,
3691 struct urb *urb, unsigned int total_packet_count)
3692{
3693 unsigned int max_burst;
3694
3695 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3696 return 0;
3697
3698 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3699 return roundup(total_packet_count, max_burst + 1) - 1;
3700}
3701
3702/*
3703 * Returns the number of packets in the last "burst" of packets. This field is
3704 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3705 * the last burst packet count is equal to the total number of packets in the
3706 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3707 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3708 * contain 1 to (bMaxBurst + 1) packets.
3709 */
3710static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3711 struct usb_device *udev,
3712 struct urb *urb, unsigned int total_packet_count)
3713{
3714 unsigned int max_burst;
3715 unsigned int residue;
3716
3717 if (xhci->hci_version < 0x100)
3718 return 0;
3719
3720 switch (udev->speed) {
3721 case USB_SPEED_SUPER:
3722 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3723 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3724 residue = total_packet_count % (max_burst + 1);
3725 /* If residue is zero, the last burst contains (max_burst + 1)
3726 * number of packets, but the TLBPC field is zero-based.
3727 */
3728 if (residue == 0)
3729 return max_burst;
3730 return residue - 1;
3731 default:
3732 if (total_packet_count == 0)
3733 return 0;
3734 return total_packet_count - 1;
3735 }
3736}
3737
3738/* This is for isoc transfer */
3739static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3740 struct urb *urb, int slot_id, unsigned int ep_index)
3741{
3742 struct xhci_ring *ep_ring;
3743 struct urb_priv *urb_priv;
3744 struct xhci_td *td;
3745 int num_tds, trbs_per_td;
3746 struct xhci_generic_trb *start_trb;
3747 bool first_trb;
3748 int start_cycle;
3749 u32 field, length_field;
3750 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3751 u64 start_addr, addr;
3752 int i, j;
3753 bool more_trbs_coming;
3754
3755 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3756
3757 num_tds = urb->number_of_packets;
3758 if (num_tds < 1) {
3759 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3760 return -EINVAL;
3761 }
3762
3763 start_addr = (u64) urb->transfer_dma;
3764 start_trb = &ep_ring->enqueue->generic;
3765 start_cycle = ep_ring->cycle_state;
3766
3767 urb_priv = urb->hcpriv;
3768 /* Queue the first TRB, even if it's zero-length */
3769 for (i = 0; i < num_tds; i++) {
3770 unsigned int total_packet_count;
3771 unsigned int burst_count;
3772 unsigned int residue;
3773
3774 first_trb = true;
3775 running_total = 0;
3776 addr = start_addr + urb->iso_frame_desc[i].offset;
3777 td_len = urb->iso_frame_desc[i].length;
3778 td_remain_len = td_len;
3779 total_packet_count = DIV_ROUND_UP(td_len,
3780 GET_MAX_PACKET(
3781 usb_endpoint_maxp(&urb->ep->desc)));
3782 /* A zero-length transfer still involves at least one packet. */
3783 if (total_packet_count == 0)
3784 total_packet_count++;
3785 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3786 total_packet_count);
3787 residue = xhci_get_last_burst_packet_count(xhci,
3788 urb->dev, urb, total_packet_count);
3789
3790 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3791
3792 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3793 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3794 if (ret < 0) {
3795 if (i == 0)
3796 return ret;
3797 goto cleanup;
3798 }
3799
3800 td = urb_priv->td[i];
3801 for (j = 0; j < trbs_per_td; j++) {
3802 u32 remainder = 0;
3803 field = 0;
3804
3805 if (first_trb) {
3806 field = TRB_TBC(burst_count) |
3807 TRB_TLBPC(residue);
3808 /* Queue the isoc TRB */
3809 field |= TRB_TYPE(TRB_ISOC);
3810 /* Assume URB_ISO_ASAP is set */
3811 field |= TRB_SIA;
3812 if (i == 0) {
3813 if (start_cycle == 0)
3814 field |= 0x1;
3815 } else
3816 field |= ep_ring->cycle_state;
3817 first_trb = false;
3818 } else {
3819 /* Queue other normal TRBs */
3820 field |= TRB_TYPE(TRB_NORMAL);
3821 field |= ep_ring->cycle_state;
3822 }
3823
3824 /* Only set interrupt on short packet for IN EPs */
3825 if (usb_urb_dir_in(urb))
3826 field |= TRB_ISP;
3827
3828 /* Chain all the TRBs together; clear the chain bit in
3829 * the last TRB to indicate it's the last TRB in the
3830 * chain.
3831 */
3832 if (j < trbs_per_td - 1) {
3833 field |= TRB_CHAIN;
3834 more_trbs_coming = true;
3835 } else {
3836 td->last_trb = ep_ring->enqueue;
3837 field |= TRB_IOC;
3838 if (xhci->hci_version == 0x100 &&
3839 !(xhci->quirks &
3840 XHCI_AVOID_BEI)) {
3841 /* Set BEI bit except for the last td */
3842 if (i < num_tds - 1)
3843 field |= TRB_BEI;
3844 }
3845 more_trbs_coming = false;
3846 }
3847
3848 /* Calculate TRB length */
3849 trb_buff_len = TRB_MAX_BUFF_SIZE -
3850 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3851 if (trb_buff_len > td_remain_len)
3852 trb_buff_len = td_remain_len;
3853
3854 /* Set the TRB length, TD size, & interrupter fields. */
3855 if (xhci->hci_version < 0x100) {
3856 remainder = xhci_td_remainder(
3857 td_len - running_total);
3858 } else {
3859 remainder = xhci_v1_0_td_remainder(
3860 running_total, trb_buff_len,
3861 total_packet_count, urb,
3862 (trbs_per_td - j - 1));
3863 }
3864 length_field = TRB_LEN(trb_buff_len) |
3865 remainder |
3866 TRB_INTR_TARGET(0);
3867
3868 queue_trb(xhci, ep_ring, more_trbs_coming,
3869 lower_32_bits(addr),
3870 upper_32_bits(addr),
3871 length_field,
3872 field);
3873 running_total += trb_buff_len;
3874
3875 addr += trb_buff_len;
3876 td_remain_len -= trb_buff_len;
3877 }
3878
3879 /* Check TD length */
3880 if (running_total != td_len) {
3881 xhci_err(xhci, "ISOC TD length unmatch\n");
3882 ret = -EINVAL;
3883 goto cleanup;
3884 }
3885 }
3886
3887 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3888 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3889 usb_amd_quirk_pll_disable();
3890 }
3891 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3892
3893 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3894 start_cycle, start_trb);
3895 return 0;
3896cleanup:
3897 /* Clean up a partially enqueued isoc transfer. */
3898
3899 for (i--; i >= 0; i--)
3900 list_del_init(&urb_priv->td[i]->td_list);
3901
3902 /* Use the first TD as a temporary variable to turn the TDs we've queued
3903 * into No-ops with a software-owned cycle bit. That way the hardware
3904 * won't accidentally start executing bogus TDs when we partially
3905 * overwrite them. td->first_trb and td->start_seg are already set.
3906 */
3907 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3908 /* Every TRB except the first & last will have its cycle bit flipped. */
3909 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3910
3911 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3912 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3913 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3914 ep_ring->cycle_state = start_cycle;
3915 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3916 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3917 return ret;
3918}
3919
3920/*
3921 * Check transfer ring to guarantee there is enough room for the urb.
3922 * Update ISO URB start_frame and interval.
3923 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3924 * update the urb->start_frame by now.
3925 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3926 */
3927int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3928 struct urb *urb, int slot_id, unsigned int ep_index)
3929{
3930 struct xhci_virt_device *xdev;
3931 struct xhci_ring *ep_ring;
3932 struct xhci_ep_ctx *ep_ctx;
3933 int start_frame;
3934 int xhci_interval;
3935 int ep_interval;
3936 int num_tds, num_trbs, i;
3937 int ret;
3938
3939 xdev = xhci->devs[slot_id];
3940 ep_ring = xdev->eps[ep_index].ring;
3941 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3942
3943 num_trbs = 0;
3944 num_tds = urb->number_of_packets;
3945 for (i = 0; i < num_tds; i++)
3946 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3947
3948 /* Check the ring to guarantee there is enough room for the whole urb.
3949 * Do not insert any td of the urb to the ring if the check failed.
3950 */
3951 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3952 num_trbs, mem_flags);
3953 if (ret)
3954 return ret;
3955
3956 start_frame = readl(&xhci->run_regs->microframe_index);
3957 start_frame &= 0x3fff;
3958
3959 urb->start_frame = start_frame;
3960 if (urb->dev->speed == USB_SPEED_LOW ||
3961 urb->dev->speed == USB_SPEED_FULL)
3962 urb->start_frame >>= 3;
3963
3964 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3965 ep_interval = urb->interval;
3966 /* Convert to microframes */
3967 if (urb->dev->speed == USB_SPEED_LOW ||
3968 urb->dev->speed == USB_SPEED_FULL)
3969 ep_interval *= 8;
3970 /* FIXME change this to a warning and a suggestion to use the new API
3971 * to set the polling interval (once the API is added).
3972 */
3973 if (xhci_interval != ep_interval) {
3974 dev_dbg_ratelimited(&urb->dev->dev,
3975 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3976 ep_interval, ep_interval == 1 ? "" : "s",
3977 xhci_interval, xhci_interval == 1 ? "" : "s");
3978 urb->interval = xhci_interval;
3979 /* Convert back to frames for LS/FS devices */
3980 if (urb->dev->speed == USB_SPEED_LOW ||
3981 urb->dev->speed == USB_SPEED_FULL)
3982 urb->interval /= 8;
3983 }
3984 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3985
3986 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3987}
3988
3989/**** Command Ring Operations ****/
3990
3991/* Generic function for queueing a command TRB on the command ring.
3992 * Check to make sure there's room on the command ring for one command TRB.
3993 * Also check that there's room reserved for commands that must not fail.
3994 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3995 * then only check for the number of reserved spots.
3996 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3997 * because the command event handler may want to resubmit a failed command.
3998 */
3999static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
4000 u32 field3, u32 field4, bool command_must_succeed)
4001{
4002 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4003 int ret;
4004
4005 if (!command_must_succeed)
4006 reserved_trbs++;
4007
4008 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4009 reserved_trbs, GFP_ATOMIC);
4010 if (ret < 0) {
4011 xhci_err(xhci, "ERR: No room for command on command ring\n");
4012 if (command_must_succeed)
4013 xhci_err(xhci, "ERR: Reserved TRB counting for "
4014 "unfailable commands failed.\n");
4015 return ret;
4016 }
4017 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4018 field4 | xhci->cmd_ring->cycle_state);
4019 return 0;
4020}
4021
4022/* Queue a slot enable or disable request on the command ring */
4023int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
4024{
4025 return queue_command(xhci, 0, 0, 0,
4026 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4027}
4028
4029/* Queue an address device command TRB */
4030int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4031 u32 slot_id, enum xhci_setup_dev setup)
4032{
4033 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4034 upper_32_bits(in_ctx_ptr), 0,
4035 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4036 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4037}
4038
4039int xhci_queue_vendor_command(struct xhci_hcd *xhci,
4040 u32 field1, u32 field2, u32 field3, u32 field4)
4041{
4042 return queue_command(xhci, field1, field2, field3, field4, false);
4043}
4044
4045/* Queue a reset device command TRB */
4046int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
4047{
4048 return queue_command(xhci, 0, 0, 0,
4049 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4050 false);
4051}
4052
4053/* Queue a configure endpoint command TRB */
4054int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4055 u32 slot_id, bool command_must_succeed)
4056{
4057 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4058 upper_32_bits(in_ctx_ptr), 0,
4059 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4060 command_must_succeed);
4061}
4062
4063/* Queue an evaluate context command TRB */
4064int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4065 u32 slot_id, bool command_must_succeed)
4066{
4067 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4068 upper_32_bits(in_ctx_ptr), 0,
4069 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4070 command_must_succeed);
4071}
4072
4073/*
4074 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4075 * activity on an endpoint that is about to be suspended.
4076 */
4077int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
4078 unsigned int ep_index, int suspend)
4079{
4080 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4081 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4082 u32 type = TRB_TYPE(TRB_STOP_RING);
4083 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4084
4085 return queue_command(xhci, 0, 0, 0,
4086 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4087}
4088
4089/* Set Transfer Ring Dequeue Pointer command.
4090 * This should not be used for endpoints that have streams enabled.
4091 */
4092static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
4093 unsigned int ep_index, unsigned int stream_id,
4094 struct xhci_segment *deq_seg,
4095 union xhci_trb *deq_ptr, u32 cycle_state)
4096{
4097 dma_addr_t addr;
4098 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4099 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4100 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4101 u32 trb_sct = 0;
4102 u32 type = TRB_TYPE(TRB_SET_DEQ);
4103 struct xhci_virt_ep *ep;
4104
4105 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
4106 if (addr == 0) {
4107 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4108 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4109 deq_seg, deq_ptr);
4110 return 0;
4111 }
4112 ep = &xhci->devs[slot_id]->eps[ep_index];
4113 if ((ep->ep_state & SET_DEQ_PENDING)) {
4114 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4115 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4116 return 0;
4117 }
4118 ep->queued_deq_seg = deq_seg;
4119 ep->queued_deq_ptr = deq_ptr;
4120 if (stream_id)
4121 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4122 return queue_command(xhci, lower_32_bits(addr) | trb_sct | cycle_state,
4123 upper_32_bits(addr), trb_stream_id,
4124 trb_slot_id | trb_ep_index | type, false);
4125}
4126
4127int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
4128 unsigned int ep_index)
4129{
4130 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4131 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4132 u32 type = TRB_TYPE(TRB_RESET_EP);
4133
4134 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
4135 false);
4136}