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1/**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26#include <linux/platform_device.h>
27#include <linux/pm_runtime.h>
28#include <linux/interrupt.h>
29#include <linux/ioport.h>
30#include <linux/io.h>
31#include <linux/list.h>
32#include <linux/delay.h>
33#include <linux/dma-mapping.h>
34#include <linux/of.h>
35
36#include <linux/usb/ch9.h>
37#include <linux/usb/gadget.h>
38#include <linux/usb/of.h>
39#include <linux/usb/otg.h>
40
41#include "platform_data.h"
42#include "core.h"
43#include "gadget.h"
44#include "io.h"
45
46#include "debug.h"
47
48/* -------------------------------------------------------------------------- */
49
50void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
51{
52 u32 reg;
53
54 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
55 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
56 reg |= DWC3_GCTL_PRTCAPDIR(mode);
57 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
58}
59
60/**
61 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
62 * @dwc: pointer to our context structure
63 */
64static int dwc3_core_soft_reset(struct dwc3 *dwc)
65{
66 u32 reg;
67 int ret;
68
69 /* Before Resetting PHY, put Core in Reset */
70 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
71 reg |= DWC3_GCTL_CORESOFTRESET;
72 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
73
74 /* Assert USB3 PHY reset */
75 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
76 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
77 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
78
79 /* Assert USB2 PHY reset */
80 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
81 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
82 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
83
84 usb_phy_init(dwc->usb2_phy);
85 usb_phy_init(dwc->usb3_phy);
86 ret = phy_init(dwc->usb2_generic_phy);
87 if (ret < 0)
88 return ret;
89
90 ret = phy_init(dwc->usb3_generic_phy);
91 if (ret < 0) {
92 phy_exit(dwc->usb2_generic_phy);
93 return ret;
94 }
95 mdelay(100);
96
97 /* Clear USB3 PHY reset */
98 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
99 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
100 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
101
102 /* Clear USB2 PHY reset */
103 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
104 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
105 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
106
107 mdelay(100);
108
109 /* After PHYs are stable we can take Core out of reset state */
110 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
111 reg &= ~DWC3_GCTL_CORESOFTRESET;
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
113
114 return 0;
115}
116
117/**
118 * dwc3_free_one_event_buffer - Frees one event buffer
119 * @dwc: Pointer to our controller context structure
120 * @evt: Pointer to event buffer to be freed
121 */
122static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
123 struct dwc3_event_buffer *evt)
124{
125 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
126}
127
128/**
129 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
130 * @dwc: Pointer to our controller context structure
131 * @length: size of the event buffer
132 *
133 * Returns a pointer to the allocated event buffer structure on success
134 * otherwise ERR_PTR(errno).
135 */
136static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
137 unsigned length)
138{
139 struct dwc3_event_buffer *evt;
140
141 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
142 if (!evt)
143 return ERR_PTR(-ENOMEM);
144
145 evt->dwc = dwc;
146 evt->length = length;
147 evt->buf = dma_alloc_coherent(dwc->dev, length,
148 &evt->dma, GFP_KERNEL);
149 if (!evt->buf)
150 return ERR_PTR(-ENOMEM);
151
152 return evt;
153}
154
155/**
156 * dwc3_free_event_buffers - frees all allocated event buffers
157 * @dwc: Pointer to our controller context structure
158 */
159static void dwc3_free_event_buffers(struct dwc3 *dwc)
160{
161 struct dwc3_event_buffer *evt;
162 int i;
163
164 for (i = 0; i < dwc->num_event_buffers; i++) {
165 evt = dwc->ev_buffs[i];
166 if (evt)
167 dwc3_free_one_event_buffer(dwc, evt);
168 }
169}
170
171/**
172 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
173 * @dwc: pointer to our controller context structure
174 * @length: size of event buffer
175 *
176 * Returns 0 on success otherwise negative errno. In the error case, dwc
177 * may contain some buffers allocated but not all which were requested.
178 */
179static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
180{
181 int num;
182 int i;
183
184 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
185 dwc->num_event_buffers = num;
186
187 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
188 GFP_KERNEL);
189 if (!dwc->ev_buffs) {
190 dev_err(dwc->dev, "can't allocate event buffers array\n");
191 return -ENOMEM;
192 }
193
194 for (i = 0; i < num; i++) {
195 struct dwc3_event_buffer *evt;
196
197 evt = dwc3_alloc_one_event_buffer(dwc, length);
198 if (IS_ERR(evt)) {
199 dev_err(dwc->dev, "can't allocate event buffer\n");
200 return PTR_ERR(evt);
201 }
202 dwc->ev_buffs[i] = evt;
203 }
204
205 return 0;
206}
207
208/**
209 * dwc3_event_buffers_setup - setup our allocated event buffers
210 * @dwc: pointer to our controller context structure
211 *
212 * Returns 0 on success otherwise negative errno.
213 */
214static int dwc3_event_buffers_setup(struct dwc3 *dwc)
215{
216 struct dwc3_event_buffer *evt;
217 int n;
218
219 for (n = 0; n < dwc->num_event_buffers; n++) {
220 evt = dwc->ev_buffs[n];
221 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
222 evt->buf, (unsigned long long) evt->dma,
223 evt->length);
224
225 evt->lpos = 0;
226
227 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
228 lower_32_bits(evt->dma));
229 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
230 upper_32_bits(evt->dma));
231 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
232 DWC3_GEVNTSIZ_SIZE(evt->length));
233 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
234 }
235
236 return 0;
237}
238
239static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
240{
241 struct dwc3_event_buffer *evt;
242 int n;
243
244 for (n = 0; n < dwc->num_event_buffers; n++) {
245 evt = dwc->ev_buffs[n];
246
247 evt->lpos = 0;
248
249 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
250 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
251 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
252 | DWC3_GEVNTSIZ_SIZE(0));
253 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
254 }
255}
256
257static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
258{
259 if (!dwc->has_hibernation)
260 return 0;
261
262 if (!dwc->nr_scratch)
263 return 0;
264
265 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
266 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
267 if (!dwc->scratchbuf)
268 return -ENOMEM;
269
270 return 0;
271}
272
273static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
274{
275 dma_addr_t scratch_addr;
276 u32 param;
277 int ret;
278
279 if (!dwc->has_hibernation)
280 return 0;
281
282 if (!dwc->nr_scratch)
283 return 0;
284
285 /* should never fall here */
286 if (!WARN_ON(dwc->scratchbuf))
287 return 0;
288
289 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
290 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
291 DMA_BIDIRECTIONAL);
292 if (dma_mapping_error(dwc->dev, scratch_addr)) {
293 dev_err(dwc->dev, "failed to map scratch buffer\n");
294 ret = -EFAULT;
295 goto err0;
296 }
297
298 dwc->scratch_addr = scratch_addr;
299
300 param = lower_32_bits(scratch_addr);
301
302 ret = dwc3_send_gadget_generic_command(dwc,
303 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
304 if (ret < 0)
305 goto err1;
306
307 param = upper_32_bits(scratch_addr);
308
309 ret = dwc3_send_gadget_generic_command(dwc,
310 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
311 if (ret < 0)
312 goto err1;
313
314 return 0;
315
316err1:
317 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
318 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
319
320err0:
321 return ret;
322}
323
324static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
325{
326 if (!dwc->has_hibernation)
327 return;
328
329 if (!dwc->nr_scratch)
330 return;
331
332 /* should never fall here */
333 if (!WARN_ON(dwc->scratchbuf))
334 return;
335
336 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
337 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
338 kfree(dwc->scratchbuf);
339}
340
341static void dwc3_core_num_eps(struct dwc3 *dwc)
342{
343 struct dwc3_hwparams *parms = &dwc->hwparams;
344
345 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
346 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
347
348 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
349 dwc->num_in_eps, dwc->num_out_eps);
350}
351
352static void dwc3_cache_hwparams(struct dwc3 *dwc)
353{
354 struct dwc3_hwparams *parms = &dwc->hwparams;
355
356 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
357 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
358 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
359 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
360 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
361 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
362 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
363 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
364 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
365}
366
367/**
368 * dwc3_core_init - Low-level initialization of DWC3 Core
369 * @dwc: Pointer to our controller context structure
370 *
371 * Returns 0 on success otherwise negative errno.
372 */
373static int dwc3_core_init(struct dwc3 *dwc)
374{
375 unsigned long timeout;
376 u32 hwparams4 = dwc->hwparams.hwparams4;
377 u32 reg;
378 int ret;
379
380 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
381 /* This should read as U3 followed by revision number */
382 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
383 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
384 ret = -ENODEV;
385 goto err0;
386 }
387 dwc->revision = reg;
388
389 /* issue device SoftReset too */
390 timeout = jiffies + msecs_to_jiffies(500);
391 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
392 do {
393 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
394 if (!(reg & DWC3_DCTL_CSFTRST))
395 break;
396
397 if (time_after(jiffies, timeout)) {
398 dev_err(dwc->dev, "Reset Timed Out\n");
399 ret = -ETIMEDOUT;
400 goto err0;
401 }
402
403 cpu_relax();
404 } while (true);
405
406 ret = dwc3_core_soft_reset(dwc);
407 if (ret)
408 goto err0;
409
410 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
411 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
412 reg &= ~DWC3_GCTL_DISSCRAMBLE;
413
414 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
415 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
416 /**
417 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
418 * issue which would cause xHCI compliance tests to fail.
419 *
420 * Because of that we cannot enable clock gating on such
421 * configurations.
422 *
423 * Refers to:
424 *
425 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
426 * SOF/ITP Mode Used
427 */
428 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
429 dwc->dr_mode == USB_DR_MODE_OTG) &&
430 (dwc->revision >= DWC3_REVISION_210A &&
431 dwc->revision <= DWC3_REVISION_250A))
432 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
433 else
434 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
435 break;
436 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
437 /* enable hibernation here */
438 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
439 break;
440 default:
441 dev_dbg(dwc->dev, "No power optimization available\n");
442 }
443
444 /*
445 * WORKAROUND: DWC3 revisions <1.90a have a bug
446 * where the device can fail to connect at SuperSpeed
447 * and falls back to high-speed mode which causes
448 * the device to enter a Connect/Disconnect loop
449 */
450 if (dwc->revision < DWC3_REVISION_190A)
451 reg |= DWC3_GCTL_U2RSTECN;
452
453 dwc3_core_num_eps(dwc);
454
455 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
456
457 ret = dwc3_alloc_scratch_buffers(dwc);
458 if (ret)
459 goto err1;
460
461 ret = dwc3_setup_scratch_buffers(dwc);
462 if (ret)
463 goto err2;
464
465 return 0;
466
467err2:
468 dwc3_free_scratch_buffers(dwc);
469
470err1:
471 usb_phy_shutdown(dwc->usb2_phy);
472 usb_phy_shutdown(dwc->usb3_phy);
473 phy_exit(dwc->usb2_generic_phy);
474 phy_exit(dwc->usb3_generic_phy);
475
476err0:
477 return ret;
478}
479
480static void dwc3_core_exit(struct dwc3 *dwc)
481{
482 dwc3_free_scratch_buffers(dwc);
483 usb_phy_shutdown(dwc->usb2_phy);
484 usb_phy_shutdown(dwc->usb3_phy);
485 phy_exit(dwc->usb2_generic_phy);
486 phy_exit(dwc->usb3_generic_phy);
487}
488
489#define DWC3_ALIGN_MASK (16 - 1)
490
491static int dwc3_probe(struct platform_device *pdev)
492{
493 struct device *dev = &pdev->dev;
494 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
495 struct device_node *node = dev->of_node;
496 struct resource *res;
497 struct dwc3 *dwc;
498
499 int ret = -ENOMEM;
500
501 void __iomem *regs;
502 void *mem;
503
504 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
505 if (!mem) {
506 dev_err(dev, "not enough memory\n");
507 return -ENOMEM;
508 }
509 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
510 dwc->mem = mem;
511
512 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
513 if (!res) {
514 dev_err(dev, "missing IRQ\n");
515 return -ENODEV;
516 }
517 dwc->xhci_resources[1].start = res->start;
518 dwc->xhci_resources[1].end = res->end;
519 dwc->xhci_resources[1].flags = res->flags;
520 dwc->xhci_resources[1].name = res->name;
521
522 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
523 if (!res) {
524 dev_err(dev, "missing memory resource\n");
525 return -ENODEV;
526 }
527
528 if (node) {
529 dwc->maximum_speed = of_usb_get_maximum_speed(node);
530
531 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
532 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
533
534 dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
535 dwc->dr_mode = of_usb_get_dr_mode(node);
536 } else if (pdata) {
537 dwc->maximum_speed = pdata->maximum_speed;
538
539 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
540 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
541
542 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
543 dwc->dr_mode = pdata->dr_mode;
544 } else {
545 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
546 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
547 }
548
549 /* default to superspeed if no maximum_speed passed */
550 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
551 dwc->maximum_speed = USB_SPEED_SUPER;
552
553 if (IS_ERR(dwc->usb2_phy)) {
554 ret = PTR_ERR(dwc->usb2_phy);
555 if (ret == -ENXIO || ret == -ENODEV) {
556 dwc->usb2_phy = NULL;
557 } else if (ret == -EPROBE_DEFER) {
558 return ret;
559 } else {
560 dev_err(dev, "no usb2 phy configured\n");
561 return ret;
562 }
563 }
564
565 if (IS_ERR(dwc->usb3_phy)) {
566 ret = PTR_ERR(dwc->usb3_phy);
567 if (ret == -ENXIO || ret == -ENODEV) {
568 dwc->usb3_phy = NULL;
569 } else if (ret == -EPROBE_DEFER) {
570 return ret;
571 } else {
572 dev_err(dev, "no usb3 phy configured\n");
573 return ret;
574 }
575 }
576
577 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
578 if (IS_ERR(dwc->usb2_generic_phy)) {
579 ret = PTR_ERR(dwc->usb2_generic_phy);
580 if (ret == -ENOSYS || ret == -ENODEV) {
581 dwc->usb2_generic_phy = NULL;
582 } else if (ret == -EPROBE_DEFER) {
583 return ret;
584 } else {
585 dev_err(dev, "no usb2 phy configured\n");
586 return ret;
587 }
588 }
589
590 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
591 if (IS_ERR(dwc->usb3_generic_phy)) {
592 ret = PTR_ERR(dwc->usb3_generic_phy);
593 if (ret == -ENOSYS || ret == -ENODEV) {
594 dwc->usb3_generic_phy = NULL;
595 } else if (ret == -EPROBE_DEFER) {
596 return ret;
597 } else {
598 dev_err(dev, "no usb3 phy configured\n");
599 return ret;
600 }
601 }
602
603 dwc->xhci_resources[0].start = res->start;
604 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
605 DWC3_XHCI_REGS_END;
606 dwc->xhci_resources[0].flags = res->flags;
607 dwc->xhci_resources[0].name = res->name;
608
609 res->start += DWC3_GLOBALS_REGS_START;
610
611 /*
612 * Request memory region but exclude xHCI regs,
613 * since it will be requested by the xhci-plat driver.
614 */
615 regs = devm_ioremap_resource(dev, res);
616 if (IS_ERR(regs))
617 return PTR_ERR(regs);
618
619 spin_lock_init(&dwc->lock);
620 platform_set_drvdata(pdev, dwc);
621
622 dwc->regs = regs;
623 dwc->regs_size = resource_size(res);
624 dwc->dev = dev;
625
626 dev->dma_mask = dev->parent->dma_mask;
627 dev->dma_parms = dev->parent->dma_parms;
628 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
629
630 pm_runtime_enable(dev);
631 pm_runtime_get_sync(dev);
632 pm_runtime_forbid(dev);
633
634 dwc3_cache_hwparams(dwc);
635
636 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
637 if (ret) {
638 dev_err(dwc->dev, "failed to allocate event buffers\n");
639 ret = -ENOMEM;
640 goto err0;
641 }
642
643 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
644 dwc->dr_mode = USB_DR_MODE_HOST;
645 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
646 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
647
648 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
649 dwc->dr_mode = USB_DR_MODE_OTG;
650
651 ret = dwc3_core_init(dwc);
652 if (ret) {
653 dev_err(dev, "failed to initialize core\n");
654 goto err0;
655 }
656
657 usb_phy_set_suspend(dwc->usb2_phy, 0);
658 usb_phy_set_suspend(dwc->usb3_phy, 0);
659 ret = phy_power_on(dwc->usb2_generic_phy);
660 if (ret < 0)
661 goto err1;
662
663 ret = phy_power_on(dwc->usb3_generic_phy);
664 if (ret < 0)
665 goto err_usb2phy_power;
666
667 ret = dwc3_event_buffers_setup(dwc);
668 if (ret) {
669 dev_err(dwc->dev, "failed to setup event buffers\n");
670 goto err_usb3phy_power;
671 }
672
673 switch (dwc->dr_mode) {
674 case USB_DR_MODE_PERIPHERAL:
675 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
676 ret = dwc3_gadget_init(dwc);
677 if (ret) {
678 dev_err(dev, "failed to initialize gadget\n");
679 goto err2;
680 }
681 break;
682 case USB_DR_MODE_HOST:
683 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
684 ret = dwc3_host_init(dwc);
685 if (ret) {
686 dev_err(dev, "failed to initialize host\n");
687 goto err2;
688 }
689 break;
690 case USB_DR_MODE_OTG:
691 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
692 ret = dwc3_host_init(dwc);
693 if (ret) {
694 dev_err(dev, "failed to initialize host\n");
695 goto err2;
696 }
697
698 ret = dwc3_gadget_init(dwc);
699 if (ret) {
700 dev_err(dev, "failed to initialize gadget\n");
701 goto err2;
702 }
703 break;
704 default:
705 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
706 goto err2;
707 }
708
709 ret = dwc3_debugfs_init(dwc);
710 if (ret) {
711 dev_err(dev, "failed to initialize debugfs\n");
712 goto err3;
713 }
714
715 pm_runtime_allow(dev);
716
717 return 0;
718
719err3:
720 switch (dwc->dr_mode) {
721 case USB_DR_MODE_PERIPHERAL:
722 dwc3_gadget_exit(dwc);
723 break;
724 case USB_DR_MODE_HOST:
725 dwc3_host_exit(dwc);
726 break;
727 case USB_DR_MODE_OTG:
728 dwc3_host_exit(dwc);
729 dwc3_gadget_exit(dwc);
730 break;
731 default:
732 /* do nothing */
733 break;
734 }
735
736err2:
737 dwc3_event_buffers_cleanup(dwc);
738
739err_usb3phy_power:
740 phy_power_off(dwc->usb3_generic_phy);
741
742err_usb2phy_power:
743 phy_power_off(dwc->usb2_generic_phy);
744
745err1:
746 usb_phy_set_suspend(dwc->usb2_phy, 1);
747 usb_phy_set_suspend(dwc->usb3_phy, 1);
748 dwc3_core_exit(dwc);
749
750err0:
751 dwc3_free_event_buffers(dwc);
752
753 return ret;
754}
755
756static int dwc3_remove(struct platform_device *pdev)
757{
758 struct dwc3 *dwc = platform_get_drvdata(pdev);
759
760 usb_phy_set_suspend(dwc->usb2_phy, 1);
761 usb_phy_set_suspend(dwc->usb3_phy, 1);
762 phy_power_off(dwc->usb2_generic_phy);
763 phy_power_off(dwc->usb3_generic_phy);
764
765 pm_runtime_put_sync(&pdev->dev);
766 pm_runtime_disable(&pdev->dev);
767
768 dwc3_debugfs_exit(dwc);
769
770 switch (dwc->dr_mode) {
771 case USB_DR_MODE_PERIPHERAL:
772 dwc3_gadget_exit(dwc);
773 break;
774 case USB_DR_MODE_HOST:
775 dwc3_host_exit(dwc);
776 break;
777 case USB_DR_MODE_OTG:
778 dwc3_host_exit(dwc);
779 dwc3_gadget_exit(dwc);
780 break;
781 default:
782 /* do nothing */
783 break;
784 }
785
786 dwc3_event_buffers_cleanup(dwc);
787 dwc3_free_event_buffers(dwc);
788 dwc3_core_exit(dwc);
789
790 return 0;
791}
792
793#ifdef CONFIG_PM_SLEEP
794static int dwc3_prepare(struct device *dev)
795{
796 struct dwc3 *dwc = dev_get_drvdata(dev);
797 unsigned long flags;
798
799 spin_lock_irqsave(&dwc->lock, flags);
800
801 switch (dwc->dr_mode) {
802 case USB_DR_MODE_PERIPHERAL:
803 case USB_DR_MODE_OTG:
804 dwc3_gadget_prepare(dwc);
805 /* FALLTHROUGH */
806 case USB_DR_MODE_HOST:
807 default:
808 dwc3_event_buffers_cleanup(dwc);
809 break;
810 }
811
812 spin_unlock_irqrestore(&dwc->lock, flags);
813
814 return 0;
815}
816
817static void dwc3_complete(struct device *dev)
818{
819 struct dwc3 *dwc = dev_get_drvdata(dev);
820 unsigned long flags;
821
822 spin_lock_irqsave(&dwc->lock, flags);
823
824 dwc3_event_buffers_setup(dwc);
825 switch (dwc->dr_mode) {
826 case USB_DR_MODE_PERIPHERAL:
827 case USB_DR_MODE_OTG:
828 dwc3_gadget_complete(dwc);
829 /* FALLTHROUGH */
830 case USB_DR_MODE_HOST:
831 default:
832 break;
833 }
834
835 spin_unlock_irqrestore(&dwc->lock, flags);
836}
837
838static int dwc3_suspend(struct device *dev)
839{
840 struct dwc3 *dwc = dev_get_drvdata(dev);
841 unsigned long flags;
842
843 spin_lock_irqsave(&dwc->lock, flags);
844
845 switch (dwc->dr_mode) {
846 case USB_DR_MODE_PERIPHERAL:
847 case USB_DR_MODE_OTG:
848 dwc3_gadget_suspend(dwc);
849 /* FALLTHROUGH */
850 case USB_DR_MODE_HOST:
851 default:
852 /* do nothing */
853 break;
854 }
855
856 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
857 spin_unlock_irqrestore(&dwc->lock, flags);
858
859 usb_phy_shutdown(dwc->usb3_phy);
860 usb_phy_shutdown(dwc->usb2_phy);
861 phy_exit(dwc->usb2_generic_phy);
862 phy_exit(dwc->usb3_generic_phy);
863
864 return 0;
865}
866
867static int dwc3_resume(struct device *dev)
868{
869 struct dwc3 *dwc = dev_get_drvdata(dev);
870 unsigned long flags;
871 int ret;
872
873 usb_phy_init(dwc->usb3_phy);
874 usb_phy_init(dwc->usb2_phy);
875 ret = phy_init(dwc->usb2_generic_phy);
876 if (ret < 0)
877 return ret;
878
879 ret = phy_init(dwc->usb3_generic_phy);
880 if (ret < 0)
881 goto err_usb2phy_init;
882
883 spin_lock_irqsave(&dwc->lock, flags);
884
885 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
886
887 switch (dwc->dr_mode) {
888 case USB_DR_MODE_PERIPHERAL:
889 case USB_DR_MODE_OTG:
890 dwc3_gadget_resume(dwc);
891 /* FALLTHROUGH */
892 case USB_DR_MODE_HOST:
893 default:
894 /* do nothing */
895 break;
896 }
897
898 spin_unlock_irqrestore(&dwc->lock, flags);
899
900 pm_runtime_disable(dev);
901 pm_runtime_set_active(dev);
902 pm_runtime_enable(dev);
903
904 return 0;
905
906err_usb2phy_init:
907 phy_exit(dwc->usb2_generic_phy);
908
909 return ret;
910}
911
912static const struct dev_pm_ops dwc3_dev_pm_ops = {
913 .prepare = dwc3_prepare,
914 .complete = dwc3_complete,
915
916 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
917};
918
919#define DWC3_PM_OPS &(dwc3_dev_pm_ops)
920#else
921#define DWC3_PM_OPS NULL
922#endif
923
924#ifdef CONFIG_OF
925static const struct of_device_id of_dwc3_match[] = {
926 {
927 .compatible = "snps,dwc3"
928 },
929 {
930 .compatible = "synopsys,dwc3"
931 },
932 { },
933};
934MODULE_DEVICE_TABLE(of, of_dwc3_match);
935#endif
936
937static struct platform_driver dwc3_driver = {
938 .probe = dwc3_probe,
939 .remove = dwc3_remove,
940 .driver = {
941 .name = "dwc3",
942 .of_match_table = of_match_ptr(of_dwc3_match),
943 .pm = DWC3_PM_OPS,
944 },
945};
946
947module_platform_driver(dwc3_driver);
948
949MODULE_ALIAS("platform:dwc3");
950MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
951MODULE_LICENSE("GPL v2");
952MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");