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1/* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
21
22#ifndef _E1000_DEFINES_H_
23#define _E1000_DEFINES_H_
24
25/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
26#define REQ_TX_DESCRIPTOR_MULTIPLE 8
27#define REQ_RX_DESCRIPTOR_MULTIPLE 8
28
29/* Definitions for power management and wakeup registers */
30/* Wake Up Control */
31#define E1000_WUC_APME 0x00000001 /* APM Enable */
32#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
33#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
34#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
35#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
36
37/* Wake Up Filter Control */
38#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
39#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
40#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
41#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
42#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
43#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
44
45/* Wake Up Status */
46#define E1000_WUS_LNKC E1000_WUFC_LNKC
47#define E1000_WUS_MAG E1000_WUFC_MAG
48#define E1000_WUS_EX E1000_WUFC_EX
49#define E1000_WUS_MC E1000_WUFC_MC
50#define E1000_WUS_BC E1000_WUFC_BC
51
52/* Extended Device Control */
53#define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */
54#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
55#define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
56#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
57#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
58#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
59#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
60#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
61#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
62#define E1000_CTRL_EXT_EIAME 0x01000000
63#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
64#define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
65#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
66#define E1000_CTRL_EXT_LSECCK 0x00001000
67#define E1000_CTRL_EXT_PHYPDEN 0x00100000
68
69/* Receive Descriptor bit definitions */
70#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
71#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
72#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
73#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
74#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
75#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
76#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
77#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
78#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
79#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
80#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
81#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
82#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
83#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
84
85#define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */
86#define E1000_RXDEXT_STATERR_CE 0x01000000
87#define E1000_RXDEXT_STATERR_SE 0x02000000
88#define E1000_RXDEXT_STATERR_SEQ 0x04000000
89#define E1000_RXDEXT_STATERR_CXE 0x10000000
90#define E1000_RXDEXT_STATERR_RXE 0x80000000
91
92/* mask to determine if packets should be dropped due to frame errors */
93#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
94 E1000_RXD_ERR_CE | \
95 E1000_RXD_ERR_SE | \
96 E1000_RXD_ERR_SEQ | \
97 E1000_RXD_ERR_CXE | \
98 E1000_RXD_ERR_RXE)
99
100/* Same mask, but for extended and packet split descriptors */
101#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
102 E1000_RXDEXT_STATERR_CE | \
103 E1000_RXDEXT_STATERR_SE | \
104 E1000_RXDEXT_STATERR_SEQ | \
105 E1000_RXDEXT_STATERR_CXE | \
106 E1000_RXDEXT_STATERR_RXE)
107
108#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
109#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
110#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
111#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
112#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
113#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
114
115#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
116
117/* Management Control */
118#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
120#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
121#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
122#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
123/* Enable MAC address filtering */
124#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
125/* Enable MNG packets to host memory */
126#define E1000_MANC_EN_MNG2HOST 0x00200000
127
128#define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */
129#define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */
130#define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */
131#define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */
132
133/* Receive Control */
134#define E1000_RCTL_EN 0x00000002 /* enable */
135#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
136#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
137#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
138#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
139#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
140#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
141#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
142#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
143#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */
144#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
145#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
146#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
147/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
148#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
149#define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
150#define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
151#define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
152/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
153#define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
154#define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
155#define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
156#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
157#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
158#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
159#define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */
160#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
161#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
162#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
163
164/* Use byte values for the following shift parameters
165 * Usage:
166 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
167 * E1000_PSRCTL_BSIZE0_MASK) |
168 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
169 * E1000_PSRCTL_BSIZE1_MASK) |
170 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
171 * E1000_PSRCTL_BSIZE2_MASK) |
172 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
173 * E1000_PSRCTL_BSIZE3_MASK))
174 * where value0 = [128..16256], default=256
175 * value1 = [1024..64512], default=4096
176 * value2 = [0..64512], default=4096
177 * value3 = [0..64512], default=0
178 */
179
180#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
181#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
182#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
183#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
184
185#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
186#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
187#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
188#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
189
190/* SWFW_SYNC Definitions */
191#define E1000_SWFW_EEP_SM 0x1
192#define E1000_SWFW_PHY0_SM 0x2
193#define E1000_SWFW_PHY1_SM 0x4
194#define E1000_SWFW_CSR_SM 0x8
195
196/* Device Control */
197#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
198#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
199#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
200#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
201#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
202#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
203#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
204#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
205#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
206#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
207#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
208#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
209#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
210#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
211#define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */
212#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
213#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
214#define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
215#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
216#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
217#define E1000_CTRL_RST 0x04000000 /* Global reset */
218#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
219#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
220#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
221#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
222
223#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
224
225#define E1000_PCS_LSTS_AN_COMPLETE 0x10000
226
227/* Device Status */
228#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
229#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
230#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
231#define E1000_STATUS_FUNC_SHIFT 2
232#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
233#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
234#define E1000_STATUS_SPEED_MASK 0x000000C0
235#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
236#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
237#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
238#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */
239#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
240#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master Req status */
241
242#define HALF_DUPLEX 1
243#define FULL_DUPLEX 2
244
245#define ADVERTISE_10_HALF 0x0001
246#define ADVERTISE_10_FULL 0x0002
247#define ADVERTISE_100_HALF 0x0004
248#define ADVERTISE_100_FULL 0x0008
249#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
250#define ADVERTISE_1000_FULL 0x0020
251
252/* 1000/H is not supported, nor spec-compliant. */
253#define E1000_ALL_SPEED_DUPLEX ( \
254 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
255 ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
256#define E1000_ALL_NOT_GIG ( \
257 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
258 ADVERTISE_100_FULL)
259#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
260#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
261#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
262
263#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
264
265/* LED Control */
266#define E1000_PHY_LED0_MODE_MASK 0x00000007
267#define E1000_PHY_LED0_IVRT 0x00000008
268#define E1000_PHY_LED0_MASK 0x0000001F
269
270#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
271#define E1000_LEDCTL_LED0_MODE_SHIFT 0
272#define E1000_LEDCTL_LED0_IVRT 0x00000040
273#define E1000_LEDCTL_LED0_BLINK 0x00000080
274
275#define E1000_LEDCTL_MODE_LINK_UP 0x2
276#define E1000_LEDCTL_MODE_LED_ON 0xE
277#define E1000_LEDCTL_MODE_LED_OFF 0xF
278
279/* Transmit Descriptor bit definitions */
280#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
281#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
282#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
283#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
284#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
285#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
286#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
287#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
288#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
289#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
290#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
291#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
292#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
293#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
294#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
295#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
296#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
297#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
298#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
299#define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
300
301/* Transmit Control */
302#define E1000_TCTL_EN 0x00000002 /* enable Tx */
303#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
304#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
305#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
306#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
307#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
308
309/* SerDes Control */
310#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
311#define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410
312
313/* Receive Checksum Control */
314#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
315#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
316#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
317
318/* Header split receive */
319#define E1000_RFCTL_NFSW_DIS 0x00000040
320#define E1000_RFCTL_NFSR_DIS 0x00000080
321#define E1000_RFCTL_ACK_DIS 0x00001000
322#define E1000_RFCTL_EXTEN 0x00008000
323#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
324#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
325
326/* Collision related configuration parameters */
327#define E1000_COLLISION_THRESHOLD 15
328#define E1000_CT_SHIFT 4
329#define E1000_COLLISION_DISTANCE 63
330#define E1000_COLD_SHIFT 12
331
332/* Default values for the transmit IPG register */
333#define DEFAULT_82543_TIPG_IPGT_COPPER 8
334
335#define E1000_TIPG_IPGT_MASK 0x000003FF
336
337#define DEFAULT_82543_TIPG_IPGR1 8
338#define E1000_TIPG_IPGR1_SHIFT 10
339
340#define DEFAULT_82543_TIPG_IPGR2 6
341#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
342#define E1000_TIPG_IPGR2_SHIFT 20
343
344#define MAX_JUMBO_FRAME_SIZE 0x3F00
345
346/* Extended Configuration Control and Size */
347#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
348#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
349#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
350#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
351#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
352#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
353#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
354#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
355#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
356
357#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
358#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
359#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
360#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
361
362#define E1000_KABGTXD_BGSQLBIAS 0x00050000
363
364/* Low Power IDLE Control */
365#define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */
366
367/* PBA constants */
368#define E1000_PBA_8K 0x0008 /* 8KB */
369#define E1000_PBA_16K 0x0010 /* 16KB */
370
371#define E1000_PBA_RXA_MASK 0xFFFF
372
373#define E1000_PBS_16K E1000_PBA_16K
374
375/* Uncorrectable/correctable ECC Error counts and enable bits */
376#define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF
377#define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00
378#define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8
379#define E1000_PBECCSTS_ECC_ENABLE 0x00010000
380
381#define IFS_MAX 80
382#define IFS_MIN 40
383#define IFS_RATIO 4
384#define IFS_STEP 10
385#define MIN_NUM_XMITS 1000
386
387/* SW Semaphore Register */
388#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
389#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
390#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
391
392#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
393
394/* Interrupt Cause Read */
395#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
396#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
397#define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
398#define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
399#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
400#define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */
401/* If this bit asserted, the driver should claim the interrupt */
402#define E1000_ICR_INT_ASSERTED 0x80000000
403#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
404#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
405#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
406#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
407#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
408
409/* PBA ECC Register */
410#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
411#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
412#define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */
413#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
414#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */
415
416/* This defines the bits that are set in the Interrupt Mask
417 * Set/Read Register. Each bit is documented below:
418 * o RXT0 = Receiver Timer Interrupt (ring 0)
419 * o TXDW = Transmit Descriptor Written Back
420 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
421 * o RXSEQ = Receive Sequence Error
422 * o LSC = Link Status Change
423 */
424#define IMS_ENABLE_MASK ( \
425 E1000_IMS_RXT0 | \
426 E1000_IMS_TXDW | \
427 E1000_IMS_RXDMT0 | \
428 E1000_IMS_RXSEQ | \
429 E1000_IMS_LSC)
430
431/* Interrupt Mask Set */
432#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
433#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
434#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
435#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
436#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
437#define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */
438#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
439#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
440#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
441#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
442#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */
443
444/* Interrupt Cause Set */
445#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
446#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
447#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
448
449/* Transmit Descriptor Control */
450#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
451#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
452#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
453#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
454#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
455#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
456/* Enable the counting of desc. still to be processed. */
457#define E1000_TXDCTL_COUNT_DESC 0x00400000
458
459/* Flow Control Constants */
460#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
461#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
462#define FLOW_CONTROL_TYPE 0x8808
463
464/* 802.1q VLAN Packet Size */
465#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
466
467/* Receive Address
468 * Number of high/low register pairs in the RAR. The RAR (Receive Address
469 * Registers) holds the directed and multicast addresses that we monitor.
470 * Technically, we have 16 spots. However, we reserve one of these spots
471 * (RAR[15]) for our directed address used by controllers with
472 * manageability enabled, allowing us room for 15 multicast addresses.
473 */
474#define E1000_RAR_ENTRIES 15
475#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
476#define E1000_RAL_MAC_ADDR_LEN 4
477#define E1000_RAH_MAC_ADDR_LEN 2
478
479/* Error Codes */
480#define E1000_ERR_NVM 1
481#define E1000_ERR_PHY 2
482#define E1000_ERR_CONFIG 3
483#define E1000_ERR_PARAM 4
484#define E1000_ERR_MAC_INIT 5
485#define E1000_ERR_PHY_TYPE 6
486#define E1000_ERR_RESET 9
487#define E1000_ERR_MASTER_REQUESTS_PENDING 10
488#define E1000_ERR_HOST_INTERFACE_COMMAND 11
489#define E1000_BLK_PHY_RESET 12
490#define E1000_ERR_SWFW_SYNC 13
491#define E1000_NOT_IMPLEMENTED 14
492#define E1000_ERR_INVALID_ARGUMENT 16
493#define E1000_ERR_NO_SPACE 17
494#define E1000_ERR_NVM_PBA_SECTION 18
495
496/* Loop limit on how long we wait for auto-negotiation to complete */
497#define FIBER_LINK_UP_LIMIT 50
498#define COPPER_LINK_UP_LIMIT 10
499#define PHY_AUTO_NEG_LIMIT 45
500#define PHY_FORCE_LIMIT 20
501/* Number of 100 microseconds we wait for PCI Express master disable */
502#define MASTER_DISABLE_TIMEOUT 800
503/* Number of milliseconds we wait for PHY configuration done after MAC reset */
504#define PHY_CFG_TIMEOUT 100
505/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
506#define MDIO_OWNERSHIP_TIMEOUT 10
507/* Number of milliseconds for NVM auto read done after MAC reset. */
508#define AUTO_READ_DONE_TIMEOUT 10
509
510/* Flow Control */
511#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
512#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
513#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
514
515/* Transmit Configuration Word */
516#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
517#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
518#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
519#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
520#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
521
522/* Receive Configuration Word */
523#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
524#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
525#define E1000_RXCW_C 0x20000000 /* Receive config */
526#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
527
528#define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
529#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
530
531#define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
532#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
533#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
534#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
535#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
536#define E1000_TSYNCRXCTL_TYPE_ALL 0x08
537#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
538#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
539#define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */
540
541#define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000
542#define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000
543
544#define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000
545#define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000
546
547#define E1000_TIMINCA_INCPERIOD_SHIFT 24
548#define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF
549
550/* PCI Express Control */
551#define E1000_GCR_RXD_NO_SNOOP 0x00000001
552#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
553#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
554#define E1000_GCR_TXD_NO_SNOOP 0x00000008
555#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
556#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
557
558#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
559 E1000_GCR_RXDSCW_NO_SNOOP | \
560 E1000_GCR_RXDSCR_NO_SNOOP | \
561 E1000_GCR_TXD_NO_SNOOP | \
562 E1000_GCR_TXDSCW_NO_SNOOP | \
563 E1000_GCR_TXDSCR_NO_SNOOP)
564
565/* NVM Control */
566#define E1000_EECD_SK 0x00000001 /* NVM Clock */
567#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
568#define E1000_EECD_DI 0x00000004 /* NVM Data In */
569#define E1000_EECD_DO 0x00000008 /* NVM Data Out */
570#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
571#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
572#define E1000_EECD_PRES 0x00000100 /* NVM Present */
573#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
574/* NVM Addressing bits based on type (0-small, 1-large) */
575#define E1000_EECD_ADDR_BITS 0x00000400
576#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
577#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
578#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
579#define E1000_EECD_SIZE_EX_SHIFT 11
580#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
581#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
582#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
583#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
584
585#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM r/w regs */
586#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
587#define E1000_NVM_RW_REG_START 1 /* Start operation */
588#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
589#define E1000_NVM_POLL_WRITE 1 /* Flag for polling write complete */
590#define E1000_NVM_POLL_READ 0 /* Flag for polling read complete */
591#define E1000_FLASH_UPDATES 2000
592
593/* NVM Word Offsets */
594#define NVM_COMPAT 0x0003
595#define NVM_ID_LED_SETTINGS 0x0004
596#define NVM_FUTURE_INIT_WORD1 0x0019
597#define NVM_COMPAT_VALID_CSUM 0x0001
598#define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040
599
600#define NVM_INIT_CONTROL2_REG 0x000F
601#define NVM_INIT_CONTROL3_PORT_B 0x0014
602#define NVM_INIT_3GIO_3 0x001A
603#define NVM_INIT_CONTROL3_PORT_A 0x0024
604#define NVM_CFG 0x0012
605#define NVM_ALT_MAC_ADDR_PTR 0x0037
606#define NVM_CHECKSUM_REG 0x003F
607
608#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */
609#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */
610
611/* Mask bits for fields in Word 0x0f of the NVM */
612#define NVM_WORD0F_PAUSE_MASK 0x3000
613#define NVM_WORD0F_PAUSE 0x1000
614#define NVM_WORD0F_ASM_DIR 0x2000
615
616/* Mask bits for fields in Word 0x1a of the NVM */
617#define NVM_WORD1A_ASPM_MASK 0x000C
618
619/* Mask bits for fields in Word 0x03 of the EEPROM */
620#define NVM_COMPAT_LOM 0x0800
621
622/* length of string needed to store PBA number */
623#define E1000_PBANUM_LENGTH 11
624
625/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
626#define NVM_SUM 0xBABA
627
628/* PBA (printed board assembly) number words */
629#define NVM_PBA_OFFSET_0 8
630#define NVM_PBA_OFFSET_1 9
631#define NVM_PBA_PTR_GUARD 0xFAFA
632#define NVM_WORD_SIZE_BASE_SHIFT 6
633
634/* NVM Commands - SPI */
635#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
636#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
637#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
638#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
639#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
640#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
641
642/* SPI NVM Status Register */
643#define NVM_STATUS_RDY_SPI 0x01
644
645/* Word definitions for ID LED Settings */
646#define ID_LED_RESERVED_0000 0x0000
647#define ID_LED_RESERVED_FFFF 0xFFFF
648#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
649 (ID_LED_OFF1_OFF2 << 8) | \
650 (ID_LED_DEF1_DEF2 << 4) | \
651 (ID_LED_DEF1_DEF2))
652#define ID_LED_DEF1_DEF2 0x1
653#define ID_LED_DEF1_ON2 0x2
654#define ID_LED_DEF1_OFF2 0x3
655#define ID_LED_ON1_DEF2 0x4
656#define ID_LED_ON1_ON2 0x5
657#define ID_LED_ON1_OFF2 0x6
658#define ID_LED_OFF1_DEF2 0x7
659#define ID_LED_OFF1_ON2 0x8
660#define ID_LED_OFF1_OFF2 0x9
661
662#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
663#define IGP_ACTIVITY_LED_ENABLE 0x0300
664#define IGP_LED3_MODE 0x07000000
665
666/* PCI/PCI-X/PCI-EX Config space */
667#define PCI_HEADER_TYPE_REGISTER 0x0E
668#define PCIE_LINK_STATUS 0x12
669
670#define PCI_HEADER_TYPE_MULTIFUNC 0x80
671#define PCIE_LINK_WIDTH_MASK 0x3F0
672#define PCIE_LINK_WIDTH_SHIFT 4
673
674#define PHY_REVISION_MASK 0xFFFFFFF0
675#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
676#define MAX_PHY_MULTI_PAGE_REG 0xF
677
678/* Bit definitions for valid PHY IDs.
679 * I = Integrated
680 * E = External
681 */
682#define M88E1000_E_PHY_ID 0x01410C50
683#define M88E1000_I_PHY_ID 0x01410C30
684#define M88E1011_I_PHY_ID 0x01410C20
685#define IGP01E1000_I_PHY_ID 0x02A80380
686#define M88E1111_I_PHY_ID 0x01410CC0
687#define GG82563_E_PHY_ID 0x01410CA0
688#define IGP03E1000_E_PHY_ID 0x02A80390
689#define IFE_E_PHY_ID 0x02A80330
690#define IFE_PLUS_E_PHY_ID 0x02A80320
691#define IFE_C_E_PHY_ID 0x02A80310
692#define BME1000_E_PHY_ID 0x01410CB0
693#define BME1000_E_PHY_ID_R2 0x01410CB1
694#define I82577_E_PHY_ID 0x01540050
695#define I82578_E_PHY_ID 0x004DD040
696#define I82579_E_PHY_ID 0x01540090
697#define I217_E_PHY_ID 0x015400A0
698
699/* M88E1000 Specific Registers */
700#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
701#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
702#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
703
704#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
705#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
706
707/* M88E1000 PHY Specific Control Register */
708#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
709#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
710 /* Manual MDI configuration */
711#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
712/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
713#define M88E1000_PSCR_AUTO_X_1000T 0x0040
714/* Auto crossover enabled all speeds */
715#define M88E1000_PSCR_AUTO_X_MODE 0x0060
716#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
717
718/* M88E1000 PHY Specific Status Register */
719#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
720#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
721#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
722/* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
723#define M88E1000_PSSR_CABLE_LENGTH 0x0380
724#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
725#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
726
727#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
728
729/* Number of times we will attempt to autonegotiate before downshifting if we
730 * are the master
731 */
732#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
733#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
734/* Number of times we will attempt to autonegotiate before downshifting if we
735 * are the slave
736 */
737#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
738#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
739#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
740
741/* M88EC018 Rev 2 specific DownShift settings */
742#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
743#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
744
745#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
746#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
747
748/* BME1000 PHY Specific Control Register */
749#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
750
751/* Bits...
752 * 15-5: page
753 * 4-0: register offset
754 */
755#define GG82563_PAGE_SHIFT 5
756#define GG82563_REG(page, reg) \
757 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
758#define GG82563_MIN_ALT_REG 30
759
760/* GG82563 Specific Registers */
761#define GG82563_PHY_SPEC_CTRL \
762 GG82563_REG(0, 16) /* PHY Specific Control */
763#define GG82563_PHY_PAGE_SELECT \
764 GG82563_REG(0, 22) /* Page Select */
765#define GG82563_PHY_SPEC_CTRL_2 \
766 GG82563_REG(0, 26) /* PHY Specific Control 2 */
767#define GG82563_PHY_PAGE_SELECT_ALT \
768 GG82563_REG(0, 29) /* Alternate Page Select */
769
770#define GG82563_PHY_MAC_SPEC_CTRL \
771 GG82563_REG(2, 21) /* MAC Specific Control Register */
772
773#define GG82563_PHY_DSP_DISTANCE \
774 GG82563_REG(5, 26) /* DSP Distance */
775
776/* Page 193 - Port Control Registers */
777#define GG82563_PHY_KMRN_MODE_CTRL \
778 GG82563_REG(193, 16) /* Kumeran Mode Control */
779#define GG82563_PHY_PWR_MGMT_CTRL \
780 GG82563_REG(193, 20) /* Power Management Control */
781
782/* Page 194 - KMRN Registers */
783#define GG82563_PHY_INBAND_CTRL \
784 GG82563_REG(194, 18) /* Inband Control */
785
786/* MDI Control */
787#define E1000_MDIC_REG_MASK 0x001F0000
788#define E1000_MDIC_REG_SHIFT 16
789#define E1000_MDIC_PHY_SHIFT 21
790#define E1000_MDIC_OP_WRITE 0x04000000
791#define E1000_MDIC_OP_READ 0x08000000
792#define E1000_MDIC_READY 0x10000000
793#define E1000_MDIC_ERROR 0x40000000
794
795/* SerDes Control */
796#define E1000_GEN_POLL_TIMEOUT 640
797
798#endif /* _E1000_DEFINES_H_ */