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1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/hdmi.h>
13#include <linux/regulator/consumer.h>
14#include <linux/reset.h>
15
16#include "hdmi.h"
17#include "drm.h"
18#include "dc.h"
19
20struct tmds_config {
21 unsigned int pclk;
22 u32 pll0;
23 u32 pll1;
24 u32 pe_current;
25 u32 drive_current;
26 u32 peak_current;
27};
28
29struct tegra_hdmi_config {
30 const struct tmds_config *tmds;
31 unsigned int num_tmds;
32
33 unsigned long fuse_override_offset;
34 unsigned long fuse_override_value;
35
36 bool has_sor_io_peak_current;
37};
38
39struct tegra_hdmi {
40 struct host1x_client client;
41 struct tegra_output output;
42 struct device *dev;
43 bool enabled;
44
45 struct regulator *vdd;
46 struct regulator *pll;
47
48 void __iomem *regs;
49 unsigned int irq;
50
51 struct clk *clk_parent;
52 struct clk *clk;
53 struct reset_control *rst;
54
55 const struct tegra_hdmi_config *config;
56
57 unsigned int audio_source;
58 unsigned int audio_freq;
59 bool stereo;
60 bool dvi;
61
62 struct drm_info_list *debugfs_files;
63 struct drm_minor *minor;
64 struct dentry *debugfs;
65};
66
67static inline struct tegra_hdmi *
68host1x_client_to_hdmi(struct host1x_client *client)
69{
70 return container_of(client, struct tegra_hdmi, client);
71}
72
73static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
74{
75 return container_of(output, struct tegra_hdmi, output);
76}
77
78#define HDMI_AUDIOCLK_FREQ 216000000
79#define HDMI_REKEY_DEFAULT 56
80
81enum {
82 AUTO = 0,
83 SPDIF,
84 HDA,
85};
86
87static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
88 unsigned long reg)
89{
90 return readl(hdmi->regs + (reg << 2));
91}
92
93static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
94 unsigned long reg)
95{
96 writel(val, hdmi->regs + (reg << 2));
97}
98
99struct tegra_hdmi_audio_config {
100 unsigned int pclk;
101 unsigned int n;
102 unsigned int cts;
103 unsigned int aval;
104};
105
106static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
107 { 25200000, 4096, 25200, 24000 },
108 { 27000000, 4096, 27000, 24000 },
109 { 74250000, 4096, 74250, 24000 },
110 { 148500000, 4096, 148500, 24000 },
111 { 0, 0, 0, 0 },
112};
113
114static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
115 { 25200000, 5880, 26250, 25000 },
116 { 27000000, 5880, 28125, 25000 },
117 { 74250000, 4704, 61875, 20000 },
118 { 148500000, 4704, 123750, 20000 },
119 { 0, 0, 0, 0 },
120};
121
122static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
123 { 25200000, 6144, 25200, 24000 },
124 { 27000000, 6144, 27000, 24000 },
125 { 74250000, 6144, 74250, 24000 },
126 { 148500000, 6144, 148500, 24000 },
127 { 0, 0, 0, 0 },
128};
129
130static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
131 { 25200000, 11760, 26250, 25000 },
132 { 27000000, 11760, 28125, 25000 },
133 { 74250000, 9408, 61875, 20000 },
134 { 148500000, 9408, 123750, 20000 },
135 { 0, 0, 0, 0 },
136};
137
138static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
139 { 25200000, 12288, 25200, 24000 },
140 { 27000000, 12288, 27000, 24000 },
141 { 74250000, 12288, 74250, 24000 },
142 { 148500000, 12288, 148500, 24000 },
143 { 0, 0, 0, 0 },
144};
145
146static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
147 { 25200000, 23520, 26250, 25000 },
148 { 27000000, 23520, 28125, 25000 },
149 { 74250000, 18816, 61875, 20000 },
150 { 148500000, 18816, 123750, 20000 },
151 { 0, 0, 0, 0 },
152};
153
154static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
155 { 25200000, 24576, 25200, 24000 },
156 { 27000000, 24576, 27000, 24000 },
157 { 74250000, 24576, 74250, 24000 },
158 { 148500000, 24576, 148500, 24000 },
159 { 0, 0, 0, 0 },
160};
161
162static const struct tmds_config tegra20_tmds_config[] = {
163 { /* slow pixel clock modes */
164 .pclk = 27000000,
165 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
166 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
167 SOR_PLL_TX_REG_LOAD(3),
168 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
169 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
170 PE_CURRENT1(PE_CURRENT_0_0_mA) |
171 PE_CURRENT2(PE_CURRENT_0_0_mA) |
172 PE_CURRENT3(PE_CURRENT_0_0_mA),
173 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
174 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
175 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
176 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
177 },
178 { /* high pixel clock modes */
179 .pclk = UINT_MAX,
180 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
181 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
182 SOR_PLL_TX_REG_LOAD(3),
183 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
184 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
185 PE_CURRENT1(PE_CURRENT_6_0_mA) |
186 PE_CURRENT2(PE_CURRENT_6_0_mA) |
187 PE_CURRENT3(PE_CURRENT_6_0_mA),
188 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
189 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
190 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
191 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
192 },
193};
194
195static const struct tmds_config tegra30_tmds_config[] = {
196 { /* 480p modes */
197 .pclk = 27000000,
198 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
199 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
200 SOR_PLL_TX_REG_LOAD(0),
201 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
202 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
203 PE_CURRENT1(PE_CURRENT_0_0_mA) |
204 PE_CURRENT2(PE_CURRENT_0_0_mA) |
205 PE_CURRENT3(PE_CURRENT_0_0_mA),
206 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
207 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
208 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
209 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
210 }, { /* 720p modes */
211 .pclk = 74250000,
212 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
213 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
214 SOR_PLL_TX_REG_LOAD(0),
215 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
216 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
217 PE_CURRENT1(PE_CURRENT_5_0_mA) |
218 PE_CURRENT2(PE_CURRENT_5_0_mA) |
219 PE_CURRENT3(PE_CURRENT_5_0_mA),
220 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
221 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
222 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
223 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
224 }, { /* 1080p modes */
225 .pclk = UINT_MAX,
226 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
227 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
228 SOR_PLL_TX_REG_LOAD(0),
229 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
230 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
231 PE_CURRENT1(PE_CURRENT_5_0_mA) |
232 PE_CURRENT2(PE_CURRENT_5_0_mA) |
233 PE_CURRENT3(PE_CURRENT_5_0_mA),
234 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
235 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
236 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
237 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
238 },
239};
240
241static const struct tmds_config tegra114_tmds_config[] = {
242 { /* 480p/576p / 25.2MHz/27MHz modes */
243 .pclk = 27000000,
244 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
245 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
246 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
247 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
248 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
249 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
250 PE_CURRENT3(PE_CURRENT_0_mA_T114),
251 .drive_current =
252 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
253 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
254 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
255 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
256 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
257 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
258 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
259 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
260 }, { /* 720p / 74.25MHz modes */
261 .pclk = 74250000,
262 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
263 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
264 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
265 SOR_PLL_TMDS_TERMADJ(0),
266 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
267 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
268 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
269 PE_CURRENT3(PE_CURRENT_15_mA_T114),
270 .drive_current =
271 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
272 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
273 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
274 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
275 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
276 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
277 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
278 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
279 }, { /* 1080p / 148.5MHz modes */
280 .pclk = 148500000,
281 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
282 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
283 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
284 SOR_PLL_TMDS_TERMADJ(0),
285 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
286 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
287 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
288 PE_CURRENT3(PE_CURRENT_10_mA_T114),
289 .drive_current =
290 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
291 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
292 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
293 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
294 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
295 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
296 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
297 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
298 }, { /* 225/297MHz modes */
299 .pclk = UINT_MAX,
300 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
301 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
302 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
303 | SOR_PLL_TMDS_TERM_ENABLE,
304 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
305 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
306 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
307 PE_CURRENT3(PE_CURRENT_0_mA_T114),
308 .drive_current =
309 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
310 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
311 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
312 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
313 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
314 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
315 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
316 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
317 },
318};
319
320static const struct tegra_hdmi_audio_config *
321tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
322{
323 const struct tegra_hdmi_audio_config *table;
324
325 switch (audio_freq) {
326 case 32000:
327 table = tegra_hdmi_audio_32k;
328 break;
329
330 case 44100:
331 table = tegra_hdmi_audio_44_1k;
332 break;
333
334 case 48000:
335 table = tegra_hdmi_audio_48k;
336 break;
337
338 case 88200:
339 table = tegra_hdmi_audio_88_2k;
340 break;
341
342 case 96000:
343 table = tegra_hdmi_audio_96k;
344 break;
345
346 case 176400:
347 table = tegra_hdmi_audio_176_4k;
348 break;
349
350 case 192000:
351 table = tegra_hdmi_audio_192k;
352 break;
353
354 default:
355 return NULL;
356 }
357
358 while (table->pclk) {
359 if (table->pclk == pclk)
360 return table;
361
362 table++;
363 }
364
365 return NULL;
366}
367
368static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
369{
370 const unsigned int freqs[] = {
371 32000, 44100, 48000, 88200, 96000, 176400, 192000
372 };
373 unsigned int i;
374
375 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
376 unsigned int f = freqs[i];
377 unsigned int eight_half;
378 unsigned long value;
379 unsigned int delta;
380
381 if (f > 96000)
382 delta = 2;
383 else if (f > 48000)
384 delta = 6;
385 else
386 delta = 9;
387
388 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
389 value = AUDIO_FS_LOW(eight_half - delta) |
390 AUDIO_FS_HIGH(eight_half + delta);
391 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
392 }
393}
394
395static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
396{
397 struct device_node *node = hdmi->dev->of_node;
398 const struct tegra_hdmi_audio_config *config;
399 unsigned int offset = 0;
400 unsigned long value;
401
402 switch (hdmi->audio_source) {
403 case HDA:
404 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
405 break;
406
407 case SPDIF:
408 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
409 break;
410
411 default:
412 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
413 break;
414 }
415
416 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
417 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
418 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
419 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
420 } else {
421 value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
422 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
423
424 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
425 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
426 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
427 }
428
429 config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
430 if (!config) {
431 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
432 hdmi->audio_freq, pclk);
433 return -EINVAL;
434 }
435
436 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
437
438 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
439 AUDIO_N_VALUE(config->n - 1);
440 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
441
442 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
443 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
444
445 value = ACR_SUBPACK_CTS(config->cts);
446 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
447
448 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
449 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
450
451 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
452 value &= ~AUDIO_N_RESETF;
453 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
454
455 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
456 switch (hdmi->audio_freq) {
457 case 32000:
458 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
459 break;
460
461 case 44100:
462 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
463 break;
464
465 case 48000:
466 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
467 break;
468
469 case 88200:
470 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
471 break;
472
473 case 96000:
474 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
475 break;
476
477 case 176400:
478 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
479 break;
480
481 case 192000:
482 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
483 break;
484 }
485
486 tegra_hdmi_writel(hdmi, config->aval, offset);
487 }
488
489 tegra_hdmi_setup_audio_fs_tables(hdmi);
490
491 return 0;
492}
493
494static inline unsigned long tegra_hdmi_subpack(const u8 *ptr, size_t size)
495{
496 unsigned long value = 0;
497 size_t i;
498
499 for (i = size; i > 0; i--)
500 value = (value << 8) | ptr[i - 1];
501
502 return value;
503}
504
505static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
506 size_t size)
507{
508 const u8 *ptr = data;
509 unsigned long offset;
510 unsigned long value;
511 size_t i, j;
512
513 switch (ptr[0]) {
514 case HDMI_INFOFRAME_TYPE_AVI:
515 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
516 break;
517
518 case HDMI_INFOFRAME_TYPE_AUDIO:
519 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
520 break;
521
522 case HDMI_INFOFRAME_TYPE_VENDOR:
523 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
524 break;
525
526 default:
527 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
528 ptr[0]);
529 return;
530 }
531
532 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
533 INFOFRAME_HEADER_VERSION(ptr[1]) |
534 INFOFRAME_HEADER_LEN(ptr[2]);
535 tegra_hdmi_writel(hdmi, value, offset);
536 offset++;
537
538 /*
539 * Each subpack contains 7 bytes, divided into:
540 * - subpack_low: bytes 0 - 3
541 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
542 */
543 for (i = 3, j = 0; i < size; i += 7, j += 8) {
544 size_t rem = size - i, num = min_t(size_t, rem, 4);
545
546 value = tegra_hdmi_subpack(&ptr[i], num);
547 tegra_hdmi_writel(hdmi, value, offset++);
548
549 num = min_t(size_t, rem - num, 3);
550
551 value = tegra_hdmi_subpack(&ptr[i + 4], num);
552 tegra_hdmi_writel(hdmi, value, offset++);
553 }
554}
555
556static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
557 struct drm_display_mode *mode)
558{
559 struct hdmi_avi_infoframe frame;
560 u8 buffer[17];
561 ssize_t err;
562
563 if (hdmi->dvi) {
564 tegra_hdmi_writel(hdmi, 0,
565 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
566 return;
567 }
568
569 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
570 if (err < 0) {
571 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
572 return;
573 }
574
575 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
576 if (err < 0) {
577 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
578 return;
579 }
580
581 tegra_hdmi_write_infopack(hdmi, buffer, err);
582
583 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
584 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
585}
586
587static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
588{
589 struct hdmi_audio_infoframe frame;
590 u8 buffer[14];
591 ssize_t err;
592
593 if (hdmi->dvi) {
594 tegra_hdmi_writel(hdmi, 0,
595 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
596 return;
597 }
598
599 err = hdmi_audio_infoframe_init(&frame);
600 if (err < 0) {
601 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
602 err);
603 return;
604 }
605
606 frame.channels = 2;
607
608 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
609 if (err < 0) {
610 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
611 err);
612 return;
613 }
614
615 /*
616 * The audio infoframe has only one set of subpack registers, so the
617 * infoframe needs to be truncated. One set of subpack registers can
618 * contain 7 bytes. Including the 3 byte header only the first 10
619 * bytes can be programmed.
620 */
621 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
622
623 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
624 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
625}
626
627static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
628{
629 struct hdmi_vendor_infoframe frame;
630 unsigned long value;
631 u8 buffer[10];
632 ssize_t err;
633
634 if (!hdmi->stereo) {
635 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
636 value &= ~GENERIC_CTRL_ENABLE;
637 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
638 return;
639 }
640
641 hdmi_vendor_infoframe_init(&frame);
642 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
643
644 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
645 if (err < 0) {
646 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
647 err);
648 return;
649 }
650
651 tegra_hdmi_write_infopack(hdmi, buffer, err);
652
653 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
654 value |= GENERIC_CTRL_ENABLE;
655 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
656}
657
658static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
659 const struct tmds_config *tmds)
660{
661 unsigned long value;
662
663 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
664 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
665 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
666
667 tegra_hdmi_writel(hdmi, tmds->drive_current,
668 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
669
670 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
671 value |= hdmi->config->fuse_override_value;
672 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
673
674 if (hdmi->config->has_sor_io_peak_current)
675 tegra_hdmi_writel(hdmi, tmds->peak_current,
676 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
677}
678
679static bool tegra_output_is_hdmi(struct tegra_output *output)
680{
681 struct edid *edid;
682
683 if (!output->connector.edid_blob_ptr)
684 return false;
685
686 edid = (struct edid *)output->connector.edid_blob_ptr->data;
687
688 return drm_detect_hdmi_monitor(edid);
689}
690
691static int tegra_output_hdmi_enable(struct tegra_output *output)
692{
693 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
694 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
695 struct drm_display_mode *mode = &dc->base.mode;
696 struct tegra_hdmi *hdmi = to_hdmi(output);
697 struct device_node *node = hdmi->dev->of_node;
698 unsigned int pulse_start, div82, pclk;
699 unsigned long value;
700 int retries = 1000;
701 int err;
702
703 if (hdmi->enabled)
704 return 0;
705
706 hdmi->dvi = !tegra_output_is_hdmi(output);
707
708 pclk = mode->clock * 1000;
709 h_sync_width = mode->hsync_end - mode->hsync_start;
710 h_back_porch = mode->htotal - mode->hsync_end;
711 h_front_porch = mode->hsync_start - mode->hdisplay;
712
713 err = regulator_enable(hdmi->pll);
714 if (err < 0) {
715 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
716 return err;
717 }
718
719 /*
720 * This assumes that the display controller will divide its parent
721 * clock by 2 to generate the pixel clock.
722 */
723 err = tegra_output_setup_clock(output, hdmi->clk, pclk * 2);
724 if (err < 0) {
725 dev_err(hdmi->dev, "failed to setup clock: %d\n", err);
726 return err;
727 }
728
729 err = clk_set_rate(hdmi->clk, pclk);
730 if (err < 0)
731 return err;
732
733 err = clk_enable(hdmi->clk);
734 if (err < 0) {
735 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
736 return err;
737 }
738
739 reset_control_assert(hdmi->rst);
740 usleep_range(1000, 2000);
741 reset_control_deassert(hdmi->rst);
742
743 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
744 DC_DISP_DISP_TIMING_OPTIONS);
745 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
746 DC_DISP_DISP_COLOR_CONTROL);
747
748 /* video_preamble uses h_pulse2 */
749 pulse_start = 1 + h_sync_width + h_back_porch - 10;
750
751 tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
752
753 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
754 PULSE_LAST_END_A;
755 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
756
757 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
758 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
759
760 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
761 VSYNC_WINDOW_ENABLE;
762 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
763
764 if (dc->pipe)
765 value = HDMI_SRC_DISPLAYB;
766 else
767 value = HDMI_SRC_DISPLAYA;
768
769 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
770 (mode->vdisplay == 576)))
771 tegra_hdmi_writel(hdmi,
772 value | ARM_VIDEO_RANGE_FULL,
773 HDMI_NV_PDISP_INPUT_CONTROL);
774 else
775 tegra_hdmi_writel(hdmi,
776 value | ARM_VIDEO_RANGE_LIMITED,
777 HDMI_NV_PDISP_INPUT_CONTROL);
778
779 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
780 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
781 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
782
783 if (!hdmi->dvi) {
784 err = tegra_hdmi_setup_audio(hdmi, pclk);
785 if (err < 0)
786 hdmi->dvi = true;
787 }
788
789 if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
790 /*
791 * TODO: add ELD support
792 */
793 }
794
795 rekey = HDMI_REKEY_DEFAULT;
796 value = HDMI_CTRL_REKEY(rekey);
797 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
798 h_front_porch - rekey - 18) / 32);
799
800 if (!hdmi->dvi)
801 value |= HDMI_CTRL_ENABLE;
802
803 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
804
805 if (hdmi->dvi)
806 tegra_hdmi_writel(hdmi, 0x0,
807 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
808 else
809 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
810 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
811
812 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
813 tegra_hdmi_setup_audio_infoframe(hdmi);
814 tegra_hdmi_setup_stereo_infoframe(hdmi);
815
816 /* TMDS CONFIG */
817 for (i = 0; i < hdmi->config->num_tmds; i++) {
818 if (pclk <= hdmi->config->tmds[i].pclk) {
819 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
820 break;
821 }
822 }
823
824 tegra_hdmi_writel(hdmi,
825 SOR_SEQ_CTL_PU_PC(0) |
826 SOR_SEQ_PU_PC_ALT(0) |
827 SOR_SEQ_PD_PC(8) |
828 SOR_SEQ_PD_PC_ALT(8),
829 HDMI_NV_PDISP_SOR_SEQ_CTL);
830
831 value = SOR_SEQ_INST_WAIT_TIME(1) |
832 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
833 SOR_SEQ_INST_HALT |
834 SOR_SEQ_INST_PIN_A_LOW |
835 SOR_SEQ_INST_PIN_B_LOW |
836 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
837
838 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
839 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
840
841 value = 0x1c800;
842 value &= ~SOR_CSTM_ROTCLK(~0);
843 value |= SOR_CSTM_ROTCLK(2);
844 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
845
846 /* start SOR */
847 tegra_hdmi_writel(hdmi,
848 SOR_PWR_NORMAL_STATE_PU |
849 SOR_PWR_NORMAL_START_NORMAL |
850 SOR_PWR_SAFE_STATE_PD |
851 SOR_PWR_SETTING_NEW_TRIGGER,
852 HDMI_NV_PDISP_SOR_PWR);
853 tegra_hdmi_writel(hdmi,
854 SOR_PWR_NORMAL_STATE_PU |
855 SOR_PWR_NORMAL_START_NORMAL |
856 SOR_PWR_SAFE_STATE_PD |
857 SOR_PWR_SETTING_NEW_DONE,
858 HDMI_NV_PDISP_SOR_PWR);
859
860 do {
861 BUG_ON(--retries < 0);
862 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
863 } while (value & SOR_PWR_SETTING_NEW_PENDING);
864
865 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
866 SOR_STATE_ASY_OWNER_HEAD0 |
867 SOR_STATE_ASY_SUBOWNER_BOTH |
868 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
869 SOR_STATE_ASY_DEPOL_POS;
870
871 /* setup sync polarities */
872 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
873 value |= SOR_STATE_ASY_HSYNCPOL_POS;
874
875 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
876 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
877
878 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
879 value |= SOR_STATE_ASY_VSYNCPOL_POS;
880
881 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
882 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
883
884 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
885
886 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
887 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
888
889 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
890 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
891 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
892 HDMI_NV_PDISP_SOR_STATE1);
893 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
894
895 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
896 value |= HDMI_ENABLE;
897 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
898
899 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
900 value &= ~DISP_CTRL_MODE_MASK;
901 value |= DISP_CTRL_MODE_C_DISPLAY;
902 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
903
904 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
905 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
906 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
907 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
908
909 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
910 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
911
912 /* TODO: add HDCP support */
913
914 hdmi->enabled = true;
915
916 return 0;
917}
918
919static int tegra_output_hdmi_disable(struct tegra_output *output)
920{
921 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
922 struct tegra_hdmi *hdmi = to_hdmi(output);
923 unsigned long value;
924
925 if (!hdmi->enabled)
926 return 0;
927
928 /*
929 * The following accesses registers of the display controller, so make
930 * sure it's only executed when the output is attached to one.
931 */
932 if (dc) {
933 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
934 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
935 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
936 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
937
938 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
939 value &= ~DISP_CTRL_MODE_MASK;
940 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
941
942 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
943 value &= ~HDMI_ENABLE;
944 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
945
946 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
947 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
948 }
949
950 reset_control_assert(hdmi->rst);
951 clk_disable(hdmi->clk);
952 regulator_disable(hdmi->pll);
953
954 hdmi->enabled = false;
955
956 return 0;
957}
958
959static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
960 struct clk *clk, unsigned long pclk)
961{
962 struct tegra_hdmi *hdmi = to_hdmi(output);
963 struct clk *base;
964 int err;
965
966 err = clk_set_parent(clk, hdmi->clk_parent);
967 if (err < 0) {
968 dev_err(output->dev, "failed to set parent: %d\n", err);
969 return err;
970 }
971
972 base = clk_get_parent(hdmi->clk_parent);
973
974 /*
975 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
976 * respectively, each of which divides the base pll_d by 2.
977 */
978 err = clk_set_rate(base, pclk * 2);
979 if (err < 0)
980 dev_err(output->dev,
981 "failed to set base clock rate to %lu Hz\n",
982 pclk * 2);
983
984 return 0;
985}
986
987static int tegra_output_hdmi_check_mode(struct tegra_output *output,
988 struct drm_display_mode *mode,
989 enum drm_mode_status *status)
990{
991 struct tegra_hdmi *hdmi = to_hdmi(output);
992 unsigned long pclk = mode->clock * 1000;
993 struct clk *parent;
994 long err;
995
996 parent = clk_get_parent(hdmi->clk_parent);
997
998 err = clk_round_rate(parent, pclk * 4);
999 if (err <= 0)
1000 *status = MODE_NOCLOCK;
1001 else
1002 *status = MODE_OK;
1003
1004 return 0;
1005}
1006
1007static const struct tegra_output_ops hdmi_ops = {
1008 .enable = tegra_output_hdmi_enable,
1009 .disable = tegra_output_hdmi_disable,
1010 .setup_clock = tegra_output_hdmi_setup_clock,
1011 .check_mode = tegra_output_hdmi_check_mode,
1012};
1013
1014static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1015{
1016 struct drm_info_node *node = s->private;
1017 struct tegra_hdmi *hdmi = node->info_ent->data;
1018 int err;
1019
1020 err = clk_enable(hdmi->clk);
1021 if (err)
1022 return err;
1023
1024#define DUMP_REG(name) \
1025 seq_printf(s, "%-56s %#05x %08lx\n", #name, name, \
1026 tegra_hdmi_readl(hdmi, name))
1027
1028 DUMP_REG(HDMI_CTXSW);
1029 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
1030 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
1031 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
1032 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
1033 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
1034 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
1035 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
1036 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
1037 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
1038 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
1039 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
1040 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
1041 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
1042 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
1043 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
1044 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
1045 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
1046 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
1047 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
1048 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
1049 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
1050 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
1051 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
1052 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
1053 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
1054 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
1055 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
1056 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
1057 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
1058 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1059 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
1060 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
1061 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
1062 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
1063 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1064 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
1065 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
1066 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1067 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
1068 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
1069 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
1070 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1071 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
1072 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
1073 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
1074 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
1075 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
1076 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
1077 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
1078 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
1079 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
1080 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
1081 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
1082 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
1083 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
1084 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1085 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1086 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
1087 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
1088 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
1089 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
1090 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
1091 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
1092 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
1093 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
1094 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
1095 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
1096 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
1097 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
1098 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1099 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
1100 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
1101 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
1102 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
1103 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
1104 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
1105 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
1106 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
1107 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
1108 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1109 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1110 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
1111 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1112 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1113 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1114 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1115 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1116 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1117 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1118 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1119 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1120 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1121 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1122 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1123 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1124 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1125 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1126 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1127 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1128 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1129 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1130 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1131 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1132 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1133 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1134 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1135 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1136 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1137 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1138 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1139 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1140 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1141 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1142 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1143 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1144 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1145 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1146 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1147 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1148 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1149 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1150 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1151 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1152 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1153 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1154 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1155 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1156 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1157 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1158 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1159 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1160 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1161 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1162 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1163 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1164 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1165 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1166 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1167 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1168 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1169 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1170 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1171 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1172 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1173 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1174 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1175 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1176 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1177 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1178 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1179 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1180 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1181 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1182 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1183 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1184 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1185 DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1186
1187#undef DUMP_REG
1188
1189 clk_disable(hdmi->clk);
1190
1191 return 0;
1192}
1193
1194static struct drm_info_list debugfs_files[] = {
1195 { "regs", tegra_hdmi_show_regs, 0, NULL },
1196};
1197
1198static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1199 struct drm_minor *minor)
1200{
1201 unsigned int i;
1202 int err;
1203
1204 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1205 if (!hdmi->debugfs)
1206 return -ENOMEM;
1207
1208 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1209 GFP_KERNEL);
1210 if (!hdmi->debugfs_files) {
1211 err = -ENOMEM;
1212 goto remove;
1213 }
1214
1215 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1216 hdmi->debugfs_files[i].data = hdmi;
1217
1218 err = drm_debugfs_create_files(hdmi->debugfs_files,
1219 ARRAY_SIZE(debugfs_files),
1220 hdmi->debugfs, minor);
1221 if (err < 0)
1222 goto free;
1223
1224 hdmi->minor = minor;
1225
1226 return 0;
1227
1228free:
1229 kfree(hdmi->debugfs_files);
1230 hdmi->debugfs_files = NULL;
1231remove:
1232 debugfs_remove(hdmi->debugfs);
1233 hdmi->debugfs = NULL;
1234
1235 return err;
1236}
1237
1238static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1239{
1240 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1241 hdmi->minor);
1242 hdmi->minor = NULL;
1243
1244 kfree(hdmi->debugfs_files);
1245 hdmi->debugfs_files = NULL;
1246
1247 debugfs_remove(hdmi->debugfs);
1248 hdmi->debugfs = NULL;
1249
1250 return 0;
1251}
1252
1253static int tegra_hdmi_init(struct host1x_client *client)
1254{
1255 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
1256 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1257 int err;
1258
1259 err = regulator_enable(hdmi->vdd);
1260 if (err < 0) {
1261 dev_err(client->dev, "failed to enable VDD regulator: %d\n",
1262 err);
1263 return err;
1264 }
1265
1266 hdmi->output.type = TEGRA_OUTPUT_HDMI;
1267 hdmi->output.dev = client->dev;
1268 hdmi->output.ops = &hdmi_ops;
1269
1270 err = tegra_output_init(tegra->drm, &hdmi->output);
1271 if (err < 0) {
1272 dev_err(client->dev, "output setup failed: %d\n", err);
1273 return err;
1274 }
1275
1276 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1277 err = tegra_hdmi_debugfs_init(hdmi, tegra->drm->primary);
1278 if (err < 0)
1279 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1280 }
1281
1282 return 0;
1283}
1284
1285static int tegra_hdmi_exit(struct host1x_client *client)
1286{
1287 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1288 int err;
1289
1290 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1291 err = tegra_hdmi_debugfs_exit(hdmi);
1292 if (err < 0)
1293 dev_err(client->dev, "debugfs cleanup failed: %d\n",
1294 err);
1295 }
1296
1297 err = tegra_output_disable(&hdmi->output);
1298 if (err < 0) {
1299 dev_err(client->dev, "output failed to disable: %d\n", err);
1300 return err;
1301 }
1302
1303 err = tegra_output_exit(&hdmi->output);
1304 if (err < 0) {
1305 dev_err(client->dev, "output cleanup failed: %d\n", err);
1306 return err;
1307 }
1308
1309 regulator_disable(hdmi->vdd);
1310
1311 return 0;
1312}
1313
1314static const struct host1x_client_ops hdmi_client_ops = {
1315 .init = tegra_hdmi_init,
1316 .exit = tegra_hdmi_exit,
1317};
1318
1319static const struct tegra_hdmi_config tegra20_hdmi_config = {
1320 .tmds = tegra20_tmds_config,
1321 .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1322 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1323 .fuse_override_value = 1 << 31,
1324 .has_sor_io_peak_current = false,
1325};
1326
1327static const struct tegra_hdmi_config tegra30_hdmi_config = {
1328 .tmds = tegra30_tmds_config,
1329 .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1330 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1331 .fuse_override_value = 1 << 31,
1332 .has_sor_io_peak_current = false,
1333};
1334
1335static const struct tegra_hdmi_config tegra114_hdmi_config = {
1336 .tmds = tegra114_tmds_config,
1337 .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1338 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1339 .fuse_override_value = 1 << 31,
1340 .has_sor_io_peak_current = true,
1341};
1342
1343static const struct of_device_id tegra_hdmi_of_match[] = {
1344 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1345 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1346 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1347 { },
1348};
1349
1350static int tegra_hdmi_probe(struct platform_device *pdev)
1351{
1352 const struct of_device_id *match;
1353 struct tegra_hdmi *hdmi;
1354 struct resource *regs;
1355 int err;
1356
1357 match = of_match_node(tegra_hdmi_of_match, pdev->dev.of_node);
1358 if (!match)
1359 return -ENODEV;
1360
1361 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1362 if (!hdmi)
1363 return -ENOMEM;
1364
1365 hdmi->config = match->data;
1366 hdmi->dev = &pdev->dev;
1367 hdmi->audio_source = AUTO;
1368 hdmi->audio_freq = 44100;
1369 hdmi->stereo = false;
1370 hdmi->dvi = false;
1371
1372 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1373 if (IS_ERR(hdmi->clk)) {
1374 dev_err(&pdev->dev, "failed to get clock\n");
1375 return PTR_ERR(hdmi->clk);
1376 }
1377
1378 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1379 if (IS_ERR(hdmi->rst)) {
1380 dev_err(&pdev->dev, "failed to get reset\n");
1381 return PTR_ERR(hdmi->rst);
1382 }
1383
1384 err = clk_prepare(hdmi->clk);
1385 if (err < 0)
1386 return err;
1387
1388 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1389 if (IS_ERR(hdmi->clk_parent))
1390 return PTR_ERR(hdmi->clk_parent);
1391
1392 err = clk_prepare(hdmi->clk_parent);
1393 if (err < 0)
1394 return err;
1395
1396 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1397 if (err < 0) {
1398 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1399 return err;
1400 }
1401
1402 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1403 if (IS_ERR(hdmi->vdd)) {
1404 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1405 return PTR_ERR(hdmi->vdd);
1406 }
1407
1408 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1409 if (IS_ERR(hdmi->pll)) {
1410 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1411 return PTR_ERR(hdmi->pll);
1412 }
1413
1414 hdmi->output.dev = &pdev->dev;
1415
1416 err = tegra_output_probe(&hdmi->output);
1417 if (err < 0)
1418 return err;
1419
1420 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1421 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1422 if (IS_ERR(hdmi->regs))
1423 return PTR_ERR(hdmi->regs);
1424
1425 err = platform_get_irq(pdev, 0);
1426 if (err < 0)
1427 return err;
1428
1429 hdmi->irq = err;
1430
1431 INIT_LIST_HEAD(&hdmi->client.list);
1432 hdmi->client.ops = &hdmi_client_ops;
1433 hdmi->client.dev = &pdev->dev;
1434
1435 err = host1x_client_register(&hdmi->client);
1436 if (err < 0) {
1437 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1438 err);
1439 return err;
1440 }
1441
1442 platform_set_drvdata(pdev, hdmi);
1443
1444 return 0;
1445}
1446
1447static int tegra_hdmi_remove(struct platform_device *pdev)
1448{
1449 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1450 int err;
1451
1452 err = host1x_client_unregister(&hdmi->client);
1453 if (err < 0) {
1454 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1455 err);
1456 return err;
1457 }
1458
1459 err = tegra_output_remove(&hdmi->output);
1460 if (err < 0) {
1461 dev_err(&pdev->dev, "failed to remove output: %d\n", err);
1462 return err;
1463 }
1464
1465 clk_unprepare(hdmi->clk_parent);
1466 clk_unprepare(hdmi->clk);
1467
1468 return 0;
1469}
1470
1471struct platform_driver tegra_hdmi_driver = {
1472 .driver = {
1473 .name = "tegra-hdmi",
1474 .owner = THIS_MODULE,
1475 .of_match_table = tegra_hdmi_of_match,
1476 },
1477 .probe = tegra_hdmi_probe,
1478 .remove = tegra_hdmi_remove,
1479};