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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
45/*
46 * r100,rv100,rs100,rv200,rs200
47 */
48struct r100_mc_save {
49 u32 GENMO_WT;
50 u32 CRTC_EXT_CNTL;
51 u32 CRTC_GEN_CNTL;
52 u32 CRTC2_GEN_CNTL;
53 u32 CUR_OFFSET;
54 u32 CUR2_OFFSET;
55};
56int r100_init(struct radeon_device *rdev);
57void r100_fini(struct radeon_device *rdev);
58int r100_suspend(struct radeon_device *rdev);
59int r100_resume(struct radeon_device *rdev);
60void r100_vga_set_state(struct radeon_device *rdev, bool state);
61bool r100_gpu_is_lockup(struct radeon_device *rdev);
62int r100_asic_reset(struct radeon_device *rdev);
63u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
64void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
65int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
66void r100_cp_commit(struct radeon_device *rdev);
67void r100_ring_start(struct radeon_device *rdev);
68int r100_irq_set(struct radeon_device *rdev);
69int r100_irq_process(struct radeon_device *rdev);
70void r100_fence_ring_emit(struct radeon_device *rdev,
71 struct radeon_fence *fence);
72int r100_cs_parse(struct radeon_cs_parser *p);
73void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
74uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
75int r100_copy_blit(struct radeon_device *rdev,
76 uint64_t src_offset,
77 uint64_t dst_offset,
78 unsigned num_gpu_pages,
79 struct radeon_fence *fence);
80int r100_set_surface_reg(struct radeon_device *rdev, int reg,
81 uint32_t tiling_flags, uint32_t pitch,
82 uint32_t offset, uint32_t obj_size);
83void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
84void r100_bandwidth_update(struct radeon_device *rdev);
85void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
86int r100_ring_test(struct radeon_device *rdev);
87void r100_hpd_init(struct radeon_device *rdev);
88void r100_hpd_fini(struct radeon_device *rdev);
89bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
90void r100_hpd_set_polarity(struct radeon_device *rdev,
91 enum radeon_hpd_id hpd);
92int r100_debugfs_rbbm_init(struct radeon_device *rdev);
93int r100_debugfs_cp_init(struct radeon_device *rdev);
94void r100_cp_disable(struct radeon_device *rdev);
95int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
96void r100_cp_fini(struct radeon_device *rdev);
97int r100_pci_gart_init(struct radeon_device *rdev);
98void r100_pci_gart_fini(struct radeon_device *rdev);
99int r100_pci_gart_enable(struct radeon_device *rdev);
100void r100_pci_gart_disable(struct radeon_device *rdev);
101int r100_debugfs_mc_info_init(struct radeon_device *rdev);
102int r100_gui_wait_for_idle(struct radeon_device *rdev);
103void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup,
104 struct radeon_cp *cp);
105bool r100_gpu_cp_is_lockup(struct radeon_device *rdev,
106 struct r100_gpu_lockup *lockup,
107 struct radeon_cp *cp);
108void r100_ib_fini(struct radeon_device *rdev);
109int r100_ib_init(struct radeon_device *rdev);
110void r100_irq_disable(struct radeon_device *rdev);
111void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
112void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
113void r100_vram_init_sizes(struct radeon_device *rdev);
114int r100_cp_reset(struct radeon_device *rdev);
115void r100_vga_render_disable(struct radeon_device *rdev);
116void r100_restore_sanity(struct radeon_device *rdev);
117int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
118 struct radeon_cs_packet *pkt,
119 struct radeon_bo *robj);
120int r100_cs_parse_packet0(struct radeon_cs_parser *p,
121 struct radeon_cs_packet *pkt,
122 const unsigned *auth, unsigned n,
123 radeon_packet0_check_t check);
124int r100_cs_packet_parse(struct radeon_cs_parser *p,
125 struct radeon_cs_packet *pkt,
126 unsigned idx);
127void r100_enable_bm(struct radeon_device *rdev);
128void r100_set_common_regs(struct radeon_device *rdev);
129void r100_bm_disable(struct radeon_device *rdev);
130extern bool r100_gui_idle(struct radeon_device *rdev);
131extern void r100_pm_misc(struct radeon_device *rdev);
132extern void r100_pm_prepare(struct radeon_device *rdev);
133extern void r100_pm_finish(struct radeon_device *rdev);
134extern void r100_pm_init_profile(struct radeon_device *rdev);
135extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
136extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
137extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
138extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
139
140/*
141 * r200,rv250,rs300,rv280
142 */
143extern int r200_copy_dma(struct radeon_device *rdev,
144 uint64_t src_offset,
145 uint64_t dst_offset,
146 unsigned num_gpu_pages,
147 struct radeon_fence *fence);
148void r200_set_safe_registers(struct radeon_device *rdev);
149
150/*
151 * r300,r350,rv350,rv380
152 */
153extern int r300_init(struct radeon_device *rdev);
154extern void r300_fini(struct radeon_device *rdev);
155extern int r300_suspend(struct radeon_device *rdev);
156extern int r300_resume(struct radeon_device *rdev);
157extern bool r300_gpu_is_lockup(struct radeon_device *rdev);
158extern int r300_asic_reset(struct radeon_device *rdev);
159extern void r300_ring_start(struct radeon_device *rdev);
160extern void r300_fence_ring_emit(struct radeon_device *rdev,
161 struct radeon_fence *fence);
162extern int r300_cs_parse(struct radeon_cs_parser *p);
163extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
164extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
165extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
166extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
167extern void r300_set_reg_safe(struct radeon_device *rdev);
168extern void r300_mc_program(struct radeon_device *rdev);
169extern void r300_mc_init(struct radeon_device *rdev);
170extern void r300_clock_startup(struct radeon_device *rdev);
171extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
172extern int rv370_pcie_gart_init(struct radeon_device *rdev);
173extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
174extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
175extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
176
177/*
178 * r420,r423,rv410
179 */
180extern int r420_init(struct radeon_device *rdev);
181extern void r420_fini(struct radeon_device *rdev);
182extern int r420_suspend(struct radeon_device *rdev);
183extern int r420_resume(struct radeon_device *rdev);
184extern void r420_pm_init_profile(struct radeon_device *rdev);
185extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
186extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
187extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
188extern void r420_pipes_init(struct radeon_device *rdev);
189
190/*
191 * rs400,rs480
192 */
193extern int rs400_init(struct radeon_device *rdev);
194extern void rs400_fini(struct radeon_device *rdev);
195extern int rs400_suspend(struct radeon_device *rdev);
196extern int rs400_resume(struct radeon_device *rdev);
197void rs400_gart_tlb_flush(struct radeon_device *rdev);
198int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
199uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
200void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
201int rs400_gart_init(struct radeon_device *rdev);
202int rs400_gart_enable(struct radeon_device *rdev);
203void rs400_gart_adjust_size(struct radeon_device *rdev);
204void rs400_gart_disable(struct radeon_device *rdev);
205void rs400_gart_fini(struct radeon_device *rdev);
206
207/*
208 * rs600.
209 */
210extern int rs600_asic_reset(struct radeon_device *rdev);
211extern int rs600_init(struct radeon_device *rdev);
212extern void rs600_fini(struct radeon_device *rdev);
213extern int rs600_suspend(struct radeon_device *rdev);
214extern int rs600_resume(struct radeon_device *rdev);
215int rs600_irq_set(struct radeon_device *rdev);
216int rs600_irq_process(struct radeon_device *rdev);
217void rs600_irq_disable(struct radeon_device *rdev);
218u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
219void rs600_gart_tlb_flush(struct radeon_device *rdev);
220int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
221uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
222void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
223void rs600_bandwidth_update(struct radeon_device *rdev);
224void rs600_hpd_init(struct radeon_device *rdev);
225void rs600_hpd_fini(struct radeon_device *rdev);
226bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
227void rs600_hpd_set_polarity(struct radeon_device *rdev,
228 enum radeon_hpd_id hpd);
229extern void rs600_pm_misc(struct radeon_device *rdev);
230extern void rs600_pm_prepare(struct radeon_device *rdev);
231extern void rs600_pm_finish(struct radeon_device *rdev);
232extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
233extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
234extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
235void rs600_set_safe_registers(struct radeon_device *rdev);
236
237
238/*
239 * rs690,rs740
240 */
241int rs690_init(struct radeon_device *rdev);
242void rs690_fini(struct radeon_device *rdev);
243int rs690_resume(struct radeon_device *rdev);
244int rs690_suspend(struct radeon_device *rdev);
245uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
246void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
247void rs690_bandwidth_update(struct radeon_device *rdev);
248void rs690_line_buffer_adjust(struct radeon_device *rdev,
249 struct drm_display_mode *mode1,
250 struct drm_display_mode *mode2);
251
252/*
253 * rv515
254 */
255struct rv515_mc_save {
256 u32 d1vga_control;
257 u32 d2vga_control;
258 u32 vga_render_control;
259 u32 vga_hdp_control;
260 u32 d1crtc_control;
261 u32 d2crtc_control;
262};
263int rv515_init(struct radeon_device *rdev);
264void rv515_fini(struct radeon_device *rdev);
265uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
266void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
267void rv515_ring_start(struct radeon_device *rdev);
268void rv515_bandwidth_update(struct radeon_device *rdev);
269int rv515_resume(struct radeon_device *rdev);
270int rv515_suspend(struct radeon_device *rdev);
271void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
272void rv515_vga_render_disable(struct radeon_device *rdev);
273void rv515_set_safe_registers(struct radeon_device *rdev);
274void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
275void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
276void rv515_clock_startup(struct radeon_device *rdev);
277void rv515_debugfs(struct radeon_device *rdev);
278
279
280/*
281 * r520,rv530,rv560,rv570,r580
282 */
283int r520_init(struct radeon_device *rdev);
284int r520_resume(struct radeon_device *rdev);
285
286/*
287 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
288 */
289int r600_init(struct radeon_device *rdev);
290void r600_fini(struct radeon_device *rdev);
291int r600_suspend(struct radeon_device *rdev);
292int r600_resume(struct radeon_device *rdev);
293void r600_vga_set_state(struct radeon_device *rdev, bool state);
294int r600_wb_init(struct radeon_device *rdev);
295void r600_wb_fini(struct radeon_device *rdev);
296void r600_cp_commit(struct radeon_device *rdev);
297void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
298uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
299void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
300int r600_cs_parse(struct radeon_cs_parser *p);
301void r600_fence_ring_emit(struct radeon_device *rdev,
302 struct radeon_fence *fence);
303bool r600_gpu_is_lockup(struct radeon_device *rdev);
304int r600_asic_reset(struct radeon_device *rdev);
305int r600_set_surface_reg(struct radeon_device *rdev, int reg,
306 uint32_t tiling_flags, uint32_t pitch,
307 uint32_t offset, uint32_t obj_size);
308void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
309int r600_ib_test(struct radeon_device *rdev);
310void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
311int r600_ring_test(struct radeon_device *rdev);
312int r600_copy_blit(struct radeon_device *rdev,
313 uint64_t src_offset, uint64_t dst_offset,
314 unsigned num_gpu_pages, struct radeon_fence *fence);
315void r600_hpd_init(struct radeon_device *rdev);
316void r600_hpd_fini(struct radeon_device *rdev);
317bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
318void r600_hpd_set_polarity(struct radeon_device *rdev,
319 enum radeon_hpd_id hpd);
320extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
321extern bool r600_gui_idle(struct radeon_device *rdev);
322extern void r600_pm_misc(struct radeon_device *rdev);
323extern void r600_pm_init_profile(struct radeon_device *rdev);
324extern void rs780_pm_init_profile(struct radeon_device *rdev);
325extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
326extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
327extern int r600_get_pcie_lanes(struct radeon_device *rdev);
328bool r600_card_posted(struct radeon_device *rdev);
329void r600_cp_stop(struct radeon_device *rdev);
330int r600_cp_start(struct radeon_device *rdev);
331void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
332int r600_cp_resume(struct radeon_device *rdev);
333void r600_cp_fini(struct radeon_device *rdev);
334int r600_count_pipe_bits(uint32_t val);
335int r600_mc_wait_for_idle(struct radeon_device *rdev);
336int r600_pcie_gart_init(struct radeon_device *rdev);
337void r600_scratch_init(struct radeon_device *rdev);
338int r600_blit_init(struct radeon_device *rdev);
339void r600_blit_fini(struct radeon_device *rdev);
340int r600_init_microcode(struct radeon_device *rdev);
341/* r600 irq */
342int r600_irq_process(struct radeon_device *rdev);
343int r600_irq_init(struct radeon_device *rdev);
344void r600_irq_fini(struct radeon_device *rdev);
345void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
346int r600_irq_set(struct radeon_device *rdev);
347void r600_irq_suspend(struct radeon_device *rdev);
348void r600_disable_interrupts(struct radeon_device *rdev);
349void r600_rlc_stop(struct radeon_device *rdev);
350/* r600 audio */
351int r600_audio_init(struct radeon_device *rdev);
352int r600_audio_tmds_index(struct drm_encoder *encoder);
353void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
354int r600_audio_channels(struct radeon_device *rdev);
355int r600_audio_bits_per_sample(struct radeon_device *rdev);
356int r600_audio_rate(struct radeon_device *rdev);
357uint8_t r600_audio_status_bits(struct radeon_device *rdev);
358uint8_t r600_audio_category_code(struct radeon_device *rdev);
359void r600_audio_schedule_polling(struct radeon_device *rdev);
360void r600_audio_enable_polling(struct drm_encoder *encoder);
361void r600_audio_disable_polling(struct drm_encoder *encoder);
362void r600_audio_fini(struct radeon_device *rdev);
363void r600_hdmi_init(struct drm_encoder *encoder);
364int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
365void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
366/* r600 blit */
367int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
368void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
369void r600_kms_blit_copy(struct radeon_device *rdev,
370 u64 src_gpu_addr, u64 dst_gpu_addr,
371 int size_bytes);
372
373/*
374 * rv770,rv730,rv710,rv740
375 */
376int rv770_init(struct radeon_device *rdev);
377void rv770_fini(struct radeon_device *rdev);
378int rv770_suspend(struct radeon_device *rdev);
379int rv770_resume(struct radeon_device *rdev);
380void rv770_pm_misc(struct radeon_device *rdev);
381u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
382void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
383void r700_cp_stop(struct radeon_device *rdev);
384void r700_cp_fini(struct radeon_device *rdev);
385
386/*
387 * evergreen
388 */
389struct evergreen_mc_save {
390 u32 vga_control[6];
391 u32 vga_render_control;
392 u32 vga_hdp_control;
393 u32 crtc_control[6];
394};
395void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
396int evergreen_init(struct radeon_device *rdev);
397void evergreen_fini(struct radeon_device *rdev);
398int evergreen_suspend(struct radeon_device *rdev);
399int evergreen_resume(struct radeon_device *rdev);
400bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
401int evergreen_asic_reset(struct radeon_device *rdev);
402void evergreen_bandwidth_update(struct radeon_device *rdev);
403void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
404int evergreen_copy_blit(struct radeon_device *rdev,
405 uint64_t src_offset, uint64_t dst_offset,
406 unsigned num_gpu_pages, struct radeon_fence *fence);
407void evergreen_hpd_init(struct radeon_device *rdev);
408void evergreen_hpd_fini(struct radeon_device *rdev);
409bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
410void evergreen_hpd_set_polarity(struct radeon_device *rdev,
411 enum radeon_hpd_id hpd);
412u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
413int evergreen_irq_set(struct radeon_device *rdev);
414int evergreen_irq_process(struct radeon_device *rdev);
415extern int evergreen_cs_parse(struct radeon_cs_parser *p);
416extern void evergreen_pm_misc(struct radeon_device *rdev);
417extern void evergreen_pm_prepare(struct radeon_device *rdev);
418extern void evergreen_pm_finish(struct radeon_device *rdev);
419extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
420extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
421extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
422void evergreen_disable_interrupt_state(struct radeon_device *rdev);
423int evergreen_blit_init(struct radeon_device *rdev);
424void evergreen_blit_fini(struct radeon_device *rdev);
425/* evergreen blit */
426int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
427void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
428void evergreen_kms_blit_copy(struct radeon_device *rdev,
429 u64 src_gpu_addr, u64 dst_gpu_addr,
430 int size_bytes);
431
432/*
433 * cayman
434 */
435void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
436int cayman_init(struct radeon_device *rdev);
437void cayman_fini(struct radeon_device *rdev);
438int cayman_suspend(struct radeon_device *rdev);
439int cayman_resume(struct radeon_device *rdev);
440bool cayman_gpu_is_lockup(struct radeon_device *rdev);
441int cayman_asic_reset(struct radeon_device *rdev);
442
443#endif
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
45void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
46u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
47void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
48u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
49
50/*
51 * r100,rv100,rs100,rv200,rs200
52 */
53struct r100_mc_save {
54 u32 GENMO_WT;
55 u32 CRTC_EXT_CNTL;
56 u32 CRTC_GEN_CNTL;
57 u32 CRTC2_GEN_CNTL;
58 u32 CUR_OFFSET;
59 u32 CUR2_OFFSET;
60};
61int r100_init(struct radeon_device *rdev);
62void r100_fini(struct radeon_device *rdev);
63int r100_suspend(struct radeon_device *rdev);
64int r100_resume(struct radeon_device *rdev);
65void r100_vga_set_state(struct radeon_device *rdev, bool state);
66bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
67int r100_asic_reset(struct radeon_device *rdev);
68u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
69void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
70int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
71void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
72int r100_irq_set(struct radeon_device *rdev);
73int r100_irq_process(struct radeon_device *rdev);
74void r100_fence_ring_emit(struct radeon_device *rdev,
75 struct radeon_fence *fence);
76bool r100_semaphore_ring_emit(struct radeon_device *rdev,
77 struct radeon_ring *cp,
78 struct radeon_semaphore *semaphore,
79 bool emit_wait);
80int r100_cs_parse(struct radeon_cs_parser *p);
81void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
82uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
83int r100_copy_blit(struct radeon_device *rdev,
84 uint64_t src_offset,
85 uint64_t dst_offset,
86 unsigned num_gpu_pages,
87 struct radeon_fence **fence);
88int r100_set_surface_reg(struct radeon_device *rdev, int reg,
89 uint32_t tiling_flags, uint32_t pitch,
90 uint32_t offset, uint32_t obj_size);
91void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
92void r100_bandwidth_update(struct radeon_device *rdev);
93void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
94int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
95void r100_hpd_init(struct radeon_device *rdev);
96void r100_hpd_fini(struct radeon_device *rdev);
97bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
98void r100_hpd_set_polarity(struct radeon_device *rdev,
99 enum radeon_hpd_id hpd);
100int r100_debugfs_rbbm_init(struct radeon_device *rdev);
101int r100_debugfs_cp_init(struct radeon_device *rdev);
102void r100_cp_disable(struct radeon_device *rdev);
103int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
104void r100_cp_fini(struct radeon_device *rdev);
105int r100_pci_gart_init(struct radeon_device *rdev);
106void r100_pci_gart_fini(struct radeon_device *rdev);
107int r100_pci_gart_enable(struct radeon_device *rdev);
108void r100_pci_gart_disable(struct radeon_device *rdev);
109int r100_debugfs_mc_info_init(struct radeon_device *rdev);
110int r100_gui_wait_for_idle(struct radeon_device *rdev);
111int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
112void r100_irq_disable(struct radeon_device *rdev);
113void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
114void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
115void r100_vram_init_sizes(struct radeon_device *rdev);
116int r100_cp_reset(struct radeon_device *rdev);
117void r100_vga_render_disable(struct radeon_device *rdev);
118void r100_restore_sanity(struct radeon_device *rdev);
119int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
120 struct radeon_cs_packet *pkt,
121 struct radeon_bo *robj);
122int r100_cs_parse_packet0(struct radeon_cs_parser *p,
123 struct radeon_cs_packet *pkt,
124 const unsigned *auth, unsigned n,
125 radeon_packet0_check_t check);
126int r100_cs_packet_parse(struct radeon_cs_parser *p,
127 struct radeon_cs_packet *pkt,
128 unsigned idx);
129void r100_enable_bm(struct radeon_device *rdev);
130void r100_set_common_regs(struct radeon_device *rdev);
131void r100_bm_disable(struct radeon_device *rdev);
132extern bool r100_gui_idle(struct radeon_device *rdev);
133extern void r100_pm_misc(struct radeon_device *rdev);
134extern void r100_pm_prepare(struct radeon_device *rdev);
135extern void r100_pm_finish(struct radeon_device *rdev);
136extern void r100_pm_init_profile(struct radeon_device *rdev);
137extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
138extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
139extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
140extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
141extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
142extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
143
144u32 r100_gfx_get_rptr(struct radeon_device *rdev,
145 struct radeon_ring *ring);
146u32 r100_gfx_get_wptr(struct radeon_device *rdev,
147 struct radeon_ring *ring);
148void r100_gfx_set_wptr(struct radeon_device *rdev,
149 struct radeon_ring *ring);
150
151/*
152 * r200,rv250,rs300,rv280
153 */
154extern int r200_copy_dma(struct radeon_device *rdev,
155 uint64_t src_offset,
156 uint64_t dst_offset,
157 unsigned num_gpu_pages,
158 struct radeon_fence **fence);
159void r200_set_safe_registers(struct radeon_device *rdev);
160
161/*
162 * r300,r350,rv350,rv380
163 */
164extern int r300_init(struct radeon_device *rdev);
165extern void r300_fini(struct radeon_device *rdev);
166extern int r300_suspend(struct radeon_device *rdev);
167extern int r300_resume(struct radeon_device *rdev);
168extern int r300_asic_reset(struct radeon_device *rdev);
169extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
170extern void r300_fence_ring_emit(struct radeon_device *rdev,
171 struct radeon_fence *fence);
172extern int r300_cs_parse(struct radeon_cs_parser *p);
173extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
174extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
175extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
176extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
177extern void r300_set_reg_safe(struct radeon_device *rdev);
178extern void r300_mc_program(struct radeon_device *rdev);
179extern void r300_mc_init(struct radeon_device *rdev);
180extern void r300_clock_startup(struct radeon_device *rdev);
181extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
182extern int rv370_pcie_gart_init(struct radeon_device *rdev);
183extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
184extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
185extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
186extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
187
188/*
189 * r420,r423,rv410
190 */
191extern int r420_init(struct radeon_device *rdev);
192extern void r420_fini(struct radeon_device *rdev);
193extern int r420_suspend(struct radeon_device *rdev);
194extern int r420_resume(struct radeon_device *rdev);
195extern void r420_pm_init_profile(struct radeon_device *rdev);
196extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
197extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
198extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
199extern void r420_pipes_init(struct radeon_device *rdev);
200
201/*
202 * rs400,rs480
203 */
204extern int rs400_init(struct radeon_device *rdev);
205extern void rs400_fini(struct radeon_device *rdev);
206extern int rs400_suspend(struct radeon_device *rdev);
207extern int rs400_resume(struct radeon_device *rdev);
208void rs400_gart_tlb_flush(struct radeon_device *rdev);
209int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
210uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
211void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
212int rs400_gart_init(struct radeon_device *rdev);
213int rs400_gart_enable(struct radeon_device *rdev);
214void rs400_gart_adjust_size(struct radeon_device *rdev);
215void rs400_gart_disable(struct radeon_device *rdev);
216void rs400_gart_fini(struct radeon_device *rdev);
217extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
218
219/*
220 * rs600.
221 */
222extern int rs600_asic_reset(struct radeon_device *rdev);
223extern int rs600_init(struct radeon_device *rdev);
224extern void rs600_fini(struct radeon_device *rdev);
225extern int rs600_suspend(struct radeon_device *rdev);
226extern int rs600_resume(struct radeon_device *rdev);
227int rs600_irq_set(struct radeon_device *rdev);
228int rs600_irq_process(struct radeon_device *rdev);
229void rs600_irq_disable(struct radeon_device *rdev);
230u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
231void rs600_gart_tlb_flush(struct radeon_device *rdev);
232int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
233uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
234void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
235void rs600_bandwidth_update(struct radeon_device *rdev);
236void rs600_hpd_init(struct radeon_device *rdev);
237void rs600_hpd_fini(struct radeon_device *rdev);
238bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
239void rs600_hpd_set_polarity(struct radeon_device *rdev,
240 enum radeon_hpd_id hpd);
241extern void rs600_pm_misc(struct radeon_device *rdev);
242extern void rs600_pm_prepare(struct radeon_device *rdev);
243extern void rs600_pm_finish(struct radeon_device *rdev);
244extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
245extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
246extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
247void rs600_set_safe_registers(struct radeon_device *rdev);
248extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
249extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
250
251/*
252 * rs690,rs740
253 */
254int rs690_init(struct radeon_device *rdev);
255void rs690_fini(struct radeon_device *rdev);
256int rs690_resume(struct radeon_device *rdev);
257int rs690_suspend(struct radeon_device *rdev);
258uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
259void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
260void rs690_bandwidth_update(struct radeon_device *rdev);
261void rs690_line_buffer_adjust(struct radeon_device *rdev,
262 struct drm_display_mode *mode1,
263 struct drm_display_mode *mode2);
264extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
265
266/*
267 * rv515
268 */
269struct rv515_mc_save {
270 u32 vga_render_control;
271 u32 vga_hdp_control;
272 bool crtc_enabled[2];
273};
274
275int rv515_init(struct radeon_device *rdev);
276void rv515_fini(struct radeon_device *rdev);
277uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
278void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
279void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
280void rv515_bandwidth_update(struct radeon_device *rdev);
281int rv515_resume(struct radeon_device *rdev);
282int rv515_suspend(struct radeon_device *rdev);
283void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
284void rv515_vga_render_disable(struct radeon_device *rdev);
285void rv515_set_safe_registers(struct radeon_device *rdev);
286void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
287void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
288void rv515_clock_startup(struct radeon_device *rdev);
289void rv515_debugfs(struct radeon_device *rdev);
290int rv515_mc_wait_for_idle(struct radeon_device *rdev);
291
292/*
293 * r520,rv530,rv560,rv570,r580
294 */
295int r520_init(struct radeon_device *rdev);
296int r520_resume(struct radeon_device *rdev);
297int r520_mc_wait_for_idle(struct radeon_device *rdev);
298
299/*
300 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
301 */
302int r600_init(struct radeon_device *rdev);
303void r600_fini(struct radeon_device *rdev);
304int r600_suspend(struct radeon_device *rdev);
305int r600_resume(struct radeon_device *rdev);
306void r600_vga_set_state(struct radeon_device *rdev, bool state);
307int r600_wb_init(struct radeon_device *rdev);
308void r600_wb_fini(struct radeon_device *rdev);
309void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
310uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
311void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
312int r600_cs_parse(struct radeon_cs_parser *p);
313int r600_dma_cs_parse(struct radeon_cs_parser *p);
314void r600_fence_ring_emit(struct radeon_device *rdev,
315 struct radeon_fence *fence);
316bool r600_semaphore_ring_emit(struct radeon_device *rdev,
317 struct radeon_ring *cp,
318 struct radeon_semaphore *semaphore,
319 bool emit_wait);
320void r600_dma_fence_ring_emit(struct radeon_device *rdev,
321 struct radeon_fence *fence);
322bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
323 struct radeon_ring *ring,
324 struct radeon_semaphore *semaphore,
325 bool emit_wait);
326void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
327bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
328bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
329int r600_asic_reset(struct radeon_device *rdev);
330int r600_set_surface_reg(struct radeon_device *rdev, int reg,
331 uint32_t tiling_flags, uint32_t pitch,
332 uint32_t offset, uint32_t obj_size);
333void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
334int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
335int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
336void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
337int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
338int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
339int r600_copy_cpdma(struct radeon_device *rdev,
340 uint64_t src_offset, uint64_t dst_offset,
341 unsigned num_gpu_pages, struct radeon_fence **fence);
342int r600_copy_dma(struct radeon_device *rdev,
343 uint64_t src_offset, uint64_t dst_offset,
344 unsigned num_gpu_pages, struct radeon_fence **fence);
345void r600_hpd_init(struct radeon_device *rdev);
346void r600_hpd_fini(struct radeon_device *rdev);
347bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
348void r600_hpd_set_polarity(struct radeon_device *rdev,
349 enum radeon_hpd_id hpd);
350extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
351extern bool r600_gui_idle(struct radeon_device *rdev);
352extern void r600_pm_misc(struct radeon_device *rdev);
353extern void r600_pm_init_profile(struct radeon_device *rdev);
354extern void rs780_pm_init_profile(struct radeon_device *rdev);
355extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
356extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
357extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
358extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
359extern int r600_get_pcie_lanes(struct radeon_device *rdev);
360bool r600_card_posted(struct radeon_device *rdev);
361void r600_cp_stop(struct radeon_device *rdev);
362int r600_cp_start(struct radeon_device *rdev);
363void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
364int r600_cp_resume(struct radeon_device *rdev);
365void r600_cp_fini(struct radeon_device *rdev);
366int r600_count_pipe_bits(uint32_t val);
367int r600_mc_wait_for_idle(struct radeon_device *rdev);
368int r600_pcie_gart_init(struct radeon_device *rdev);
369void r600_scratch_init(struct radeon_device *rdev);
370int r600_init_microcode(struct radeon_device *rdev);
371u32 r600_gfx_get_rptr(struct radeon_device *rdev,
372 struct radeon_ring *ring);
373u32 r600_gfx_get_wptr(struct radeon_device *rdev,
374 struct radeon_ring *ring);
375void r600_gfx_set_wptr(struct radeon_device *rdev,
376 struct radeon_ring *ring);
377/* r600 irq */
378int r600_irq_process(struct radeon_device *rdev);
379int r600_irq_init(struct radeon_device *rdev);
380void r600_irq_fini(struct radeon_device *rdev);
381void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
382int r600_irq_set(struct radeon_device *rdev);
383void r600_irq_suspend(struct radeon_device *rdev);
384void r600_disable_interrupts(struct radeon_device *rdev);
385void r600_rlc_stop(struct radeon_device *rdev);
386/* r600 audio */
387int r600_audio_init(struct radeon_device *rdev);
388struct r600_audio_pin r600_audio_status(struct radeon_device *rdev);
389void r600_audio_fini(struct radeon_device *rdev);
390int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
391void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
392void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
393void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
394int r600_mc_wait_for_idle(struct radeon_device *rdev);
395u32 r600_get_xclk(struct radeon_device *rdev);
396uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
397int rv6xx_get_temp(struct radeon_device *rdev);
398int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
399int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
400void r600_dpm_post_set_power_state(struct radeon_device *rdev);
401int r600_dpm_late_enable(struct radeon_device *rdev);
402/* r600 dma */
403uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
404 struct radeon_ring *ring);
405uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
406 struct radeon_ring *ring);
407void r600_dma_set_wptr(struct radeon_device *rdev,
408 struct radeon_ring *ring);
409/* rv6xx dpm */
410int rv6xx_dpm_init(struct radeon_device *rdev);
411int rv6xx_dpm_enable(struct radeon_device *rdev);
412void rv6xx_dpm_disable(struct radeon_device *rdev);
413int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
414void rv6xx_setup_asic(struct radeon_device *rdev);
415void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
416void rv6xx_dpm_fini(struct radeon_device *rdev);
417u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
418u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
419void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
420 struct radeon_ps *ps);
421void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
422 struct seq_file *m);
423int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
424 enum radeon_dpm_forced_level level);
425/* rs780 dpm */
426int rs780_dpm_init(struct radeon_device *rdev);
427int rs780_dpm_enable(struct radeon_device *rdev);
428void rs780_dpm_disable(struct radeon_device *rdev);
429int rs780_dpm_set_power_state(struct radeon_device *rdev);
430void rs780_dpm_setup_asic(struct radeon_device *rdev);
431void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
432void rs780_dpm_fini(struct radeon_device *rdev);
433u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
434u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
435void rs780_dpm_print_power_state(struct radeon_device *rdev,
436 struct radeon_ps *ps);
437void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
438 struct seq_file *m);
439int rs780_dpm_force_performance_level(struct radeon_device *rdev,
440 enum radeon_dpm_forced_level level);
441
442/*
443 * rv770,rv730,rv710,rv740
444 */
445int rv770_init(struct radeon_device *rdev);
446void rv770_fini(struct radeon_device *rdev);
447int rv770_suspend(struct radeon_device *rdev);
448int rv770_resume(struct radeon_device *rdev);
449void rv770_pm_misc(struct radeon_device *rdev);
450u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
451void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
452void r700_cp_stop(struct radeon_device *rdev);
453void r700_cp_fini(struct radeon_device *rdev);
454int rv770_copy_dma(struct radeon_device *rdev,
455 uint64_t src_offset, uint64_t dst_offset,
456 unsigned num_gpu_pages,
457 struct radeon_fence **fence);
458u32 rv770_get_xclk(struct radeon_device *rdev);
459int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
460int rv770_get_temp(struct radeon_device *rdev);
461/* rv7xx pm */
462int rv770_dpm_init(struct radeon_device *rdev);
463int rv770_dpm_enable(struct radeon_device *rdev);
464int rv770_dpm_late_enable(struct radeon_device *rdev);
465void rv770_dpm_disable(struct radeon_device *rdev);
466int rv770_dpm_set_power_state(struct radeon_device *rdev);
467void rv770_dpm_setup_asic(struct radeon_device *rdev);
468void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
469void rv770_dpm_fini(struct radeon_device *rdev);
470u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
471u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
472void rv770_dpm_print_power_state(struct radeon_device *rdev,
473 struct radeon_ps *ps);
474void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
475 struct seq_file *m);
476int rv770_dpm_force_performance_level(struct radeon_device *rdev,
477 enum radeon_dpm_forced_level level);
478bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
479
480/*
481 * evergreen
482 */
483struct evergreen_mc_save {
484 u32 vga_render_control;
485 u32 vga_hdp_control;
486 bool crtc_enabled[RADEON_MAX_CRTCS];
487};
488
489void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
490int evergreen_init(struct radeon_device *rdev);
491void evergreen_fini(struct radeon_device *rdev);
492int evergreen_suspend(struct radeon_device *rdev);
493int evergreen_resume(struct radeon_device *rdev);
494bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
495bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
496int evergreen_asic_reset(struct radeon_device *rdev);
497void evergreen_bandwidth_update(struct radeon_device *rdev);
498void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
499void evergreen_hpd_init(struct radeon_device *rdev);
500void evergreen_hpd_fini(struct radeon_device *rdev);
501bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
502void evergreen_hpd_set_polarity(struct radeon_device *rdev,
503 enum radeon_hpd_id hpd);
504u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
505int evergreen_irq_set(struct radeon_device *rdev);
506int evergreen_irq_process(struct radeon_device *rdev);
507extern int evergreen_cs_parse(struct radeon_cs_parser *p);
508extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
509extern void evergreen_pm_misc(struct radeon_device *rdev);
510extern void evergreen_pm_prepare(struct radeon_device *rdev);
511extern void evergreen_pm_finish(struct radeon_device *rdev);
512extern void sumo_pm_init_profile(struct radeon_device *rdev);
513extern void btc_pm_init_profile(struct radeon_device *rdev);
514int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
515int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
516extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
517extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
518extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
519extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
520void evergreen_disable_interrupt_state(struct radeon_device *rdev);
521int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
522void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
523 struct radeon_fence *fence);
524void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
525 struct radeon_ib *ib);
526int evergreen_copy_dma(struct radeon_device *rdev,
527 uint64_t src_offset, uint64_t dst_offset,
528 unsigned num_gpu_pages,
529 struct radeon_fence **fence);
530void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
531void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
532int evergreen_get_temp(struct radeon_device *rdev);
533int sumo_get_temp(struct radeon_device *rdev);
534int tn_get_temp(struct radeon_device *rdev);
535int cypress_dpm_init(struct radeon_device *rdev);
536void cypress_dpm_setup_asic(struct radeon_device *rdev);
537int cypress_dpm_enable(struct radeon_device *rdev);
538void cypress_dpm_disable(struct radeon_device *rdev);
539int cypress_dpm_set_power_state(struct radeon_device *rdev);
540void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
541void cypress_dpm_fini(struct radeon_device *rdev);
542bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
543int btc_dpm_init(struct radeon_device *rdev);
544void btc_dpm_setup_asic(struct radeon_device *rdev);
545int btc_dpm_enable(struct radeon_device *rdev);
546void btc_dpm_disable(struct radeon_device *rdev);
547int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
548int btc_dpm_set_power_state(struct radeon_device *rdev);
549void btc_dpm_post_set_power_state(struct radeon_device *rdev);
550void btc_dpm_fini(struct radeon_device *rdev);
551u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
552u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
553bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
554void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
555 struct seq_file *m);
556int sumo_dpm_init(struct radeon_device *rdev);
557int sumo_dpm_enable(struct radeon_device *rdev);
558int sumo_dpm_late_enable(struct radeon_device *rdev);
559void sumo_dpm_disable(struct radeon_device *rdev);
560int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
561int sumo_dpm_set_power_state(struct radeon_device *rdev);
562void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
563void sumo_dpm_setup_asic(struct radeon_device *rdev);
564void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
565void sumo_dpm_fini(struct radeon_device *rdev);
566u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
567u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
568void sumo_dpm_print_power_state(struct radeon_device *rdev,
569 struct radeon_ps *ps);
570void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
571 struct seq_file *m);
572int sumo_dpm_force_performance_level(struct radeon_device *rdev,
573 enum radeon_dpm_forced_level level);
574
575/*
576 * cayman
577 */
578void cayman_fence_ring_emit(struct radeon_device *rdev,
579 struct radeon_fence *fence);
580void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
581int cayman_init(struct radeon_device *rdev);
582void cayman_fini(struct radeon_device *rdev);
583int cayman_suspend(struct radeon_device *rdev);
584int cayman_resume(struct radeon_device *rdev);
585int cayman_asic_reset(struct radeon_device *rdev);
586void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
587int cayman_vm_init(struct radeon_device *rdev);
588void cayman_vm_fini(struct radeon_device *rdev);
589void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
590uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
591int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
592int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
593void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
594 struct radeon_ib *ib);
595bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
596bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
597void cayman_dma_vm_set_page(struct radeon_device *rdev,
598 struct radeon_ib *ib,
599 uint64_t pe,
600 uint64_t addr, unsigned count,
601 uint32_t incr, uint32_t flags);
602
603void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
604
605u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
606 struct radeon_ring *ring);
607u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
608 struct radeon_ring *ring);
609void cayman_gfx_set_wptr(struct radeon_device *rdev,
610 struct radeon_ring *ring);
611uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
612 struct radeon_ring *ring);
613uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
614 struct radeon_ring *ring);
615void cayman_dma_set_wptr(struct radeon_device *rdev,
616 struct radeon_ring *ring);
617
618int ni_dpm_init(struct radeon_device *rdev);
619void ni_dpm_setup_asic(struct radeon_device *rdev);
620int ni_dpm_enable(struct radeon_device *rdev);
621void ni_dpm_disable(struct radeon_device *rdev);
622int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
623int ni_dpm_set_power_state(struct radeon_device *rdev);
624void ni_dpm_post_set_power_state(struct radeon_device *rdev);
625void ni_dpm_fini(struct radeon_device *rdev);
626u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
627u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
628void ni_dpm_print_power_state(struct radeon_device *rdev,
629 struct radeon_ps *ps);
630void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
631 struct seq_file *m);
632int ni_dpm_force_performance_level(struct radeon_device *rdev,
633 enum radeon_dpm_forced_level level);
634bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
635int trinity_dpm_init(struct radeon_device *rdev);
636int trinity_dpm_enable(struct radeon_device *rdev);
637int trinity_dpm_late_enable(struct radeon_device *rdev);
638void trinity_dpm_disable(struct radeon_device *rdev);
639int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
640int trinity_dpm_set_power_state(struct radeon_device *rdev);
641void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
642void trinity_dpm_setup_asic(struct radeon_device *rdev);
643void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
644void trinity_dpm_fini(struct radeon_device *rdev);
645u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
646u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
647void trinity_dpm_print_power_state(struct radeon_device *rdev,
648 struct radeon_ps *ps);
649void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
650 struct seq_file *m);
651int trinity_dpm_force_performance_level(struct radeon_device *rdev,
652 enum radeon_dpm_forced_level level);
653void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
654
655/* DCE6 - SI */
656void dce6_bandwidth_update(struct radeon_device *rdev);
657int dce6_audio_init(struct radeon_device *rdev);
658void dce6_audio_fini(struct radeon_device *rdev);
659
660/*
661 * si
662 */
663void si_fence_ring_emit(struct radeon_device *rdev,
664 struct radeon_fence *fence);
665void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
666int si_init(struct radeon_device *rdev);
667void si_fini(struct radeon_device *rdev);
668int si_suspend(struct radeon_device *rdev);
669int si_resume(struct radeon_device *rdev);
670bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
671bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
672int si_asic_reset(struct radeon_device *rdev);
673void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
674int si_irq_set(struct radeon_device *rdev);
675int si_irq_process(struct radeon_device *rdev);
676int si_vm_init(struct radeon_device *rdev);
677void si_vm_fini(struct radeon_device *rdev);
678void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
679int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
680int si_copy_dma(struct radeon_device *rdev,
681 uint64_t src_offset, uint64_t dst_offset,
682 unsigned num_gpu_pages,
683 struct radeon_fence **fence);
684void si_dma_vm_set_page(struct radeon_device *rdev,
685 struct radeon_ib *ib,
686 uint64_t pe,
687 uint64_t addr, unsigned count,
688 uint32_t incr, uint32_t flags);
689void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
690u32 si_get_xclk(struct radeon_device *rdev);
691uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
692int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
693int si_get_temp(struct radeon_device *rdev);
694int si_dpm_init(struct radeon_device *rdev);
695void si_dpm_setup_asic(struct radeon_device *rdev);
696int si_dpm_enable(struct radeon_device *rdev);
697int si_dpm_late_enable(struct radeon_device *rdev);
698void si_dpm_disable(struct radeon_device *rdev);
699int si_dpm_pre_set_power_state(struct radeon_device *rdev);
700int si_dpm_set_power_state(struct radeon_device *rdev);
701void si_dpm_post_set_power_state(struct radeon_device *rdev);
702void si_dpm_fini(struct radeon_device *rdev);
703void si_dpm_display_configuration_changed(struct radeon_device *rdev);
704void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
705 struct seq_file *m);
706int si_dpm_force_performance_level(struct radeon_device *rdev,
707 enum radeon_dpm_forced_level level);
708
709/* DCE8 - CIK */
710void dce8_bandwidth_update(struct radeon_device *rdev);
711
712/*
713 * cik
714 */
715uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
716u32 cik_get_xclk(struct radeon_device *rdev);
717uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
718void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
719int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
720int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
721void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
722 struct radeon_fence *fence);
723bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
724 struct radeon_ring *ring,
725 struct radeon_semaphore *semaphore,
726 bool emit_wait);
727void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
728int cik_copy_dma(struct radeon_device *rdev,
729 uint64_t src_offset, uint64_t dst_offset,
730 unsigned num_gpu_pages,
731 struct radeon_fence **fence);
732int cik_copy_cpdma(struct radeon_device *rdev,
733 uint64_t src_offset, uint64_t dst_offset,
734 unsigned num_gpu_pages,
735 struct radeon_fence **fence);
736int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
737int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
738bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
739void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
740 struct radeon_fence *fence);
741void cik_fence_compute_ring_emit(struct radeon_device *rdev,
742 struct radeon_fence *fence);
743bool cik_semaphore_ring_emit(struct radeon_device *rdev,
744 struct radeon_ring *cp,
745 struct radeon_semaphore *semaphore,
746 bool emit_wait);
747void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
748int cik_init(struct radeon_device *rdev);
749void cik_fini(struct radeon_device *rdev);
750int cik_suspend(struct radeon_device *rdev);
751int cik_resume(struct radeon_device *rdev);
752bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
753int cik_asic_reset(struct radeon_device *rdev);
754void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
755int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
756int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
757int cik_irq_set(struct radeon_device *rdev);
758int cik_irq_process(struct radeon_device *rdev);
759int cik_vm_init(struct radeon_device *rdev);
760void cik_vm_fini(struct radeon_device *rdev);
761void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
762void cik_sdma_vm_set_page(struct radeon_device *rdev,
763 struct radeon_ib *ib,
764 uint64_t pe,
765 uint64_t addr, unsigned count,
766 uint32_t incr, uint32_t flags);
767void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
768int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
769u32 cik_gfx_get_rptr(struct radeon_device *rdev,
770 struct radeon_ring *ring);
771u32 cik_gfx_get_wptr(struct radeon_device *rdev,
772 struct radeon_ring *ring);
773void cik_gfx_set_wptr(struct radeon_device *rdev,
774 struct radeon_ring *ring);
775u32 cik_compute_get_rptr(struct radeon_device *rdev,
776 struct radeon_ring *ring);
777u32 cik_compute_get_wptr(struct radeon_device *rdev,
778 struct radeon_ring *ring);
779void cik_compute_set_wptr(struct radeon_device *rdev,
780 struct radeon_ring *ring);
781u32 cik_sdma_get_rptr(struct radeon_device *rdev,
782 struct radeon_ring *ring);
783u32 cik_sdma_get_wptr(struct radeon_device *rdev,
784 struct radeon_ring *ring);
785void cik_sdma_set_wptr(struct radeon_device *rdev,
786 struct radeon_ring *ring);
787int ci_get_temp(struct radeon_device *rdev);
788int kv_get_temp(struct radeon_device *rdev);
789
790int ci_dpm_init(struct radeon_device *rdev);
791int ci_dpm_enable(struct radeon_device *rdev);
792int ci_dpm_late_enable(struct radeon_device *rdev);
793void ci_dpm_disable(struct radeon_device *rdev);
794int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
795int ci_dpm_set_power_state(struct radeon_device *rdev);
796void ci_dpm_post_set_power_state(struct radeon_device *rdev);
797void ci_dpm_setup_asic(struct radeon_device *rdev);
798void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
799void ci_dpm_fini(struct radeon_device *rdev);
800u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
801u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
802void ci_dpm_print_power_state(struct radeon_device *rdev,
803 struct radeon_ps *ps);
804void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
805 struct seq_file *m);
806int ci_dpm_force_performance_level(struct radeon_device *rdev,
807 enum radeon_dpm_forced_level level);
808bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
809void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
810
811int kv_dpm_init(struct radeon_device *rdev);
812int kv_dpm_enable(struct radeon_device *rdev);
813int kv_dpm_late_enable(struct radeon_device *rdev);
814void kv_dpm_disable(struct radeon_device *rdev);
815int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
816int kv_dpm_set_power_state(struct radeon_device *rdev);
817void kv_dpm_post_set_power_state(struct radeon_device *rdev);
818void kv_dpm_setup_asic(struct radeon_device *rdev);
819void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
820void kv_dpm_fini(struct radeon_device *rdev);
821u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
822u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
823void kv_dpm_print_power_state(struct radeon_device *rdev,
824 struct radeon_ps *ps);
825void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
826 struct seq_file *m);
827int kv_dpm_force_performance_level(struct radeon_device *rdev,
828 enum radeon_dpm_forced_level level);
829void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
830void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
831
832/* uvd v1.0 */
833uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
834 struct radeon_ring *ring);
835uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
836 struct radeon_ring *ring);
837void uvd_v1_0_set_wptr(struct radeon_device *rdev,
838 struct radeon_ring *ring);
839
840int uvd_v1_0_init(struct radeon_device *rdev);
841void uvd_v1_0_fini(struct radeon_device *rdev);
842int uvd_v1_0_start(struct radeon_device *rdev);
843void uvd_v1_0_stop(struct radeon_device *rdev);
844
845int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
846int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
847bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
848 struct radeon_ring *ring,
849 struct radeon_semaphore *semaphore,
850 bool emit_wait);
851void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
852
853/* uvd v2.2 */
854int uvd_v2_2_resume(struct radeon_device *rdev);
855void uvd_v2_2_fence_emit(struct radeon_device *rdev,
856 struct radeon_fence *fence);
857
858/* uvd v3.1 */
859bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
860 struct radeon_ring *ring,
861 struct radeon_semaphore *semaphore,
862 bool emit_wait);
863
864/* uvd v4.2 */
865int uvd_v4_2_resume(struct radeon_device *rdev);
866
867/* vce v1.0 */
868uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
869 struct radeon_ring *ring);
870uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
871 struct radeon_ring *ring);
872void vce_v1_0_set_wptr(struct radeon_device *rdev,
873 struct radeon_ring *ring);
874int vce_v1_0_init(struct radeon_device *rdev);
875int vce_v1_0_start(struct radeon_device *rdev);
876
877/* vce v2.0 */
878int vce_v2_0_resume(struct radeon_device *rdev);
879
880#endif