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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
45/*
46 * r100,rv100,rs100,rv200,rs200
47 */
48struct r100_mc_save {
49 u32 GENMO_WT;
50 u32 CRTC_EXT_CNTL;
51 u32 CRTC_GEN_CNTL;
52 u32 CRTC2_GEN_CNTL;
53 u32 CUR_OFFSET;
54 u32 CUR2_OFFSET;
55};
56int r100_init(struct radeon_device *rdev);
57void r100_fini(struct radeon_device *rdev);
58int r100_suspend(struct radeon_device *rdev);
59int r100_resume(struct radeon_device *rdev);
60void r100_vga_set_state(struct radeon_device *rdev, bool state);
61bool r100_gpu_is_lockup(struct radeon_device *rdev);
62int r100_asic_reset(struct radeon_device *rdev);
63u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
64void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
65int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
66void r100_cp_commit(struct radeon_device *rdev);
67void r100_ring_start(struct radeon_device *rdev);
68int r100_irq_set(struct radeon_device *rdev);
69int r100_irq_process(struct radeon_device *rdev);
70void r100_fence_ring_emit(struct radeon_device *rdev,
71 struct radeon_fence *fence);
72int r100_cs_parse(struct radeon_cs_parser *p);
73void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
74uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
75int r100_copy_blit(struct radeon_device *rdev,
76 uint64_t src_offset,
77 uint64_t dst_offset,
78 unsigned num_gpu_pages,
79 struct radeon_fence *fence);
80int r100_set_surface_reg(struct radeon_device *rdev, int reg,
81 uint32_t tiling_flags, uint32_t pitch,
82 uint32_t offset, uint32_t obj_size);
83void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
84void r100_bandwidth_update(struct radeon_device *rdev);
85void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
86int r100_ring_test(struct radeon_device *rdev);
87void r100_hpd_init(struct radeon_device *rdev);
88void r100_hpd_fini(struct radeon_device *rdev);
89bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
90void r100_hpd_set_polarity(struct radeon_device *rdev,
91 enum radeon_hpd_id hpd);
92int r100_debugfs_rbbm_init(struct radeon_device *rdev);
93int r100_debugfs_cp_init(struct radeon_device *rdev);
94void r100_cp_disable(struct radeon_device *rdev);
95int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
96void r100_cp_fini(struct radeon_device *rdev);
97int r100_pci_gart_init(struct radeon_device *rdev);
98void r100_pci_gart_fini(struct radeon_device *rdev);
99int r100_pci_gart_enable(struct radeon_device *rdev);
100void r100_pci_gart_disable(struct radeon_device *rdev);
101int r100_debugfs_mc_info_init(struct radeon_device *rdev);
102int r100_gui_wait_for_idle(struct radeon_device *rdev);
103void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup,
104 struct radeon_cp *cp);
105bool r100_gpu_cp_is_lockup(struct radeon_device *rdev,
106 struct r100_gpu_lockup *lockup,
107 struct radeon_cp *cp);
108void r100_ib_fini(struct radeon_device *rdev);
109int r100_ib_init(struct radeon_device *rdev);
110void r100_irq_disable(struct radeon_device *rdev);
111void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
112void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
113void r100_vram_init_sizes(struct radeon_device *rdev);
114int r100_cp_reset(struct radeon_device *rdev);
115void r100_vga_render_disable(struct radeon_device *rdev);
116void r100_restore_sanity(struct radeon_device *rdev);
117int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
118 struct radeon_cs_packet *pkt,
119 struct radeon_bo *robj);
120int r100_cs_parse_packet0(struct radeon_cs_parser *p,
121 struct radeon_cs_packet *pkt,
122 const unsigned *auth, unsigned n,
123 radeon_packet0_check_t check);
124int r100_cs_packet_parse(struct radeon_cs_parser *p,
125 struct radeon_cs_packet *pkt,
126 unsigned idx);
127void r100_enable_bm(struct radeon_device *rdev);
128void r100_set_common_regs(struct radeon_device *rdev);
129void r100_bm_disable(struct radeon_device *rdev);
130extern bool r100_gui_idle(struct radeon_device *rdev);
131extern void r100_pm_misc(struct radeon_device *rdev);
132extern void r100_pm_prepare(struct radeon_device *rdev);
133extern void r100_pm_finish(struct radeon_device *rdev);
134extern void r100_pm_init_profile(struct radeon_device *rdev);
135extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
136extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
137extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
138extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
139
140/*
141 * r200,rv250,rs300,rv280
142 */
143extern int r200_copy_dma(struct radeon_device *rdev,
144 uint64_t src_offset,
145 uint64_t dst_offset,
146 unsigned num_gpu_pages,
147 struct radeon_fence *fence);
148void r200_set_safe_registers(struct radeon_device *rdev);
149
150/*
151 * r300,r350,rv350,rv380
152 */
153extern int r300_init(struct radeon_device *rdev);
154extern void r300_fini(struct radeon_device *rdev);
155extern int r300_suspend(struct radeon_device *rdev);
156extern int r300_resume(struct radeon_device *rdev);
157extern bool r300_gpu_is_lockup(struct radeon_device *rdev);
158extern int r300_asic_reset(struct radeon_device *rdev);
159extern void r300_ring_start(struct radeon_device *rdev);
160extern void r300_fence_ring_emit(struct radeon_device *rdev,
161 struct radeon_fence *fence);
162extern int r300_cs_parse(struct radeon_cs_parser *p);
163extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
164extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
165extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
166extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
167extern void r300_set_reg_safe(struct radeon_device *rdev);
168extern void r300_mc_program(struct radeon_device *rdev);
169extern void r300_mc_init(struct radeon_device *rdev);
170extern void r300_clock_startup(struct radeon_device *rdev);
171extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
172extern int rv370_pcie_gart_init(struct radeon_device *rdev);
173extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
174extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
175extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
176
177/*
178 * r420,r423,rv410
179 */
180extern int r420_init(struct radeon_device *rdev);
181extern void r420_fini(struct radeon_device *rdev);
182extern int r420_suspend(struct radeon_device *rdev);
183extern int r420_resume(struct radeon_device *rdev);
184extern void r420_pm_init_profile(struct radeon_device *rdev);
185extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
186extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
187extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
188extern void r420_pipes_init(struct radeon_device *rdev);
189
190/*
191 * rs400,rs480
192 */
193extern int rs400_init(struct radeon_device *rdev);
194extern void rs400_fini(struct radeon_device *rdev);
195extern int rs400_suspend(struct radeon_device *rdev);
196extern int rs400_resume(struct radeon_device *rdev);
197void rs400_gart_tlb_flush(struct radeon_device *rdev);
198int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
199uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
200void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
201int rs400_gart_init(struct radeon_device *rdev);
202int rs400_gart_enable(struct radeon_device *rdev);
203void rs400_gart_adjust_size(struct radeon_device *rdev);
204void rs400_gart_disable(struct radeon_device *rdev);
205void rs400_gart_fini(struct radeon_device *rdev);
206
207/*
208 * rs600.
209 */
210extern int rs600_asic_reset(struct radeon_device *rdev);
211extern int rs600_init(struct radeon_device *rdev);
212extern void rs600_fini(struct radeon_device *rdev);
213extern int rs600_suspend(struct radeon_device *rdev);
214extern int rs600_resume(struct radeon_device *rdev);
215int rs600_irq_set(struct radeon_device *rdev);
216int rs600_irq_process(struct radeon_device *rdev);
217void rs600_irq_disable(struct radeon_device *rdev);
218u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
219void rs600_gart_tlb_flush(struct radeon_device *rdev);
220int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
221uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
222void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
223void rs600_bandwidth_update(struct radeon_device *rdev);
224void rs600_hpd_init(struct radeon_device *rdev);
225void rs600_hpd_fini(struct radeon_device *rdev);
226bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
227void rs600_hpd_set_polarity(struct radeon_device *rdev,
228 enum radeon_hpd_id hpd);
229extern void rs600_pm_misc(struct radeon_device *rdev);
230extern void rs600_pm_prepare(struct radeon_device *rdev);
231extern void rs600_pm_finish(struct radeon_device *rdev);
232extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
233extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
234extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
235void rs600_set_safe_registers(struct radeon_device *rdev);
236
237
238/*
239 * rs690,rs740
240 */
241int rs690_init(struct radeon_device *rdev);
242void rs690_fini(struct radeon_device *rdev);
243int rs690_resume(struct radeon_device *rdev);
244int rs690_suspend(struct radeon_device *rdev);
245uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
246void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
247void rs690_bandwidth_update(struct radeon_device *rdev);
248void rs690_line_buffer_adjust(struct radeon_device *rdev,
249 struct drm_display_mode *mode1,
250 struct drm_display_mode *mode2);
251
252/*
253 * rv515
254 */
255struct rv515_mc_save {
256 u32 d1vga_control;
257 u32 d2vga_control;
258 u32 vga_render_control;
259 u32 vga_hdp_control;
260 u32 d1crtc_control;
261 u32 d2crtc_control;
262};
263int rv515_init(struct radeon_device *rdev);
264void rv515_fini(struct radeon_device *rdev);
265uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
266void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
267void rv515_ring_start(struct radeon_device *rdev);
268void rv515_bandwidth_update(struct radeon_device *rdev);
269int rv515_resume(struct radeon_device *rdev);
270int rv515_suspend(struct radeon_device *rdev);
271void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
272void rv515_vga_render_disable(struct radeon_device *rdev);
273void rv515_set_safe_registers(struct radeon_device *rdev);
274void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
275void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
276void rv515_clock_startup(struct radeon_device *rdev);
277void rv515_debugfs(struct radeon_device *rdev);
278
279
280/*
281 * r520,rv530,rv560,rv570,r580
282 */
283int r520_init(struct radeon_device *rdev);
284int r520_resume(struct radeon_device *rdev);
285
286/*
287 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
288 */
289int r600_init(struct radeon_device *rdev);
290void r600_fini(struct radeon_device *rdev);
291int r600_suspend(struct radeon_device *rdev);
292int r600_resume(struct radeon_device *rdev);
293void r600_vga_set_state(struct radeon_device *rdev, bool state);
294int r600_wb_init(struct radeon_device *rdev);
295void r600_wb_fini(struct radeon_device *rdev);
296void r600_cp_commit(struct radeon_device *rdev);
297void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
298uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
299void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
300int r600_cs_parse(struct radeon_cs_parser *p);
301void r600_fence_ring_emit(struct radeon_device *rdev,
302 struct radeon_fence *fence);
303bool r600_gpu_is_lockup(struct radeon_device *rdev);
304int r600_asic_reset(struct radeon_device *rdev);
305int r600_set_surface_reg(struct radeon_device *rdev, int reg,
306 uint32_t tiling_flags, uint32_t pitch,
307 uint32_t offset, uint32_t obj_size);
308void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
309int r600_ib_test(struct radeon_device *rdev);
310void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
311int r600_ring_test(struct radeon_device *rdev);
312int r600_copy_blit(struct radeon_device *rdev,
313 uint64_t src_offset, uint64_t dst_offset,
314 unsigned num_gpu_pages, struct radeon_fence *fence);
315void r600_hpd_init(struct radeon_device *rdev);
316void r600_hpd_fini(struct radeon_device *rdev);
317bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
318void r600_hpd_set_polarity(struct radeon_device *rdev,
319 enum radeon_hpd_id hpd);
320extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
321extern bool r600_gui_idle(struct radeon_device *rdev);
322extern void r600_pm_misc(struct radeon_device *rdev);
323extern void r600_pm_init_profile(struct radeon_device *rdev);
324extern void rs780_pm_init_profile(struct radeon_device *rdev);
325extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
326extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
327extern int r600_get_pcie_lanes(struct radeon_device *rdev);
328bool r600_card_posted(struct radeon_device *rdev);
329void r600_cp_stop(struct radeon_device *rdev);
330int r600_cp_start(struct radeon_device *rdev);
331void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
332int r600_cp_resume(struct radeon_device *rdev);
333void r600_cp_fini(struct radeon_device *rdev);
334int r600_count_pipe_bits(uint32_t val);
335int r600_mc_wait_for_idle(struct radeon_device *rdev);
336int r600_pcie_gart_init(struct radeon_device *rdev);
337void r600_scratch_init(struct radeon_device *rdev);
338int r600_blit_init(struct radeon_device *rdev);
339void r600_blit_fini(struct radeon_device *rdev);
340int r600_init_microcode(struct radeon_device *rdev);
341/* r600 irq */
342int r600_irq_process(struct radeon_device *rdev);
343int r600_irq_init(struct radeon_device *rdev);
344void r600_irq_fini(struct radeon_device *rdev);
345void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
346int r600_irq_set(struct radeon_device *rdev);
347void r600_irq_suspend(struct radeon_device *rdev);
348void r600_disable_interrupts(struct radeon_device *rdev);
349void r600_rlc_stop(struct radeon_device *rdev);
350/* r600 audio */
351int r600_audio_init(struct radeon_device *rdev);
352int r600_audio_tmds_index(struct drm_encoder *encoder);
353void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
354int r600_audio_channels(struct radeon_device *rdev);
355int r600_audio_bits_per_sample(struct radeon_device *rdev);
356int r600_audio_rate(struct radeon_device *rdev);
357uint8_t r600_audio_status_bits(struct radeon_device *rdev);
358uint8_t r600_audio_category_code(struct radeon_device *rdev);
359void r600_audio_schedule_polling(struct radeon_device *rdev);
360void r600_audio_enable_polling(struct drm_encoder *encoder);
361void r600_audio_disable_polling(struct drm_encoder *encoder);
362void r600_audio_fini(struct radeon_device *rdev);
363void r600_hdmi_init(struct drm_encoder *encoder);
364int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
365void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
366/* r600 blit */
367int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
368void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
369void r600_kms_blit_copy(struct radeon_device *rdev,
370 u64 src_gpu_addr, u64 dst_gpu_addr,
371 int size_bytes);
372
373/*
374 * rv770,rv730,rv710,rv740
375 */
376int rv770_init(struct radeon_device *rdev);
377void rv770_fini(struct radeon_device *rdev);
378int rv770_suspend(struct radeon_device *rdev);
379int rv770_resume(struct radeon_device *rdev);
380void rv770_pm_misc(struct radeon_device *rdev);
381u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
382void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
383void r700_cp_stop(struct radeon_device *rdev);
384void r700_cp_fini(struct radeon_device *rdev);
385
386/*
387 * evergreen
388 */
389struct evergreen_mc_save {
390 u32 vga_control[6];
391 u32 vga_render_control;
392 u32 vga_hdp_control;
393 u32 crtc_control[6];
394};
395void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
396int evergreen_init(struct radeon_device *rdev);
397void evergreen_fini(struct radeon_device *rdev);
398int evergreen_suspend(struct radeon_device *rdev);
399int evergreen_resume(struct radeon_device *rdev);
400bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
401int evergreen_asic_reset(struct radeon_device *rdev);
402void evergreen_bandwidth_update(struct radeon_device *rdev);
403void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
404int evergreen_copy_blit(struct radeon_device *rdev,
405 uint64_t src_offset, uint64_t dst_offset,
406 unsigned num_gpu_pages, struct radeon_fence *fence);
407void evergreen_hpd_init(struct radeon_device *rdev);
408void evergreen_hpd_fini(struct radeon_device *rdev);
409bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
410void evergreen_hpd_set_polarity(struct radeon_device *rdev,
411 enum radeon_hpd_id hpd);
412u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
413int evergreen_irq_set(struct radeon_device *rdev);
414int evergreen_irq_process(struct radeon_device *rdev);
415extern int evergreen_cs_parse(struct radeon_cs_parser *p);
416extern void evergreen_pm_misc(struct radeon_device *rdev);
417extern void evergreen_pm_prepare(struct radeon_device *rdev);
418extern void evergreen_pm_finish(struct radeon_device *rdev);
419extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
420extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
421extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
422void evergreen_disable_interrupt_state(struct radeon_device *rdev);
423int evergreen_blit_init(struct radeon_device *rdev);
424void evergreen_blit_fini(struct radeon_device *rdev);
425/* evergreen blit */
426int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
427void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
428void evergreen_kms_blit_copy(struct radeon_device *rdev,
429 u64 src_gpu_addr, u64 dst_gpu_addr,
430 int size_bytes);
431
432/*
433 * cayman
434 */
435void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
436int cayman_init(struct radeon_device *rdev);
437void cayman_fini(struct radeon_device *rdev);
438int cayman_suspend(struct radeon_device *rdev);
439int cayman_resume(struct radeon_device *rdev);
440bool cayman_gpu_is_lockup(struct radeon_device *rdev);
441int cayman_asic_reset(struct radeon_device *rdev);
442
443#endif
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
45/*
46 * r100,rv100,rs100,rv200,rs200
47 */
48struct r100_mc_save {
49 u32 GENMO_WT;
50 u32 CRTC_EXT_CNTL;
51 u32 CRTC_GEN_CNTL;
52 u32 CRTC2_GEN_CNTL;
53 u32 CUR_OFFSET;
54 u32 CUR2_OFFSET;
55};
56int r100_init(struct radeon_device *rdev);
57void r100_fini(struct radeon_device *rdev);
58int r100_suspend(struct radeon_device *rdev);
59int r100_resume(struct radeon_device *rdev);
60void r100_vga_set_state(struct radeon_device *rdev, bool state);
61bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
62int r100_asic_reset(struct radeon_device *rdev);
63u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
64void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
65int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
66void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
67int r100_irq_set(struct radeon_device *rdev);
68int r100_irq_process(struct radeon_device *rdev);
69void r100_fence_ring_emit(struct radeon_device *rdev,
70 struct radeon_fence *fence);
71void r100_semaphore_ring_emit(struct radeon_device *rdev,
72 struct radeon_ring *cp,
73 struct radeon_semaphore *semaphore,
74 bool emit_wait);
75int r100_cs_parse(struct radeon_cs_parser *p);
76void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
77uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
78int r100_copy_blit(struct radeon_device *rdev,
79 uint64_t src_offset,
80 uint64_t dst_offset,
81 unsigned num_gpu_pages,
82 struct radeon_fence *fence);
83int r100_set_surface_reg(struct radeon_device *rdev, int reg,
84 uint32_t tiling_flags, uint32_t pitch,
85 uint32_t offset, uint32_t obj_size);
86void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
87void r100_bandwidth_update(struct radeon_device *rdev);
88void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
89int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
90void r100_hpd_init(struct radeon_device *rdev);
91void r100_hpd_fini(struct radeon_device *rdev);
92bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
93void r100_hpd_set_polarity(struct radeon_device *rdev,
94 enum radeon_hpd_id hpd);
95int r100_debugfs_rbbm_init(struct radeon_device *rdev);
96int r100_debugfs_cp_init(struct radeon_device *rdev);
97void r100_cp_disable(struct radeon_device *rdev);
98int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
99void r100_cp_fini(struct radeon_device *rdev);
100int r100_pci_gart_init(struct radeon_device *rdev);
101void r100_pci_gart_fini(struct radeon_device *rdev);
102int r100_pci_gart_enable(struct radeon_device *rdev);
103void r100_pci_gart_disable(struct radeon_device *rdev);
104int r100_debugfs_mc_info_init(struct radeon_device *rdev);
105int r100_gui_wait_for_idle(struct radeon_device *rdev);
106void r100_ib_fini(struct radeon_device *rdev);
107int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
108void r100_irq_disable(struct radeon_device *rdev);
109void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
110void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
111void r100_vram_init_sizes(struct radeon_device *rdev);
112int r100_cp_reset(struct radeon_device *rdev);
113void r100_vga_render_disable(struct radeon_device *rdev);
114void r100_restore_sanity(struct radeon_device *rdev);
115int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
116 struct radeon_cs_packet *pkt,
117 struct radeon_bo *robj);
118int r100_cs_parse_packet0(struct radeon_cs_parser *p,
119 struct radeon_cs_packet *pkt,
120 const unsigned *auth, unsigned n,
121 radeon_packet0_check_t check);
122int r100_cs_packet_parse(struct radeon_cs_parser *p,
123 struct radeon_cs_packet *pkt,
124 unsigned idx);
125void r100_enable_bm(struct radeon_device *rdev);
126void r100_set_common_regs(struct radeon_device *rdev);
127void r100_bm_disable(struct radeon_device *rdev);
128extern bool r100_gui_idle(struct radeon_device *rdev);
129extern void r100_pm_misc(struct radeon_device *rdev);
130extern void r100_pm_prepare(struct radeon_device *rdev);
131extern void r100_pm_finish(struct radeon_device *rdev);
132extern void r100_pm_init_profile(struct radeon_device *rdev);
133extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
134extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
135extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
136extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
137extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
138extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
139
140/*
141 * r200,rv250,rs300,rv280
142 */
143extern int r200_copy_dma(struct radeon_device *rdev,
144 uint64_t src_offset,
145 uint64_t dst_offset,
146 unsigned num_gpu_pages,
147 struct radeon_fence *fence);
148void r200_set_safe_registers(struct radeon_device *rdev);
149
150/*
151 * r300,r350,rv350,rv380
152 */
153extern int r300_init(struct radeon_device *rdev);
154extern void r300_fini(struct radeon_device *rdev);
155extern int r300_suspend(struct radeon_device *rdev);
156extern int r300_resume(struct radeon_device *rdev);
157extern int r300_asic_reset(struct radeon_device *rdev);
158extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
159extern void r300_fence_ring_emit(struct radeon_device *rdev,
160 struct radeon_fence *fence);
161extern int r300_cs_parse(struct radeon_cs_parser *p);
162extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
163extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
164extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
165extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
166extern void r300_set_reg_safe(struct radeon_device *rdev);
167extern void r300_mc_program(struct radeon_device *rdev);
168extern void r300_mc_init(struct radeon_device *rdev);
169extern void r300_clock_startup(struct radeon_device *rdev);
170extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
171extern int rv370_pcie_gart_init(struct radeon_device *rdev);
172extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
173extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
174extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
175extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
176
177/*
178 * r420,r423,rv410
179 */
180extern int r420_init(struct radeon_device *rdev);
181extern void r420_fini(struct radeon_device *rdev);
182extern int r420_suspend(struct radeon_device *rdev);
183extern int r420_resume(struct radeon_device *rdev);
184extern void r420_pm_init_profile(struct radeon_device *rdev);
185extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
186extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
187extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
188extern void r420_pipes_init(struct radeon_device *rdev);
189
190/*
191 * rs400,rs480
192 */
193extern int rs400_init(struct radeon_device *rdev);
194extern void rs400_fini(struct radeon_device *rdev);
195extern int rs400_suspend(struct radeon_device *rdev);
196extern int rs400_resume(struct radeon_device *rdev);
197void rs400_gart_tlb_flush(struct radeon_device *rdev);
198int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
199uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
200void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
201int rs400_gart_init(struct radeon_device *rdev);
202int rs400_gart_enable(struct radeon_device *rdev);
203void rs400_gart_adjust_size(struct radeon_device *rdev);
204void rs400_gart_disable(struct radeon_device *rdev);
205void rs400_gart_fini(struct radeon_device *rdev);
206extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
207
208/*
209 * rs600.
210 */
211extern int rs600_asic_reset(struct radeon_device *rdev);
212extern int rs600_init(struct radeon_device *rdev);
213extern void rs600_fini(struct radeon_device *rdev);
214extern int rs600_suspend(struct radeon_device *rdev);
215extern int rs600_resume(struct radeon_device *rdev);
216int rs600_irq_set(struct radeon_device *rdev);
217int rs600_irq_process(struct radeon_device *rdev);
218void rs600_irq_disable(struct radeon_device *rdev);
219u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
220void rs600_gart_tlb_flush(struct radeon_device *rdev);
221int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
222uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
223void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
224void rs600_bandwidth_update(struct radeon_device *rdev);
225void rs600_hpd_init(struct radeon_device *rdev);
226void rs600_hpd_fini(struct radeon_device *rdev);
227bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
228void rs600_hpd_set_polarity(struct radeon_device *rdev,
229 enum radeon_hpd_id hpd);
230extern void rs600_pm_misc(struct radeon_device *rdev);
231extern void rs600_pm_prepare(struct radeon_device *rdev);
232extern void rs600_pm_finish(struct radeon_device *rdev);
233extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
234extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
235extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
236void rs600_set_safe_registers(struct radeon_device *rdev);
237extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
238extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
239
240/*
241 * rs690,rs740
242 */
243int rs690_init(struct radeon_device *rdev);
244void rs690_fini(struct radeon_device *rdev);
245int rs690_resume(struct radeon_device *rdev);
246int rs690_suspend(struct radeon_device *rdev);
247uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
248void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
249void rs690_bandwidth_update(struct radeon_device *rdev);
250void rs690_line_buffer_adjust(struct radeon_device *rdev,
251 struct drm_display_mode *mode1,
252 struct drm_display_mode *mode2);
253extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
254
255/*
256 * rv515
257 */
258struct rv515_mc_save {
259 u32 vga_render_control;
260 u32 vga_hdp_control;
261};
262
263int rv515_init(struct radeon_device *rdev);
264void rv515_fini(struct radeon_device *rdev);
265uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
266void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
267void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
268void rv515_bandwidth_update(struct radeon_device *rdev);
269int rv515_resume(struct radeon_device *rdev);
270int rv515_suspend(struct radeon_device *rdev);
271void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
272void rv515_vga_render_disable(struct radeon_device *rdev);
273void rv515_set_safe_registers(struct radeon_device *rdev);
274void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
275void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
276void rv515_clock_startup(struct radeon_device *rdev);
277void rv515_debugfs(struct radeon_device *rdev);
278int rv515_mc_wait_for_idle(struct radeon_device *rdev);
279
280/*
281 * r520,rv530,rv560,rv570,r580
282 */
283int r520_init(struct radeon_device *rdev);
284int r520_resume(struct radeon_device *rdev);
285int r520_mc_wait_for_idle(struct radeon_device *rdev);
286
287/*
288 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
289 */
290int r600_init(struct radeon_device *rdev);
291void r600_fini(struct radeon_device *rdev);
292int r600_suspend(struct radeon_device *rdev);
293int r600_resume(struct radeon_device *rdev);
294void r600_vga_set_state(struct radeon_device *rdev, bool state);
295int r600_wb_init(struct radeon_device *rdev);
296void r600_wb_fini(struct radeon_device *rdev);
297void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
298uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
299void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
300int r600_cs_parse(struct radeon_cs_parser *p);
301void r600_fence_ring_emit(struct radeon_device *rdev,
302 struct radeon_fence *fence);
303void r600_semaphore_ring_emit(struct radeon_device *rdev,
304 struct radeon_ring *cp,
305 struct radeon_semaphore *semaphore,
306 bool emit_wait);
307bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
308int r600_asic_reset(struct radeon_device *rdev);
309int r600_set_surface_reg(struct radeon_device *rdev, int reg,
310 uint32_t tiling_flags, uint32_t pitch,
311 uint32_t offset, uint32_t obj_size);
312void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
313int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
314void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
315int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
316int r600_copy_blit(struct radeon_device *rdev,
317 uint64_t src_offset, uint64_t dst_offset,
318 unsigned num_gpu_pages, struct radeon_fence *fence);
319void r600_hpd_init(struct radeon_device *rdev);
320void r600_hpd_fini(struct radeon_device *rdev);
321bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
322void r600_hpd_set_polarity(struct radeon_device *rdev,
323 enum radeon_hpd_id hpd);
324extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
325extern bool r600_gui_idle(struct radeon_device *rdev);
326extern void r600_pm_misc(struct radeon_device *rdev);
327extern void r600_pm_init_profile(struct radeon_device *rdev);
328extern void rs780_pm_init_profile(struct radeon_device *rdev);
329extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
330extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
331extern int r600_get_pcie_lanes(struct radeon_device *rdev);
332bool r600_card_posted(struct radeon_device *rdev);
333void r600_cp_stop(struct radeon_device *rdev);
334int r600_cp_start(struct radeon_device *rdev);
335void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
336int r600_cp_resume(struct radeon_device *rdev);
337void r600_cp_fini(struct radeon_device *rdev);
338int r600_count_pipe_bits(uint32_t val);
339int r600_mc_wait_for_idle(struct radeon_device *rdev);
340int r600_pcie_gart_init(struct radeon_device *rdev);
341void r600_scratch_init(struct radeon_device *rdev);
342int r600_blit_init(struct radeon_device *rdev);
343void r600_blit_fini(struct radeon_device *rdev);
344int r600_init_microcode(struct radeon_device *rdev);
345/* r600 irq */
346int r600_irq_process(struct radeon_device *rdev);
347int r600_irq_init(struct radeon_device *rdev);
348void r600_irq_fini(struct radeon_device *rdev);
349void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
350int r600_irq_set(struct radeon_device *rdev);
351void r600_irq_suspend(struct radeon_device *rdev);
352void r600_disable_interrupts(struct radeon_device *rdev);
353void r600_rlc_stop(struct radeon_device *rdev);
354/* r600 audio */
355int r600_audio_init(struct radeon_device *rdev);
356void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
357struct r600_audio r600_audio_status(struct radeon_device *rdev);
358void r600_audio_fini(struct radeon_device *rdev);
359int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
360void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
361/* r600 blit */
362int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
363 struct radeon_sa_bo **vb);
364void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence,
365 struct radeon_sa_bo *vb);
366void r600_kms_blit_copy(struct radeon_device *rdev,
367 u64 src_gpu_addr, u64 dst_gpu_addr,
368 unsigned num_gpu_pages,
369 struct radeon_sa_bo *vb);
370int r600_mc_wait_for_idle(struct radeon_device *rdev);
371
372/*
373 * rv770,rv730,rv710,rv740
374 */
375int rv770_init(struct radeon_device *rdev);
376void rv770_fini(struct radeon_device *rdev);
377int rv770_suspend(struct radeon_device *rdev);
378int rv770_resume(struct radeon_device *rdev);
379void rv770_pm_misc(struct radeon_device *rdev);
380u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
381void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
382void r700_cp_stop(struct radeon_device *rdev);
383void r700_cp_fini(struct radeon_device *rdev);
384
385/*
386 * evergreen
387 */
388struct evergreen_mc_save {
389 u32 vga_render_control;
390 u32 vga_hdp_control;
391};
392
393void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
394int evergreen_init(struct radeon_device *rdev);
395void evergreen_fini(struct radeon_device *rdev);
396int evergreen_suspend(struct radeon_device *rdev);
397int evergreen_resume(struct radeon_device *rdev);
398bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
399int evergreen_asic_reset(struct radeon_device *rdev);
400void evergreen_bandwidth_update(struct radeon_device *rdev);
401void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
402void evergreen_hpd_init(struct radeon_device *rdev);
403void evergreen_hpd_fini(struct radeon_device *rdev);
404bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
405void evergreen_hpd_set_polarity(struct radeon_device *rdev,
406 enum radeon_hpd_id hpd);
407u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
408int evergreen_irq_set(struct radeon_device *rdev);
409int evergreen_irq_process(struct radeon_device *rdev);
410extern int evergreen_cs_parse(struct radeon_cs_parser *p);
411extern void evergreen_pm_misc(struct radeon_device *rdev);
412extern void evergreen_pm_prepare(struct radeon_device *rdev);
413extern void evergreen_pm_finish(struct radeon_device *rdev);
414extern void sumo_pm_init_profile(struct radeon_device *rdev);
415extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
416extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
417extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
418extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
419void evergreen_disable_interrupt_state(struct radeon_device *rdev);
420int evergreen_blit_init(struct radeon_device *rdev);
421int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
422
423/*
424 * cayman
425 */
426void cayman_fence_ring_emit(struct radeon_device *rdev,
427 struct radeon_fence *fence);
428void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
429int cayman_init(struct radeon_device *rdev);
430void cayman_fini(struct radeon_device *rdev);
431int cayman_suspend(struct radeon_device *rdev);
432int cayman_resume(struct radeon_device *rdev);
433int cayman_asic_reset(struct radeon_device *rdev);
434void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
435int cayman_vm_init(struct radeon_device *rdev);
436void cayman_vm_fini(struct radeon_device *rdev);
437int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id);
438void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
439void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm);
440uint32_t cayman_vm_page_flags(struct radeon_device *rdev,
441 struct radeon_vm *vm,
442 uint32_t flags);
443void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
444 unsigned pfn, uint64_t addr, uint32_t flags);
445int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
446
447/* DCE6 - SI */
448void dce6_bandwidth_update(struct radeon_device *rdev);
449
450/*
451 * si
452 */
453void si_fence_ring_emit(struct radeon_device *rdev,
454 struct radeon_fence *fence);
455void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
456int si_init(struct radeon_device *rdev);
457void si_fini(struct radeon_device *rdev);
458int si_suspend(struct radeon_device *rdev);
459int si_resume(struct radeon_device *rdev);
460bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
461int si_asic_reset(struct radeon_device *rdev);
462void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
463int si_irq_set(struct radeon_device *rdev);
464int si_irq_process(struct radeon_device *rdev);
465int si_vm_init(struct radeon_device *rdev);
466void si_vm_fini(struct radeon_device *rdev);
467int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id);
468void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
469void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm);
470int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
471
472#endif