1/*
  2 * Copyright (C) 2013 Red Hat
  3 * Author: Rob Clark <robdclark@gmail.com>
  4 *
  5 * This program is free software; you can redistribute it and/or modify it
  6 * under the terms of the GNU General Public License version 2 as published by
  7 * the Free Software Foundation.
  8 *
  9 * This program is distributed in the hope that it will be useful, but WITHOUT
 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12 * more details.
 13 *
 14 * You should have received a copy of the GNU General Public License along with
 15 * this program.  If not, see <http://www.gnu.org/licenses/>.
 16 */
 17
 18#include "msm_gpu.h"
 19#include "msm_gem.h"
 20#include "msm_mmu.h"
 21
 22
 23/*
 24 * Power Management:
 25 */
 26
 27#ifdef CONFIG_MSM_BUS_SCALING
 28#include <mach/board.h>
 29static void bs_init(struct msm_gpu *gpu)
 30{
 31	if (gpu->bus_scale_table) {
 32		gpu->bsc = msm_bus_scale_register_client(gpu->bus_scale_table);
 33		DBG("bus scale client: %08x", gpu->bsc);
 34	}
 35}
 36
 37static void bs_fini(struct msm_gpu *gpu)
 38{
 39	if (gpu->bsc) {
 40		msm_bus_scale_unregister_client(gpu->bsc);
 41		gpu->bsc = 0;
 42	}
 43}
 44
 45static void bs_set(struct msm_gpu *gpu, int idx)
 46{
 47	if (gpu->bsc) {
 48		DBG("set bus scaling: %d", idx);
 49		msm_bus_scale_client_update_request(gpu->bsc, idx);
 50	}
 51}
 52#else
 53static void bs_init(struct msm_gpu *gpu) {}
 54static void bs_fini(struct msm_gpu *gpu) {}
 55static void bs_set(struct msm_gpu *gpu, int idx) {}
 56#endif
 57
 58static int enable_pwrrail(struct msm_gpu *gpu)
 59{
 60	struct drm_device *dev = gpu->dev;
 61	int ret = 0;
 62
 63	if (gpu->gpu_reg) {
 64		ret = regulator_enable(gpu->gpu_reg);
 65		if (ret) {
 66			dev_err(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
 67			return ret;
 68		}
 69	}
 70
 71	if (gpu->gpu_cx) {
 72		ret = regulator_enable(gpu->gpu_cx);
 73		if (ret) {
 74			dev_err(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
 75			return ret;
 76		}
 77	}
 78
 79	return 0;
 80}
 81
 82static int disable_pwrrail(struct msm_gpu *gpu)
 83{
 84	if (gpu->gpu_cx)
 85		regulator_disable(gpu->gpu_cx);
 86	if (gpu->gpu_reg)
 87		regulator_disable(gpu->gpu_reg);
 88	return 0;
 89}
 90
 91static int enable_clk(struct msm_gpu *gpu)
 92{
 93	struct clk *rate_clk = NULL;
 94	int i;
 95
 96	/* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */
 97	for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) {
 98		if (gpu->grp_clks[i]) {
 99			clk_prepare(gpu->grp_clks[i]);
100			rate_clk = gpu->grp_clks[i];
101		}
102	}
103
104	if (rate_clk && gpu->fast_rate)
105		clk_set_rate(rate_clk, gpu->fast_rate);
106
107	for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--)
108		if (gpu->grp_clks[i])
109			clk_enable(gpu->grp_clks[i]);
110
111	return 0;
112}
113
114static int disable_clk(struct msm_gpu *gpu)
115{
116	struct clk *rate_clk = NULL;
117	int i;
118
119	/* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */
120	for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) {
121		if (gpu->grp_clks[i]) {
122			clk_disable(gpu->grp_clks[i]);
123			rate_clk = gpu->grp_clks[i];
124		}
125	}
126
127	if (rate_clk && gpu->slow_rate)
128		clk_set_rate(rate_clk, gpu->slow_rate);
129
130	for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--)
131		if (gpu->grp_clks[i])
132			clk_unprepare(gpu->grp_clks[i]);
133
134	return 0;
135}
136
137static int enable_axi(struct msm_gpu *gpu)
138{
139	if (gpu->ebi1_clk)
140		clk_prepare_enable(gpu->ebi1_clk);
141	if (gpu->bus_freq)
142		bs_set(gpu, gpu->bus_freq);
143	return 0;
144}
145
146static int disable_axi(struct msm_gpu *gpu)
147{
148	if (gpu->ebi1_clk)
149		clk_disable_unprepare(gpu->ebi1_clk);
150	if (gpu->bus_freq)
151		bs_set(gpu, 0);
152	return 0;
153}
154
155int msm_gpu_pm_resume(struct msm_gpu *gpu)
156{
157	struct drm_device *dev = gpu->dev;
158	int ret;
159
160	DBG("%s: active_cnt=%d", gpu->name, gpu->active_cnt);
161
162	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
163
164	if (gpu->active_cnt++ > 0)
165		return 0;
166
167	if (WARN_ON(gpu->active_cnt <= 0))
168		return -EINVAL;
169
170	ret = enable_pwrrail(gpu);
171	if (ret)
172		return ret;
173
174	ret = enable_clk(gpu);
175	if (ret)
176		return ret;
177
178	ret = enable_axi(gpu);
179	if (ret)
180		return ret;
181
182	return 0;
183}
184
185int msm_gpu_pm_suspend(struct msm_gpu *gpu)
186{
187	struct drm_device *dev = gpu->dev;
188	int ret;
189
190	DBG("%s: active_cnt=%d", gpu->name, gpu->active_cnt);
191
192	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
193
194	if (--gpu->active_cnt > 0)
195		return 0;
196
197	if (WARN_ON(gpu->active_cnt < 0))
198		return -EINVAL;
199
200	ret = disable_axi(gpu);
201	if (ret)
202		return ret;
203
204	ret = disable_clk(gpu);
205	if (ret)
206		return ret;
207
208	ret = disable_pwrrail(gpu);
209	if (ret)
210		return ret;
211
212	return 0;
213}
214
215/*
216 * Inactivity detection (for suspend):
217 */
218
219static void inactive_worker(struct work_struct *work)
220{
221	struct msm_gpu *gpu = container_of(work, struct msm_gpu, inactive_work);
222	struct drm_device *dev = gpu->dev;
223
224	if (gpu->inactive)
225		return;
226
227	DBG("%s: inactive!\n", gpu->name);
228	mutex_lock(&dev->struct_mutex);
229	if (!(msm_gpu_active(gpu) || gpu->inactive)) {
230		disable_axi(gpu);
231		disable_clk(gpu);
232		gpu->inactive = true;
233	}
234	mutex_unlock(&dev->struct_mutex);
235}
236
237static void inactive_handler(unsigned long data)
238{
239	struct msm_gpu *gpu = (struct msm_gpu *)data;
240	struct msm_drm_private *priv = gpu->dev->dev_private;
241
242	queue_work(priv->wq, &gpu->inactive_work);
243}
244
245/* cancel inactive timer and make sure we are awake: */
246static void inactive_cancel(struct msm_gpu *gpu)
247{
248	DBG("%s", gpu->name);
249	del_timer(&gpu->inactive_timer);
250	if (gpu->inactive) {
251		enable_clk(gpu);
252		enable_axi(gpu);
253		gpu->inactive = false;
254	}
255}
256
257static void inactive_start(struct msm_gpu *gpu)
258{
259	DBG("%s", gpu->name);
260	mod_timer(&gpu->inactive_timer,
261			round_jiffies_up(jiffies + DRM_MSM_INACTIVE_JIFFIES));
262}
263
264/*
265 * Hangcheck detection for locked gpu:
266 */
267
268static void recover_worker(struct work_struct *work)
269{
270	struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
271	struct drm_device *dev = gpu->dev;
272
273	dev_err(dev->dev, "%s: hangcheck recover!\n", gpu->name);
274
275	mutex_lock(&dev->struct_mutex);
276	if (msm_gpu_active(gpu)) {
277		inactive_cancel(gpu);
278		gpu->funcs->recover(gpu);
279	}
280	mutex_unlock(&dev->struct_mutex);
281
282	msm_gpu_retire(gpu);
283}
284
285static void hangcheck_timer_reset(struct msm_gpu *gpu)
286{
287	DBG("%s", gpu->name);
288	mod_timer(&gpu->hangcheck_timer,
289			round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
290}
291
292static void hangcheck_handler(unsigned long data)
293{
294	struct msm_gpu *gpu = (struct msm_gpu *)data;
295	struct drm_device *dev = gpu->dev;
296	struct msm_drm_private *priv = dev->dev_private;
297	uint32_t fence = gpu->funcs->last_fence(gpu);
298
299	if (fence != gpu->hangcheck_fence) {
300		/* some progress has been made.. ya! */
301		gpu->hangcheck_fence = fence;
302	} else if (fence < gpu->submitted_fence) {
303		/* no progress and not done.. hung! */
304		gpu->hangcheck_fence = fence;
305		dev_err(dev->dev, "%s: hangcheck detected gpu lockup!\n",
306				gpu->name);
307		dev_err(dev->dev, "%s:     completed fence: %u\n",
308				gpu->name, fence);
309		dev_err(dev->dev, "%s:     submitted fence: %u\n",
310				gpu->name, gpu->submitted_fence);
311		queue_work(priv->wq, &gpu->recover_work);
312	}
313
314	/* if still more pending work, reset the hangcheck timer: */
315	if (gpu->submitted_fence > gpu->hangcheck_fence)
316		hangcheck_timer_reset(gpu);
317
318	/* workaround for missing irq: */
319	queue_work(priv->wq, &gpu->retire_work);
320}
321
322/*
323 * Cmdstream submission/retirement:
324 */
325
326static void retire_worker(struct work_struct *work)
327{
328	struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
329	struct drm_device *dev = gpu->dev;
330	uint32_t fence = gpu->funcs->last_fence(gpu);
331
332	msm_update_fence(gpu->dev, fence);
333
334	mutex_lock(&dev->struct_mutex);
335
336	while (!list_empty(&gpu->active_list)) {
337		struct msm_gem_object *obj;
338
339		obj = list_first_entry(&gpu->active_list,
340				struct msm_gem_object, mm_list);
341
342		if ((obj->read_fence <= fence) &&
343				(obj->write_fence <= fence)) {
344			/* move to inactive: */
345			msm_gem_move_to_inactive(&obj->base);
346			msm_gem_put_iova(&obj->base, gpu->id);
347			drm_gem_object_unreference(&obj->base);
348		} else {
349			break;
350		}
351	}
352
353	mutex_unlock(&dev->struct_mutex);
354
355	if (!msm_gpu_active(gpu))
356		inactive_start(gpu);
357}
358
359/* call from irq handler to schedule work to retire bo's */
360void msm_gpu_retire(struct msm_gpu *gpu)
361{
362	struct msm_drm_private *priv = gpu->dev->dev_private;
363	queue_work(priv->wq, &gpu->retire_work);
364}
365
366/* add bo's to gpu's ring, and kick gpu: */
367int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
368		struct msm_file_private *ctx)
369{
370	struct drm_device *dev = gpu->dev;
371	struct msm_drm_private *priv = dev->dev_private;
372	int i, ret;
373
374	submit->fence = ++priv->next_fence;
375
376	gpu->submitted_fence = submit->fence;
377
378	inactive_cancel(gpu);
379
380	ret = gpu->funcs->submit(gpu, submit, ctx);
381	priv->lastctx = ctx;
382
383	for (i = 0; i < submit->nr_bos; i++) {
384		struct msm_gem_object *msm_obj = submit->bos[i].obj;
385
386		/* can't happen yet.. but when we add 2d support we'll have
387		 * to deal w/ cross-ring synchronization:
388		 */
389		WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu));
390
391		if (!is_active(msm_obj)) {
392			uint32_t iova;
393
394			/* ring takes a reference to the bo and iova: */
395			drm_gem_object_reference(&msm_obj->base);
396			msm_gem_get_iova_locked(&msm_obj->base,
397					submit->gpu->id, &iova);
398		}
399
400		if (submit->bos[i].flags & MSM_SUBMIT_BO_READ)
401			msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
402
403		if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
404			msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
405	}
406	hangcheck_timer_reset(gpu);
407
408	return ret;
409}
410
411/*
412 * Init/Cleanup:
413 */
414
415static irqreturn_t irq_handler(int irq, void *data)
416{
417	struct msm_gpu *gpu = data;
418	return gpu->funcs->irq(gpu);
419}
420
421static const char *clk_names[] = {
422		"src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk",
423};
424
425int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
426		struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
427		const char *name, const char *ioname, const char *irqname, int ringsz)
428{
429	struct iommu_domain *iommu;
430	int i, ret;
431
432	gpu->dev = drm;
433	gpu->funcs = funcs;
434	gpu->name = name;
435	gpu->inactive = true;
436
437	INIT_LIST_HEAD(&gpu->active_list);
438	INIT_WORK(&gpu->retire_work, retire_worker);
439	INIT_WORK(&gpu->inactive_work, inactive_worker);
440	INIT_WORK(&gpu->recover_work, recover_worker);
441
442	setup_timer(&gpu->inactive_timer, inactive_handler,
443			(unsigned long)gpu);
444	setup_timer(&gpu->hangcheck_timer, hangcheck_handler,
445			(unsigned long)gpu);
446
447	BUG_ON(ARRAY_SIZE(clk_names) != ARRAY_SIZE(gpu->grp_clks));
448
449	/* Map registers: */
450	gpu->mmio = msm_ioremap(pdev, ioname, name);
451	if (IS_ERR(gpu->mmio)) {
452		ret = PTR_ERR(gpu->mmio);
453		goto fail;
454	}
455
456	/* Get Interrupt: */
457	gpu->irq = platform_get_irq_byname(pdev, irqname);
458	if (gpu->irq < 0) {
459		ret = gpu->irq;
460		dev_err(drm->dev, "failed to get irq: %d\n", ret);
461		goto fail;
462	}
463
464	ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
465			IRQF_TRIGGER_HIGH, gpu->name, gpu);
466	if (ret) {
467		dev_err(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
468		goto fail;
469	}
470
471	/* Acquire clocks: */
472	for (i = 0; i < ARRAY_SIZE(clk_names); i++) {
473		gpu->grp_clks[i] = devm_clk_get(&pdev->dev, clk_names[i]);
474		DBG("grp_clks[%s]: %p", clk_names[i], gpu->grp_clks[i]);
475		if (IS_ERR(gpu->grp_clks[i]))
476			gpu->grp_clks[i] = NULL;
477	}
478
479	gpu->ebi1_clk = devm_clk_get(&pdev->dev, "bus_clk");
480	DBG("ebi1_clk: %p", gpu->ebi1_clk);
481	if (IS_ERR(gpu->ebi1_clk))
482		gpu->ebi1_clk = NULL;
483
484	/* Acquire regulators: */
485	gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
486	DBG("gpu_reg: %p", gpu->gpu_reg);
487	if (IS_ERR(gpu->gpu_reg))
488		gpu->gpu_reg = NULL;
489
490	gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
491	DBG("gpu_cx: %p", gpu->gpu_cx);
492	if (IS_ERR(gpu->gpu_cx))
493		gpu->gpu_cx = NULL;
494
495	/* Setup IOMMU.. eventually we will (I think) do this once per context
496	 * and have separate page tables per context.  For now, to keep things
497	 * simple and to get something working, just use a single address space:
498	 */
499	iommu = iommu_domain_alloc(&platform_bus_type);
500	if (iommu) {
501		dev_info(drm->dev, "%s: using IOMMU\n", name);
502		gpu->mmu = msm_iommu_new(drm, iommu);
503	} else {
504		dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
505	}
506	gpu->id = msm_register_mmu(drm, gpu->mmu);
507
508	/* Create ringbuffer: */
509	gpu->rb = msm_ringbuffer_new(gpu, ringsz);
510	if (IS_ERR(gpu->rb)) {
511		ret = PTR_ERR(gpu->rb);
512		gpu->rb = NULL;
513		dev_err(drm->dev, "could not create ringbuffer: %d\n", ret);
514		goto fail;
515	}
516
517	ret = msm_gem_get_iova_locked(gpu->rb->bo, gpu->id, &gpu->rb_iova);
518	if (ret) {
519		gpu->rb_iova = 0;
520		dev_err(drm->dev, "could not map ringbuffer: %d\n", ret);
521		goto fail;
522	}
523
524	bs_init(gpu);
525
526	return 0;
527
528fail:
529	return ret;
530}
531
532void msm_gpu_cleanup(struct msm_gpu *gpu)
533{
534	DBG("%s", gpu->name);
535
536	WARN_ON(!list_empty(&gpu->active_list));
537
538	bs_fini(gpu);
539
540	if (gpu->rb) {
541		if (gpu->rb_iova)
542			msm_gem_put_iova(gpu->rb->bo, gpu->id);
543		msm_ringbuffer_destroy(gpu->rb);
544	}
545
546	if (gpu->mmu)
547		gpu->mmu->funcs->destroy(gpu->mmu);
548}