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1#include <linux/clocksource.h>
2#include <linux/clockchips.h>
3#include <linux/interrupt.h>
4#include <linux/sysdev.h>
5#include <linux/delay.h>
6#include <linux/errno.h>
7#include <linux/i8253.h>
8#include <linux/slab.h>
9#include <linux/hpet.h>
10#include <linux/init.h>
11#include <linux/cpu.h>
12#include <linux/pm.h>
13#include <linux/io.h>
14
15#include <asm/fixmap.h>
16#include <asm/hpet.h>
17#include <asm/time.h>
18
19#define HPET_MASK CLOCKSOURCE_MASK(32)
20
21/* FSEC = 10^-15
22 NSEC = 10^-9 */
23#define FSEC_PER_NSEC 1000000L
24
25#define HPET_DEV_USED_BIT 2
26#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
27#define HPET_DEV_VALID 0x8
28#define HPET_DEV_FSB_CAP 0x1000
29#define HPET_DEV_PERI_CAP 0x2000
30
31#define HPET_MIN_CYCLES 128
32#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
33
34#define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
35
36/*
37 * HPET address is set in acpi/boot.c, when an ACPI entry exists
38 */
39unsigned long hpet_address;
40u8 hpet_blockid; /* OS timer block num */
41u8 hpet_msi_disable;
42
43#ifdef CONFIG_PCI_MSI
44static unsigned long hpet_num_timers;
45#endif
46static void __iomem *hpet_virt_address;
47
48struct hpet_dev {
49 struct clock_event_device evt;
50 unsigned int num;
51 int cpu;
52 unsigned int irq;
53 unsigned int flags;
54 char name[10];
55};
56
57inline unsigned int hpet_readl(unsigned int a)
58{
59 return readl(hpet_virt_address + a);
60}
61
62static inline void hpet_writel(unsigned int d, unsigned int a)
63{
64 writel(d, hpet_virt_address + a);
65}
66
67#ifdef CONFIG_X86_64
68#include <asm/pgtable.h>
69#endif
70
71static inline void hpet_set_mapping(void)
72{
73 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
74#ifdef CONFIG_X86_64
75 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
76#endif
77}
78
79static inline void hpet_clear_mapping(void)
80{
81 iounmap(hpet_virt_address);
82 hpet_virt_address = NULL;
83}
84
85/*
86 * HPET command line enable / disable
87 */
88static int boot_hpet_disable;
89int hpet_force_user;
90static int hpet_verbose;
91
92static int __init hpet_setup(char *str)
93{
94 if (str) {
95 if (!strncmp("disable", str, 7))
96 boot_hpet_disable = 1;
97 if (!strncmp("force", str, 5))
98 hpet_force_user = 1;
99 if (!strncmp("verbose", str, 7))
100 hpet_verbose = 1;
101 }
102 return 1;
103}
104__setup("hpet=", hpet_setup);
105
106static int __init disable_hpet(char *str)
107{
108 boot_hpet_disable = 1;
109 return 1;
110}
111__setup("nohpet", disable_hpet);
112
113static inline int is_hpet_capable(void)
114{
115 return !boot_hpet_disable && hpet_address;
116}
117
118/*
119 * HPET timer interrupt enable / disable
120 */
121static int hpet_legacy_int_enabled;
122
123/**
124 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
125 */
126int is_hpet_enabled(void)
127{
128 return is_hpet_capable() && hpet_legacy_int_enabled;
129}
130EXPORT_SYMBOL_GPL(is_hpet_enabled);
131
132static void _hpet_print_config(const char *function, int line)
133{
134 u32 i, timers, l, h;
135 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
136 l = hpet_readl(HPET_ID);
137 h = hpet_readl(HPET_PERIOD);
138 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
139 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
140 l = hpet_readl(HPET_CFG);
141 h = hpet_readl(HPET_STATUS);
142 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
143 l = hpet_readl(HPET_COUNTER);
144 h = hpet_readl(HPET_COUNTER+4);
145 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
146
147 for (i = 0; i < timers; i++) {
148 l = hpet_readl(HPET_Tn_CFG(i));
149 h = hpet_readl(HPET_Tn_CFG(i)+4);
150 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
151 i, l, h);
152 l = hpet_readl(HPET_Tn_CMP(i));
153 h = hpet_readl(HPET_Tn_CMP(i)+4);
154 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
155 i, l, h);
156 l = hpet_readl(HPET_Tn_ROUTE(i));
157 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
158 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
159 i, l, h);
160 }
161}
162
163#define hpet_print_config() \
164do { \
165 if (hpet_verbose) \
166 _hpet_print_config(__FUNCTION__, __LINE__); \
167} while (0)
168
169/*
170 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
171 * timer 0 and timer 1 in case of RTC emulation.
172 */
173#ifdef CONFIG_HPET
174
175static void hpet_reserve_msi_timers(struct hpet_data *hd);
176
177static void hpet_reserve_platform_timers(unsigned int id)
178{
179 struct hpet __iomem *hpet = hpet_virt_address;
180 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
181 unsigned int nrtimers, i;
182 struct hpet_data hd;
183
184 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
185
186 memset(&hd, 0, sizeof(hd));
187 hd.hd_phys_address = hpet_address;
188 hd.hd_address = hpet;
189 hd.hd_nirqs = nrtimers;
190 hpet_reserve_timer(&hd, 0);
191
192#ifdef CONFIG_HPET_EMULATE_RTC
193 hpet_reserve_timer(&hd, 1);
194#endif
195
196 /*
197 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
198 * is wrong for i8259!) not the output IRQ. Many BIOS writers
199 * don't bother configuring *any* comparator interrupts.
200 */
201 hd.hd_irq[0] = HPET_LEGACY_8254;
202 hd.hd_irq[1] = HPET_LEGACY_RTC;
203
204 for (i = 2; i < nrtimers; timer++, i++) {
205 hd.hd_irq[i] = (readl(&timer->hpet_config) &
206 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
207 }
208
209 hpet_reserve_msi_timers(&hd);
210
211 hpet_alloc(&hd);
212
213}
214#else
215static void hpet_reserve_platform_timers(unsigned int id) { }
216#endif
217
218/*
219 * Common hpet info
220 */
221static unsigned long hpet_freq;
222
223static void hpet_legacy_set_mode(enum clock_event_mode mode,
224 struct clock_event_device *evt);
225static int hpet_legacy_next_event(unsigned long delta,
226 struct clock_event_device *evt);
227
228/*
229 * The hpet clock event device
230 */
231static struct clock_event_device hpet_clockevent = {
232 .name = "hpet",
233 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
234 .set_mode = hpet_legacy_set_mode,
235 .set_next_event = hpet_legacy_next_event,
236 .irq = 0,
237 .rating = 50,
238};
239
240static void hpet_stop_counter(void)
241{
242 unsigned long cfg = hpet_readl(HPET_CFG);
243 cfg &= ~HPET_CFG_ENABLE;
244 hpet_writel(cfg, HPET_CFG);
245}
246
247static void hpet_reset_counter(void)
248{
249 hpet_writel(0, HPET_COUNTER);
250 hpet_writel(0, HPET_COUNTER + 4);
251}
252
253static void hpet_start_counter(void)
254{
255 unsigned int cfg = hpet_readl(HPET_CFG);
256 cfg |= HPET_CFG_ENABLE;
257 hpet_writel(cfg, HPET_CFG);
258}
259
260static void hpet_restart_counter(void)
261{
262 hpet_stop_counter();
263 hpet_reset_counter();
264 hpet_start_counter();
265}
266
267static void hpet_resume_device(void)
268{
269 force_hpet_resume();
270}
271
272static void hpet_resume_counter(struct clocksource *cs)
273{
274 hpet_resume_device();
275 hpet_restart_counter();
276}
277
278static void hpet_enable_legacy_int(void)
279{
280 unsigned int cfg = hpet_readl(HPET_CFG);
281
282 cfg |= HPET_CFG_LEGACY;
283 hpet_writel(cfg, HPET_CFG);
284 hpet_legacy_int_enabled = 1;
285}
286
287static void hpet_legacy_clockevent_register(void)
288{
289 /* Start HPET legacy interrupts */
290 hpet_enable_legacy_int();
291
292 /*
293 * Start hpet with the boot cpu mask and make it
294 * global after the IO_APIC has been initialized.
295 */
296 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
297 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
298 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
299 global_clock_event = &hpet_clockevent;
300 printk(KERN_DEBUG "hpet clockevent registered\n");
301}
302
303static int hpet_setup_msi_irq(unsigned int irq);
304
305static void hpet_set_mode(enum clock_event_mode mode,
306 struct clock_event_device *evt, int timer)
307{
308 unsigned int cfg, cmp, now;
309 uint64_t delta;
310
311 switch (mode) {
312 case CLOCK_EVT_MODE_PERIODIC:
313 hpet_stop_counter();
314 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
315 delta >>= evt->shift;
316 now = hpet_readl(HPET_COUNTER);
317 cmp = now + (unsigned int) delta;
318 cfg = hpet_readl(HPET_Tn_CFG(timer));
319 /* Make sure we use edge triggered interrupts */
320 cfg &= ~HPET_TN_LEVEL;
321 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
322 HPET_TN_SETVAL | HPET_TN_32BIT;
323 hpet_writel(cfg, HPET_Tn_CFG(timer));
324 hpet_writel(cmp, HPET_Tn_CMP(timer));
325 udelay(1);
326 /*
327 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
328 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
329 * bit is automatically cleared after the first write.
330 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
331 * Publication # 24674)
332 */
333 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
334 hpet_start_counter();
335 hpet_print_config();
336 break;
337
338 case CLOCK_EVT_MODE_ONESHOT:
339 cfg = hpet_readl(HPET_Tn_CFG(timer));
340 cfg &= ~HPET_TN_PERIODIC;
341 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
342 hpet_writel(cfg, HPET_Tn_CFG(timer));
343 break;
344
345 case CLOCK_EVT_MODE_UNUSED:
346 case CLOCK_EVT_MODE_SHUTDOWN:
347 cfg = hpet_readl(HPET_Tn_CFG(timer));
348 cfg &= ~HPET_TN_ENABLE;
349 hpet_writel(cfg, HPET_Tn_CFG(timer));
350 break;
351
352 case CLOCK_EVT_MODE_RESUME:
353 if (timer == 0) {
354 hpet_enable_legacy_int();
355 } else {
356 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
357 hpet_setup_msi_irq(hdev->irq);
358 disable_irq(hdev->irq);
359 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
360 enable_irq(hdev->irq);
361 }
362 hpet_print_config();
363 break;
364 }
365}
366
367static int hpet_next_event(unsigned long delta,
368 struct clock_event_device *evt, int timer)
369{
370 u32 cnt;
371 s32 res;
372
373 cnt = hpet_readl(HPET_COUNTER);
374 cnt += (u32) delta;
375 hpet_writel(cnt, HPET_Tn_CMP(timer));
376
377 /*
378 * HPETs are a complete disaster. The compare register is
379 * based on a equal comparison and neither provides a less
380 * than or equal functionality (which would require to take
381 * the wraparound into account) nor a simple count down event
382 * mode. Further the write to the comparator register is
383 * delayed internally up to two HPET clock cycles in certain
384 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
385 * longer delays. We worked around that by reading back the
386 * compare register, but that required another workaround for
387 * ICH9,10 chips where the first readout after write can
388 * return the old stale value. We already had a minimum
389 * programming delta of 5us enforced, but a NMI or SMI hitting
390 * between the counter readout and the comparator write can
391 * move us behind that point easily. Now instead of reading
392 * the compare register back several times, we make the ETIME
393 * decision based on the following: Return ETIME if the
394 * counter value after the write is less than HPET_MIN_CYCLES
395 * away from the event or if the counter is already ahead of
396 * the event. The minimum programming delta for the generic
397 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
398 */
399 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
400
401 return res < HPET_MIN_CYCLES ? -ETIME : 0;
402}
403
404static void hpet_legacy_set_mode(enum clock_event_mode mode,
405 struct clock_event_device *evt)
406{
407 hpet_set_mode(mode, evt, 0);
408}
409
410static int hpet_legacy_next_event(unsigned long delta,
411 struct clock_event_device *evt)
412{
413 return hpet_next_event(delta, evt, 0);
414}
415
416/*
417 * HPET MSI Support
418 */
419#ifdef CONFIG_PCI_MSI
420
421static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
422static struct hpet_dev *hpet_devs;
423
424void hpet_msi_unmask(struct irq_data *data)
425{
426 struct hpet_dev *hdev = data->handler_data;
427 unsigned int cfg;
428
429 /* unmask it */
430 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
431 cfg |= HPET_TN_FSB;
432 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
433}
434
435void hpet_msi_mask(struct irq_data *data)
436{
437 struct hpet_dev *hdev = data->handler_data;
438 unsigned int cfg;
439
440 /* mask it */
441 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
442 cfg &= ~HPET_TN_FSB;
443 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
444}
445
446void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
447{
448 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
449 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
450}
451
452void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
453{
454 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
455 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
456 msg->address_hi = 0;
457}
458
459static void hpet_msi_set_mode(enum clock_event_mode mode,
460 struct clock_event_device *evt)
461{
462 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
463 hpet_set_mode(mode, evt, hdev->num);
464}
465
466static int hpet_msi_next_event(unsigned long delta,
467 struct clock_event_device *evt)
468{
469 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
470 return hpet_next_event(delta, evt, hdev->num);
471}
472
473static int hpet_setup_msi_irq(unsigned int irq)
474{
475 if (arch_setup_hpet_msi(irq, hpet_blockid)) {
476 destroy_irq(irq);
477 return -EINVAL;
478 }
479 return 0;
480}
481
482static int hpet_assign_irq(struct hpet_dev *dev)
483{
484 unsigned int irq;
485
486 irq = create_irq_nr(0, -1);
487 if (!irq)
488 return -EINVAL;
489
490 irq_set_handler_data(irq, dev);
491
492 if (hpet_setup_msi_irq(irq))
493 return -EINVAL;
494
495 dev->irq = irq;
496 return 0;
497}
498
499static irqreturn_t hpet_interrupt_handler(int irq, void *data)
500{
501 struct hpet_dev *dev = (struct hpet_dev *)data;
502 struct clock_event_device *hevt = &dev->evt;
503
504 if (!hevt->event_handler) {
505 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
506 dev->num);
507 return IRQ_HANDLED;
508 }
509
510 hevt->event_handler(hevt);
511 return IRQ_HANDLED;
512}
513
514static int hpet_setup_irq(struct hpet_dev *dev)
515{
516
517 if (request_irq(dev->irq, hpet_interrupt_handler,
518 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
519 dev->name, dev))
520 return -1;
521
522 disable_irq(dev->irq);
523 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
524 enable_irq(dev->irq);
525
526 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
527 dev->name, dev->irq);
528
529 return 0;
530}
531
532/* This should be called in specific @cpu */
533static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
534{
535 struct clock_event_device *evt = &hdev->evt;
536
537 WARN_ON(cpu != smp_processor_id());
538 if (!(hdev->flags & HPET_DEV_VALID))
539 return;
540
541 if (hpet_setup_msi_irq(hdev->irq))
542 return;
543
544 hdev->cpu = cpu;
545 per_cpu(cpu_hpet_dev, cpu) = hdev;
546 evt->name = hdev->name;
547 hpet_setup_irq(hdev);
548 evt->irq = hdev->irq;
549
550 evt->rating = 110;
551 evt->features = CLOCK_EVT_FEAT_ONESHOT;
552 if (hdev->flags & HPET_DEV_PERI_CAP)
553 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
554
555 evt->set_mode = hpet_msi_set_mode;
556 evt->set_next_event = hpet_msi_next_event;
557 evt->cpumask = cpumask_of(hdev->cpu);
558
559 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
560 0x7FFFFFFF);
561}
562
563#ifdef CONFIG_HPET
564/* Reserve at least one timer for userspace (/dev/hpet) */
565#define RESERVE_TIMERS 1
566#else
567#define RESERVE_TIMERS 0
568#endif
569
570static void hpet_msi_capability_lookup(unsigned int start_timer)
571{
572 unsigned int id;
573 unsigned int num_timers;
574 unsigned int num_timers_used = 0;
575 int i;
576
577 if (hpet_msi_disable)
578 return;
579
580 if (boot_cpu_has(X86_FEATURE_ARAT))
581 return;
582 id = hpet_readl(HPET_ID);
583
584 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
585 num_timers++; /* Value read out starts from 0 */
586 hpet_print_config();
587
588 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
589 if (!hpet_devs)
590 return;
591
592 hpet_num_timers = num_timers;
593
594 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
595 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
596 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
597
598 /* Only consider HPET timer with MSI support */
599 if (!(cfg & HPET_TN_FSB_CAP))
600 continue;
601
602 hdev->flags = 0;
603 if (cfg & HPET_TN_PERIODIC_CAP)
604 hdev->flags |= HPET_DEV_PERI_CAP;
605 hdev->num = i;
606
607 sprintf(hdev->name, "hpet%d", i);
608 if (hpet_assign_irq(hdev))
609 continue;
610
611 hdev->flags |= HPET_DEV_FSB_CAP;
612 hdev->flags |= HPET_DEV_VALID;
613 num_timers_used++;
614 if (num_timers_used == num_possible_cpus())
615 break;
616 }
617
618 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
619 num_timers, num_timers_used);
620}
621
622#ifdef CONFIG_HPET
623static void hpet_reserve_msi_timers(struct hpet_data *hd)
624{
625 int i;
626
627 if (!hpet_devs)
628 return;
629
630 for (i = 0; i < hpet_num_timers; i++) {
631 struct hpet_dev *hdev = &hpet_devs[i];
632
633 if (!(hdev->flags & HPET_DEV_VALID))
634 continue;
635
636 hd->hd_irq[hdev->num] = hdev->irq;
637 hpet_reserve_timer(hd, hdev->num);
638 }
639}
640#endif
641
642static struct hpet_dev *hpet_get_unused_timer(void)
643{
644 int i;
645
646 if (!hpet_devs)
647 return NULL;
648
649 for (i = 0; i < hpet_num_timers; i++) {
650 struct hpet_dev *hdev = &hpet_devs[i];
651
652 if (!(hdev->flags & HPET_DEV_VALID))
653 continue;
654 if (test_and_set_bit(HPET_DEV_USED_BIT,
655 (unsigned long *)&hdev->flags))
656 continue;
657 return hdev;
658 }
659 return NULL;
660}
661
662struct hpet_work_struct {
663 struct delayed_work work;
664 struct completion complete;
665};
666
667static void hpet_work(struct work_struct *w)
668{
669 struct hpet_dev *hdev;
670 int cpu = smp_processor_id();
671 struct hpet_work_struct *hpet_work;
672
673 hpet_work = container_of(w, struct hpet_work_struct, work.work);
674
675 hdev = hpet_get_unused_timer();
676 if (hdev)
677 init_one_hpet_msi_clockevent(hdev, cpu);
678
679 complete(&hpet_work->complete);
680}
681
682static int hpet_cpuhp_notify(struct notifier_block *n,
683 unsigned long action, void *hcpu)
684{
685 unsigned long cpu = (unsigned long)hcpu;
686 struct hpet_work_struct work;
687 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
688
689 switch (action & 0xf) {
690 case CPU_ONLINE:
691 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
692 init_completion(&work.complete);
693 /* FIXME: add schedule_work_on() */
694 schedule_delayed_work_on(cpu, &work.work, 0);
695 wait_for_completion(&work.complete);
696 destroy_timer_on_stack(&work.work.timer);
697 break;
698 case CPU_DEAD:
699 if (hdev) {
700 free_irq(hdev->irq, hdev);
701 hdev->flags &= ~HPET_DEV_USED;
702 per_cpu(cpu_hpet_dev, cpu) = NULL;
703 }
704 break;
705 }
706 return NOTIFY_OK;
707}
708#else
709
710static int hpet_setup_msi_irq(unsigned int irq)
711{
712 return 0;
713}
714static void hpet_msi_capability_lookup(unsigned int start_timer)
715{
716 return;
717}
718
719#ifdef CONFIG_HPET
720static void hpet_reserve_msi_timers(struct hpet_data *hd)
721{
722 return;
723}
724#endif
725
726static int hpet_cpuhp_notify(struct notifier_block *n,
727 unsigned long action, void *hcpu)
728{
729 return NOTIFY_OK;
730}
731
732#endif
733
734/*
735 * Clock source related code
736 */
737static cycle_t read_hpet(struct clocksource *cs)
738{
739 return (cycle_t)hpet_readl(HPET_COUNTER);
740}
741
742static struct clocksource clocksource_hpet = {
743 .name = "hpet",
744 .rating = 250,
745 .read = read_hpet,
746 .mask = HPET_MASK,
747 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
748 .resume = hpet_resume_counter,
749#ifdef CONFIG_X86_64
750 .archdata = { .vclock_mode = VCLOCK_HPET },
751#endif
752};
753
754static int hpet_clocksource_register(void)
755{
756 u64 start, now;
757 cycle_t t1;
758
759 /* Start the counter */
760 hpet_restart_counter();
761
762 /* Verify whether hpet counter works */
763 t1 = hpet_readl(HPET_COUNTER);
764 rdtscll(start);
765
766 /*
767 * We don't know the TSC frequency yet, but waiting for
768 * 200000 TSC cycles is safe:
769 * 4 GHz == 50us
770 * 1 GHz == 200us
771 */
772 do {
773 rep_nop();
774 rdtscll(now);
775 } while ((now - start) < 200000UL);
776
777 if (t1 == hpet_readl(HPET_COUNTER)) {
778 printk(KERN_WARNING
779 "HPET counter not counting. HPET disabled\n");
780 return -ENODEV;
781 }
782
783 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
784 return 0;
785}
786
787/**
788 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
789 */
790int __init hpet_enable(void)
791{
792 unsigned long hpet_period;
793 unsigned int id;
794 u64 freq;
795 int i;
796
797 if (!is_hpet_capable())
798 return 0;
799
800 hpet_set_mapping();
801
802 /*
803 * Read the period and check for a sane value:
804 */
805 hpet_period = hpet_readl(HPET_PERIOD);
806
807 /*
808 * AMD SB700 based systems with spread spectrum enabled use a
809 * SMM based HPET emulation to provide proper frequency
810 * setting. The SMM code is initialized with the first HPET
811 * register access and takes some time to complete. During
812 * this time the config register reads 0xffffffff. We check
813 * for max. 1000 loops whether the config register reads a non
814 * 0xffffffff value to make sure that HPET is up and running
815 * before we go further. A counting loop is safe, as the HPET
816 * access takes thousands of CPU cycles. On non SB700 based
817 * machines this check is only done once and has no side
818 * effects.
819 */
820 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
821 if (i == 1000) {
822 printk(KERN_WARNING
823 "HPET config register value = 0xFFFFFFFF. "
824 "Disabling HPET\n");
825 goto out_nohpet;
826 }
827 }
828
829 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
830 goto out_nohpet;
831
832 /*
833 * The period is a femto seconds value. Convert it to a
834 * frequency.
835 */
836 freq = FSEC_PER_SEC;
837 do_div(freq, hpet_period);
838 hpet_freq = freq;
839
840 /*
841 * Read the HPET ID register to retrieve the IRQ routing
842 * information and the number of channels
843 */
844 id = hpet_readl(HPET_ID);
845 hpet_print_config();
846
847#ifdef CONFIG_HPET_EMULATE_RTC
848 /*
849 * The legacy routing mode needs at least two channels, tick timer
850 * and the rtc emulation channel.
851 */
852 if (!(id & HPET_ID_NUMBER))
853 goto out_nohpet;
854#endif
855
856 if (hpet_clocksource_register())
857 goto out_nohpet;
858
859 if (id & HPET_ID_LEGSUP) {
860 hpet_legacy_clockevent_register();
861 return 1;
862 }
863 return 0;
864
865out_nohpet:
866 hpet_clear_mapping();
867 hpet_address = 0;
868 return 0;
869}
870
871/*
872 * Needs to be late, as the reserve_timer code calls kalloc !
873 *
874 * Not a problem on i386 as hpet_enable is called from late_time_init,
875 * but on x86_64 it is necessary !
876 */
877static __init int hpet_late_init(void)
878{
879 int cpu;
880
881 if (boot_hpet_disable)
882 return -ENODEV;
883
884 if (!hpet_address) {
885 if (!force_hpet_address)
886 return -ENODEV;
887
888 hpet_address = force_hpet_address;
889 hpet_enable();
890 }
891
892 if (!hpet_virt_address)
893 return -ENODEV;
894
895 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
896 hpet_msi_capability_lookup(2);
897 else
898 hpet_msi_capability_lookup(0);
899
900 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
901 hpet_print_config();
902
903 if (hpet_msi_disable)
904 return 0;
905
906 if (boot_cpu_has(X86_FEATURE_ARAT))
907 return 0;
908
909 for_each_online_cpu(cpu) {
910 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
911 }
912
913 /* This notifier should be called after workqueue is ready */
914 hotcpu_notifier(hpet_cpuhp_notify, -20);
915
916 return 0;
917}
918fs_initcall(hpet_late_init);
919
920void hpet_disable(void)
921{
922 if (is_hpet_capable() && hpet_virt_address) {
923 unsigned int cfg = hpet_readl(HPET_CFG);
924
925 if (hpet_legacy_int_enabled) {
926 cfg &= ~HPET_CFG_LEGACY;
927 hpet_legacy_int_enabled = 0;
928 }
929 cfg &= ~HPET_CFG_ENABLE;
930 hpet_writel(cfg, HPET_CFG);
931 }
932}
933
934#ifdef CONFIG_HPET_EMULATE_RTC
935
936/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
937 * is enabled, we support RTC interrupt functionality in software.
938 * RTC has 3 kinds of interrupts:
939 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
940 * is updated
941 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
942 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
943 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
944 * (1) and (2) above are implemented using polling at a frequency of
945 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
946 * overhead. (DEFAULT_RTC_INT_FREQ)
947 * For (3), we use interrupts at 64Hz or user specified periodic
948 * frequency, whichever is higher.
949 */
950#include <linux/mc146818rtc.h>
951#include <linux/rtc.h>
952#include <asm/rtc.h>
953
954#define DEFAULT_RTC_INT_FREQ 64
955#define DEFAULT_RTC_SHIFT 6
956#define RTC_NUM_INTS 1
957
958static unsigned long hpet_rtc_flags;
959static int hpet_prev_update_sec;
960static struct rtc_time hpet_alarm_time;
961static unsigned long hpet_pie_count;
962static u32 hpet_t1_cmp;
963static u32 hpet_default_delta;
964static u32 hpet_pie_delta;
965static unsigned long hpet_pie_limit;
966
967static rtc_irq_handler irq_handler;
968
969/*
970 * Check that the hpet counter c1 is ahead of the c2
971 */
972static inline int hpet_cnt_ahead(u32 c1, u32 c2)
973{
974 return (s32)(c2 - c1) < 0;
975}
976
977/*
978 * Registers a IRQ handler.
979 */
980int hpet_register_irq_handler(rtc_irq_handler handler)
981{
982 if (!is_hpet_enabled())
983 return -ENODEV;
984 if (irq_handler)
985 return -EBUSY;
986
987 irq_handler = handler;
988
989 return 0;
990}
991EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
992
993/*
994 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
995 * and does cleanup.
996 */
997void hpet_unregister_irq_handler(rtc_irq_handler handler)
998{
999 if (!is_hpet_enabled())
1000 return;
1001
1002 irq_handler = NULL;
1003 hpet_rtc_flags = 0;
1004}
1005EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1006
1007/*
1008 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1009 * is not supported by all HPET implementations for timer 1.
1010 *
1011 * hpet_rtc_timer_init() is called when the rtc is initialized.
1012 */
1013int hpet_rtc_timer_init(void)
1014{
1015 unsigned int cfg, cnt, delta;
1016 unsigned long flags;
1017
1018 if (!is_hpet_enabled())
1019 return 0;
1020
1021 if (!hpet_default_delta) {
1022 uint64_t clc;
1023
1024 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1025 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1026 hpet_default_delta = clc;
1027 }
1028
1029 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1030 delta = hpet_default_delta;
1031 else
1032 delta = hpet_pie_delta;
1033
1034 local_irq_save(flags);
1035
1036 cnt = delta + hpet_readl(HPET_COUNTER);
1037 hpet_writel(cnt, HPET_T1_CMP);
1038 hpet_t1_cmp = cnt;
1039
1040 cfg = hpet_readl(HPET_T1_CFG);
1041 cfg &= ~HPET_TN_PERIODIC;
1042 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1043 hpet_writel(cfg, HPET_T1_CFG);
1044
1045 local_irq_restore(flags);
1046
1047 return 1;
1048}
1049EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1050
1051/*
1052 * The functions below are called from rtc driver.
1053 * Return 0 if HPET is not being used.
1054 * Otherwise do the necessary changes and return 1.
1055 */
1056int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1057{
1058 if (!is_hpet_enabled())
1059 return 0;
1060
1061 hpet_rtc_flags &= ~bit_mask;
1062 return 1;
1063}
1064EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1065
1066int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1067{
1068 unsigned long oldbits = hpet_rtc_flags;
1069
1070 if (!is_hpet_enabled())
1071 return 0;
1072
1073 hpet_rtc_flags |= bit_mask;
1074
1075 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1076 hpet_prev_update_sec = -1;
1077
1078 if (!oldbits)
1079 hpet_rtc_timer_init();
1080
1081 return 1;
1082}
1083EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1084
1085int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1086 unsigned char sec)
1087{
1088 if (!is_hpet_enabled())
1089 return 0;
1090
1091 hpet_alarm_time.tm_hour = hrs;
1092 hpet_alarm_time.tm_min = min;
1093 hpet_alarm_time.tm_sec = sec;
1094
1095 return 1;
1096}
1097EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1098
1099int hpet_set_periodic_freq(unsigned long freq)
1100{
1101 uint64_t clc;
1102
1103 if (!is_hpet_enabled())
1104 return 0;
1105
1106 if (freq <= DEFAULT_RTC_INT_FREQ)
1107 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1108 else {
1109 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1110 do_div(clc, freq);
1111 clc >>= hpet_clockevent.shift;
1112 hpet_pie_delta = clc;
1113 hpet_pie_limit = 0;
1114 }
1115 return 1;
1116}
1117EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1118
1119int hpet_rtc_dropped_irq(void)
1120{
1121 return is_hpet_enabled();
1122}
1123EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1124
1125static void hpet_rtc_timer_reinit(void)
1126{
1127 unsigned int cfg, delta;
1128 int lost_ints = -1;
1129
1130 if (unlikely(!hpet_rtc_flags)) {
1131 cfg = hpet_readl(HPET_T1_CFG);
1132 cfg &= ~HPET_TN_ENABLE;
1133 hpet_writel(cfg, HPET_T1_CFG);
1134 return;
1135 }
1136
1137 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1138 delta = hpet_default_delta;
1139 else
1140 delta = hpet_pie_delta;
1141
1142 /*
1143 * Increment the comparator value until we are ahead of the
1144 * current count.
1145 */
1146 do {
1147 hpet_t1_cmp += delta;
1148 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1149 lost_ints++;
1150 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1151
1152 if (lost_ints) {
1153 if (hpet_rtc_flags & RTC_PIE)
1154 hpet_pie_count += lost_ints;
1155 if (printk_ratelimit())
1156 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1157 lost_ints);
1158 }
1159}
1160
1161irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1162{
1163 struct rtc_time curr_time;
1164 unsigned long rtc_int_flag = 0;
1165
1166 hpet_rtc_timer_reinit();
1167 memset(&curr_time, 0, sizeof(struct rtc_time));
1168
1169 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1170 get_rtc_time(&curr_time);
1171
1172 if (hpet_rtc_flags & RTC_UIE &&
1173 curr_time.tm_sec != hpet_prev_update_sec) {
1174 if (hpet_prev_update_sec >= 0)
1175 rtc_int_flag = RTC_UF;
1176 hpet_prev_update_sec = curr_time.tm_sec;
1177 }
1178
1179 if (hpet_rtc_flags & RTC_PIE &&
1180 ++hpet_pie_count >= hpet_pie_limit) {
1181 rtc_int_flag |= RTC_PF;
1182 hpet_pie_count = 0;
1183 }
1184
1185 if (hpet_rtc_flags & RTC_AIE &&
1186 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1187 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1188 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1189 rtc_int_flag |= RTC_AF;
1190
1191 if (rtc_int_flag) {
1192 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1193 if (irq_handler)
1194 irq_handler(rtc_int_flag, dev_id);
1195 }
1196 return IRQ_HANDLED;
1197}
1198EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1199#endif
1#include <linux/clocksource.h>
2#include <linux/clockchips.h>
3#include <linux/interrupt.h>
4#include <linux/export.h>
5#include <linux/delay.h>
6#include <linux/errno.h>
7#include <linux/i8253.h>
8#include <linux/slab.h>
9#include <linux/hpet.h>
10#include <linux/init.h>
11#include <linux/cpu.h>
12#include <linux/pm.h>
13#include <linux/io.h>
14
15#include <asm/fixmap.h>
16#include <asm/hpet.h>
17#include <asm/time.h>
18
19#define HPET_MASK CLOCKSOURCE_MASK(32)
20
21/* FSEC = 10^-15
22 NSEC = 10^-9 */
23#define FSEC_PER_NSEC 1000000L
24
25#define HPET_DEV_USED_BIT 2
26#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
27#define HPET_DEV_VALID 0x8
28#define HPET_DEV_FSB_CAP 0x1000
29#define HPET_DEV_PERI_CAP 0x2000
30
31#define HPET_MIN_CYCLES 128
32#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
33
34/*
35 * HPET address is set in acpi/boot.c, when an ACPI entry exists
36 */
37unsigned long hpet_address;
38u8 hpet_blockid; /* OS timer block num */
39u8 hpet_msi_disable;
40
41#ifdef CONFIG_PCI_MSI
42static unsigned long hpet_num_timers;
43#endif
44static void __iomem *hpet_virt_address;
45
46struct hpet_dev {
47 struct clock_event_device evt;
48 unsigned int num;
49 int cpu;
50 unsigned int irq;
51 unsigned int flags;
52 char name[10];
53};
54
55inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
56{
57 return container_of(evtdev, struct hpet_dev, evt);
58}
59
60inline unsigned int hpet_readl(unsigned int a)
61{
62 return readl(hpet_virt_address + a);
63}
64
65static inline void hpet_writel(unsigned int d, unsigned int a)
66{
67 writel(d, hpet_virt_address + a);
68}
69
70#ifdef CONFIG_X86_64
71#include <asm/pgtable.h>
72#endif
73
74static inline void hpet_set_mapping(void)
75{
76 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
77#ifdef CONFIG_X86_64
78 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
79#endif
80}
81
82static inline void hpet_clear_mapping(void)
83{
84 iounmap(hpet_virt_address);
85 hpet_virt_address = NULL;
86}
87
88/*
89 * HPET command line enable / disable
90 */
91int boot_hpet_disable;
92int hpet_force_user;
93static int hpet_verbose;
94
95static int __init hpet_setup(char *str)
96{
97 while (str) {
98 char *next = strchr(str, ',');
99
100 if (next)
101 *next++ = 0;
102 if (!strncmp("disable", str, 7))
103 boot_hpet_disable = 1;
104 if (!strncmp("force", str, 5))
105 hpet_force_user = 1;
106 if (!strncmp("verbose", str, 7))
107 hpet_verbose = 1;
108 str = next;
109 }
110 return 1;
111}
112__setup("hpet=", hpet_setup);
113
114static int __init disable_hpet(char *str)
115{
116 boot_hpet_disable = 1;
117 return 1;
118}
119__setup("nohpet", disable_hpet);
120
121static inline int is_hpet_capable(void)
122{
123 return !boot_hpet_disable && hpet_address;
124}
125
126/*
127 * HPET timer interrupt enable / disable
128 */
129static int hpet_legacy_int_enabled;
130
131/**
132 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
133 */
134int is_hpet_enabled(void)
135{
136 return is_hpet_capable() && hpet_legacy_int_enabled;
137}
138EXPORT_SYMBOL_GPL(is_hpet_enabled);
139
140static void _hpet_print_config(const char *function, int line)
141{
142 u32 i, timers, l, h;
143 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
144 l = hpet_readl(HPET_ID);
145 h = hpet_readl(HPET_PERIOD);
146 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
147 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
148 l = hpet_readl(HPET_CFG);
149 h = hpet_readl(HPET_STATUS);
150 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
151 l = hpet_readl(HPET_COUNTER);
152 h = hpet_readl(HPET_COUNTER+4);
153 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
154
155 for (i = 0; i < timers; i++) {
156 l = hpet_readl(HPET_Tn_CFG(i));
157 h = hpet_readl(HPET_Tn_CFG(i)+4);
158 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
159 i, l, h);
160 l = hpet_readl(HPET_Tn_CMP(i));
161 h = hpet_readl(HPET_Tn_CMP(i)+4);
162 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
163 i, l, h);
164 l = hpet_readl(HPET_Tn_ROUTE(i));
165 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
166 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
167 i, l, h);
168 }
169}
170
171#define hpet_print_config() \
172do { \
173 if (hpet_verbose) \
174 _hpet_print_config(__FUNCTION__, __LINE__); \
175} while (0)
176
177/*
178 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
179 * timer 0 and timer 1 in case of RTC emulation.
180 */
181#ifdef CONFIG_HPET
182
183static void hpet_reserve_msi_timers(struct hpet_data *hd);
184
185static void hpet_reserve_platform_timers(unsigned int id)
186{
187 struct hpet __iomem *hpet = hpet_virt_address;
188 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
189 unsigned int nrtimers, i;
190 struct hpet_data hd;
191
192 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
193
194 memset(&hd, 0, sizeof(hd));
195 hd.hd_phys_address = hpet_address;
196 hd.hd_address = hpet;
197 hd.hd_nirqs = nrtimers;
198 hpet_reserve_timer(&hd, 0);
199
200#ifdef CONFIG_HPET_EMULATE_RTC
201 hpet_reserve_timer(&hd, 1);
202#endif
203
204 /*
205 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
206 * is wrong for i8259!) not the output IRQ. Many BIOS writers
207 * don't bother configuring *any* comparator interrupts.
208 */
209 hd.hd_irq[0] = HPET_LEGACY_8254;
210 hd.hd_irq[1] = HPET_LEGACY_RTC;
211
212 for (i = 2; i < nrtimers; timer++, i++) {
213 hd.hd_irq[i] = (readl(&timer->hpet_config) &
214 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
215 }
216
217 hpet_reserve_msi_timers(&hd);
218
219 hpet_alloc(&hd);
220
221}
222#else
223static void hpet_reserve_platform_timers(unsigned int id) { }
224#endif
225
226/*
227 * Common hpet info
228 */
229static unsigned long hpet_freq;
230
231static void hpet_legacy_set_mode(enum clock_event_mode mode,
232 struct clock_event_device *evt);
233static int hpet_legacy_next_event(unsigned long delta,
234 struct clock_event_device *evt);
235
236/*
237 * The hpet clock event device
238 */
239static struct clock_event_device hpet_clockevent = {
240 .name = "hpet",
241 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
242 .set_mode = hpet_legacy_set_mode,
243 .set_next_event = hpet_legacy_next_event,
244 .irq = 0,
245 .rating = 50,
246};
247
248static void hpet_stop_counter(void)
249{
250 unsigned long cfg = hpet_readl(HPET_CFG);
251 cfg &= ~HPET_CFG_ENABLE;
252 hpet_writel(cfg, HPET_CFG);
253}
254
255static void hpet_reset_counter(void)
256{
257 hpet_writel(0, HPET_COUNTER);
258 hpet_writel(0, HPET_COUNTER + 4);
259}
260
261static void hpet_start_counter(void)
262{
263 unsigned int cfg = hpet_readl(HPET_CFG);
264 cfg |= HPET_CFG_ENABLE;
265 hpet_writel(cfg, HPET_CFG);
266}
267
268static void hpet_restart_counter(void)
269{
270 hpet_stop_counter();
271 hpet_reset_counter();
272 hpet_start_counter();
273}
274
275static void hpet_resume_device(void)
276{
277 force_hpet_resume();
278}
279
280static void hpet_resume_counter(struct clocksource *cs)
281{
282 hpet_resume_device();
283 hpet_restart_counter();
284}
285
286static void hpet_enable_legacy_int(void)
287{
288 unsigned int cfg = hpet_readl(HPET_CFG);
289
290 cfg |= HPET_CFG_LEGACY;
291 hpet_writel(cfg, HPET_CFG);
292 hpet_legacy_int_enabled = 1;
293}
294
295static void hpet_legacy_clockevent_register(void)
296{
297 /* Start HPET legacy interrupts */
298 hpet_enable_legacy_int();
299
300 /*
301 * Start hpet with the boot cpu mask and make it
302 * global after the IO_APIC has been initialized.
303 */
304 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
305 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
306 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
307 global_clock_event = &hpet_clockevent;
308 printk(KERN_DEBUG "hpet clockevent registered\n");
309}
310
311static int hpet_setup_msi_irq(unsigned int irq);
312
313static void hpet_set_mode(enum clock_event_mode mode,
314 struct clock_event_device *evt, int timer)
315{
316 unsigned int cfg, cmp, now;
317 uint64_t delta;
318
319 switch (mode) {
320 case CLOCK_EVT_MODE_PERIODIC:
321 hpet_stop_counter();
322 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
323 delta >>= evt->shift;
324 now = hpet_readl(HPET_COUNTER);
325 cmp = now + (unsigned int) delta;
326 cfg = hpet_readl(HPET_Tn_CFG(timer));
327 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
328 HPET_TN_SETVAL | HPET_TN_32BIT;
329 hpet_writel(cfg, HPET_Tn_CFG(timer));
330 hpet_writel(cmp, HPET_Tn_CMP(timer));
331 udelay(1);
332 /*
333 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
334 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
335 * bit is automatically cleared after the first write.
336 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
337 * Publication # 24674)
338 */
339 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
340 hpet_start_counter();
341 hpet_print_config();
342 break;
343
344 case CLOCK_EVT_MODE_ONESHOT:
345 cfg = hpet_readl(HPET_Tn_CFG(timer));
346 cfg &= ~HPET_TN_PERIODIC;
347 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
348 hpet_writel(cfg, HPET_Tn_CFG(timer));
349 break;
350
351 case CLOCK_EVT_MODE_UNUSED:
352 case CLOCK_EVT_MODE_SHUTDOWN:
353 cfg = hpet_readl(HPET_Tn_CFG(timer));
354 cfg &= ~HPET_TN_ENABLE;
355 hpet_writel(cfg, HPET_Tn_CFG(timer));
356 break;
357
358 case CLOCK_EVT_MODE_RESUME:
359 if (timer == 0) {
360 hpet_enable_legacy_int();
361 } else {
362 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
363 hpet_setup_msi_irq(hdev->irq);
364 disable_irq(hdev->irq);
365 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
366 enable_irq(hdev->irq);
367 }
368 hpet_print_config();
369 break;
370 }
371}
372
373static int hpet_next_event(unsigned long delta,
374 struct clock_event_device *evt, int timer)
375{
376 u32 cnt;
377 s32 res;
378
379 cnt = hpet_readl(HPET_COUNTER);
380 cnt += (u32) delta;
381 hpet_writel(cnt, HPET_Tn_CMP(timer));
382
383 /*
384 * HPETs are a complete disaster. The compare register is
385 * based on a equal comparison and neither provides a less
386 * than or equal functionality (which would require to take
387 * the wraparound into account) nor a simple count down event
388 * mode. Further the write to the comparator register is
389 * delayed internally up to two HPET clock cycles in certain
390 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
391 * longer delays. We worked around that by reading back the
392 * compare register, but that required another workaround for
393 * ICH9,10 chips where the first readout after write can
394 * return the old stale value. We already had a minimum
395 * programming delta of 5us enforced, but a NMI or SMI hitting
396 * between the counter readout and the comparator write can
397 * move us behind that point easily. Now instead of reading
398 * the compare register back several times, we make the ETIME
399 * decision based on the following: Return ETIME if the
400 * counter value after the write is less than HPET_MIN_CYCLES
401 * away from the event or if the counter is already ahead of
402 * the event. The minimum programming delta for the generic
403 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
404 */
405 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
406
407 return res < HPET_MIN_CYCLES ? -ETIME : 0;
408}
409
410static void hpet_legacy_set_mode(enum clock_event_mode mode,
411 struct clock_event_device *evt)
412{
413 hpet_set_mode(mode, evt, 0);
414}
415
416static int hpet_legacy_next_event(unsigned long delta,
417 struct clock_event_device *evt)
418{
419 return hpet_next_event(delta, evt, 0);
420}
421
422/*
423 * HPET MSI Support
424 */
425#ifdef CONFIG_PCI_MSI
426
427static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
428static struct hpet_dev *hpet_devs;
429
430void hpet_msi_unmask(struct irq_data *data)
431{
432 struct hpet_dev *hdev = data->handler_data;
433 unsigned int cfg;
434
435 /* unmask it */
436 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
437 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
438 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
439}
440
441void hpet_msi_mask(struct irq_data *data)
442{
443 struct hpet_dev *hdev = data->handler_data;
444 unsigned int cfg;
445
446 /* mask it */
447 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
448 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
449 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
450}
451
452void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
453{
454 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
455 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
456}
457
458void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
459{
460 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
461 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
462 msg->address_hi = 0;
463}
464
465static void hpet_msi_set_mode(enum clock_event_mode mode,
466 struct clock_event_device *evt)
467{
468 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
469 hpet_set_mode(mode, evt, hdev->num);
470}
471
472static int hpet_msi_next_event(unsigned long delta,
473 struct clock_event_device *evt)
474{
475 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
476 return hpet_next_event(delta, evt, hdev->num);
477}
478
479static int hpet_setup_msi_irq(unsigned int irq)
480{
481 if (x86_msi.setup_hpet_msi(irq, hpet_blockid)) {
482 destroy_irq(irq);
483 return -EINVAL;
484 }
485 return 0;
486}
487
488static int hpet_assign_irq(struct hpet_dev *dev)
489{
490 unsigned int irq;
491
492 irq = create_irq_nr(0, -1);
493 if (!irq)
494 return -EINVAL;
495
496 irq_set_handler_data(irq, dev);
497
498 if (hpet_setup_msi_irq(irq))
499 return -EINVAL;
500
501 dev->irq = irq;
502 return 0;
503}
504
505static irqreturn_t hpet_interrupt_handler(int irq, void *data)
506{
507 struct hpet_dev *dev = (struct hpet_dev *)data;
508 struct clock_event_device *hevt = &dev->evt;
509
510 if (!hevt->event_handler) {
511 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
512 dev->num);
513 return IRQ_HANDLED;
514 }
515
516 hevt->event_handler(hevt);
517 return IRQ_HANDLED;
518}
519
520static int hpet_setup_irq(struct hpet_dev *dev)
521{
522
523 if (request_irq(dev->irq, hpet_interrupt_handler,
524 IRQF_TIMER | IRQF_NOBALANCING,
525 dev->name, dev))
526 return -1;
527
528 disable_irq(dev->irq);
529 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
530 enable_irq(dev->irq);
531
532 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
533 dev->name, dev->irq);
534
535 return 0;
536}
537
538/* This should be called in specific @cpu */
539static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
540{
541 struct clock_event_device *evt = &hdev->evt;
542
543 WARN_ON(cpu != smp_processor_id());
544 if (!(hdev->flags & HPET_DEV_VALID))
545 return;
546
547 if (hpet_setup_msi_irq(hdev->irq))
548 return;
549
550 hdev->cpu = cpu;
551 per_cpu(cpu_hpet_dev, cpu) = hdev;
552 evt->name = hdev->name;
553 hpet_setup_irq(hdev);
554 evt->irq = hdev->irq;
555
556 evt->rating = 110;
557 evt->features = CLOCK_EVT_FEAT_ONESHOT;
558 if (hdev->flags & HPET_DEV_PERI_CAP)
559 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
560
561 evt->set_mode = hpet_msi_set_mode;
562 evt->set_next_event = hpet_msi_next_event;
563 evt->cpumask = cpumask_of(hdev->cpu);
564
565 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
566 0x7FFFFFFF);
567}
568
569#ifdef CONFIG_HPET
570/* Reserve at least one timer for userspace (/dev/hpet) */
571#define RESERVE_TIMERS 1
572#else
573#define RESERVE_TIMERS 0
574#endif
575
576static void hpet_msi_capability_lookup(unsigned int start_timer)
577{
578 unsigned int id;
579 unsigned int num_timers;
580 unsigned int num_timers_used = 0;
581 int i;
582
583 if (hpet_msi_disable)
584 return;
585
586 if (boot_cpu_has(X86_FEATURE_ARAT))
587 return;
588 id = hpet_readl(HPET_ID);
589
590 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
591 num_timers++; /* Value read out starts from 0 */
592 hpet_print_config();
593
594 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
595 if (!hpet_devs)
596 return;
597
598 hpet_num_timers = num_timers;
599
600 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
601 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
602 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
603
604 /* Only consider HPET timer with MSI support */
605 if (!(cfg & HPET_TN_FSB_CAP))
606 continue;
607
608 hdev->flags = 0;
609 if (cfg & HPET_TN_PERIODIC_CAP)
610 hdev->flags |= HPET_DEV_PERI_CAP;
611 hdev->num = i;
612
613 sprintf(hdev->name, "hpet%d", i);
614 if (hpet_assign_irq(hdev))
615 continue;
616
617 hdev->flags |= HPET_DEV_FSB_CAP;
618 hdev->flags |= HPET_DEV_VALID;
619 num_timers_used++;
620 if (num_timers_used == num_possible_cpus())
621 break;
622 }
623
624 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
625 num_timers, num_timers_used);
626}
627
628#ifdef CONFIG_HPET
629static void hpet_reserve_msi_timers(struct hpet_data *hd)
630{
631 int i;
632
633 if (!hpet_devs)
634 return;
635
636 for (i = 0; i < hpet_num_timers; i++) {
637 struct hpet_dev *hdev = &hpet_devs[i];
638
639 if (!(hdev->flags & HPET_DEV_VALID))
640 continue;
641
642 hd->hd_irq[hdev->num] = hdev->irq;
643 hpet_reserve_timer(hd, hdev->num);
644 }
645}
646#endif
647
648static struct hpet_dev *hpet_get_unused_timer(void)
649{
650 int i;
651
652 if (!hpet_devs)
653 return NULL;
654
655 for (i = 0; i < hpet_num_timers; i++) {
656 struct hpet_dev *hdev = &hpet_devs[i];
657
658 if (!(hdev->flags & HPET_DEV_VALID))
659 continue;
660 if (test_and_set_bit(HPET_DEV_USED_BIT,
661 (unsigned long *)&hdev->flags))
662 continue;
663 return hdev;
664 }
665 return NULL;
666}
667
668struct hpet_work_struct {
669 struct delayed_work work;
670 struct completion complete;
671};
672
673static void hpet_work(struct work_struct *w)
674{
675 struct hpet_dev *hdev;
676 int cpu = smp_processor_id();
677 struct hpet_work_struct *hpet_work;
678
679 hpet_work = container_of(w, struct hpet_work_struct, work.work);
680
681 hdev = hpet_get_unused_timer();
682 if (hdev)
683 init_one_hpet_msi_clockevent(hdev, cpu);
684
685 complete(&hpet_work->complete);
686}
687
688static int hpet_cpuhp_notify(struct notifier_block *n,
689 unsigned long action, void *hcpu)
690{
691 unsigned long cpu = (unsigned long)hcpu;
692 struct hpet_work_struct work;
693 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
694
695 switch (action & 0xf) {
696 case CPU_ONLINE:
697 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
698 init_completion(&work.complete);
699 /* FIXME: add schedule_work_on() */
700 schedule_delayed_work_on(cpu, &work.work, 0);
701 wait_for_completion(&work.complete);
702 destroy_delayed_work_on_stack(&work.work);
703 break;
704 case CPU_DEAD:
705 if (hdev) {
706 free_irq(hdev->irq, hdev);
707 hdev->flags &= ~HPET_DEV_USED;
708 per_cpu(cpu_hpet_dev, cpu) = NULL;
709 }
710 break;
711 }
712 return NOTIFY_OK;
713}
714#else
715
716static int hpet_setup_msi_irq(unsigned int irq)
717{
718 return 0;
719}
720static void hpet_msi_capability_lookup(unsigned int start_timer)
721{
722 return;
723}
724
725#ifdef CONFIG_HPET
726static void hpet_reserve_msi_timers(struct hpet_data *hd)
727{
728 return;
729}
730#endif
731
732static int hpet_cpuhp_notify(struct notifier_block *n,
733 unsigned long action, void *hcpu)
734{
735 return NOTIFY_OK;
736}
737
738#endif
739
740/*
741 * Clock source related code
742 */
743static cycle_t read_hpet(struct clocksource *cs)
744{
745 return (cycle_t)hpet_readl(HPET_COUNTER);
746}
747
748static struct clocksource clocksource_hpet = {
749 .name = "hpet",
750 .rating = 250,
751 .read = read_hpet,
752 .mask = HPET_MASK,
753 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
754 .resume = hpet_resume_counter,
755 .archdata = { .vclock_mode = VCLOCK_HPET },
756};
757
758static int hpet_clocksource_register(void)
759{
760 u64 start, now;
761 cycle_t t1;
762
763 /* Start the counter */
764 hpet_restart_counter();
765
766 /* Verify whether hpet counter works */
767 t1 = hpet_readl(HPET_COUNTER);
768 rdtscll(start);
769
770 /*
771 * We don't know the TSC frequency yet, but waiting for
772 * 200000 TSC cycles is safe:
773 * 4 GHz == 50us
774 * 1 GHz == 200us
775 */
776 do {
777 rep_nop();
778 rdtscll(now);
779 } while ((now - start) < 200000UL);
780
781 if (t1 == hpet_readl(HPET_COUNTER)) {
782 printk(KERN_WARNING
783 "HPET counter not counting. HPET disabled\n");
784 return -ENODEV;
785 }
786
787 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
788 return 0;
789}
790
791static u32 *hpet_boot_cfg;
792
793/**
794 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
795 */
796int __init hpet_enable(void)
797{
798 u32 hpet_period, cfg, id;
799 u64 freq;
800 unsigned int i, last;
801
802 if (!is_hpet_capable())
803 return 0;
804
805 hpet_set_mapping();
806
807 /*
808 * Read the period and check for a sane value:
809 */
810 hpet_period = hpet_readl(HPET_PERIOD);
811
812 /*
813 * AMD SB700 based systems with spread spectrum enabled use a
814 * SMM based HPET emulation to provide proper frequency
815 * setting. The SMM code is initialized with the first HPET
816 * register access and takes some time to complete. During
817 * this time the config register reads 0xffffffff. We check
818 * for max. 1000 loops whether the config register reads a non
819 * 0xffffffff value to make sure that HPET is up and running
820 * before we go further. A counting loop is safe, as the HPET
821 * access takes thousands of CPU cycles. On non SB700 based
822 * machines this check is only done once and has no side
823 * effects.
824 */
825 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
826 if (i == 1000) {
827 printk(KERN_WARNING
828 "HPET config register value = 0xFFFFFFFF. "
829 "Disabling HPET\n");
830 goto out_nohpet;
831 }
832 }
833
834 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
835 goto out_nohpet;
836
837 /*
838 * The period is a femto seconds value. Convert it to a
839 * frequency.
840 */
841 freq = FSEC_PER_SEC;
842 do_div(freq, hpet_period);
843 hpet_freq = freq;
844
845 /*
846 * Read the HPET ID register to retrieve the IRQ routing
847 * information and the number of channels
848 */
849 id = hpet_readl(HPET_ID);
850 hpet_print_config();
851
852 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
853
854#ifdef CONFIG_HPET_EMULATE_RTC
855 /*
856 * The legacy routing mode needs at least two channels, tick timer
857 * and the rtc emulation channel.
858 */
859 if (!last)
860 goto out_nohpet;
861#endif
862
863 cfg = hpet_readl(HPET_CFG);
864 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
865 GFP_KERNEL);
866 if (hpet_boot_cfg)
867 *hpet_boot_cfg = cfg;
868 else
869 pr_warn("HPET initial state will not be saved\n");
870 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
871 hpet_writel(cfg, HPET_CFG);
872 if (cfg)
873 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
874 cfg);
875
876 for (i = 0; i <= last; ++i) {
877 cfg = hpet_readl(HPET_Tn_CFG(i));
878 if (hpet_boot_cfg)
879 hpet_boot_cfg[i + 1] = cfg;
880 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
881 hpet_writel(cfg, HPET_Tn_CFG(i));
882 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
883 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
884 | HPET_TN_FSB | HPET_TN_FSB_CAP);
885 if (cfg)
886 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
887 cfg, i);
888 }
889 hpet_print_config();
890
891 if (hpet_clocksource_register())
892 goto out_nohpet;
893
894 if (id & HPET_ID_LEGSUP) {
895 hpet_legacy_clockevent_register();
896 return 1;
897 }
898 return 0;
899
900out_nohpet:
901 hpet_clear_mapping();
902 hpet_address = 0;
903 return 0;
904}
905
906/*
907 * Needs to be late, as the reserve_timer code calls kalloc !
908 *
909 * Not a problem on i386 as hpet_enable is called from late_time_init,
910 * but on x86_64 it is necessary !
911 */
912static __init int hpet_late_init(void)
913{
914 int cpu;
915
916 if (boot_hpet_disable)
917 return -ENODEV;
918
919 if (!hpet_address) {
920 if (!force_hpet_address)
921 return -ENODEV;
922
923 hpet_address = force_hpet_address;
924 hpet_enable();
925 }
926
927 if (!hpet_virt_address)
928 return -ENODEV;
929
930 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
931 hpet_msi_capability_lookup(2);
932 else
933 hpet_msi_capability_lookup(0);
934
935 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
936 hpet_print_config();
937
938 if (hpet_msi_disable)
939 return 0;
940
941 if (boot_cpu_has(X86_FEATURE_ARAT))
942 return 0;
943
944 cpu_notifier_register_begin();
945 for_each_online_cpu(cpu) {
946 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
947 }
948
949 /* This notifier should be called after workqueue is ready */
950 __hotcpu_notifier(hpet_cpuhp_notify, -20);
951 cpu_notifier_register_done();
952
953 return 0;
954}
955fs_initcall(hpet_late_init);
956
957void hpet_disable(void)
958{
959 if (is_hpet_capable() && hpet_virt_address) {
960 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
961
962 if (hpet_boot_cfg)
963 cfg = *hpet_boot_cfg;
964 else if (hpet_legacy_int_enabled) {
965 cfg &= ~HPET_CFG_LEGACY;
966 hpet_legacy_int_enabled = 0;
967 }
968 cfg &= ~HPET_CFG_ENABLE;
969 hpet_writel(cfg, HPET_CFG);
970
971 if (!hpet_boot_cfg)
972 return;
973
974 id = hpet_readl(HPET_ID);
975 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
976
977 for (id = 0; id <= last; ++id)
978 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
979
980 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
981 hpet_writel(*hpet_boot_cfg, HPET_CFG);
982 }
983}
984
985#ifdef CONFIG_HPET_EMULATE_RTC
986
987/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
988 * is enabled, we support RTC interrupt functionality in software.
989 * RTC has 3 kinds of interrupts:
990 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
991 * is updated
992 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
993 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
994 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
995 * (1) and (2) above are implemented using polling at a frequency of
996 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
997 * overhead. (DEFAULT_RTC_INT_FREQ)
998 * For (3), we use interrupts at 64Hz or user specified periodic
999 * frequency, whichever is higher.
1000 */
1001#include <linux/mc146818rtc.h>
1002#include <linux/rtc.h>
1003#include <asm/rtc.h>
1004
1005#define DEFAULT_RTC_INT_FREQ 64
1006#define DEFAULT_RTC_SHIFT 6
1007#define RTC_NUM_INTS 1
1008
1009static unsigned long hpet_rtc_flags;
1010static int hpet_prev_update_sec;
1011static struct rtc_time hpet_alarm_time;
1012static unsigned long hpet_pie_count;
1013static u32 hpet_t1_cmp;
1014static u32 hpet_default_delta;
1015static u32 hpet_pie_delta;
1016static unsigned long hpet_pie_limit;
1017
1018static rtc_irq_handler irq_handler;
1019
1020/*
1021 * Check that the hpet counter c1 is ahead of the c2
1022 */
1023static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1024{
1025 return (s32)(c2 - c1) < 0;
1026}
1027
1028/*
1029 * Registers a IRQ handler.
1030 */
1031int hpet_register_irq_handler(rtc_irq_handler handler)
1032{
1033 if (!is_hpet_enabled())
1034 return -ENODEV;
1035 if (irq_handler)
1036 return -EBUSY;
1037
1038 irq_handler = handler;
1039
1040 return 0;
1041}
1042EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1043
1044/*
1045 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1046 * and does cleanup.
1047 */
1048void hpet_unregister_irq_handler(rtc_irq_handler handler)
1049{
1050 if (!is_hpet_enabled())
1051 return;
1052
1053 irq_handler = NULL;
1054 hpet_rtc_flags = 0;
1055}
1056EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1057
1058/*
1059 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1060 * is not supported by all HPET implementations for timer 1.
1061 *
1062 * hpet_rtc_timer_init() is called when the rtc is initialized.
1063 */
1064int hpet_rtc_timer_init(void)
1065{
1066 unsigned int cfg, cnt, delta;
1067 unsigned long flags;
1068
1069 if (!is_hpet_enabled())
1070 return 0;
1071
1072 if (!hpet_default_delta) {
1073 uint64_t clc;
1074
1075 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1076 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1077 hpet_default_delta = clc;
1078 }
1079
1080 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1081 delta = hpet_default_delta;
1082 else
1083 delta = hpet_pie_delta;
1084
1085 local_irq_save(flags);
1086
1087 cnt = delta + hpet_readl(HPET_COUNTER);
1088 hpet_writel(cnt, HPET_T1_CMP);
1089 hpet_t1_cmp = cnt;
1090
1091 cfg = hpet_readl(HPET_T1_CFG);
1092 cfg &= ~HPET_TN_PERIODIC;
1093 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1094 hpet_writel(cfg, HPET_T1_CFG);
1095
1096 local_irq_restore(flags);
1097
1098 return 1;
1099}
1100EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1101
1102static void hpet_disable_rtc_channel(void)
1103{
1104 unsigned long cfg;
1105 cfg = hpet_readl(HPET_T1_CFG);
1106 cfg &= ~HPET_TN_ENABLE;
1107 hpet_writel(cfg, HPET_T1_CFG);
1108}
1109
1110/*
1111 * The functions below are called from rtc driver.
1112 * Return 0 if HPET is not being used.
1113 * Otherwise do the necessary changes and return 1.
1114 */
1115int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1116{
1117 if (!is_hpet_enabled())
1118 return 0;
1119
1120 hpet_rtc_flags &= ~bit_mask;
1121 if (unlikely(!hpet_rtc_flags))
1122 hpet_disable_rtc_channel();
1123
1124 return 1;
1125}
1126EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1127
1128int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1129{
1130 unsigned long oldbits = hpet_rtc_flags;
1131
1132 if (!is_hpet_enabled())
1133 return 0;
1134
1135 hpet_rtc_flags |= bit_mask;
1136
1137 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1138 hpet_prev_update_sec = -1;
1139
1140 if (!oldbits)
1141 hpet_rtc_timer_init();
1142
1143 return 1;
1144}
1145EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1146
1147int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1148 unsigned char sec)
1149{
1150 if (!is_hpet_enabled())
1151 return 0;
1152
1153 hpet_alarm_time.tm_hour = hrs;
1154 hpet_alarm_time.tm_min = min;
1155 hpet_alarm_time.tm_sec = sec;
1156
1157 return 1;
1158}
1159EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1160
1161int hpet_set_periodic_freq(unsigned long freq)
1162{
1163 uint64_t clc;
1164
1165 if (!is_hpet_enabled())
1166 return 0;
1167
1168 if (freq <= DEFAULT_RTC_INT_FREQ)
1169 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1170 else {
1171 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1172 do_div(clc, freq);
1173 clc >>= hpet_clockevent.shift;
1174 hpet_pie_delta = clc;
1175 hpet_pie_limit = 0;
1176 }
1177 return 1;
1178}
1179EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1180
1181int hpet_rtc_dropped_irq(void)
1182{
1183 return is_hpet_enabled();
1184}
1185EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1186
1187static void hpet_rtc_timer_reinit(void)
1188{
1189 unsigned int delta;
1190 int lost_ints = -1;
1191
1192 if (unlikely(!hpet_rtc_flags))
1193 hpet_disable_rtc_channel();
1194
1195 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1196 delta = hpet_default_delta;
1197 else
1198 delta = hpet_pie_delta;
1199
1200 /*
1201 * Increment the comparator value until we are ahead of the
1202 * current count.
1203 */
1204 do {
1205 hpet_t1_cmp += delta;
1206 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1207 lost_ints++;
1208 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1209
1210 if (lost_ints) {
1211 if (hpet_rtc_flags & RTC_PIE)
1212 hpet_pie_count += lost_ints;
1213 if (printk_ratelimit())
1214 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1215 lost_ints);
1216 }
1217}
1218
1219irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1220{
1221 struct rtc_time curr_time;
1222 unsigned long rtc_int_flag = 0;
1223
1224 hpet_rtc_timer_reinit();
1225 memset(&curr_time, 0, sizeof(struct rtc_time));
1226
1227 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1228 get_rtc_time(&curr_time);
1229
1230 if (hpet_rtc_flags & RTC_UIE &&
1231 curr_time.tm_sec != hpet_prev_update_sec) {
1232 if (hpet_prev_update_sec >= 0)
1233 rtc_int_flag = RTC_UF;
1234 hpet_prev_update_sec = curr_time.tm_sec;
1235 }
1236
1237 if (hpet_rtc_flags & RTC_PIE &&
1238 ++hpet_pie_count >= hpet_pie_limit) {
1239 rtc_int_flag |= RTC_PF;
1240 hpet_pie_count = 0;
1241 }
1242
1243 if (hpet_rtc_flags & RTC_AIE &&
1244 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1245 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1246 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1247 rtc_int_flag |= RTC_AF;
1248
1249 if (rtc_int_flag) {
1250 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1251 if (irq_handler)
1252 irq_handler(rtc_int_flag, dev_id);
1253 }
1254 return IRQ_HANDLED;
1255}
1256EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1257#endif