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1#include <linux/clocksource.h>
2#include <linux/clockchips.h>
3#include <linux/interrupt.h>
4#include <linux/sysdev.h>
5#include <linux/delay.h>
6#include <linux/errno.h>
7#include <linux/i8253.h>
8#include <linux/slab.h>
9#include <linux/hpet.h>
10#include <linux/init.h>
11#include <linux/cpu.h>
12#include <linux/pm.h>
13#include <linux/io.h>
14
15#include <asm/fixmap.h>
16#include <asm/hpet.h>
17#include <asm/time.h>
18
19#define HPET_MASK CLOCKSOURCE_MASK(32)
20
21/* FSEC = 10^-15
22 NSEC = 10^-9 */
23#define FSEC_PER_NSEC 1000000L
24
25#define HPET_DEV_USED_BIT 2
26#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
27#define HPET_DEV_VALID 0x8
28#define HPET_DEV_FSB_CAP 0x1000
29#define HPET_DEV_PERI_CAP 0x2000
30
31#define HPET_MIN_CYCLES 128
32#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
33
34#define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
35
36/*
37 * HPET address is set in acpi/boot.c, when an ACPI entry exists
38 */
39unsigned long hpet_address;
40u8 hpet_blockid; /* OS timer block num */
41u8 hpet_msi_disable;
42
43#ifdef CONFIG_PCI_MSI
44static unsigned long hpet_num_timers;
45#endif
46static void __iomem *hpet_virt_address;
47
48struct hpet_dev {
49 struct clock_event_device evt;
50 unsigned int num;
51 int cpu;
52 unsigned int irq;
53 unsigned int flags;
54 char name[10];
55};
56
57inline unsigned int hpet_readl(unsigned int a)
58{
59 return readl(hpet_virt_address + a);
60}
61
62static inline void hpet_writel(unsigned int d, unsigned int a)
63{
64 writel(d, hpet_virt_address + a);
65}
66
67#ifdef CONFIG_X86_64
68#include <asm/pgtable.h>
69#endif
70
71static inline void hpet_set_mapping(void)
72{
73 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
74#ifdef CONFIG_X86_64
75 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
76#endif
77}
78
79static inline void hpet_clear_mapping(void)
80{
81 iounmap(hpet_virt_address);
82 hpet_virt_address = NULL;
83}
84
85/*
86 * HPET command line enable / disable
87 */
88static int boot_hpet_disable;
89int hpet_force_user;
90static int hpet_verbose;
91
92static int __init hpet_setup(char *str)
93{
94 if (str) {
95 if (!strncmp("disable", str, 7))
96 boot_hpet_disable = 1;
97 if (!strncmp("force", str, 5))
98 hpet_force_user = 1;
99 if (!strncmp("verbose", str, 7))
100 hpet_verbose = 1;
101 }
102 return 1;
103}
104__setup("hpet=", hpet_setup);
105
106static int __init disable_hpet(char *str)
107{
108 boot_hpet_disable = 1;
109 return 1;
110}
111__setup("nohpet", disable_hpet);
112
113static inline int is_hpet_capable(void)
114{
115 return !boot_hpet_disable && hpet_address;
116}
117
118/*
119 * HPET timer interrupt enable / disable
120 */
121static int hpet_legacy_int_enabled;
122
123/**
124 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
125 */
126int is_hpet_enabled(void)
127{
128 return is_hpet_capable() && hpet_legacy_int_enabled;
129}
130EXPORT_SYMBOL_GPL(is_hpet_enabled);
131
132static void _hpet_print_config(const char *function, int line)
133{
134 u32 i, timers, l, h;
135 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
136 l = hpet_readl(HPET_ID);
137 h = hpet_readl(HPET_PERIOD);
138 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
139 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
140 l = hpet_readl(HPET_CFG);
141 h = hpet_readl(HPET_STATUS);
142 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
143 l = hpet_readl(HPET_COUNTER);
144 h = hpet_readl(HPET_COUNTER+4);
145 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
146
147 for (i = 0; i < timers; i++) {
148 l = hpet_readl(HPET_Tn_CFG(i));
149 h = hpet_readl(HPET_Tn_CFG(i)+4);
150 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
151 i, l, h);
152 l = hpet_readl(HPET_Tn_CMP(i));
153 h = hpet_readl(HPET_Tn_CMP(i)+4);
154 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
155 i, l, h);
156 l = hpet_readl(HPET_Tn_ROUTE(i));
157 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
158 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
159 i, l, h);
160 }
161}
162
163#define hpet_print_config() \
164do { \
165 if (hpet_verbose) \
166 _hpet_print_config(__FUNCTION__, __LINE__); \
167} while (0)
168
169/*
170 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
171 * timer 0 and timer 1 in case of RTC emulation.
172 */
173#ifdef CONFIG_HPET
174
175static void hpet_reserve_msi_timers(struct hpet_data *hd);
176
177static void hpet_reserve_platform_timers(unsigned int id)
178{
179 struct hpet __iomem *hpet = hpet_virt_address;
180 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
181 unsigned int nrtimers, i;
182 struct hpet_data hd;
183
184 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
185
186 memset(&hd, 0, sizeof(hd));
187 hd.hd_phys_address = hpet_address;
188 hd.hd_address = hpet;
189 hd.hd_nirqs = nrtimers;
190 hpet_reserve_timer(&hd, 0);
191
192#ifdef CONFIG_HPET_EMULATE_RTC
193 hpet_reserve_timer(&hd, 1);
194#endif
195
196 /*
197 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
198 * is wrong for i8259!) not the output IRQ. Many BIOS writers
199 * don't bother configuring *any* comparator interrupts.
200 */
201 hd.hd_irq[0] = HPET_LEGACY_8254;
202 hd.hd_irq[1] = HPET_LEGACY_RTC;
203
204 for (i = 2; i < nrtimers; timer++, i++) {
205 hd.hd_irq[i] = (readl(&timer->hpet_config) &
206 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
207 }
208
209 hpet_reserve_msi_timers(&hd);
210
211 hpet_alloc(&hd);
212
213}
214#else
215static void hpet_reserve_platform_timers(unsigned int id) { }
216#endif
217
218/*
219 * Common hpet info
220 */
221static unsigned long hpet_freq;
222
223static void hpet_legacy_set_mode(enum clock_event_mode mode,
224 struct clock_event_device *evt);
225static int hpet_legacy_next_event(unsigned long delta,
226 struct clock_event_device *evt);
227
228/*
229 * The hpet clock event device
230 */
231static struct clock_event_device hpet_clockevent = {
232 .name = "hpet",
233 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
234 .set_mode = hpet_legacy_set_mode,
235 .set_next_event = hpet_legacy_next_event,
236 .irq = 0,
237 .rating = 50,
238};
239
240static void hpet_stop_counter(void)
241{
242 unsigned long cfg = hpet_readl(HPET_CFG);
243 cfg &= ~HPET_CFG_ENABLE;
244 hpet_writel(cfg, HPET_CFG);
245}
246
247static void hpet_reset_counter(void)
248{
249 hpet_writel(0, HPET_COUNTER);
250 hpet_writel(0, HPET_COUNTER + 4);
251}
252
253static void hpet_start_counter(void)
254{
255 unsigned int cfg = hpet_readl(HPET_CFG);
256 cfg |= HPET_CFG_ENABLE;
257 hpet_writel(cfg, HPET_CFG);
258}
259
260static void hpet_restart_counter(void)
261{
262 hpet_stop_counter();
263 hpet_reset_counter();
264 hpet_start_counter();
265}
266
267static void hpet_resume_device(void)
268{
269 force_hpet_resume();
270}
271
272static void hpet_resume_counter(struct clocksource *cs)
273{
274 hpet_resume_device();
275 hpet_restart_counter();
276}
277
278static void hpet_enable_legacy_int(void)
279{
280 unsigned int cfg = hpet_readl(HPET_CFG);
281
282 cfg |= HPET_CFG_LEGACY;
283 hpet_writel(cfg, HPET_CFG);
284 hpet_legacy_int_enabled = 1;
285}
286
287static void hpet_legacy_clockevent_register(void)
288{
289 /* Start HPET legacy interrupts */
290 hpet_enable_legacy_int();
291
292 /*
293 * Start hpet with the boot cpu mask and make it
294 * global after the IO_APIC has been initialized.
295 */
296 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
297 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
298 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
299 global_clock_event = &hpet_clockevent;
300 printk(KERN_DEBUG "hpet clockevent registered\n");
301}
302
303static int hpet_setup_msi_irq(unsigned int irq);
304
305static void hpet_set_mode(enum clock_event_mode mode,
306 struct clock_event_device *evt, int timer)
307{
308 unsigned int cfg, cmp, now;
309 uint64_t delta;
310
311 switch (mode) {
312 case CLOCK_EVT_MODE_PERIODIC:
313 hpet_stop_counter();
314 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
315 delta >>= evt->shift;
316 now = hpet_readl(HPET_COUNTER);
317 cmp = now + (unsigned int) delta;
318 cfg = hpet_readl(HPET_Tn_CFG(timer));
319 /* Make sure we use edge triggered interrupts */
320 cfg &= ~HPET_TN_LEVEL;
321 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
322 HPET_TN_SETVAL | HPET_TN_32BIT;
323 hpet_writel(cfg, HPET_Tn_CFG(timer));
324 hpet_writel(cmp, HPET_Tn_CMP(timer));
325 udelay(1);
326 /*
327 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
328 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
329 * bit is automatically cleared after the first write.
330 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
331 * Publication # 24674)
332 */
333 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
334 hpet_start_counter();
335 hpet_print_config();
336 break;
337
338 case CLOCK_EVT_MODE_ONESHOT:
339 cfg = hpet_readl(HPET_Tn_CFG(timer));
340 cfg &= ~HPET_TN_PERIODIC;
341 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
342 hpet_writel(cfg, HPET_Tn_CFG(timer));
343 break;
344
345 case CLOCK_EVT_MODE_UNUSED:
346 case CLOCK_EVT_MODE_SHUTDOWN:
347 cfg = hpet_readl(HPET_Tn_CFG(timer));
348 cfg &= ~HPET_TN_ENABLE;
349 hpet_writel(cfg, HPET_Tn_CFG(timer));
350 break;
351
352 case CLOCK_EVT_MODE_RESUME:
353 if (timer == 0) {
354 hpet_enable_legacy_int();
355 } else {
356 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
357 hpet_setup_msi_irq(hdev->irq);
358 disable_irq(hdev->irq);
359 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
360 enable_irq(hdev->irq);
361 }
362 hpet_print_config();
363 break;
364 }
365}
366
367static int hpet_next_event(unsigned long delta,
368 struct clock_event_device *evt, int timer)
369{
370 u32 cnt;
371 s32 res;
372
373 cnt = hpet_readl(HPET_COUNTER);
374 cnt += (u32) delta;
375 hpet_writel(cnt, HPET_Tn_CMP(timer));
376
377 /*
378 * HPETs are a complete disaster. The compare register is
379 * based on a equal comparison and neither provides a less
380 * than or equal functionality (which would require to take
381 * the wraparound into account) nor a simple count down event
382 * mode. Further the write to the comparator register is
383 * delayed internally up to two HPET clock cycles in certain
384 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
385 * longer delays. We worked around that by reading back the
386 * compare register, but that required another workaround for
387 * ICH9,10 chips where the first readout after write can
388 * return the old stale value. We already had a minimum
389 * programming delta of 5us enforced, but a NMI or SMI hitting
390 * between the counter readout and the comparator write can
391 * move us behind that point easily. Now instead of reading
392 * the compare register back several times, we make the ETIME
393 * decision based on the following: Return ETIME if the
394 * counter value after the write is less than HPET_MIN_CYCLES
395 * away from the event or if the counter is already ahead of
396 * the event. The minimum programming delta for the generic
397 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
398 */
399 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
400
401 return res < HPET_MIN_CYCLES ? -ETIME : 0;
402}
403
404static void hpet_legacy_set_mode(enum clock_event_mode mode,
405 struct clock_event_device *evt)
406{
407 hpet_set_mode(mode, evt, 0);
408}
409
410static int hpet_legacy_next_event(unsigned long delta,
411 struct clock_event_device *evt)
412{
413 return hpet_next_event(delta, evt, 0);
414}
415
416/*
417 * HPET MSI Support
418 */
419#ifdef CONFIG_PCI_MSI
420
421static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
422static struct hpet_dev *hpet_devs;
423
424void hpet_msi_unmask(struct irq_data *data)
425{
426 struct hpet_dev *hdev = data->handler_data;
427 unsigned int cfg;
428
429 /* unmask it */
430 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
431 cfg |= HPET_TN_FSB;
432 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
433}
434
435void hpet_msi_mask(struct irq_data *data)
436{
437 struct hpet_dev *hdev = data->handler_data;
438 unsigned int cfg;
439
440 /* mask it */
441 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
442 cfg &= ~HPET_TN_FSB;
443 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
444}
445
446void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
447{
448 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
449 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
450}
451
452void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
453{
454 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
455 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
456 msg->address_hi = 0;
457}
458
459static void hpet_msi_set_mode(enum clock_event_mode mode,
460 struct clock_event_device *evt)
461{
462 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
463 hpet_set_mode(mode, evt, hdev->num);
464}
465
466static int hpet_msi_next_event(unsigned long delta,
467 struct clock_event_device *evt)
468{
469 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
470 return hpet_next_event(delta, evt, hdev->num);
471}
472
473static int hpet_setup_msi_irq(unsigned int irq)
474{
475 if (arch_setup_hpet_msi(irq, hpet_blockid)) {
476 destroy_irq(irq);
477 return -EINVAL;
478 }
479 return 0;
480}
481
482static int hpet_assign_irq(struct hpet_dev *dev)
483{
484 unsigned int irq;
485
486 irq = create_irq_nr(0, -1);
487 if (!irq)
488 return -EINVAL;
489
490 irq_set_handler_data(irq, dev);
491
492 if (hpet_setup_msi_irq(irq))
493 return -EINVAL;
494
495 dev->irq = irq;
496 return 0;
497}
498
499static irqreturn_t hpet_interrupt_handler(int irq, void *data)
500{
501 struct hpet_dev *dev = (struct hpet_dev *)data;
502 struct clock_event_device *hevt = &dev->evt;
503
504 if (!hevt->event_handler) {
505 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
506 dev->num);
507 return IRQ_HANDLED;
508 }
509
510 hevt->event_handler(hevt);
511 return IRQ_HANDLED;
512}
513
514static int hpet_setup_irq(struct hpet_dev *dev)
515{
516
517 if (request_irq(dev->irq, hpet_interrupt_handler,
518 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
519 dev->name, dev))
520 return -1;
521
522 disable_irq(dev->irq);
523 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
524 enable_irq(dev->irq);
525
526 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
527 dev->name, dev->irq);
528
529 return 0;
530}
531
532/* This should be called in specific @cpu */
533static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
534{
535 struct clock_event_device *evt = &hdev->evt;
536
537 WARN_ON(cpu != smp_processor_id());
538 if (!(hdev->flags & HPET_DEV_VALID))
539 return;
540
541 if (hpet_setup_msi_irq(hdev->irq))
542 return;
543
544 hdev->cpu = cpu;
545 per_cpu(cpu_hpet_dev, cpu) = hdev;
546 evt->name = hdev->name;
547 hpet_setup_irq(hdev);
548 evt->irq = hdev->irq;
549
550 evt->rating = 110;
551 evt->features = CLOCK_EVT_FEAT_ONESHOT;
552 if (hdev->flags & HPET_DEV_PERI_CAP)
553 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
554
555 evt->set_mode = hpet_msi_set_mode;
556 evt->set_next_event = hpet_msi_next_event;
557 evt->cpumask = cpumask_of(hdev->cpu);
558
559 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
560 0x7FFFFFFF);
561}
562
563#ifdef CONFIG_HPET
564/* Reserve at least one timer for userspace (/dev/hpet) */
565#define RESERVE_TIMERS 1
566#else
567#define RESERVE_TIMERS 0
568#endif
569
570static void hpet_msi_capability_lookup(unsigned int start_timer)
571{
572 unsigned int id;
573 unsigned int num_timers;
574 unsigned int num_timers_used = 0;
575 int i;
576
577 if (hpet_msi_disable)
578 return;
579
580 if (boot_cpu_has(X86_FEATURE_ARAT))
581 return;
582 id = hpet_readl(HPET_ID);
583
584 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
585 num_timers++; /* Value read out starts from 0 */
586 hpet_print_config();
587
588 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
589 if (!hpet_devs)
590 return;
591
592 hpet_num_timers = num_timers;
593
594 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
595 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
596 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
597
598 /* Only consider HPET timer with MSI support */
599 if (!(cfg & HPET_TN_FSB_CAP))
600 continue;
601
602 hdev->flags = 0;
603 if (cfg & HPET_TN_PERIODIC_CAP)
604 hdev->flags |= HPET_DEV_PERI_CAP;
605 hdev->num = i;
606
607 sprintf(hdev->name, "hpet%d", i);
608 if (hpet_assign_irq(hdev))
609 continue;
610
611 hdev->flags |= HPET_DEV_FSB_CAP;
612 hdev->flags |= HPET_DEV_VALID;
613 num_timers_used++;
614 if (num_timers_used == num_possible_cpus())
615 break;
616 }
617
618 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
619 num_timers, num_timers_used);
620}
621
622#ifdef CONFIG_HPET
623static void hpet_reserve_msi_timers(struct hpet_data *hd)
624{
625 int i;
626
627 if (!hpet_devs)
628 return;
629
630 for (i = 0; i < hpet_num_timers; i++) {
631 struct hpet_dev *hdev = &hpet_devs[i];
632
633 if (!(hdev->flags & HPET_DEV_VALID))
634 continue;
635
636 hd->hd_irq[hdev->num] = hdev->irq;
637 hpet_reserve_timer(hd, hdev->num);
638 }
639}
640#endif
641
642static struct hpet_dev *hpet_get_unused_timer(void)
643{
644 int i;
645
646 if (!hpet_devs)
647 return NULL;
648
649 for (i = 0; i < hpet_num_timers; i++) {
650 struct hpet_dev *hdev = &hpet_devs[i];
651
652 if (!(hdev->flags & HPET_DEV_VALID))
653 continue;
654 if (test_and_set_bit(HPET_DEV_USED_BIT,
655 (unsigned long *)&hdev->flags))
656 continue;
657 return hdev;
658 }
659 return NULL;
660}
661
662struct hpet_work_struct {
663 struct delayed_work work;
664 struct completion complete;
665};
666
667static void hpet_work(struct work_struct *w)
668{
669 struct hpet_dev *hdev;
670 int cpu = smp_processor_id();
671 struct hpet_work_struct *hpet_work;
672
673 hpet_work = container_of(w, struct hpet_work_struct, work.work);
674
675 hdev = hpet_get_unused_timer();
676 if (hdev)
677 init_one_hpet_msi_clockevent(hdev, cpu);
678
679 complete(&hpet_work->complete);
680}
681
682static int hpet_cpuhp_notify(struct notifier_block *n,
683 unsigned long action, void *hcpu)
684{
685 unsigned long cpu = (unsigned long)hcpu;
686 struct hpet_work_struct work;
687 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
688
689 switch (action & 0xf) {
690 case CPU_ONLINE:
691 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
692 init_completion(&work.complete);
693 /* FIXME: add schedule_work_on() */
694 schedule_delayed_work_on(cpu, &work.work, 0);
695 wait_for_completion(&work.complete);
696 destroy_timer_on_stack(&work.work.timer);
697 break;
698 case CPU_DEAD:
699 if (hdev) {
700 free_irq(hdev->irq, hdev);
701 hdev->flags &= ~HPET_DEV_USED;
702 per_cpu(cpu_hpet_dev, cpu) = NULL;
703 }
704 break;
705 }
706 return NOTIFY_OK;
707}
708#else
709
710static int hpet_setup_msi_irq(unsigned int irq)
711{
712 return 0;
713}
714static void hpet_msi_capability_lookup(unsigned int start_timer)
715{
716 return;
717}
718
719#ifdef CONFIG_HPET
720static void hpet_reserve_msi_timers(struct hpet_data *hd)
721{
722 return;
723}
724#endif
725
726static int hpet_cpuhp_notify(struct notifier_block *n,
727 unsigned long action, void *hcpu)
728{
729 return NOTIFY_OK;
730}
731
732#endif
733
734/*
735 * Clock source related code
736 */
737static cycle_t read_hpet(struct clocksource *cs)
738{
739 return (cycle_t)hpet_readl(HPET_COUNTER);
740}
741
742static struct clocksource clocksource_hpet = {
743 .name = "hpet",
744 .rating = 250,
745 .read = read_hpet,
746 .mask = HPET_MASK,
747 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
748 .resume = hpet_resume_counter,
749#ifdef CONFIG_X86_64
750 .archdata = { .vclock_mode = VCLOCK_HPET },
751#endif
752};
753
754static int hpet_clocksource_register(void)
755{
756 u64 start, now;
757 cycle_t t1;
758
759 /* Start the counter */
760 hpet_restart_counter();
761
762 /* Verify whether hpet counter works */
763 t1 = hpet_readl(HPET_COUNTER);
764 rdtscll(start);
765
766 /*
767 * We don't know the TSC frequency yet, but waiting for
768 * 200000 TSC cycles is safe:
769 * 4 GHz == 50us
770 * 1 GHz == 200us
771 */
772 do {
773 rep_nop();
774 rdtscll(now);
775 } while ((now - start) < 200000UL);
776
777 if (t1 == hpet_readl(HPET_COUNTER)) {
778 printk(KERN_WARNING
779 "HPET counter not counting. HPET disabled\n");
780 return -ENODEV;
781 }
782
783 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
784 return 0;
785}
786
787/**
788 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
789 */
790int __init hpet_enable(void)
791{
792 unsigned long hpet_period;
793 unsigned int id;
794 u64 freq;
795 int i;
796
797 if (!is_hpet_capable())
798 return 0;
799
800 hpet_set_mapping();
801
802 /*
803 * Read the period and check for a sane value:
804 */
805 hpet_period = hpet_readl(HPET_PERIOD);
806
807 /*
808 * AMD SB700 based systems with spread spectrum enabled use a
809 * SMM based HPET emulation to provide proper frequency
810 * setting. The SMM code is initialized with the first HPET
811 * register access and takes some time to complete. During
812 * this time the config register reads 0xffffffff. We check
813 * for max. 1000 loops whether the config register reads a non
814 * 0xffffffff value to make sure that HPET is up and running
815 * before we go further. A counting loop is safe, as the HPET
816 * access takes thousands of CPU cycles. On non SB700 based
817 * machines this check is only done once and has no side
818 * effects.
819 */
820 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
821 if (i == 1000) {
822 printk(KERN_WARNING
823 "HPET config register value = 0xFFFFFFFF. "
824 "Disabling HPET\n");
825 goto out_nohpet;
826 }
827 }
828
829 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
830 goto out_nohpet;
831
832 /*
833 * The period is a femto seconds value. Convert it to a
834 * frequency.
835 */
836 freq = FSEC_PER_SEC;
837 do_div(freq, hpet_period);
838 hpet_freq = freq;
839
840 /*
841 * Read the HPET ID register to retrieve the IRQ routing
842 * information and the number of channels
843 */
844 id = hpet_readl(HPET_ID);
845 hpet_print_config();
846
847#ifdef CONFIG_HPET_EMULATE_RTC
848 /*
849 * The legacy routing mode needs at least two channels, tick timer
850 * and the rtc emulation channel.
851 */
852 if (!(id & HPET_ID_NUMBER))
853 goto out_nohpet;
854#endif
855
856 if (hpet_clocksource_register())
857 goto out_nohpet;
858
859 if (id & HPET_ID_LEGSUP) {
860 hpet_legacy_clockevent_register();
861 return 1;
862 }
863 return 0;
864
865out_nohpet:
866 hpet_clear_mapping();
867 hpet_address = 0;
868 return 0;
869}
870
871/*
872 * Needs to be late, as the reserve_timer code calls kalloc !
873 *
874 * Not a problem on i386 as hpet_enable is called from late_time_init,
875 * but on x86_64 it is necessary !
876 */
877static __init int hpet_late_init(void)
878{
879 int cpu;
880
881 if (boot_hpet_disable)
882 return -ENODEV;
883
884 if (!hpet_address) {
885 if (!force_hpet_address)
886 return -ENODEV;
887
888 hpet_address = force_hpet_address;
889 hpet_enable();
890 }
891
892 if (!hpet_virt_address)
893 return -ENODEV;
894
895 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
896 hpet_msi_capability_lookup(2);
897 else
898 hpet_msi_capability_lookup(0);
899
900 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
901 hpet_print_config();
902
903 if (hpet_msi_disable)
904 return 0;
905
906 if (boot_cpu_has(X86_FEATURE_ARAT))
907 return 0;
908
909 for_each_online_cpu(cpu) {
910 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
911 }
912
913 /* This notifier should be called after workqueue is ready */
914 hotcpu_notifier(hpet_cpuhp_notify, -20);
915
916 return 0;
917}
918fs_initcall(hpet_late_init);
919
920void hpet_disable(void)
921{
922 if (is_hpet_capable() && hpet_virt_address) {
923 unsigned int cfg = hpet_readl(HPET_CFG);
924
925 if (hpet_legacy_int_enabled) {
926 cfg &= ~HPET_CFG_LEGACY;
927 hpet_legacy_int_enabled = 0;
928 }
929 cfg &= ~HPET_CFG_ENABLE;
930 hpet_writel(cfg, HPET_CFG);
931 }
932}
933
934#ifdef CONFIG_HPET_EMULATE_RTC
935
936/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
937 * is enabled, we support RTC interrupt functionality in software.
938 * RTC has 3 kinds of interrupts:
939 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
940 * is updated
941 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
942 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
943 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
944 * (1) and (2) above are implemented using polling at a frequency of
945 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
946 * overhead. (DEFAULT_RTC_INT_FREQ)
947 * For (3), we use interrupts at 64Hz or user specified periodic
948 * frequency, whichever is higher.
949 */
950#include <linux/mc146818rtc.h>
951#include <linux/rtc.h>
952#include <asm/rtc.h>
953
954#define DEFAULT_RTC_INT_FREQ 64
955#define DEFAULT_RTC_SHIFT 6
956#define RTC_NUM_INTS 1
957
958static unsigned long hpet_rtc_flags;
959static int hpet_prev_update_sec;
960static struct rtc_time hpet_alarm_time;
961static unsigned long hpet_pie_count;
962static u32 hpet_t1_cmp;
963static u32 hpet_default_delta;
964static u32 hpet_pie_delta;
965static unsigned long hpet_pie_limit;
966
967static rtc_irq_handler irq_handler;
968
969/*
970 * Check that the hpet counter c1 is ahead of the c2
971 */
972static inline int hpet_cnt_ahead(u32 c1, u32 c2)
973{
974 return (s32)(c2 - c1) < 0;
975}
976
977/*
978 * Registers a IRQ handler.
979 */
980int hpet_register_irq_handler(rtc_irq_handler handler)
981{
982 if (!is_hpet_enabled())
983 return -ENODEV;
984 if (irq_handler)
985 return -EBUSY;
986
987 irq_handler = handler;
988
989 return 0;
990}
991EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
992
993/*
994 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
995 * and does cleanup.
996 */
997void hpet_unregister_irq_handler(rtc_irq_handler handler)
998{
999 if (!is_hpet_enabled())
1000 return;
1001
1002 irq_handler = NULL;
1003 hpet_rtc_flags = 0;
1004}
1005EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1006
1007/*
1008 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1009 * is not supported by all HPET implementations for timer 1.
1010 *
1011 * hpet_rtc_timer_init() is called when the rtc is initialized.
1012 */
1013int hpet_rtc_timer_init(void)
1014{
1015 unsigned int cfg, cnt, delta;
1016 unsigned long flags;
1017
1018 if (!is_hpet_enabled())
1019 return 0;
1020
1021 if (!hpet_default_delta) {
1022 uint64_t clc;
1023
1024 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1025 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1026 hpet_default_delta = clc;
1027 }
1028
1029 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1030 delta = hpet_default_delta;
1031 else
1032 delta = hpet_pie_delta;
1033
1034 local_irq_save(flags);
1035
1036 cnt = delta + hpet_readl(HPET_COUNTER);
1037 hpet_writel(cnt, HPET_T1_CMP);
1038 hpet_t1_cmp = cnt;
1039
1040 cfg = hpet_readl(HPET_T1_CFG);
1041 cfg &= ~HPET_TN_PERIODIC;
1042 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1043 hpet_writel(cfg, HPET_T1_CFG);
1044
1045 local_irq_restore(flags);
1046
1047 return 1;
1048}
1049EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1050
1051/*
1052 * The functions below are called from rtc driver.
1053 * Return 0 if HPET is not being used.
1054 * Otherwise do the necessary changes and return 1.
1055 */
1056int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1057{
1058 if (!is_hpet_enabled())
1059 return 0;
1060
1061 hpet_rtc_flags &= ~bit_mask;
1062 return 1;
1063}
1064EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1065
1066int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1067{
1068 unsigned long oldbits = hpet_rtc_flags;
1069
1070 if (!is_hpet_enabled())
1071 return 0;
1072
1073 hpet_rtc_flags |= bit_mask;
1074
1075 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1076 hpet_prev_update_sec = -1;
1077
1078 if (!oldbits)
1079 hpet_rtc_timer_init();
1080
1081 return 1;
1082}
1083EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1084
1085int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1086 unsigned char sec)
1087{
1088 if (!is_hpet_enabled())
1089 return 0;
1090
1091 hpet_alarm_time.tm_hour = hrs;
1092 hpet_alarm_time.tm_min = min;
1093 hpet_alarm_time.tm_sec = sec;
1094
1095 return 1;
1096}
1097EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1098
1099int hpet_set_periodic_freq(unsigned long freq)
1100{
1101 uint64_t clc;
1102
1103 if (!is_hpet_enabled())
1104 return 0;
1105
1106 if (freq <= DEFAULT_RTC_INT_FREQ)
1107 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1108 else {
1109 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1110 do_div(clc, freq);
1111 clc >>= hpet_clockevent.shift;
1112 hpet_pie_delta = clc;
1113 hpet_pie_limit = 0;
1114 }
1115 return 1;
1116}
1117EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1118
1119int hpet_rtc_dropped_irq(void)
1120{
1121 return is_hpet_enabled();
1122}
1123EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1124
1125static void hpet_rtc_timer_reinit(void)
1126{
1127 unsigned int cfg, delta;
1128 int lost_ints = -1;
1129
1130 if (unlikely(!hpet_rtc_flags)) {
1131 cfg = hpet_readl(HPET_T1_CFG);
1132 cfg &= ~HPET_TN_ENABLE;
1133 hpet_writel(cfg, HPET_T1_CFG);
1134 return;
1135 }
1136
1137 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1138 delta = hpet_default_delta;
1139 else
1140 delta = hpet_pie_delta;
1141
1142 /*
1143 * Increment the comparator value until we are ahead of the
1144 * current count.
1145 */
1146 do {
1147 hpet_t1_cmp += delta;
1148 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1149 lost_ints++;
1150 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1151
1152 if (lost_ints) {
1153 if (hpet_rtc_flags & RTC_PIE)
1154 hpet_pie_count += lost_ints;
1155 if (printk_ratelimit())
1156 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1157 lost_ints);
1158 }
1159}
1160
1161irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1162{
1163 struct rtc_time curr_time;
1164 unsigned long rtc_int_flag = 0;
1165
1166 hpet_rtc_timer_reinit();
1167 memset(&curr_time, 0, sizeof(struct rtc_time));
1168
1169 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1170 get_rtc_time(&curr_time);
1171
1172 if (hpet_rtc_flags & RTC_UIE &&
1173 curr_time.tm_sec != hpet_prev_update_sec) {
1174 if (hpet_prev_update_sec >= 0)
1175 rtc_int_flag = RTC_UF;
1176 hpet_prev_update_sec = curr_time.tm_sec;
1177 }
1178
1179 if (hpet_rtc_flags & RTC_PIE &&
1180 ++hpet_pie_count >= hpet_pie_limit) {
1181 rtc_int_flag |= RTC_PF;
1182 hpet_pie_count = 0;
1183 }
1184
1185 if (hpet_rtc_flags & RTC_AIE &&
1186 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1187 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1188 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1189 rtc_int_flag |= RTC_AF;
1190
1191 if (rtc_int_flag) {
1192 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1193 if (irq_handler)
1194 irq_handler(rtc_int_flag, dev_id);
1195 }
1196 return IRQ_HANDLED;
1197}
1198EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1199#endif
1#include <linux/clocksource.h>
2#include <linux/clockchips.h>
3#include <linux/interrupt.h>
4#include <linux/export.h>
5#include <linux/delay.h>
6#include <linux/errno.h>
7#include <linux/i8253.h>
8#include <linux/slab.h>
9#include <linux/hpet.h>
10#include <linux/init.h>
11#include <linux/cpu.h>
12#include <linux/pm.h>
13#include <linux/io.h>
14
15#include <asm/cpufeature.h>
16#include <asm/irqdomain.h>
17#include <asm/fixmap.h>
18#include <asm/hpet.h>
19#include <asm/time.h>
20
21#define HPET_MASK CLOCKSOURCE_MASK(32)
22
23/* FSEC = 10^-15
24 NSEC = 10^-9 */
25#define FSEC_PER_NSEC 1000000L
26
27#define HPET_DEV_USED_BIT 2
28#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
29#define HPET_DEV_VALID 0x8
30#define HPET_DEV_FSB_CAP 0x1000
31#define HPET_DEV_PERI_CAP 0x2000
32
33#define HPET_MIN_CYCLES 128
34#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
35
36/*
37 * HPET address is set in acpi/boot.c, when an ACPI entry exists
38 */
39unsigned long hpet_address;
40u8 hpet_blockid; /* OS timer block num */
41bool hpet_msi_disable;
42
43#ifdef CONFIG_PCI_MSI
44static unsigned int hpet_num_timers;
45#endif
46static void __iomem *hpet_virt_address;
47
48struct hpet_dev {
49 struct clock_event_device evt;
50 unsigned int num;
51 int cpu;
52 unsigned int irq;
53 unsigned int flags;
54 char name[10];
55};
56
57inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
58{
59 return container_of(evtdev, struct hpet_dev, evt);
60}
61
62inline unsigned int hpet_readl(unsigned int a)
63{
64 return readl(hpet_virt_address + a);
65}
66
67static inline void hpet_writel(unsigned int d, unsigned int a)
68{
69 writel(d, hpet_virt_address + a);
70}
71
72#ifdef CONFIG_X86_64
73#include <asm/pgtable.h>
74#endif
75
76static inline void hpet_set_mapping(void)
77{
78 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
79}
80
81static inline void hpet_clear_mapping(void)
82{
83 iounmap(hpet_virt_address);
84 hpet_virt_address = NULL;
85}
86
87/*
88 * HPET command line enable / disable
89 */
90bool boot_hpet_disable;
91bool hpet_force_user;
92static bool hpet_verbose;
93
94static int __init hpet_setup(char *str)
95{
96 while (str) {
97 char *next = strchr(str, ',');
98
99 if (next)
100 *next++ = 0;
101 if (!strncmp("disable", str, 7))
102 boot_hpet_disable = true;
103 if (!strncmp("force", str, 5))
104 hpet_force_user = true;
105 if (!strncmp("verbose", str, 7))
106 hpet_verbose = true;
107 str = next;
108 }
109 return 1;
110}
111__setup("hpet=", hpet_setup);
112
113static int __init disable_hpet(char *str)
114{
115 boot_hpet_disable = true;
116 return 1;
117}
118__setup("nohpet", disable_hpet);
119
120static inline int is_hpet_capable(void)
121{
122 return !boot_hpet_disable && hpet_address;
123}
124
125/*
126 * HPET timer interrupt enable / disable
127 */
128static bool hpet_legacy_int_enabled;
129
130/**
131 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
132 */
133int is_hpet_enabled(void)
134{
135 return is_hpet_capable() && hpet_legacy_int_enabled;
136}
137EXPORT_SYMBOL_GPL(is_hpet_enabled);
138
139static void _hpet_print_config(const char *function, int line)
140{
141 u32 i, timers, l, h;
142 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
143 l = hpet_readl(HPET_ID);
144 h = hpet_readl(HPET_PERIOD);
145 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
146 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
147 l = hpet_readl(HPET_CFG);
148 h = hpet_readl(HPET_STATUS);
149 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
150 l = hpet_readl(HPET_COUNTER);
151 h = hpet_readl(HPET_COUNTER+4);
152 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
153
154 for (i = 0; i < timers; i++) {
155 l = hpet_readl(HPET_Tn_CFG(i));
156 h = hpet_readl(HPET_Tn_CFG(i)+4);
157 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
158 i, l, h);
159 l = hpet_readl(HPET_Tn_CMP(i));
160 h = hpet_readl(HPET_Tn_CMP(i)+4);
161 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
162 i, l, h);
163 l = hpet_readl(HPET_Tn_ROUTE(i));
164 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
165 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
166 i, l, h);
167 }
168}
169
170#define hpet_print_config() \
171do { \
172 if (hpet_verbose) \
173 _hpet_print_config(__func__, __LINE__); \
174} while (0)
175
176/*
177 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
178 * timer 0 and timer 1 in case of RTC emulation.
179 */
180#ifdef CONFIG_HPET
181
182static void hpet_reserve_msi_timers(struct hpet_data *hd);
183
184static void hpet_reserve_platform_timers(unsigned int id)
185{
186 struct hpet __iomem *hpet = hpet_virt_address;
187 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
188 unsigned int nrtimers, i;
189 struct hpet_data hd;
190
191 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
192
193 memset(&hd, 0, sizeof(hd));
194 hd.hd_phys_address = hpet_address;
195 hd.hd_address = hpet;
196 hd.hd_nirqs = nrtimers;
197 hpet_reserve_timer(&hd, 0);
198
199#ifdef CONFIG_HPET_EMULATE_RTC
200 hpet_reserve_timer(&hd, 1);
201#endif
202
203 /*
204 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
205 * is wrong for i8259!) not the output IRQ. Many BIOS writers
206 * don't bother configuring *any* comparator interrupts.
207 */
208 hd.hd_irq[0] = HPET_LEGACY_8254;
209 hd.hd_irq[1] = HPET_LEGACY_RTC;
210
211 for (i = 2; i < nrtimers; timer++, i++) {
212 hd.hd_irq[i] = (readl(&timer->hpet_config) &
213 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
214 }
215
216 hpet_reserve_msi_timers(&hd);
217
218 hpet_alloc(&hd);
219
220}
221#else
222static void hpet_reserve_platform_timers(unsigned int id) { }
223#endif
224
225/*
226 * Common hpet info
227 */
228static unsigned long hpet_freq;
229
230static struct clock_event_device hpet_clockevent;
231
232static void hpet_stop_counter(void)
233{
234 u32 cfg = hpet_readl(HPET_CFG);
235 cfg &= ~HPET_CFG_ENABLE;
236 hpet_writel(cfg, HPET_CFG);
237}
238
239static void hpet_reset_counter(void)
240{
241 hpet_writel(0, HPET_COUNTER);
242 hpet_writel(0, HPET_COUNTER + 4);
243}
244
245static void hpet_start_counter(void)
246{
247 unsigned int cfg = hpet_readl(HPET_CFG);
248 cfg |= HPET_CFG_ENABLE;
249 hpet_writel(cfg, HPET_CFG);
250}
251
252static void hpet_restart_counter(void)
253{
254 hpet_stop_counter();
255 hpet_reset_counter();
256 hpet_start_counter();
257}
258
259static void hpet_resume_device(void)
260{
261 force_hpet_resume();
262}
263
264static void hpet_resume_counter(struct clocksource *cs)
265{
266 hpet_resume_device();
267 hpet_restart_counter();
268}
269
270static void hpet_enable_legacy_int(void)
271{
272 unsigned int cfg = hpet_readl(HPET_CFG);
273
274 cfg |= HPET_CFG_LEGACY;
275 hpet_writel(cfg, HPET_CFG);
276 hpet_legacy_int_enabled = true;
277}
278
279static void hpet_legacy_clockevent_register(void)
280{
281 /* Start HPET legacy interrupts */
282 hpet_enable_legacy_int();
283
284 /*
285 * Start hpet with the boot cpu mask and make it
286 * global after the IO_APIC has been initialized.
287 */
288 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
289 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
290 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
291 global_clock_event = &hpet_clockevent;
292 printk(KERN_DEBUG "hpet clockevent registered\n");
293}
294
295static int hpet_set_periodic(struct clock_event_device *evt, int timer)
296{
297 unsigned int cfg, cmp, now;
298 uint64_t delta;
299
300 hpet_stop_counter();
301 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
302 delta >>= evt->shift;
303 now = hpet_readl(HPET_COUNTER);
304 cmp = now + (unsigned int)delta;
305 cfg = hpet_readl(HPET_Tn_CFG(timer));
306 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
307 HPET_TN_32BIT;
308 hpet_writel(cfg, HPET_Tn_CFG(timer));
309 hpet_writel(cmp, HPET_Tn_CMP(timer));
310 udelay(1);
311 /*
312 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
313 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
314 * bit is automatically cleared after the first write.
315 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
316 * Publication # 24674)
317 */
318 hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer));
319 hpet_start_counter();
320 hpet_print_config();
321
322 return 0;
323}
324
325static int hpet_set_oneshot(struct clock_event_device *evt, int timer)
326{
327 unsigned int cfg;
328
329 cfg = hpet_readl(HPET_Tn_CFG(timer));
330 cfg &= ~HPET_TN_PERIODIC;
331 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
332 hpet_writel(cfg, HPET_Tn_CFG(timer));
333
334 return 0;
335}
336
337static int hpet_shutdown(struct clock_event_device *evt, int timer)
338{
339 unsigned int cfg;
340
341 cfg = hpet_readl(HPET_Tn_CFG(timer));
342 cfg &= ~HPET_TN_ENABLE;
343 hpet_writel(cfg, HPET_Tn_CFG(timer));
344
345 return 0;
346}
347
348static int hpet_resume(struct clock_event_device *evt, int timer)
349{
350 if (!timer) {
351 hpet_enable_legacy_int();
352 } else {
353 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
354
355 irq_domain_activate_irq(irq_get_irq_data(hdev->irq));
356 disable_irq(hdev->irq);
357 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
358 enable_irq(hdev->irq);
359 }
360 hpet_print_config();
361
362 return 0;
363}
364
365static int hpet_next_event(unsigned long delta,
366 struct clock_event_device *evt, int timer)
367{
368 u32 cnt;
369 s32 res;
370
371 cnt = hpet_readl(HPET_COUNTER);
372 cnt += (u32) delta;
373 hpet_writel(cnt, HPET_Tn_CMP(timer));
374
375 /*
376 * HPETs are a complete disaster. The compare register is
377 * based on a equal comparison and neither provides a less
378 * than or equal functionality (which would require to take
379 * the wraparound into account) nor a simple count down event
380 * mode. Further the write to the comparator register is
381 * delayed internally up to two HPET clock cycles in certain
382 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
383 * longer delays. We worked around that by reading back the
384 * compare register, but that required another workaround for
385 * ICH9,10 chips where the first readout after write can
386 * return the old stale value. We already had a minimum
387 * programming delta of 5us enforced, but a NMI or SMI hitting
388 * between the counter readout and the comparator write can
389 * move us behind that point easily. Now instead of reading
390 * the compare register back several times, we make the ETIME
391 * decision based on the following: Return ETIME if the
392 * counter value after the write is less than HPET_MIN_CYCLES
393 * away from the event or if the counter is already ahead of
394 * the event. The minimum programming delta for the generic
395 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
396 */
397 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
398
399 return res < HPET_MIN_CYCLES ? -ETIME : 0;
400}
401
402static int hpet_legacy_shutdown(struct clock_event_device *evt)
403{
404 return hpet_shutdown(evt, 0);
405}
406
407static int hpet_legacy_set_oneshot(struct clock_event_device *evt)
408{
409 return hpet_set_oneshot(evt, 0);
410}
411
412static int hpet_legacy_set_periodic(struct clock_event_device *evt)
413{
414 return hpet_set_periodic(evt, 0);
415}
416
417static int hpet_legacy_resume(struct clock_event_device *evt)
418{
419 return hpet_resume(evt, 0);
420}
421
422static int hpet_legacy_next_event(unsigned long delta,
423 struct clock_event_device *evt)
424{
425 return hpet_next_event(delta, evt, 0);
426}
427
428/*
429 * The hpet clock event device
430 */
431static struct clock_event_device hpet_clockevent = {
432 .name = "hpet",
433 .features = CLOCK_EVT_FEAT_PERIODIC |
434 CLOCK_EVT_FEAT_ONESHOT,
435 .set_state_periodic = hpet_legacy_set_periodic,
436 .set_state_oneshot = hpet_legacy_set_oneshot,
437 .set_state_shutdown = hpet_legacy_shutdown,
438 .tick_resume = hpet_legacy_resume,
439 .set_next_event = hpet_legacy_next_event,
440 .irq = 0,
441 .rating = 50,
442};
443
444/*
445 * HPET MSI Support
446 */
447#ifdef CONFIG_PCI_MSI
448
449static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
450static struct hpet_dev *hpet_devs;
451static struct irq_domain *hpet_domain;
452
453void hpet_msi_unmask(struct irq_data *data)
454{
455 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
456 unsigned int cfg;
457
458 /* unmask it */
459 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
460 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
461 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
462}
463
464void hpet_msi_mask(struct irq_data *data)
465{
466 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
467 unsigned int cfg;
468
469 /* mask it */
470 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
471 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
472 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
473}
474
475void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
476{
477 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
478 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
479}
480
481void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
482{
483 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
484 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
485 msg->address_hi = 0;
486}
487
488static int hpet_msi_shutdown(struct clock_event_device *evt)
489{
490 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
491
492 return hpet_shutdown(evt, hdev->num);
493}
494
495static int hpet_msi_set_oneshot(struct clock_event_device *evt)
496{
497 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
498
499 return hpet_set_oneshot(evt, hdev->num);
500}
501
502static int hpet_msi_set_periodic(struct clock_event_device *evt)
503{
504 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
505
506 return hpet_set_periodic(evt, hdev->num);
507}
508
509static int hpet_msi_resume(struct clock_event_device *evt)
510{
511 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
512
513 return hpet_resume(evt, hdev->num);
514}
515
516static int hpet_msi_next_event(unsigned long delta,
517 struct clock_event_device *evt)
518{
519 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
520 return hpet_next_event(delta, evt, hdev->num);
521}
522
523static irqreturn_t hpet_interrupt_handler(int irq, void *data)
524{
525 struct hpet_dev *dev = (struct hpet_dev *)data;
526 struct clock_event_device *hevt = &dev->evt;
527
528 if (!hevt->event_handler) {
529 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
530 dev->num);
531 return IRQ_HANDLED;
532 }
533
534 hevt->event_handler(hevt);
535 return IRQ_HANDLED;
536}
537
538static int hpet_setup_irq(struct hpet_dev *dev)
539{
540
541 if (request_irq(dev->irq, hpet_interrupt_handler,
542 IRQF_TIMER | IRQF_NOBALANCING,
543 dev->name, dev))
544 return -1;
545
546 disable_irq(dev->irq);
547 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
548 enable_irq(dev->irq);
549
550 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
551 dev->name, dev->irq);
552
553 return 0;
554}
555
556/* This should be called in specific @cpu */
557static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
558{
559 struct clock_event_device *evt = &hdev->evt;
560
561 WARN_ON(cpu != smp_processor_id());
562 if (!(hdev->flags & HPET_DEV_VALID))
563 return;
564
565 hdev->cpu = cpu;
566 per_cpu(cpu_hpet_dev, cpu) = hdev;
567 evt->name = hdev->name;
568 hpet_setup_irq(hdev);
569 evt->irq = hdev->irq;
570
571 evt->rating = 110;
572 evt->features = CLOCK_EVT_FEAT_ONESHOT;
573 if (hdev->flags & HPET_DEV_PERI_CAP) {
574 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
575 evt->set_state_periodic = hpet_msi_set_periodic;
576 }
577
578 evt->set_state_shutdown = hpet_msi_shutdown;
579 evt->set_state_oneshot = hpet_msi_set_oneshot;
580 evt->tick_resume = hpet_msi_resume;
581 evt->set_next_event = hpet_msi_next_event;
582 evt->cpumask = cpumask_of(hdev->cpu);
583
584 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
585 0x7FFFFFFF);
586}
587
588#ifdef CONFIG_HPET
589/* Reserve at least one timer for userspace (/dev/hpet) */
590#define RESERVE_TIMERS 1
591#else
592#define RESERVE_TIMERS 0
593#endif
594
595static void hpet_msi_capability_lookup(unsigned int start_timer)
596{
597 unsigned int id;
598 unsigned int num_timers;
599 unsigned int num_timers_used = 0;
600 int i, irq;
601
602 if (hpet_msi_disable)
603 return;
604
605 if (boot_cpu_has(X86_FEATURE_ARAT))
606 return;
607 id = hpet_readl(HPET_ID);
608
609 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
610 num_timers++; /* Value read out starts from 0 */
611 hpet_print_config();
612
613 hpet_domain = hpet_create_irq_domain(hpet_blockid);
614 if (!hpet_domain)
615 return;
616
617 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
618 if (!hpet_devs)
619 return;
620
621 hpet_num_timers = num_timers;
622
623 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
624 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
625 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
626
627 /* Only consider HPET timer with MSI support */
628 if (!(cfg & HPET_TN_FSB_CAP))
629 continue;
630
631 hdev->flags = 0;
632 if (cfg & HPET_TN_PERIODIC_CAP)
633 hdev->flags |= HPET_DEV_PERI_CAP;
634 sprintf(hdev->name, "hpet%d", i);
635 hdev->num = i;
636
637 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num);
638 if (irq <= 0)
639 continue;
640
641 hdev->irq = irq;
642 hdev->flags |= HPET_DEV_FSB_CAP;
643 hdev->flags |= HPET_DEV_VALID;
644 num_timers_used++;
645 if (num_timers_used == num_possible_cpus())
646 break;
647 }
648
649 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
650 num_timers, num_timers_used);
651}
652
653#ifdef CONFIG_HPET
654static void hpet_reserve_msi_timers(struct hpet_data *hd)
655{
656 int i;
657
658 if (!hpet_devs)
659 return;
660
661 for (i = 0; i < hpet_num_timers; i++) {
662 struct hpet_dev *hdev = &hpet_devs[i];
663
664 if (!(hdev->flags & HPET_DEV_VALID))
665 continue;
666
667 hd->hd_irq[hdev->num] = hdev->irq;
668 hpet_reserve_timer(hd, hdev->num);
669 }
670}
671#endif
672
673static struct hpet_dev *hpet_get_unused_timer(void)
674{
675 int i;
676
677 if (!hpet_devs)
678 return NULL;
679
680 for (i = 0; i < hpet_num_timers; i++) {
681 struct hpet_dev *hdev = &hpet_devs[i];
682
683 if (!(hdev->flags & HPET_DEV_VALID))
684 continue;
685 if (test_and_set_bit(HPET_DEV_USED_BIT,
686 (unsigned long *)&hdev->flags))
687 continue;
688 return hdev;
689 }
690 return NULL;
691}
692
693struct hpet_work_struct {
694 struct delayed_work work;
695 struct completion complete;
696};
697
698static void hpet_work(struct work_struct *w)
699{
700 struct hpet_dev *hdev;
701 int cpu = smp_processor_id();
702 struct hpet_work_struct *hpet_work;
703
704 hpet_work = container_of(w, struct hpet_work_struct, work.work);
705
706 hdev = hpet_get_unused_timer();
707 if (hdev)
708 init_one_hpet_msi_clockevent(hdev, cpu);
709
710 complete(&hpet_work->complete);
711}
712
713static int hpet_cpuhp_notify(struct notifier_block *n,
714 unsigned long action, void *hcpu)
715{
716 unsigned long cpu = (unsigned long)hcpu;
717 struct hpet_work_struct work;
718 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
719
720 switch (action & ~CPU_TASKS_FROZEN) {
721 case CPU_ONLINE:
722 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
723 init_completion(&work.complete);
724 /* FIXME: add schedule_work_on() */
725 schedule_delayed_work_on(cpu, &work.work, 0);
726 wait_for_completion(&work.complete);
727 destroy_delayed_work_on_stack(&work.work);
728 break;
729 case CPU_DEAD:
730 if (hdev) {
731 free_irq(hdev->irq, hdev);
732 hdev->flags &= ~HPET_DEV_USED;
733 per_cpu(cpu_hpet_dev, cpu) = NULL;
734 }
735 break;
736 }
737 return NOTIFY_OK;
738}
739#else
740
741static void hpet_msi_capability_lookup(unsigned int start_timer)
742{
743 return;
744}
745
746#ifdef CONFIG_HPET
747static void hpet_reserve_msi_timers(struct hpet_data *hd)
748{
749 return;
750}
751#endif
752
753static int hpet_cpuhp_notify(struct notifier_block *n,
754 unsigned long action, void *hcpu)
755{
756 return NOTIFY_OK;
757}
758
759#endif
760
761/*
762 * Clock source related code
763 */
764static cycle_t read_hpet(struct clocksource *cs)
765{
766 return (cycle_t)hpet_readl(HPET_COUNTER);
767}
768
769static struct clocksource clocksource_hpet = {
770 .name = "hpet",
771 .rating = 250,
772 .read = read_hpet,
773 .mask = HPET_MASK,
774 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
775 .resume = hpet_resume_counter,
776 .archdata = { .vclock_mode = VCLOCK_HPET },
777};
778
779static int hpet_clocksource_register(void)
780{
781 u64 start, now;
782 cycle_t t1;
783
784 /* Start the counter */
785 hpet_restart_counter();
786
787 /* Verify whether hpet counter works */
788 t1 = hpet_readl(HPET_COUNTER);
789 start = rdtsc();
790
791 /*
792 * We don't know the TSC frequency yet, but waiting for
793 * 200000 TSC cycles is safe:
794 * 4 GHz == 50us
795 * 1 GHz == 200us
796 */
797 do {
798 rep_nop();
799 now = rdtsc();
800 } while ((now - start) < 200000UL);
801
802 if (t1 == hpet_readl(HPET_COUNTER)) {
803 printk(KERN_WARNING
804 "HPET counter not counting. HPET disabled\n");
805 return -ENODEV;
806 }
807
808 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
809 return 0;
810}
811
812static u32 *hpet_boot_cfg;
813
814/**
815 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
816 */
817int __init hpet_enable(void)
818{
819 u32 hpet_period, cfg, id;
820 u64 freq;
821 unsigned int i, last;
822
823 if (!is_hpet_capable())
824 return 0;
825
826 hpet_set_mapping();
827
828 /*
829 * Read the period and check for a sane value:
830 */
831 hpet_period = hpet_readl(HPET_PERIOD);
832
833 /*
834 * AMD SB700 based systems with spread spectrum enabled use a
835 * SMM based HPET emulation to provide proper frequency
836 * setting. The SMM code is initialized with the first HPET
837 * register access and takes some time to complete. During
838 * this time the config register reads 0xffffffff. We check
839 * for max. 1000 loops whether the config register reads a non
840 * 0xffffffff value to make sure that HPET is up and running
841 * before we go further. A counting loop is safe, as the HPET
842 * access takes thousands of CPU cycles. On non SB700 based
843 * machines this check is only done once and has no side
844 * effects.
845 */
846 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
847 if (i == 1000) {
848 printk(KERN_WARNING
849 "HPET config register value = 0xFFFFFFFF. "
850 "Disabling HPET\n");
851 goto out_nohpet;
852 }
853 }
854
855 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
856 goto out_nohpet;
857
858 /*
859 * The period is a femto seconds value. Convert it to a
860 * frequency.
861 */
862 freq = FSEC_PER_SEC;
863 do_div(freq, hpet_period);
864 hpet_freq = freq;
865
866 /*
867 * Read the HPET ID register to retrieve the IRQ routing
868 * information and the number of channels
869 */
870 id = hpet_readl(HPET_ID);
871 hpet_print_config();
872
873 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
874
875#ifdef CONFIG_HPET_EMULATE_RTC
876 /*
877 * The legacy routing mode needs at least two channels, tick timer
878 * and the rtc emulation channel.
879 */
880 if (!last)
881 goto out_nohpet;
882#endif
883
884 cfg = hpet_readl(HPET_CFG);
885 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
886 GFP_KERNEL);
887 if (hpet_boot_cfg)
888 *hpet_boot_cfg = cfg;
889 else
890 pr_warn("HPET initial state will not be saved\n");
891 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
892 hpet_writel(cfg, HPET_CFG);
893 if (cfg)
894 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
895 cfg);
896
897 for (i = 0; i <= last; ++i) {
898 cfg = hpet_readl(HPET_Tn_CFG(i));
899 if (hpet_boot_cfg)
900 hpet_boot_cfg[i + 1] = cfg;
901 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
902 hpet_writel(cfg, HPET_Tn_CFG(i));
903 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
904 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
905 | HPET_TN_FSB | HPET_TN_FSB_CAP);
906 if (cfg)
907 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
908 cfg, i);
909 }
910 hpet_print_config();
911
912 if (hpet_clocksource_register())
913 goto out_nohpet;
914
915 if (id & HPET_ID_LEGSUP) {
916 hpet_legacy_clockevent_register();
917 return 1;
918 }
919 return 0;
920
921out_nohpet:
922 hpet_clear_mapping();
923 hpet_address = 0;
924 return 0;
925}
926
927/*
928 * Needs to be late, as the reserve_timer code calls kalloc !
929 *
930 * Not a problem on i386 as hpet_enable is called from late_time_init,
931 * but on x86_64 it is necessary !
932 */
933static __init int hpet_late_init(void)
934{
935 int cpu;
936
937 if (boot_hpet_disable)
938 return -ENODEV;
939
940 if (!hpet_address) {
941 if (!force_hpet_address)
942 return -ENODEV;
943
944 hpet_address = force_hpet_address;
945 hpet_enable();
946 }
947
948 if (!hpet_virt_address)
949 return -ENODEV;
950
951 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
952 hpet_msi_capability_lookup(2);
953 else
954 hpet_msi_capability_lookup(0);
955
956 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
957 hpet_print_config();
958
959 if (hpet_msi_disable)
960 return 0;
961
962 if (boot_cpu_has(X86_FEATURE_ARAT))
963 return 0;
964
965 cpu_notifier_register_begin();
966 for_each_online_cpu(cpu) {
967 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
968 }
969
970 /* This notifier should be called after workqueue is ready */
971 __hotcpu_notifier(hpet_cpuhp_notify, -20);
972 cpu_notifier_register_done();
973
974 return 0;
975}
976fs_initcall(hpet_late_init);
977
978void hpet_disable(void)
979{
980 if (is_hpet_capable() && hpet_virt_address) {
981 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
982
983 if (hpet_boot_cfg)
984 cfg = *hpet_boot_cfg;
985 else if (hpet_legacy_int_enabled) {
986 cfg &= ~HPET_CFG_LEGACY;
987 hpet_legacy_int_enabled = false;
988 }
989 cfg &= ~HPET_CFG_ENABLE;
990 hpet_writel(cfg, HPET_CFG);
991
992 if (!hpet_boot_cfg)
993 return;
994
995 id = hpet_readl(HPET_ID);
996 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
997
998 for (id = 0; id <= last; ++id)
999 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
1000
1001 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
1002 hpet_writel(*hpet_boot_cfg, HPET_CFG);
1003 }
1004}
1005
1006#ifdef CONFIG_HPET_EMULATE_RTC
1007
1008/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1009 * is enabled, we support RTC interrupt functionality in software.
1010 * RTC has 3 kinds of interrupts:
1011 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1012 * is updated
1013 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1014 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1015 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1016 * (1) and (2) above are implemented using polling at a frequency of
1017 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1018 * overhead. (DEFAULT_RTC_INT_FREQ)
1019 * For (3), we use interrupts at 64Hz or user specified periodic
1020 * frequency, whichever is higher.
1021 */
1022#include <linux/mc146818rtc.h>
1023#include <linux/rtc.h>
1024#include <asm/rtc.h>
1025
1026#define DEFAULT_RTC_INT_FREQ 64
1027#define DEFAULT_RTC_SHIFT 6
1028#define RTC_NUM_INTS 1
1029
1030static unsigned long hpet_rtc_flags;
1031static int hpet_prev_update_sec;
1032static struct rtc_time hpet_alarm_time;
1033static unsigned long hpet_pie_count;
1034static u32 hpet_t1_cmp;
1035static u32 hpet_default_delta;
1036static u32 hpet_pie_delta;
1037static unsigned long hpet_pie_limit;
1038
1039static rtc_irq_handler irq_handler;
1040
1041/*
1042 * Check that the hpet counter c1 is ahead of the c2
1043 */
1044static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1045{
1046 return (s32)(c2 - c1) < 0;
1047}
1048
1049/*
1050 * Registers a IRQ handler.
1051 */
1052int hpet_register_irq_handler(rtc_irq_handler handler)
1053{
1054 if (!is_hpet_enabled())
1055 return -ENODEV;
1056 if (irq_handler)
1057 return -EBUSY;
1058
1059 irq_handler = handler;
1060
1061 return 0;
1062}
1063EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1064
1065/*
1066 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1067 * and does cleanup.
1068 */
1069void hpet_unregister_irq_handler(rtc_irq_handler handler)
1070{
1071 if (!is_hpet_enabled())
1072 return;
1073
1074 irq_handler = NULL;
1075 hpet_rtc_flags = 0;
1076}
1077EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1078
1079/*
1080 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1081 * is not supported by all HPET implementations for timer 1.
1082 *
1083 * hpet_rtc_timer_init() is called when the rtc is initialized.
1084 */
1085int hpet_rtc_timer_init(void)
1086{
1087 unsigned int cfg, cnt, delta;
1088 unsigned long flags;
1089
1090 if (!is_hpet_enabled())
1091 return 0;
1092
1093 if (!hpet_default_delta) {
1094 uint64_t clc;
1095
1096 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1097 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1098 hpet_default_delta = clc;
1099 }
1100
1101 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1102 delta = hpet_default_delta;
1103 else
1104 delta = hpet_pie_delta;
1105
1106 local_irq_save(flags);
1107
1108 cnt = delta + hpet_readl(HPET_COUNTER);
1109 hpet_writel(cnt, HPET_T1_CMP);
1110 hpet_t1_cmp = cnt;
1111
1112 cfg = hpet_readl(HPET_T1_CFG);
1113 cfg &= ~HPET_TN_PERIODIC;
1114 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1115 hpet_writel(cfg, HPET_T1_CFG);
1116
1117 local_irq_restore(flags);
1118
1119 return 1;
1120}
1121EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1122
1123static void hpet_disable_rtc_channel(void)
1124{
1125 u32 cfg = hpet_readl(HPET_T1_CFG);
1126 cfg &= ~HPET_TN_ENABLE;
1127 hpet_writel(cfg, HPET_T1_CFG);
1128}
1129
1130/*
1131 * The functions below are called from rtc driver.
1132 * Return 0 if HPET is not being used.
1133 * Otherwise do the necessary changes and return 1.
1134 */
1135int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1136{
1137 if (!is_hpet_enabled())
1138 return 0;
1139
1140 hpet_rtc_flags &= ~bit_mask;
1141 if (unlikely(!hpet_rtc_flags))
1142 hpet_disable_rtc_channel();
1143
1144 return 1;
1145}
1146EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1147
1148int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1149{
1150 unsigned long oldbits = hpet_rtc_flags;
1151
1152 if (!is_hpet_enabled())
1153 return 0;
1154
1155 hpet_rtc_flags |= bit_mask;
1156
1157 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1158 hpet_prev_update_sec = -1;
1159
1160 if (!oldbits)
1161 hpet_rtc_timer_init();
1162
1163 return 1;
1164}
1165EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1166
1167int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1168 unsigned char sec)
1169{
1170 if (!is_hpet_enabled())
1171 return 0;
1172
1173 hpet_alarm_time.tm_hour = hrs;
1174 hpet_alarm_time.tm_min = min;
1175 hpet_alarm_time.tm_sec = sec;
1176
1177 return 1;
1178}
1179EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1180
1181int hpet_set_periodic_freq(unsigned long freq)
1182{
1183 uint64_t clc;
1184
1185 if (!is_hpet_enabled())
1186 return 0;
1187
1188 if (freq <= DEFAULT_RTC_INT_FREQ)
1189 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1190 else {
1191 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1192 do_div(clc, freq);
1193 clc >>= hpet_clockevent.shift;
1194 hpet_pie_delta = clc;
1195 hpet_pie_limit = 0;
1196 }
1197 return 1;
1198}
1199EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1200
1201int hpet_rtc_dropped_irq(void)
1202{
1203 return is_hpet_enabled();
1204}
1205EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1206
1207static void hpet_rtc_timer_reinit(void)
1208{
1209 unsigned int delta;
1210 int lost_ints = -1;
1211
1212 if (unlikely(!hpet_rtc_flags))
1213 hpet_disable_rtc_channel();
1214
1215 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1216 delta = hpet_default_delta;
1217 else
1218 delta = hpet_pie_delta;
1219
1220 /*
1221 * Increment the comparator value until we are ahead of the
1222 * current count.
1223 */
1224 do {
1225 hpet_t1_cmp += delta;
1226 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1227 lost_ints++;
1228 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1229
1230 if (lost_ints) {
1231 if (hpet_rtc_flags & RTC_PIE)
1232 hpet_pie_count += lost_ints;
1233 if (printk_ratelimit())
1234 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1235 lost_ints);
1236 }
1237}
1238
1239irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1240{
1241 struct rtc_time curr_time;
1242 unsigned long rtc_int_flag = 0;
1243
1244 hpet_rtc_timer_reinit();
1245 memset(&curr_time, 0, sizeof(struct rtc_time));
1246
1247 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1248 get_rtc_time(&curr_time);
1249
1250 if (hpet_rtc_flags & RTC_UIE &&
1251 curr_time.tm_sec != hpet_prev_update_sec) {
1252 if (hpet_prev_update_sec >= 0)
1253 rtc_int_flag = RTC_UF;
1254 hpet_prev_update_sec = curr_time.tm_sec;
1255 }
1256
1257 if (hpet_rtc_flags & RTC_PIE &&
1258 ++hpet_pie_count >= hpet_pie_limit) {
1259 rtc_int_flag |= RTC_PF;
1260 hpet_pie_count = 0;
1261 }
1262
1263 if (hpet_rtc_flags & RTC_AIE &&
1264 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1265 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1266 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1267 rtc_int_flag |= RTC_AF;
1268
1269 if (rtc_int_flag) {
1270 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1271 if (irq_handler)
1272 irq_handler(rtc_int_flag, dev_id);
1273 }
1274 return IRQ_HANDLED;
1275}
1276EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1277#endif