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1/*
2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36#include <linux/sched.h>
37#include <linux/module.h>
38#include <linux/debugfs.h>
39#include <linux/perf_event.h>
40
41#include <asm/inst.h>
42#include <asm/bootinfo.h>
43#include <asm/processor.h>
44#include <asm/ptrace.h>
45#include <asm/signal.h>
46#include <asm/mipsregs.h>
47#include <asm/fpu_emulator.h>
48#include <asm/uaccess.h>
49#include <asm/branch.h>
50
51#include "ieee754.h"
52
53/* Strap kernel emulator for full MIPS IV emulation */
54
55#ifdef __mips
56#undef __mips
57#endif
58#define __mips 4
59
60/* Function which emulates a floating point instruction. */
61
62static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
63 mips_instruction);
64
65#if __mips >= 4 && __mips != 32
66static int fpux_emu(struct pt_regs *,
67 struct mips_fpu_struct *, mips_instruction, void *__user *);
68#endif
69
70/* Further private data for which no space exists in mips_fpu_struct */
71
72#ifdef CONFIG_DEBUG_FS
73DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
74#endif
75
76/* Control registers */
77
78#define FPCREG_RID 0 /* $0 = revision id */
79#define FPCREG_CSR 31 /* $31 = csr */
80
81/* Determine rounding mode from the RM bits of the FCSR */
82#define modeindex(v) ((v) & FPU_CSR_RM)
83
84/* Convert Mips rounding mode (0..3) to IEEE library modes. */
85static const unsigned char ieee_rm[4] = {
86 [FPU_CSR_RN] = IEEE754_RN,
87 [FPU_CSR_RZ] = IEEE754_RZ,
88 [FPU_CSR_RU] = IEEE754_RU,
89 [FPU_CSR_RD] = IEEE754_RD,
90};
91/* Convert IEEE library modes to Mips rounding mode (0..3). */
92static const unsigned char mips_rm[4] = {
93 [IEEE754_RN] = FPU_CSR_RN,
94 [IEEE754_RZ] = FPU_CSR_RZ,
95 [IEEE754_RD] = FPU_CSR_RD,
96 [IEEE754_RU] = FPU_CSR_RU,
97};
98
99#if __mips >= 4
100/* convert condition code register number to csr bit */
101static const unsigned int fpucondbit[8] = {
102 FPU_CSR_COND0,
103 FPU_CSR_COND1,
104 FPU_CSR_COND2,
105 FPU_CSR_COND3,
106 FPU_CSR_COND4,
107 FPU_CSR_COND5,
108 FPU_CSR_COND6,
109 FPU_CSR_COND7
110};
111#endif
112
113
114/*
115 * Redundant with logic already in kernel/branch.c,
116 * embedded in compute_return_epc. At some point,
117 * a single subroutine should be used across both
118 * modules.
119 */
120static int isBranchInstr(mips_instruction * i)
121{
122 switch (MIPSInst_OPCODE(*i)) {
123 case spec_op:
124 switch (MIPSInst_FUNC(*i)) {
125 case jalr_op:
126 case jr_op:
127 return 1;
128 }
129 break;
130
131 case bcond_op:
132 switch (MIPSInst_RT(*i)) {
133 case bltz_op:
134 case bgez_op:
135 case bltzl_op:
136 case bgezl_op:
137 case bltzal_op:
138 case bgezal_op:
139 case bltzall_op:
140 case bgezall_op:
141 return 1;
142 }
143 break;
144
145 case j_op:
146 case jal_op:
147 case jalx_op:
148 case beq_op:
149 case bne_op:
150 case blez_op:
151 case bgtz_op:
152 case beql_op:
153 case bnel_op:
154 case blezl_op:
155 case bgtzl_op:
156 return 1;
157
158 case cop0_op:
159 case cop1_op:
160 case cop2_op:
161 case cop1x_op:
162 if (MIPSInst_RS(*i) == bc_op)
163 return 1;
164 break;
165 }
166
167 return 0;
168}
169
170/*
171 * In the Linux kernel, we support selection of FPR format on the
172 * basis of the Status.FR bit. If an FPU is not present, the FR bit
173 * is hardwired to zero, which would imply a 32-bit FPU even for
174 * 64-bit CPUs. For 64-bit kernels with no FPU we use TIF_32BIT_REGS
175 * as a proxy for the FR bit so that a 64-bit FPU is emulated. In any
176 * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the
177 * even FPRs are used (Status.FR = 0).
178 */
179static inline int cop1_64bit(struct pt_regs *xcp)
180{
181 if (cpu_has_fpu)
182 return xcp->cp0_status & ST0_FR;
183#ifdef CONFIG_64BIT
184 return !test_thread_flag(TIF_32BIT_REGS);
185#else
186 return 0;
187#endif
188}
189
190#define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
191 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
192
193#define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
194 cop1_64bit(xcp) || !(x & 1) ? \
195 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
196 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
197
198#define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
199#define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
200
201#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
202#define SPTOREG(sp, x) SITOREG((sp).bits, x)
203#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
204#define DPTOREG(dp, x) DITOREG((dp).bits, x)
205
206/*
207 * Emulate the single floating point instruction pointed at by EPC.
208 * Two instructions if the instruction is in a branch delay slot.
209 */
210
211static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
212 void *__user *fault_addr)
213{
214 mips_instruction ir;
215 unsigned long emulpc, contpc;
216 unsigned int cond;
217
218 if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) {
219 MIPS_FPU_EMU_INC_STATS(errors);
220 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
221 return SIGBUS;
222 }
223 if (__get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
224 MIPS_FPU_EMU_INC_STATS(errors);
225 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
226 return SIGSEGV;
227 }
228
229 /* XXX NEC Vr54xx bug workaround */
230 if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
231 xcp->cp0_cause &= ~CAUSEF_BD;
232
233 if (xcp->cp0_cause & CAUSEF_BD) {
234 /*
235 * The instruction to be emulated is in a branch delay slot
236 * which means that we have to emulate the branch instruction
237 * BEFORE we do the cop1 instruction.
238 *
239 * This branch could be a COP1 branch, but in that case we
240 * would have had a trap for that instruction, and would not
241 * come through this route.
242 *
243 * Linux MIPS branch emulator operates on context, updating the
244 * cp0_epc.
245 */
246 emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */
247
248 if (__compute_return_epc(xcp)) {
249#ifdef CP1DBG
250 printk("failed to emulate branch at %p\n",
251 (void *) (xcp->cp0_epc));
252#endif
253 return SIGILL;
254 }
255 if (!access_ok(VERIFY_READ, emulpc, sizeof(mips_instruction))) {
256 MIPS_FPU_EMU_INC_STATS(errors);
257 *fault_addr = (mips_instruction __user *)emulpc;
258 return SIGBUS;
259 }
260 if (__get_user(ir, (mips_instruction __user *) emulpc)) {
261 MIPS_FPU_EMU_INC_STATS(errors);
262 *fault_addr = (mips_instruction __user *)emulpc;
263 return SIGSEGV;
264 }
265 /* __compute_return_epc() will have updated cp0_epc */
266 contpc = xcp->cp0_epc;
267 /* In order not to confuse ptrace() et al, tweak context */
268 xcp->cp0_epc = emulpc - 4;
269 } else {
270 emulpc = xcp->cp0_epc;
271 contpc = xcp->cp0_epc + 4;
272 }
273
274 emul:
275 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
276 MIPS_FPU_EMU_INC_STATS(emulated);
277 switch (MIPSInst_OPCODE(ir)) {
278 case ldc1_op:{
279 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
280 MIPSInst_SIMM(ir));
281 u64 val;
282
283 MIPS_FPU_EMU_INC_STATS(loads);
284
285 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
286 MIPS_FPU_EMU_INC_STATS(errors);
287 *fault_addr = va;
288 return SIGBUS;
289 }
290 if (__get_user(val, va)) {
291 MIPS_FPU_EMU_INC_STATS(errors);
292 *fault_addr = va;
293 return SIGSEGV;
294 }
295 DITOREG(val, MIPSInst_RT(ir));
296 break;
297 }
298
299 case sdc1_op:{
300 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
301 MIPSInst_SIMM(ir));
302 u64 val;
303
304 MIPS_FPU_EMU_INC_STATS(stores);
305 DIFROMREG(val, MIPSInst_RT(ir));
306 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
307 MIPS_FPU_EMU_INC_STATS(errors);
308 *fault_addr = va;
309 return SIGBUS;
310 }
311 if (__put_user(val, va)) {
312 MIPS_FPU_EMU_INC_STATS(errors);
313 *fault_addr = va;
314 return SIGSEGV;
315 }
316 break;
317 }
318
319 case lwc1_op:{
320 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
321 MIPSInst_SIMM(ir));
322 u32 val;
323
324 MIPS_FPU_EMU_INC_STATS(loads);
325 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
326 MIPS_FPU_EMU_INC_STATS(errors);
327 *fault_addr = va;
328 return SIGBUS;
329 }
330 if (__get_user(val, va)) {
331 MIPS_FPU_EMU_INC_STATS(errors);
332 *fault_addr = va;
333 return SIGSEGV;
334 }
335 SITOREG(val, MIPSInst_RT(ir));
336 break;
337 }
338
339 case swc1_op:{
340 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
341 MIPSInst_SIMM(ir));
342 u32 val;
343
344 MIPS_FPU_EMU_INC_STATS(stores);
345 SIFROMREG(val, MIPSInst_RT(ir));
346 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
347 MIPS_FPU_EMU_INC_STATS(errors);
348 *fault_addr = va;
349 return SIGBUS;
350 }
351 if (__put_user(val, va)) {
352 MIPS_FPU_EMU_INC_STATS(errors);
353 *fault_addr = va;
354 return SIGSEGV;
355 }
356 break;
357 }
358
359 case cop1_op:
360 switch (MIPSInst_RS(ir)) {
361
362#if defined(__mips64)
363 case dmfc_op:
364 /* copregister fs -> gpr[rt] */
365 if (MIPSInst_RT(ir) != 0) {
366 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
367 MIPSInst_RD(ir));
368 }
369 break;
370
371 case dmtc_op:
372 /* copregister fs <- rt */
373 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
374 break;
375#endif
376
377 case mfc_op:
378 /* copregister rd -> gpr[rt] */
379 if (MIPSInst_RT(ir) != 0) {
380 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
381 MIPSInst_RD(ir));
382 }
383 break;
384
385 case mtc_op:
386 /* copregister rd <- rt */
387 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
388 break;
389
390 case cfc_op:{
391 /* cop control register rd -> gpr[rt] */
392 u32 value;
393
394 if (MIPSInst_RD(ir) == FPCREG_CSR) {
395 value = ctx->fcr31;
396 value = (value & ~FPU_CSR_RM) |
397 mips_rm[modeindex(value)];
398#ifdef CSRTRACE
399 printk("%p gpr[%d]<-csr=%08x\n",
400 (void *) (xcp->cp0_epc),
401 MIPSInst_RT(ir), value);
402#endif
403 }
404 else if (MIPSInst_RD(ir) == FPCREG_RID)
405 value = 0;
406 else
407 value = 0;
408 if (MIPSInst_RT(ir))
409 xcp->regs[MIPSInst_RT(ir)] = value;
410 break;
411 }
412
413 case ctc_op:{
414 /* copregister rd <- rt */
415 u32 value;
416
417 if (MIPSInst_RT(ir) == 0)
418 value = 0;
419 else
420 value = xcp->regs[MIPSInst_RT(ir)];
421
422 /* we only have one writable control reg
423 */
424 if (MIPSInst_RD(ir) == FPCREG_CSR) {
425#ifdef CSRTRACE
426 printk("%p gpr[%d]->csr=%08x\n",
427 (void *) (xcp->cp0_epc),
428 MIPSInst_RT(ir), value);
429#endif
430
431 /*
432 * Don't write reserved bits,
433 * and convert to ieee library modes
434 */
435 ctx->fcr31 = (value &
436 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
437 ieee_rm[modeindex(value)];
438 }
439 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
440 return SIGFPE;
441 }
442 break;
443 }
444
445 case bc_op:{
446 int likely = 0;
447
448 if (xcp->cp0_cause & CAUSEF_BD)
449 return SIGILL;
450
451#if __mips >= 4
452 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
453#else
454 cond = ctx->fcr31 & FPU_CSR_COND;
455#endif
456 switch (MIPSInst_RT(ir) & 3) {
457 case bcfl_op:
458 likely = 1;
459 case bcf_op:
460 cond = !cond;
461 break;
462 case bctl_op:
463 likely = 1;
464 case bct_op:
465 break;
466 default:
467 /* thats an illegal instruction */
468 return SIGILL;
469 }
470
471 xcp->cp0_cause |= CAUSEF_BD;
472 if (cond) {
473 /* branch taken: emulate dslot
474 * instruction
475 */
476 xcp->cp0_epc += 4;
477 contpc = (xcp->cp0_epc +
478 (MIPSInst_SIMM(ir) << 2));
479
480 if (!access_ok(VERIFY_READ, xcp->cp0_epc,
481 sizeof(mips_instruction))) {
482 MIPS_FPU_EMU_INC_STATS(errors);
483 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
484 return SIGBUS;
485 }
486 if (__get_user(ir,
487 (mips_instruction __user *) xcp->cp0_epc)) {
488 MIPS_FPU_EMU_INC_STATS(errors);
489 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
490 return SIGSEGV;
491 }
492
493 switch (MIPSInst_OPCODE(ir)) {
494 case lwc1_op:
495 case swc1_op:
496#if (__mips >= 2 || defined(__mips64))
497 case ldc1_op:
498 case sdc1_op:
499#endif
500 case cop1_op:
501#if __mips >= 4 && __mips != 32
502 case cop1x_op:
503#endif
504 /* its one of ours */
505 goto emul;
506#if __mips >= 4
507 case spec_op:
508 if (MIPSInst_FUNC(ir) == movc_op)
509 goto emul;
510 break;
511#endif
512 }
513
514 /*
515 * Single step the non-cp1
516 * instruction in the dslot
517 */
518 return mips_dsemul(xcp, ir, contpc);
519 }
520 else {
521 /* branch not taken */
522 if (likely) {
523 /*
524 * branch likely nullifies
525 * dslot if not taken
526 */
527 xcp->cp0_epc += 4;
528 contpc += 4;
529 /*
530 * else continue & execute
531 * dslot as normal insn
532 */
533 }
534 }
535 break;
536 }
537
538 default:
539 if (!(MIPSInst_RS(ir) & 0x10))
540 return SIGILL;
541 {
542 int sig;
543
544 /* a real fpu computation instruction */
545 if ((sig = fpu_emu(xcp, ctx, ir)))
546 return sig;
547 }
548 }
549 break;
550
551#if __mips >= 4 && __mips != 32
552 case cop1x_op:{
553 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
554 if (sig)
555 return sig;
556 break;
557 }
558#endif
559
560#if __mips >= 4
561 case spec_op:
562 if (MIPSInst_FUNC(ir) != movc_op)
563 return SIGILL;
564 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
565 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
566 xcp->regs[MIPSInst_RD(ir)] =
567 xcp->regs[MIPSInst_RS(ir)];
568 break;
569#endif
570
571 default:
572 return SIGILL;
573 }
574
575 /* we did it !! */
576 xcp->cp0_epc = contpc;
577 xcp->cp0_cause &= ~CAUSEF_BD;
578
579 return 0;
580}
581
582/*
583 * Conversion table from MIPS compare ops 48-63
584 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
585 */
586static const unsigned char cmptab[8] = {
587 0, /* cmp_0 (sig) cmp_sf */
588 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
589 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
590 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
591 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
592 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
593 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
594 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
595};
596
597
598#if __mips >= 4 && __mips != 32
599
600/*
601 * Additional MIPS4 instructions
602 */
603
604#define DEF3OP(name, p, f1, f2, f3) \
605static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
606 ieee754##p t) \
607{ \
608 struct _ieee754_csr ieee754_csr_save; \
609 s = f1(s, t); \
610 ieee754_csr_save = ieee754_csr; \
611 s = f2(s, r); \
612 ieee754_csr_save.cx |= ieee754_csr.cx; \
613 ieee754_csr_save.sx |= ieee754_csr.sx; \
614 s = f3(s); \
615 ieee754_csr.cx |= ieee754_csr_save.cx; \
616 ieee754_csr.sx |= ieee754_csr_save.sx; \
617 return s; \
618}
619
620static ieee754dp fpemu_dp_recip(ieee754dp d)
621{
622 return ieee754dp_div(ieee754dp_one(0), d);
623}
624
625static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
626{
627 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
628}
629
630static ieee754sp fpemu_sp_recip(ieee754sp s)
631{
632 return ieee754sp_div(ieee754sp_one(0), s);
633}
634
635static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
636{
637 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
638}
639
640DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
641DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
642DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
643DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
644DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
645DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
646DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
647DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
648
649static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
650 mips_instruction ir, void *__user *fault_addr)
651{
652 unsigned rcsr = 0; /* resulting csr */
653
654 MIPS_FPU_EMU_INC_STATS(cp1xops);
655
656 switch (MIPSInst_FMA_FFMT(ir)) {
657 case s_fmt:{ /* 0 */
658
659 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
660 ieee754sp fd, fr, fs, ft;
661 u32 __user *va;
662 u32 val;
663
664 switch (MIPSInst_FUNC(ir)) {
665 case lwxc1_op:
666 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
667 xcp->regs[MIPSInst_FT(ir)]);
668
669 MIPS_FPU_EMU_INC_STATS(loads);
670 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
671 MIPS_FPU_EMU_INC_STATS(errors);
672 *fault_addr = va;
673 return SIGBUS;
674 }
675 if (__get_user(val, va)) {
676 MIPS_FPU_EMU_INC_STATS(errors);
677 *fault_addr = va;
678 return SIGSEGV;
679 }
680 SITOREG(val, MIPSInst_FD(ir));
681 break;
682
683 case swxc1_op:
684 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
685 xcp->regs[MIPSInst_FT(ir)]);
686
687 MIPS_FPU_EMU_INC_STATS(stores);
688
689 SIFROMREG(val, MIPSInst_FS(ir));
690 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
691 MIPS_FPU_EMU_INC_STATS(errors);
692 *fault_addr = va;
693 return SIGBUS;
694 }
695 if (put_user(val, va)) {
696 MIPS_FPU_EMU_INC_STATS(errors);
697 *fault_addr = va;
698 return SIGSEGV;
699 }
700 break;
701
702 case madd_s_op:
703 handler = fpemu_sp_madd;
704 goto scoptop;
705 case msub_s_op:
706 handler = fpemu_sp_msub;
707 goto scoptop;
708 case nmadd_s_op:
709 handler = fpemu_sp_nmadd;
710 goto scoptop;
711 case nmsub_s_op:
712 handler = fpemu_sp_nmsub;
713 goto scoptop;
714
715 scoptop:
716 SPFROMREG(fr, MIPSInst_FR(ir));
717 SPFROMREG(fs, MIPSInst_FS(ir));
718 SPFROMREG(ft, MIPSInst_FT(ir));
719 fd = (*handler) (fr, fs, ft);
720 SPTOREG(fd, MIPSInst_FD(ir));
721
722 copcsr:
723 if (ieee754_cxtest(IEEE754_INEXACT))
724 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
725 if (ieee754_cxtest(IEEE754_UNDERFLOW))
726 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
727 if (ieee754_cxtest(IEEE754_OVERFLOW))
728 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
729 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
730 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
731
732 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
733 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
734 /*printk ("SIGFPE: fpu csr = %08x\n",
735 ctx->fcr31); */
736 return SIGFPE;
737 }
738
739 break;
740
741 default:
742 return SIGILL;
743 }
744 break;
745 }
746
747 case d_fmt:{ /* 1 */
748 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
749 ieee754dp fd, fr, fs, ft;
750 u64 __user *va;
751 u64 val;
752
753 switch (MIPSInst_FUNC(ir)) {
754 case ldxc1_op:
755 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
756 xcp->regs[MIPSInst_FT(ir)]);
757
758 MIPS_FPU_EMU_INC_STATS(loads);
759 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
760 MIPS_FPU_EMU_INC_STATS(errors);
761 *fault_addr = va;
762 return SIGBUS;
763 }
764 if (__get_user(val, va)) {
765 MIPS_FPU_EMU_INC_STATS(errors);
766 *fault_addr = va;
767 return SIGSEGV;
768 }
769 DITOREG(val, MIPSInst_FD(ir));
770 break;
771
772 case sdxc1_op:
773 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
774 xcp->regs[MIPSInst_FT(ir)]);
775
776 MIPS_FPU_EMU_INC_STATS(stores);
777 DIFROMREG(val, MIPSInst_FS(ir));
778 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
779 MIPS_FPU_EMU_INC_STATS(errors);
780 *fault_addr = va;
781 return SIGBUS;
782 }
783 if (__put_user(val, va)) {
784 MIPS_FPU_EMU_INC_STATS(errors);
785 *fault_addr = va;
786 return SIGSEGV;
787 }
788 break;
789
790 case madd_d_op:
791 handler = fpemu_dp_madd;
792 goto dcoptop;
793 case msub_d_op:
794 handler = fpemu_dp_msub;
795 goto dcoptop;
796 case nmadd_d_op:
797 handler = fpemu_dp_nmadd;
798 goto dcoptop;
799 case nmsub_d_op:
800 handler = fpemu_dp_nmsub;
801 goto dcoptop;
802
803 dcoptop:
804 DPFROMREG(fr, MIPSInst_FR(ir));
805 DPFROMREG(fs, MIPSInst_FS(ir));
806 DPFROMREG(ft, MIPSInst_FT(ir));
807 fd = (*handler) (fr, fs, ft);
808 DPTOREG(fd, MIPSInst_FD(ir));
809 goto copcsr;
810
811 default:
812 return SIGILL;
813 }
814 break;
815 }
816
817 case 0x7: /* 7 */
818 if (MIPSInst_FUNC(ir) != pfetch_op) {
819 return SIGILL;
820 }
821 /* ignore prefx operation */
822 break;
823
824 default:
825 return SIGILL;
826 }
827
828 return 0;
829}
830#endif
831
832
833
834/*
835 * Emulate a single COP1 arithmetic instruction.
836 */
837static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
838 mips_instruction ir)
839{
840 int rfmt; /* resulting format */
841 unsigned rcsr = 0; /* resulting csr */
842 unsigned cond;
843 union {
844 ieee754dp d;
845 ieee754sp s;
846 int w;
847#ifdef __mips64
848 s64 l;
849#endif
850 } rv; /* resulting value */
851
852 MIPS_FPU_EMU_INC_STATS(cp1ops);
853 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
854 case s_fmt:{ /* 0 */
855 union {
856 ieee754sp(*b) (ieee754sp, ieee754sp);
857 ieee754sp(*u) (ieee754sp);
858 } handler;
859
860 switch (MIPSInst_FUNC(ir)) {
861 /* binary ops */
862 case fadd_op:
863 handler.b = ieee754sp_add;
864 goto scopbop;
865 case fsub_op:
866 handler.b = ieee754sp_sub;
867 goto scopbop;
868 case fmul_op:
869 handler.b = ieee754sp_mul;
870 goto scopbop;
871 case fdiv_op:
872 handler.b = ieee754sp_div;
873 goto scopbop;
874
875 /* unary ops */
876#if __mips >= 2 || defined(__mips64)
877 case fsqrt_op:
878 handler.u = ieee754sp_sqrt;
879 goto scopuop;
880#endif
881#if __mips >= 4 && __mips != 32
882 case frsqrt_op:
883 handler.u = fpemu_sp_rsqrt;
884 goto scopuop;
885 case frecip_op:
886 handler.u = fpemu_sp_recip;
887 goto scopuop;
888#endif
889#if __mips >= 4
890 case fmovc_op:
891 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
892 if (((ctx->fcr31 & cond) != 0) !=
893 ((MIPSInst_FT(ir) & 1) != 0))
894 return 0;
895 SPFROMREG(rv.s, MIPSInst_FS(ir));
896 break;
897 case fmovz_op:
898 if (xcp->regs[MIPSInst_FT(ir)] != 0)
899 return 0;
900 SPFROMREG(rv.s, MIPSInst_FS(ir));
901 break;
902 case fmovn_op:
903 if (xcp->regs[MIPSInst_FT(ir)] == 0)
904 return 0;
905 SPFROMREG(rv.s, MIPSInst_FS(ir));
906 break;
907#endif
908 case fabs_op:
909 handler.u = ieee754sp_abs;
910 goto scopuop;
911 case fneg_op:
912 handler.u = ieee754sp_neg;
913 goto scopuop;
914 case fmov_op:
915 /* an easy one */
916 SPFROMREG(rv.s, MIPSInst_FS(ir));
917 goto copcsr;
918
919 /* binary op on handler */
920 scopbop:
921 {
922 ieee754sp fs, ft;
923
924 SPFROMREG(fs, MIPSInst_FS(ir));
925 SPFROMREG(ft, MIPSInst_FT(ir));
926
927 rv.s = (*handler.b) (fs, ft);
928 goto copcsr;
929 }
930 scopuop:
931 {
932 ieee754sp fs;
933
934 SPFROMREG(fs, MIPSInst_FS(ir));
935 rv.s = (*handler.u) (fs);
936 goto copcsr;
937 }
938 copcsr:
939 if (ieee754_cxtest(IEEE754_INEXACT))
940 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
941 if (ieee754_cxtest(IEEE754_UNDERFLOW))
942 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
943 if (ieee754_cxtest(IEEE754_OVERFLOW))
944 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
945 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
946 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
947 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
948 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
949 break;
950
951 /* unary conv ops */
952 case fcvts_op:
953 return SIGILL; /* not defined */
954 case fcvtd_op:{
955 ieee754sp fs;
956
957 SPFROMREG(fs, MIPSInst_FS(ir));
958 rv.d = ieee754dp_fsp(fs);
959 rfmt = d_fmt;
960 goto copcsr;
961 }
962 case fcvtw_op:{
963 ieee754sp fs;
964
965 SPFROMREG(fs, MIPSInst_FS(ir));
966 rv.w = ieee754sp_tint(fs);
967 rfmt = w_fmt;
968 goto copcsr;
969 }
970
971#if __mips >= 2 || defined(__mips64)
972 case fround_op:
973 case ftrunc_op:
974 case fceil_op:
975 case ffloor_op:{
976 unsigned int oldrm = ieee754_csr.rm;
977 ieee754sp fs;
978
979 SPFROMREG(fs, MIPSInst_FS(ir));
980 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
981 rv.w = ieee754sp_tint(fs);
982 ieee754_csr.rm = oldrm;
983 rfmt = w_fmt;
984 goto copcsr;
985 }
986#endif /* __mips >= 2 */
987
988#if defined(__mips64)
989 case fcvtl_op:{
990 ieee754sp fs;
991
992 SPFROMREG(fs, MIPSInst_FS(ir));
993 rv.l = ieee754sp_tlong(fs);
994 rfmt = l_fmt;
995 goto copcsr;
996 }
997
998 case froundl_op:
999 case ftruncl_op:
1000 case fceill_op:
1001 case ffloorl_op:{
1002 unsigned int oldrm = ieee754_csr.rm;
1003 ieee754sp fs;
1004
1005 SPFROMREG(fs, MIPSInst_FS(ir));
1006 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1007 rv.l = ieee754sp_tlong(fs);
1008 ieee754_csr.rm = oldrm;
1009 rfmt = l_fmt;
1010 goto copcsr;
1011 }
1012#endif /* defined(__mips64) */
1013
1014 default:
1015 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1016 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1017 ieee754sp fs, ft;
1018
1019 SPFROMREG(fs, MIPSInst_FS(ir));
1020 SPFROMREG(ft, MIPSInst_FT(ir));
1021 rv.w = ieee754sp_cmp(fs, ft,
1022 cmptab[cmpop & 0x7], cmpop & 0x8);
1023 rfmt = -1;
1024 if ((cmpop & 0x8) && ieee754_cxtest
1025 (IEEE754_INVALID_OPERATION))
1026 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1027 else
1028 goto copcsr;
1029
1030 }
1031 else {
1032 return SIGILL;
1033 }
1034 break;
1035 }
1036 break;
1037 }
1038
1039 case d_fmt:{
1040 union {
1041 ieee754dp(*b) (ieee754dp, ieee754dp);
1042 ieee754dp(*u) (ieee754dp);
1043 } handler;
1044
1045 switch (MIPSInst_FUNC(ir)) {
1046 /* binary ops */
1047 case fadd_op:
1048 handler.b = ieee754dp_add;
1049 goto dcopbop;
1050 case fsub_op:
1051 handler.b = ieee754dp_sub;
1052 goto dcopbop;
1053 case fmul_op:
1054 handler.b = ieee754dp_mul;
1055 goto dcopbop;
1056 case fdiv_op:
1057 handler.b = ieee754dp_div;
1058 goto dcopbop;
1059
1060 /* unary ops */
1061#if __mips >= 2 || defined(__mips64)
1062 case fsqrt_op:
1063 handler.u = ieee754dp_sqrt;
1064 goto dcopuop;
1065#endif
1066#if __mips >= 4 && __mips != 32
1067 case frsqrt_op:
1068 handler.u = fpemu_dp_rsqrt;
1069 goto dcopuop;
1070 case frecip_op:
1071 handler.u = fpemu_dp_recip;
1072 goto dcopuop;
1073#endif
1074#if __mips >= 4
1075 case fmovc_op:
1076 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1077 if (((ctx->fcr31 & cond) != 0) !=
1078 ((MIPSInst_FT(ir) & 1) != 0))
1079 return 0;
1080 DPFROMREG(rv.d, MIPSInst_FS(ir));
1081 break;
1082 case fmovz_op:
1083 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1084 return 0;
1085 DPFROMREG(rv.d, MIPSInst_FS(ir));
1086 break;
1087 case fmovn_op:
1088 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1089 return 0;
1090 DPFROMREG(rv.d, MIPSInst_FS(ir));
1091 break;
1092#endif
1093 case fabs_op:
1094 handler.u = ieee754dp_abs;
1095 goto dcopuop;
1096
1097 case fneg_op:
1098 handler.u = ieee754dp_neg;
1099 goto dcopuop;
1100
1101 case fmov_op:
1102 /* an easy one */
1103 DPFROMREG(rv.d, MIPSInst_FS(ir));
1104 goto copcsr;
1105
1106 /* binary op on handler */
1107 dcopbop:{
1108 ieee754dp fs, ft;
1109
1110 DPFROMREG(fs, MIPSInst_FS(ir));
1111 DPFROMREG(ft, MIPSInst_FT(ir));
1112
1113 rv.d = (*handler.b) (fs, ft);
1114 goto copcsr;
1115 }
1116 dcopuop:{
1117 ieee754dp fs;
1118
1119 DPFROMREG(fs, MIPSInst_FS(ir));
1120 rv.d = (*handler.u) (fs);
1121 goto copcsr;
1122 }
1123
1124 /* unary conv ops */
1125 case fcvts_op:{
1126 ieee754dp fs;
1127
1128 DPFROMREG(fs, MIPSInst_FS(ir));
1129 rv.s = ieee754sp_fdp(fs);
1130 rfmt = s_fmt;
1131 goto copcsr;
1132 }
1133 case fcvtd_op:
1134 return SIGILL; /* not defined */
1135
1136 case fcvtw_op:{
1137 ieee754dp fs;
1138
1139 DPFROMREG(fs, MIPSInst_FS(ir));
1140 rv.w = ieee754dp_tint(fs); /* wrong */
1141 rfmt = w_fmt;
1142 goto copcsr;
1143 }
1144
1145#if __mips >= 2 || defined(__mips64)
1146 case fround_op:
1147 case ftrunc_op:
1148 case fceil_op:
1149 case ffloor_op:{
1150 unsigned int oldrm = ieee754_csr.rm;
1151 ieee754dp fs;
1152
1153 DPFROMREG(fs, MIPSInst_FS(ir));
1154 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1155 rv.w = ieee754dp_tint(fs);
1156 ieee754_csr.rm = oldrm;
1157 rfmt = w_fmt;
1158 goto copcsr;
1159 }
1160#endif
1161
1162#if defined(__mips64)
1163 case fcvtl_op:{
1164 ieee754dp fs;
1165
1166 DPFROMREG(fs, MIPSInst_FS(ir));
1167 rv.l = ieee754dp_tlong(fs);
1168 rfmt = l_fmt;
1169 goto copcsr;
1170 }
1171
1172 case froundl_op:
1173 case ftruncl_op:
1174 case fceill_op:
1175 case ffloorl_op:{
1176 unsigned int oldrm = ieee754_csr.rm;
1177 ieee754dp fs;
1178
1179 DPFROMREG(fs, MIPSInst_FS(ir));
1180 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1181 rv.l = ieee754dp_tlong(fs);
1182 ieee754_csr.rm = oldrm;
1183 rfmt = l_fmt;
1184 goto copcsr;
1185 }
1186#endif /* __mips >= 3 */
1187
1188 default:
1189 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1190 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1191 ieee754dp fs, ft;
1192
1193 DPFROMREG(fs, MIPSInst_FS(ir));
1194 DPFROMREG(ft, MIPSInst_FT(ir));
1195 rv.w = ieee754dp_cmp(fs, ft,
1196 cmptab[cmpop & 0x7], cmpop & 0x8);
1197 rfmt = -1;
1198 if ((cmpop & 0x8)
1199 &&
1200 ieee754_cxtest
1201 (IEEE754_INVALID_OPERATION))
1202 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1203 else
1204 goto copcsr;
1205
1206 }
1207 else {
1208 return SIGILL;
1209 }
1210 break;
1211 }
1212 break;
1213 }
1214
1215 case w_fmt:{
1216 ieee754sp fs;
1217
1218 switch (MIPSInst_FUNC(ir)) {
1219 case fcvts_op:
1220 /* convert word to single precision real */
1221 SPFROMREG(fs, MIPSInst_FS(ir));
1222 rv.s = ieee754sp_fint(fs.bits);
1223 rfmt = s_fmt;
1224 goto copcsr;
1225 case fcvtd_op:
1226 /* convert word to double precision real */
1227 SPFROMREG(fs, MIPSInst_FS(ir));
1228 rv.d = ieee754dp_fint(fs.bits);
1229 rfmt = d_fmt;
1230 goto copcsr;
1231 default:
1232 return SIGILL;
1233 }
1234 break;
1235 }
1236
1237#if defined(__mips64)
1238 case l_fmt:{
1239 switch (MIPSInst_FUNC(ir)) {
1240 case fcvts_op:
1241 /* convert long to single precision real */
1242 rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1243 rfmt = s_fmt;
1244 goto copcsr;
1245 case fcvtd_op:
1246 /* convert long to double precision real */
1247 rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1248 rfmt = d_fmt;
1249 goto copcsr;
1250 default:
1251 return SIGILL;
1252 }
1253 break;
1254 }
1255#endif
1256
1257 default:
1258 return SIGILL;
1259 }
1260
1261 /*
1262 * Update the fpu CSR register for this operation.
1263 * If an exception is required, generate a tidy SIGFPE exception,
1264 * without updating the result register.
1265 * Note: cause exception bits do not accumulate, they are rewritten
1266 * for each op; only the flag/sticky bits accumulate.
1267 */
1268 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1269 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1270 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1271 return SIGFPE;
1272 }
1273
1274 /*
1275 * Now we can safely write the result back to the register file.
1276 */
1277 switch (rfmt) {
1278 case -1:{
1279#if __mips >= 4
1280 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1281#else
1282 cond = FPU_CSR_COND;
1283#endif
1284 if (rv.w)
1285 ctx->fcr31 |= cond;
1286 else
1287 ctx->fcr31 &= ~cond;
1288 break;
1289 }
1290 case d_fmt:
1291 DPTOREG(rv.d, MIPSInst_FD(ir));
1292 break;
1293 case s_fmt:
1294 SPTOREG(rv.s, MIPSInst_FD(ir));
1295 break;
1296 case w_fmt:
1297 SITOREG(rv.w, MIPSInst_FD(ir));
1298 break;
1299#if defined(__mips64)
1300 case l_fmt:
1301 DITOREG(rv.l, MIPSInst_FD(ir));
1302 break;
1303#endif
1304 default:
1305 return SIGILL;
1306 }
1307
1308 return 0;
1309}
1310
1311int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1312 int has_fpu, void *__user *fault_addr)
1313{
1314 unsigned long oldepc, prevepc;
1315 mips_instruction insn;
1316 int sig = 0;
1317
1318 oldepc = xcp->cp0_epc;
1319 do {
1320 prevepc = xcp->cp0_epc;
1321
1322 if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) {
1323 MIPS_FPU_EMU_INC_STATS(errors);
1324 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
1325 return SIGBUS;
1326 }
1327 if (__get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1328 MIPS_FPU_EMU_INC_STATS(errors);
1329 *fault_addr = (mips_instruction __user *)xcp->cp0_epc;
1330 return SIGSEGV;
1331 }
1332 if (insn == 0)
1333 xcp->cp0_epc += 4; /* skip nops */
1334 else {
1335 /*
1336 * The 'ieee754_csr' is an alias of
1337 * ctx->fcr31. No need to copy ctx->fcr31 to
1338 * ieee754_csr. But ieee754_csr.rm is ieee
1339 * library modes. (not mips rounding mode)
1340 */
1341 /* convert to ieee library modes */
1342 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
1343 sig = cop1Emulate(xcp, ctx, fault_addr);
1344 /* revert to mips rounding mode */
1345 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1346 }
1347
1348 if (has_fpu)
1349 break;
1350 if (sig)
1351 break;
1352
1353 cond_resched();
1354 } while (xcp->cp0_epc > prevepc);
1355
1356 /* SIGILL indicates a non-fpu instruction */
1357 if (sig == SIGILL && xcp->cp0_epc != oldepc)
1358 /* but if epc has advanced, then ignore it */
1359 sig = 0;
1360
1361 return sig;
1362}
1363
1364#ifdef CONFIG_DEBUG_FS
1365
1366static int fpuemu_stat_get(void *data, u64 *val)
1367{
1368 int cpu;
1369 unsigned long sum = 0;
1370 for_each_online_cpu(cpu) {
1371 struct mips_fpu_emulator_stats *ps;
1372 local_t *pv;
1373 ps = &per_cpu(fpuemustats, cpu);
1374 pv = (void *)ps + (unsigned long)data;
1375 sum += local_read(pv);
1376 }
1377 *val = sum;
1378 return 0;
1379}
1380DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
1381
1382extern struct dentry *mips_debugfs_dir;
1383static int __init debugfs_fpuemu(void)
1384{
1385 struct dentry *d, *dir;
1386
1387 if (!mips_debugfs_dir)
1388 return -ENODEV;
1389 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
1390 if (!dir)
1391 return -ENOMEM;
1392
1393#define FPU_STAT_CREATE(M) \
1394 do { \
1395 d = debugfs_create_file(#M , S_IRUGO, dir, \
1396 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
1397 &fops_fpuemu_stat); \
1398 if (!d) \
1399 return -ENOMEM; \
1400 } while (0)
1401
1402 FPU_STAT_CREATE(emulated);
1403 FPU_STAT_CREATE(loads);
1404 FPU_STAT_CREATE(stores);
1405 FPU_STAT_CREATE(cp1ops);
1406 FPU_STAT_CREATE(cp1xops);
1407 FPU_STAT_CREATE(errors);
1408
1409 return 0;
1410}
1411__initcall(debugfs_fpuemu);
1412#endif
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36#include <linux/sched.h>
37#include <linux/module.h>
38#include <linux/debugfs.h>
39#include <linux/perf_event.h>
40
41#include <asm/inst.h>
42#include <asm/bootinfo.h>
43#include <asm/processor.h>
44#include <asm/ptrace.h>
45#include <asm/signal.h>
46#include <asm/mipsregs.h>
47#include <asm/fpu_emulator.h>
48#include <asm/fpu.h>
49#include <asm/uaccess.h>
50#include <asm/branch.h>
51
52#include "ieee754.h"
53
54/* Strap kernel emulator for full MIPS IV emulation */
55
56#ifdef __mips
57#undef __mips
58#endif
59#define __mips 4
60
61/* Function which emulates a floating point instruction. */
62
63static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
64 mips_instruction);
65
66#if __mips >= 4 && __mips != 32
67static int fpux_emu(struct pt_regs *,
68 struct mips_fpu_struct *, mips_instruction, void *__user *);
69#endif
70
71/* Further private data for which no space exists in mips_fpu_struct */
72
73#ifdef CONFIG_DEBUG_FS
74DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
75#endif
76
77/* Control registers */
78
79#define FPCREG_RID 0 /* $0 = revision id */
80#define FPCREG_CSR 31 /* $31 = csr */
81
82/* Determine rounding mode from the RM bits of the FCSR */
83#define modeindex(v) ((v) & FPU_CSR_RM)
84
85/* microMIPS bitfields */
86#define MM_POOL32A_MINOR_MASK 0x3f
87#define MM_POOL32A_MINOR_SHIFT 0x6
88#define MM_MIPS32_COND_FC 0x30
89
90/* Convert Mips rounding mode (0..3) to IEEE library modes. */
91static const unsigned char ieee_rm[4] = {
92 [FPU_CSR_RN] = IEEE754_RN,
93 [FPU_CSR_RZ] = IEEE754_RZ,
94 [FPU_CSR_RU] = IEEE754_RU,
95 [FPU_CSR_RD] = IEEE754_RD,
96};
97/* Convert IEEE library modes to Mips rounding mode (0..3). */
98static const unsigned char mips_rm[4] = {
99 [IEEE754_RN] = FPU_CSR_RN,
100 [IEEE754_RZ] = FPU_CSR_RZ,
101 [IEEE754_RD] = FPU_CSR_RD,
102 [IEEE754_RU] = FPU_CSR_RU,
103};
104
105#if __mips >= 4
106/* convert condition code register number to csr bit */
107static const unsigned int fpucondbit[8] = {
108 FPU_CSR_COND0,
109 FPU_CSR_COND1,
110 FPU_CSR_COND2,
111 FPU_CSR_COND3,
112 FPU_CSR_COND4,
113 FPU_CSR_COND5,
114 FPU_CSR_COND6,
115 FPU_CSR_COND7
116};
117#endif
118
119/* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
120static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
121
122/* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
123static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
124static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
125static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
126static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
127
128/*
129 * This functions translates a 32-bit microMIPS instruction
130 * into a 32-bit MIPS32 instruction. Returns 0 on success
131 * and SIGILL otherwise.
132 */
133static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
134{
135 union mips_instruction insn = *insn_ptr;
136 union mips_instruction mips32_insn = insn;
137 int func, fmt, op;
138
139 switch (insn.mm_i_format.opcode) {
140 case mm_ldc132_op:
141 mips32_insn.mm_i_format.opcode = ldc1_op;
142 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
143 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
144 break;
145 case mm_lwc132_op:
146 mips32_insn.mm_i_format.opcode = lwc1_op;
147 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
148 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
149 break;
150 case mm_sdc132_op:
151 mips32_insn.mm_i_format.opcode = sdc1_op;
152 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
153 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
154 break;
155 case mm_swc132_op:
156 mips32_insn.mm_i_format.opcode = swc1_op;
157 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
158 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
159 break;
160 case mm_pool32i_op:
161 /* NOTE: offset is << by 1 if in microMIPS mode. */
162 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
163 (insn.mm_i_format.rt == mm_bc1t_op)) {
164 mips32_insn.fb_format.opcode = cop1_op;
165 mips32_insn.fb_format.bc = bc_op;
166 mips32_insn.fb_format.flag =
167 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
168 } else
169 return SIGILL;
170 break;
171 case mm_pool32f_op:
172 switch (insn.mm_fp0_format.func) {
173 case mm_32f_01_op:
174 case mm_32f_11_op:
175 case mm_32f_02_op:
176 case mm_32f_12_op:
177 case mm_32f_41_op:
178 case mm_32f_51_op:
179 case mm_32f_42_op:
180 case mm_32f_52_op:
181 op = insn.mm_fp0_format.func;
182 if (op == mm_32f_01_op)
183 func = madd_s_op;
184 else if (op == mm_32f_11_op)
185 func = madd_d_op;
186 else if (op == mm_32f_02_op)
187 func = nmadd_s_op;
188 else if (op == mm_32f_12_op)
189 func = nmadd_d_op;
190 else if (op == mm_32f_41_op)
191 func = msub_s_op;
192 else if (op == mm_32f_51_op)
193 func = msub_d_op;
194 else if (op == mm_32f_42_op)
195 func = nmsub_s_op;
196 else
197 func = nmsub_d_op;
198 mips32_insn.fp6_format.opcode = cop1x_op;
199 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
200 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
201 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
202 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
203 mips32_insn.fp6_format.func = func;
204 break;
205 case mm_32f_10_op:
206 func = -1; /* Invalid */
207 op = insn.mm_fp5_format.op & 0x7;
208 if (op == mm_ldxc1_op)
209 func = ldxc1_op;
210 else if (op == mm_sdxc1_op)
211 func = sdxc1_op;
212 else if (op == mm_lwxc1_op)
213 func = lwxc1_op;
214 else if (op == mm_swxc1_op)
215 func = swxc1_op;
216
217 if (func != -1) {
218 mips32_insn.r_format.opcode = cop1x_op;
219 mips32_insn.r_format.rs =
220 insn.mm_fp5_format.base;
221 mips32_insn.r_format.rt =
222 insn.mm_fp5_format.index;
223 mips32_insn.r_format.rd = 0;
224 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
225 mips32_insn.r_format.func = func;
226 } else
227 return SIGILL;
228 break;
229 case mm_32f_40_op:
230 op = -1; /* Invalid */
231 if (insn.mm_fp2_format.op == mm_fmovt_op)
232 op = 1;
233 else if (insn.mm_fp2_format.op == mm_fmovf_op)
234 op = 0;
235 if (op != -1) {
236 mips32_insn.fp0_format.opcode = cop1_op;
237 mips32_insn.fp0_format.fmt =
238 sdps_format[insn.mm_fp2_format.fmt];
239 mips32_insn.fp0_format.ft =
240 (insn.mm_fp2_format.cc<<2) + op;
241 mips32_insn.fp0_format.fs =
242 insn.mm_fp2_format.fs;
243 mips32_insn.fp0_format.fd =
244 insn.mm_fp2_format.fd;
245 mips32_insn.fp0_format.func = fmovc_op;
246 } else
247 return SIGILL;
248 break;
249 case mm_32f_60_op:
250 func = -1; /* Invalid */
251 if (insn.mm_fp0_format.op == mm_fadd_op)
252 func = fadd_op;
253 else if (insn.mm_fp0_format.op == mm_fsub_op)
254 func = fsub_op;
255 else if (insn.mm_fp0_format.op == mm_fmul_op)
256 func = fmul_op;
257 else if (insn.mm_fp0_format.op == mm_fdiv_op)
258 func = fdiv_op;
259 if (func != -1) {
260 mips32_insn.fp0_format.opcode = cop1_op;
261 mips32_insn.fp0_format.fmt =
262 sdps_format[insn.mm_fp0_format.fmt];
263 mips32_insn.fp0_format.ft =
264 insn.mm_fp0_format.ft;
265 mips32_insn.fp0_format.fs =
266 insn.mm_fp0_format.fs;
267 mips32_insn.fp0_format.fd =
268 insn.mm_fp0_format.fd;
269 mips32_insn.fp0_format.func = func;
270 } else
271 return SIGILL;
272 break;
273 case mm_32f_70_op:
274 func = -1; /* Invalid */
275 if (insn.mm_fp0_format.op == mm_fmovn_op)
276 func = fmovn_op;
277 else if (insn.mm_fp0_format.op == mm_fmovz_op)
278 func = fmovz_op;
279 if (func != -1) {
280 mips32_insn.fp0_format.opcode = cop1_op;
281 mips32_insn.fp0_format.fmt =
282 sdps_format[insn.mm_fp0_format.fmt];
283 mips32_insn.fp0_format.ft =
284 insn.mm_fp0_format.ft;
285 mips32_insn.fp0_format.fs =
286 insn.mm_fp0_format.fs;
287 mips32_insn.fp0_format.fd =
288 insn.mm_fp0_format.fd;
289 mips32_insn.fp0_format.func = func;
290 } else
291 return SIGILL;
292 break;
293 case mm_32f_73_op: /* POOL32FXF */
294 switch (insn.mm_fp1_format.op) {
295 case mm_movf0_op:
296 case mm_movf1_op:
297 case mm_movt0_op:
298 case mm_movt1_op:
299 if ((insn.mm_fp1_format.op & 0x7f) ==
300 mm_movf0_op)
301 op = 0;
302 else
303 op = 1;
304 mips32_insn.r_format.opcode = spec_op;
305 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
306 mips32_insn.r_format.rt =
307 (insn.mm_fp4_format.cc << 2) + op;
308 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
309 mips32_insn.r_format.re = 0;
310 mips32_insn.r_format.func = movc_op;
311 break;
312 case mm_fcvtd0_op:
313 case mm_fcvtd1_op:
314 case mm_fcvts0_op:
315 case mm_fcvts1_op:
316 if ((insn.mm_fp1_format.op & 0x7f) ==
317 mm_fcvtd0_op) {
318 func = fcvtd_op;
319 fmt = swl_format[insn.mm_fp3_format.fmt];
320 } else {
321 func = fcvts_op;
322 fmt = dwl_format[insn.mm_fp3_format.fmt];
323 }
324 mips32_insn.fp0_format.opcode = cop1_op;
325 mips32_insn.fp0_format.fmt = fmt;
326 mips32_insn.fp0_format.ft = 0;
327 mips32_insn.fp0_format.fs =
328 insn.mm_fp3_format.fs;
329 mips32_insn.fp0_format.fd =
330 insn.mm_fp3_format.rt;
331 mips32_insn.fp0_format.func = func;
332 break;
333 case mm_fmov0_op:
334 case mm_fmov1_op:
335 case mm_fabs0_op:
336 case mm_fabs1_op:
337 case mm_fneg0_op:
338 case mm_fneg1_op:
339 if ((insn.mm_fp1_format.op & 0x7f) ==
340 mm_fmov0_op)
341 func = fmov_op;
342 else if ((insn.mm_fp1_format.op & 0x7f) ==
343 mm_fabs0_op)
344 func = fabs_op;
345 else
346 func = fneg_op;
347 mips32_insn.fp0_format.opcode = cop1_op;
348 mips32_insn.fp0_format.fmt =
349 sdps_format[insn.mm_fp3_format.fmt];
350 mips32_insn.fp0_format.ft = 0;
351 mips32_insn.fp0_format.fs =
352 insn.mm_fp3_format.fs;
353 mips32_insn.fp0_format.fd =
354 insn.mm_fp3_format.rt;
355 mips32_insn.fp0_format.func = func;
356 break;
357 case mm_ffloorl_op:
358 case mm_ffloorw_op:
359 case mm_fceill_op:
360 case mm_fceilw_op:
361 case mm_ftruncl_op:
362 case mm_ftruncw_op:
363 case mm_froundl_op:
364 case mm_froundw_op:
365 case mm_fcvtl_op:
366 case mm_fcvtw_op:
367 if (insn.mm_fp1_format.op == mm_ffloorl_op)
368 func = ffloorl_op;
369 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
370 func = ffloor_op;
371 else if (insn.mm_fp1_format.op == mm_fceill_op)
372 func = fceill_op;
373 else if (insn.mm_fp1_format.op == mm_fceilw_op)
374 func = fceil_op;
375 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
376 func = ftruncl_op;
377 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
378 func = ftrunc_op;
379 else if (insn.mm_fp1_format.op == mm_froundl_op)
380 func = froundl_op;
381 else if (insn.mm_fp1_format.op == mm_froundw_op)
382 func = fround_op;
383 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
384 func = fcvtl_op;
385 else
386 func = fcvtw_op;
387 mips32_insn.fp0_format.opcode = cop1_op;
388 mips32_insn.fp0_format.fmt =
389 sd_format[insn.mm_fp1_format.fmt];
390 mips32_insn.fp0_format.ft = 0;
391 mips32_insn.fp0_format.fs =
392 insn.mm_fp1_format.fs;
393 mips32_insn.fp0_format.fd =
394 insn.mm_fp1_format.rt;
395 mips32_insn.fp0_format.func = func;
396 break;
397 case mm_frsqrt_op:
398 case mm_fsqrt_op:
399 case mm_frecip_op:
400 if (insn.mm_fp1_format.op == mm_frsqrt_op)
401 func = frsqrt_op;
402 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
403 func = fsqrt_op;
404 else
405 func = frecip_op;
406 mips32_insn.fp0_format.opcode = cop1_op;
407 mips32_insn.fp0_format.fmt =
408 sdps_format[insn.mm_fp1_format.fmt];
409 mips32_insn.fp0_format.ft = 0;
410 mips32_insn.fp0_format.fs =
411 insn.mm_fp1_format.fs;
412 mips32_insn.fp0_format.fd =
413 insn.mm_fp1_format.rt;
414 mips32_insn.fp0_format.func = func;
415 break;
416 case mm_mfc1_op:
417 case mm_mtc1_op:
418 case mm_cfc1_op:
419 case mm_ctc1_op:
420 case mm_mfhc1_op:
421 case mm_mthc1_op:
422 if (insn.mm_fp1_format.op == mm_mfc1_op)
423 op = mfc_op;
424 else if (insn.mm_fp1_format.op == mm_mtc1_op)
425 op = mtc_op;
426 else if (insn.mm_fp1_format.op == mm_cfc1_op)
427 op = cfc_op;
428 else if (insn.mm_fp1_format.op == mm_ctc1_op)
429 op = ctc_op;
430 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
431 op = mfhc_op;
432 else
433 op = mthc_op;
434 mips32_insn.fp1_format.opcode = cop1_op;
435 mips32_insn.fp1_format.op = op;
436 mips32_insn.fp1_format.rt =
437 insn.mm_fp1_format.rt;
438 mips32_insn.fp1_format.fs =
439 insn.mm_fp1_format.fs;
440 mips32_insn.fp1_format.fd = 0;
441 mips32_insn.fp1_format.func = 0;
442 break;
443 default:
444 return SIGILL;
445 }
446 break;
447 case mm_32f_74_op: /* c.cond.fmt */
448 mips32_insn.fp0_format.opcode = cop1_op;
449 mips32_insn.fp0_format.fmt =
450 sdps_format[insn.mm_fp4_format.fmt];
451 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
452 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
453 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
454 mips32_insn.fp0_format.func =
455 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
456 break;
457 default:
458 return SIGILL;
459 }
460 break;
461 default:
462 return SIGILL;
463 }
464
465 *insn_ptr = mips32_insn;
466 return 0;
467}
468
469int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
470 unsigned long *contpc)
471{
472 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
473 int bc_false = 0;
474 unsigned int fcr31;
475 unsigned int bit;
476
477 if (!cpu_has_mmips)
478 return 0;
479
480 switch (insn.mm_i_format.opcode) {
481 case mm_pool32a_op:
482 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
483 mm_pool32axf_op) {
484 switch (insn.mm_i_format.simmediate >>
485 MM_POOL32A_MINOR_SHIFT) {
486 case mm_jalr_op:
487 case mm_jalrhb_op:
488 case mm_jalrs_op:
489 case mm_jalrshb_op:
490 if (insn.mm_i_format.rt != 0) /* Not mm_jr */
491 regs->regs[insn.mm_i_format.rt] =
492 regs->cp0_epc +
493 dec_insn.pc_inc +
494 dec_insn.next_pc_inc;
495 *contpc = regs->regs[insn.mm_i_format.rs];
496 return 1;
497 }
498 }
499 break;
500 case mm_pool32i_op:
501 switch (insn.mm_i_format.rt) {
502 case mm_bltzals_op:
503 case mm_bltzal_op:
504 regs->regs[31] = regs->cp0_epc +
505 dec_insn.pc_inc +
506 dec_insn.next_pc_inc;
507 /* Fall through */
508 case mm_bltz_op:
509 if ((long)regs->regs[insn.mm_i_format.rs] < 0)
510 *contpc = regs->cp0_epc +
511 dec_insn.pc_inc +
512 (insn.mm_i_format.simmediate << 1);
513 else
514 *contpc = regs->cp0_epc +
515 dec_insn.pc_inc +
516 dec_insn.next_pc_inc;
517 return 1;
518 case mm_bgezals_op:
519 case mm_bgezal_op:
520 regs->regs[31] = regs->cp0_epc +
521 dec_insn.pc_inc +
522 dec_insn.next_pc_inc;
523 /* Fall through */
524 case mm_bgez_op:
525 if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
526 *contpc = regs->cp0_epc +
527 dec_insn.pc_inc +
528 (insn.mm_i_format.simmediate << 1);
529 else
530 *contpc = regs->cp0_epc +
531 dec_insn.pc_inc +
532 dec_insn.next_pc_inc;
533 return 1;
534 case mm_blez_op:
535 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
536 *contpc = regs->cp0_epc +
537 dec_insn.pc_inc +
538 (insn.mm_i_format.simmediate << 1);
539 else
540 *contpc = regs->cp0_epc +
541 dec_insn.pc_inc +
542 dec_insn.next_pc_inc;
543 return 1;
544 case mm_bgtz_op:
545 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
546 *contpc = regs->cp0_epc +
547 dec_insn.pc_inc +
548 (insn.mm_i_format.simmediate << 1);
549 else
550 *contpc = regs->cp0_epc +
551 dec_insn.pc_inc +
552 dec_insn.next_pc_inc;
553 return 1;
554 case mm_bc2f_op:
555 case mm_bc1f_op:
556 bc_false = 1;
557 /* Fall through */
558 case mm_bc2t_op:
559 case mm_bc1t_op:
560 preempt_disable();
561 if (is_fpu_owner())
562 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
563 else
564 fcr31 = current->thread.fpu.fcr31;
565 preempt_enable();
566
567 if (bc_false)
568 fcr31 = ~fcr31;
569
570 bit = (insn.mm_i_format.rs >> 2);
571 bit += (bit != 0);
572 bit += 23;
573 if (fcr31 & (1 << bit))
574 *contpc = regs->cp0_epc +
575 dec_insn.pc_inc +
576 (insn.mm_i_format.simmediate << 1);
577 else
578 *contpc = regs->cp0_epc +
579 dec_insn.pc_inc + dec_insn.next_pc_inc;
580 return 1;
581 }
582 break;
583 case mm_pool16c_op:
584 switch (insn.mm_i_format.rt) {
585 case mm_jalr16_op:
586 case mm_jalrs16_op:
587 regs->regs[31] = regs->cp0_epc +
588 dec_insn.pc_inc + dec_insn.next_pc_inc;
589 /* Fall through */
590 case mm_jr16_op:
591 *contpc = regs->regs[insn.mm_i_format.rs];
592 return 1;
593 }
594 break;
595 case mm_beqz16_op:
596 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
597 *contpc = regs->cp0_epc +
598 dec_insn.pc_inc +
599 (insn.mm_b1_format.simmediate << 1);
600 else
601 *contpc = regs->cp0_epc +
602 dec_insn.pc_inc + dec_insn.next_pc_inc;
603 return 1;
604 case mm_bnez16_op:
605 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
606 *contpc = regs->cp0_epc +
607 dec_insn.pc_inc +
608 (insn.mm_b1_format.simmediate << 1);
609 else
610 *contpc = regs->cp0_epc +
611 dec_insn.pc_inc + dec_insn.next_pc_inc;
612 return 1;
613 case mm_b16_op:
614 *contpc = regs->cp0_epc + dec_insn.pc_inc +
615 (insn.mm_b0_format.simmediate << 1);
616 return 1;
617 case mm_beq32_op:
618 if (regs->regs[insn.mm_i_format.rs] ==
619 regs->regs[insn.mm_i_format.rt])
620 *contpc = regs->cp0_epc +
621 dec_insn.pc_inc +
622 (insn.mm_i_format.simmediate << 1);
623 else
624 *contpc = regs->cp0_epc +
625 dec_insn.pc_inc +
626 dec_insn.next_pc_inc;
627 return 1;
628 case mm_bne32_op:
629 if (regs->regs[insn.mm_i_format.rs] !=
630 regs->regs[insn.mm_i_format.rt])
631 *contpc = regs->cp0_epc +
632 dec_insn.pc_inc +
633 (insn.mm_i_format.simmediate << 1);
634 else
635 *contpc = regs->cp0_epc +
636 dec_insn.pc_inc + dec_insn.next_pc_inc;
637 return 1;
638 case mm_jalx32_op:
639 regs->regs[31] = regs->cp0_epc +
640 dec_insn.pc_inc + dec_insn.next_pc_inc;
641 *contpc = regs->cp0_epc + dec_insn.pc_inc;
642 *contpc >>= 28;
643 *contpc <<= 28;
644 *contpc |= (insn.j_format.target << 2);
645 return 1;
646 case mm_jals32_op:
647 case mm_jal32_op:
648 regs->regs[31] = regs->cp0_epc +
649 dec_insn.pc_inc + dec_insn.next_pc_inc;
650 /* Fall through */
651 case mm_j32_op:
652 *contpc = regs->cp0_epc + dec_insn.pc_inc;
653 *contpc >>= 27;
654 *contpc <<= 27;
655 *contpc |= (insn.j_format.target << 1);
656 set_isa16_mode(*contpc);
657 return 1;
658 }
659 return 0;
660}
661
662/*
663 * Redundant with logic already in kernel/branch.c,
664 * embedded in compute_return_epc. At some point,
665 * a single subroutine should be used across both
666 * modules.
667 */
668static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
669 unsigned long *contpc)
670{
671 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
672 unsigned int fcr31;
673 unsigned int bit = 0;
674
675 switch (insn.i_format.opcode) {
676 case spec_op:
677 switch (insn.r_format.func) {
678 case jalr_op:
679 regs->regs[insn.r_format.rd] =
680 regs->cp0_epc + dec_insn.pc_inc +
681 dec_insn.next_pc_inc;
682 /* Fall through */
683 case jr_op:
684 *contpc = regs->regs[insn.r_format.rs];
685 return 1;
686 }
687 break;
688 case bcond_op:
689 switch (insn.i_format.rt) {
690 case bltzal_op:
691 case bltzall_op:
692 regs->regs[31] = regs->cp0_epc +
693 dec_insn.pc_inc +
694 dec_insn.next_pc_inc;
695 /* Fall through */
696 case bltz_op:
697 case bltzl_op:
698 if ((long)regs->regs[insn.i_format.rs] < 0)
699 *contpc = regs->cp0_epc +
700 dec_insn.pc_inc +
701 (insn.i_format.simmediate << 2);
702 else
703 *contpc = regs->cp0_epc +
704 dec_insn.pc_inc +
705 dec_insn.next_pc_inc;
706 return 1;
707 case bgezal_op:
708 case bgezall_op:
709 regs->regs[31] = regs->cp0_epc +
710 dec_insn.pc_inc +
711 dec_insn.next_pc_inc;
712 /* Fall through */
713 case bgez_op:
714 case bgezl_op:
715 if ((long)regs->regs[insn.i_format.rs] >= 0)
716 *contpc = regs->cp0_epc +
717 dec_insn.pc_inc +
718 (insn.i_format.simmediate << 2);
719 else
720 *contpc = regs->cp0_epc +
721 dec_insn.pc_inc +
722 dec_insn.next_pc_inc;
723 return 1;
724 }
725 break;
726 case jalx_op:
727 set_isa16_mode(bit);
728 case jal_op:
729 regs->regs[31] = regs->cp0_epc +
730 dec_insn.pc_inc +
731 dec_insn.next_pc_inc;
732 /* Fall through */
733 case j_op:
734 *contpc = regs->cp0_epc + dec_insn.pc_inc;
735 *contpc >>= 28;
736 *contpc <<= 28;
737 *contpc |= (insn.j_format.target << 2);
738 /* Set microMIPS mode bit: XOR for jalx. */
739 *contpc ^= bit;
740 return 1;
741 case beq_op:
742 case beql_op:
743 if (regs->regs[insn.i_format.rs] ==
744 regs->regs[insn.i_format.rt])
745 *contpc = regs->cp0_epc +
746 dec_insn.pc_inc +
747 (insn.i_format.simmediate << 2);
748 else
749 *contpc = regs->cp0_epc +
750 dec_insn.pc_inc +
751 dec_insn.next_pc_inc;
752 return 1;
753 case bne_op:
754 case bnel_op:
755 if (regs->regs[insn.i_format.rs] !=
756 regs->regs[insn.i_format.rt])
757 *contpc = regs->cp0_epc +
758 dec_insn.pc_inc +
759 (insn.i_format.simmediate << 2);
760 else
761 *contpc = regs->cp0_epc +
762 dec_insn.pc_inc +
763 dec_insn.next_pc_inc;
764 return 1;
765 case blez_op:
766 case blezl_op:
767 if ((long)regs->regs[insn.i_format.rs] <= 0)
768 *contpc = regs->cp0_epc +
769 dec_insn.pc_inc +
770 (insn.i_format.simmediate << 2);
771 else
772 *contpc = regs->cp0_epc +
773 dec_insn.pc_inc +
774 dec_insn.next_pc_inc;
775 return 1;
776 case bgtz_op:
777 case bgtzl_op:
778 if ((long)regs->regs[insn.i_format.rs] > 0)
779 *contpc = regs->cp0_epc +
780 dec_insn.pc_inc +
781 (insn.i_format.simmediate << 2);
782 else
783 *contpc = regs->cp0_epc +
784 dec_insn.pc_inc +
785 dec_insn.next_pc_inc;
786 return 1;
787#ifdef CONFIG_CPU_CAVIUM_OCTEON
788 case lwc2_op: /* This is bbit0 on Octeon */
789 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
790 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
791 else
792 *contpc = regs->cp0_epc + 8;
793 return 1;
794 case ldc2_op: /* This is bbit032 on Octeon */
795 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
796 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
797 else
798 *contpc = regs->cp0_epc + 8;
799 return 1;
800 case swc2_op: /* This is bbit1 on Octeon */
801 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
802 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
803 else
804 *contpc = regs->cp0_epc + 8;
805 return 1;
806 case sdc2_op: /* This is bbit132 on Octeon */
807 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
808 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
809 else
810 *contpc = regs->cp0_epc + 8;
811 return 1;
812#endif
813 case cop0_op:
814 case cop1_op:
815 case cop2_op:
816 case cop1x_op:
817 if (insn.i_format.rs == bc_op) {
818 preempt_disable();
819 if (is_fpu_owner())
820 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
821 else
822 fcr31 = current->thread.fpu.fcr31;
823 preempt_enable();
824
825 bit = (insn.i_format.rt >> 2);
826 bit += (bit != 0);
827 bit += 23;
828 switch (insn.i_format.rt & 3) {
829 case 0: /* bc1f */
830 case 2: /* bc1fl */
831 if (~fcr31 & (1 << bit))
832 *contpc = regs->cp0_epc +
833 dec_insn.pc_inc +
834 (insn.i_format.simmediate << 2);
835 else
836 *contpc = regs->cp0_epc +
837 dec_insn.pc_inc +
838 dec_insn.next_pc_inc;
839 return 1;
840 case 1: /* bc1t */
841 case 3: /* bc1tl */
842 if (fcr31 & (1 << bit))
843 *contpc = regs->cp0_epc +
844 dec_insn.pc_inc +
845 (insn.i_format.simmediate << 2);
846 else
847 *contpc = regs->cp0_epc +
848 dec_insn.pc_inc +
849 dec_insn.next_pc_inc;
850 return 1;
851 }
852 }
853 break;
854 }
855 return 0;
856}
857
858/*
859 * In the Linux kernel, we support selection of FPR format on the
860 * basis of the Status.FR bit. If an FPU is not present, the FR bit
861 * is hardwired to zero, which would imply a 32-bit FPU even for
862 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
863 * FPU emu is slow and bulky and optimizing this function offers fairly
864 * sizeable benefits so we try to be clever and make this function return
865 * a constant whenever possible, that is on 64-bit kernels without O32
866 * compatibility enabled and on 32-bit without 64-bit FPU support.
867 */
868static inline int cop1_64bit(struct pt_regs *xcp)
869{
870#if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
871 return 1;
872#elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT)
873 return 0;
874#else
875 return !test_thread_flag(TIF_32BIT_FPREGS);
876#endif
877}
878
879#define SIFROMREG(si, x) do { \
880 if (cop1_64bit(xcp)) \
881 (si) = get_fpr32(&ctx->fpr[x], 0); \
882 else \
883 (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
884} while (0)
885
886#define SITOREG(si, x) do { \
887 if (cop1_64bit(xcp)) { \
888 unsigned i; \
889 set_fpr32(&ctx->fpr[x], 0, si); \
890 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
891 set_fpr32(&ctx->fpr[x], i, 0); \
892 } else { \
893 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
894 } \
895} while (0)
896
897#define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1))
898
899#define SITOHREG(si, x) do { \
900 unsigned i; \
901 set_fpr32(&ctx->fpr[x], 1, si); \
902 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
903 set_fpr32(&ctx->fpr[x], i, 0); \
904} while (0)
905
906#define DIFROMREG(di, x) \
907 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
908
909#define DITOREG(di, x) do { \
910 unsigned fpr, i; \
911 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
912 set_fpr64(&ctx->fpr[fpr], 0, di); \
913 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
914 set_fpr64(&ctx->fpr[fpr], i, 0); \
915} while (0)
916
917#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
918#define SPTOREG(sp, x) SITOREG((sp).bits, x)
919#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
920#define DPTOREG(dp, x) DITOREG((dp).bits, x)
921
922/*
923 * Emulate the single floating point instruction pointed at by EPC.
924 * Two instructions if the instruction is in a branch delay slot.
925 */
926
927static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
928 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
929{
930 mips_instruction ir;
931 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
932 unsigned int cond;
933 int pc_inc;
934
935 /* XXX NEC Vr54xx bug workaround */
936 if (xcp->cp0_cause & CAUSEF_BD) {
937 if (dec_insn.micro_mips_mode) {
938 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
939 xcp->cp0_cause &= ~CAUSEF_BD;
940 } else {
941 if (!isBranchInstr(xcp, dec_insn, &contpc))
942 xcp->cp0_cause &= ~CAUSEF_BD;
943 }
944 }
945
946 if (xcp->cp0_cause & CAUSEF_BD) {
947 /*
948 * The instruction to be emulated is in a branch delay slot
949 * which means that we have to emulate the branch instruction
950 * BEFORE we do the cop1 instruction.
951 *
952 * This branch could be a COP1 branch, but in that case we
953 * would have had a trap for that instruction, and would not
954 * come through this route.
955 *
956 * Linux MIPS branch emulator operates on context, updating the
957 * cp0_epc.
958 */
959 ir = dec_insn.next_insn; /* process delay slot instr */
960 pc_inc = dec_insn.next_pc_inc;
961 } else {
962 ir = dec_insn.insn; /* process current instr */
963 pc_inc = dec_insn.pc_inc;
964 }
965
966 /*
967 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
968 * instructions, we want to convert microMIPS FPU instructions
969 * into MIPS32 instructions so that we could reuse all of the
970 * FPU emulation code.
971 *
972 * NOTE: We cannot do this for branch instructions since they
973 * are not a subset. Example: Cannot emulate a 16-bit
974 * aligned target address with a MIPS32 instruction.
975 */
976 if (dec_insn.micro_mips_mode) {
977 /*
978 * If next instruction is a 16-bit instruction, then it
979 * it cannot be a FPU instruction. This could happen
980 * since we can be called for non-FPU instructions.
981 */
982 if ((pc_inc == 2) ||
983 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
984 == SIGILL))
985 return SIGILL;
986 }
987
988 emul:
989 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
990 MIPS_FPU_EMU_INC_STATS(emulated);
991 switch (MIPSInst_OPCODE(ir)) {
992 case ldc1_op:{
993 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
994 MIPSInst_SIMM(ir));
995 u64 val;
996
997 MIPS_FPU_EMU_INC_STATS(loads);
998
999 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1000 MIPS_FPU_EMU_INC_STATS(errors);
1001 *fault_addr = va;
1002 return SIGBUS;
1003 }
1004 if (__get_user(val, va)) {
1005 MIPS_FPU_EMU_INC_STATS(errors);
1006 *fault_addr = va;
1007 return SIGSEGV;
1008 }
1009 DITOREG(val, MIPSInst_RT(ir));
1010 break;
1011 }
1012
1013 case sdc1_op:{
1014 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1015 MIPSInst_SIMM(ir));
1016 u64 val;
1017
1018 MIPS_FPU_EMU_INC_STATS(stores);
1019 DIFROMREG(val, MIPSInst_RT(ir));
1020 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1021 MIPS_FPU_EMU_INC_STATS(errors);
1022 *fault_addr = va;
1023 return SIGBUS;
1024 }
1025 if (__put_user(val, va)) {
1026 MIPS_FPU_EMU_INC_STATS(errors);
1027 *fault_addr = va;
1028 return SIGSEGV;
1029 }
1030 break;
1031 }
1032
1033 case lwc1_op:{
1034 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1035 MIPSInst_SIMM(ir));
1036 u32 val;
1037
1038 MIPS_FPU_EMU_INC_STATS(loads);
1039 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1040 MIPS_FPU_EMU_INC_STATS(errors);
1041 *fault_addr = va;
1042 return SIGBUS;
1043 }
1044 if (__get_user(val, va)) {
1045 MIPS_FPU_EMU_INC_STATS(errors);
1046 *fault_addr = va;
1047 return SIGSEGV;
1048 }
1049 SITOREG(val, MIPSInst_RT(ir));
1050 break;
1051 }
1052
1053 case swc1_op:{
1054 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1055 MIPSInst_SIMM(ir));
1056 u32 val;
1057
1058 MIPS_FPU_EMU_INC_STATS(stores);
1059 SIFROMREG(val, MIPSInst_RT(ir));
1060 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1061 MIPS_FPU_EMU_INC_STATS(errors);
1062 *fault_addr = va;
1063 return SIGBUS;
1064 }
1065 if (__put_user(val, va)) {
1066 MIPS_FPU_EMU_INC_STATS(errors);
1067 *fault_addr = va;
1068 return SIGSEGV;
1069 }
1070 break;
1071 }
1072
1073 case cop1_op:
1074 switch (MIPSInst_RS(ir)) {
1075
1076#if defined(__mips64)
1077 case dmfc_op:
1078 /* copregister fs -> gpr[rt] */
1079 if (MIPSInst_RT(ir) != 0) {
1080 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1081 MIPSInst_RD(ir));
1082 }
1083 break;
1084
1085 case dmtc_op:
1086 /* copregister fs <- rt */
1087 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1088 break;
1089#endif
1090
1091 case mfhc_op:
1092 if (!cpu_has_mips_r2)
1093 goto sigill;
1094
1095 /* copregister rd -> gpr[rt] */
1096 if (MIPSInst_RT(ir) != 0) {
1097 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1098 MIPSInst_RD(ir));
1099 }
1100 break;
1101
1102 case mthc_op:
1103 if (!cpu_has_mips_r2)
1104 goto sigill;
1105
1106 /* copregister rd <- gpr[rt] */
1107 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1108 break;
1109
1110 case mfc_op:
1111 /* copregister rd -> gpr[rt] */
1112 if (MIPSInst_RT(ir) != 0) {
1113 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1114 MIPSInst_RD(ir));
1115 }
1116 break;
1117
1118 case mtc_op:
1119 /* copregister rd <- rt */
1120 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1121 break;
1122
1123 case cfc_op:{
1124 /* cop control register rd -> gpr[rt] */
1125 u32 value;
1126
1127 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1128 value = ctx->fcr31;
1129 value = (value & ~FPU_CSR_RM) |
1130 mips_rm[modeindex(value)];
1131#ifdef CSRTRACE
1132 printk("%p gpr[%d]<-csr=%08x\n",
1133 (void *) (xcp->cp0_epc),
1134 MIPSInst_RT(ir), value);
1135#endif
1136 }
1137 else if (MIPSInst_RD(ir) == FPCREG_RID)
1138 value = 0;
1139 else
1140 value = 0;
1141 if (MIPSInst_RT(ir))
1142 xcp->regs[MIPSInst_RT(ir)] = value;
1143 break;
1144 }
1145
1146 case ctc_op:{
1147 /* copregister rd <- rt */
1148 u32 value;
1149
1150 if (MIPSInst_RT(ir) == 0)
1151 value = 0;
1152 else
1153 value = xcp->regs[MIPSInst_RT(ir)];
1154
1155 /* we only have one writable control reg
1156 */
1157 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1158#ifdef CSRTRACE
1159 printk("%p gpr[%d]->csr=%08x\n",
1160 (void *) (xcp->cp0_epc),
1161 MIPSInst_RT(ir), value);
1162#endif
1163
1164 /*
1165 * Don't write reserved bits,
1166 * and convert to ieee library modes
1167 */
1168 ctx->fcr31 = (value &
1169 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1170 ieee_rm[modeindex(value)];
1171 }
1172 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1173 return SIGFPE;
1174 }
1175 break;
1176 }
1177
1178 case bc_op:{
1179 int likely = 0;
1180
1181 if (xcp->cp0_cause & CAUSEF_BD)
1182 return SIGILL;
1183
1184#if __mips >= 4
1185 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
1186#else
1187 cond = ctx->fcr31 & FPU_CSR_COND;
1188#endif
1189 switch (MIPSInst_RT(ir) & 3) {
1190 case bcfl_op:
1191 likely = 1;
1192 case bcf_op:
1193 cond = !cond;
1194 break;
1195 case bctl_op:
1196 likely = 1;
1197 case bct_op:
1198 break;
1199 default:
1200 /* thats an illegal instruction */
1201 return SIGILL;
1202 }
1203
1204 xcp->cp0_cause |= CAUSEF_BD;
1205 if (cond) {
1206 /* branch taken: emulate dslot
1207 * instruction
1208 */
1209 xcp->cp0_epc += dec_insn.pc_inc;
1210
1211 contpc = MIPSInst_SIMM(ir);
1212 ir = dec_insn.next_insn;
1213 if (dec_insn.micro_mips_mode) {
1214 contpc = (xcp->cp0_epc + (contpc << 1));
1215
1216 /* If 16-bit instruction, not FPU. */
1217 if ((dec_insn.next_pc_inc == 2) ||
1218 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1219
1220 /*
1221 * Since this instruction will
1222 * be put on the stack with
1223 * 32-bit words, get around
1224 * this problem by putting a
1225 * NOP16 as the second one.
1226 */
1227 if (dec_insn.next_pc_inc == 2)
1228 ir = (ir & (~0xffff)) | MM_NOP16;
1229
1230 /*
1231 * Single step the non-CP1
1232 * instruction in the dslot.
1233 */
1234 return mips_dsemul(xcp, ir, contpc);
1235 }
1236 } else
1237 contpc = (xcp->cp0_epc + (contpc << 2));
1238
1239 switch (MIPSInst_OPCODE(ir)) {
1240 case lwc1_op:
1241 case swc1_op:
1242#if (__mips >= 2 || defined(__mips64))
1243 case ldc1_op:
1244 case sdc1_op:
1245#endif
1246 case cop1_op:
1247#if __mips >= 4 && __mips != 32
1248 case cop1x_op:
1249#endif
1250 /* its one of ours */
1251 goto emul;
1252#if __mips >= 4
1253 case spec_op:
1254 if (MIPSInst_FUNC(ir) == movc_op)
1255 goto emul;
1256 break;
1257#endif
1258 }
1259
1260 /*
1261 * Single step the non-cp1
1262 * instruction in the dslot
1263 */
1264 return mips_dsemul(xcp, ir, contpc);
1265 }
1266 else {
1267 /* branch not taken */
1268 if (likely) {
1269 /*
1270 * branch likely nullifies
1271 * dslot if not taken
1272 */
1273 xcp->cp0_epc += dec_insn.pc_inc;
1274 contpc += dec_insn.pc_inc;
1275 /*
1276 * else continue & execute
1277 * dslot as normal insn
1278 */
1279 }
1280 }
1281 break;
1282 }
1283
1284 default:
1285 if (!(MIPSInst_RS(ir) & 0x10))
1286 return SIGILL;
1287 {
1288 int sig;
1289
1290 /* a real fpu computation instruction */
1291 if ((sig = fpu_emu(xcp, ctx, ir)))
1292 return sig;
1293 }
1294 }
1295 break;
1296
1297#if __mips >= 4 && __mips != 32
1298 case cop1x_op:{
1299 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
1300 if (sig)
1301 return sig;
1302 break;
1303 }
1304#endif
1305
1306#if __mips >= 4
1307 case spec_op:
1308 if (MIPSInst_FUNC(ir) != movc_op)
1309 return SIGILL;
1310 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1311 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1312 xcp->regs[MIPSInst_RD(ir)] =
1313 xcp->regs[MIPSInst_RS(ir)];
1314 break;
1315#endif
1316
1317 default:
1318sigill:
1319 return SIGILL;
1320 }
1321
1322 /* we did it !! */
1323 xcp->cp0_epc = contpc;
1324 xcp->cp0_cause &= ~CAUSEF_BD;
1325
1326 return 0;
1327}
1328
1329/*
1330 * Conversion table from MIPS compare ops 48-63
1331 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1332 */
1333static const unsigned char cmptab[8] = {
1334 0, /* cmp_0 (sig) cmp_sf */
1335 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1336 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1337 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1338 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1339 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1340 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1341 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1342};
1343
1344
1345#if __mips >= 4 && __mips != 32
1346
1347/*
1348 * Additional MIPS4 instructions
1349 */
1350
1351#define DEF3OP(name, p, f1, f2, f3) \
1352static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
1353 ieee754##p t) \
1354{ \
1355 struct _ieee754_csr ieee754_csr_save; \
1356 s = f1(s, t); \
1357 ieee754_csr_save = ieee754_csr; \
1358 s = f2(s, r); \
1359 ieee754_csr_save.cx |= ieee754_csr.cx; \
1360 ieee754_csr_save.sx |= ieee754_csr.sx; \
1361 s = f3(s); \
1362 ieee754_csr.cx |= ieee754_csr_save.cx; \
1363 ieee754_csr.sx |= ieee754_csr_save.sx; \
1364 return s; \
1365}
1366
1367static ieee754dp fpemu_dp_recip(ieee754dp d)
1368{
1369 return ieee754dp_div(ieee754dp_one(0), d);
1370}
1371
1372static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
1373{
1374 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1375}
1376
1377static ieee754sp fpemu_sp_recip(ieee754sp s)
1378{
1379 return ieee754sp_div(ieee754sp_one(0), s);
1380}
1381
1382static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
1383{
1384 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1385}
1386
1387DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1388DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1389DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1390DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1391DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1392DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1393DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1394DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1395
1396static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1397 mips_instruction ir, void *__user *fault_addr)
1398{
1399 unsigned rcsr = 0; /* resulting csr */
1400
1401 MIPS_FPU_EMU_INC_STATS(cp1xops);
1402
1403 switch (MIPSInst_FMA_FFMT(ir)) {
1404 case s_fmt:{ /* 0 */
1405
1406 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
1407 ieee754sp fd, fr, fs, ft;
1408 u32 __user *va;
1409 u32 val;
1410
1411 switch (MIPSInst_FUNC(ir)) {
1412 case lwxc1_op:
1413 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1414 xcp->regs[MIPSInst_FT(ir)]);
1415
1416 MIPS_FPU_EMU_INC_STATS(loads);
1417 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1418 MIPS_FPU_EMU_INC_STATS(errors);
1419 *fault_addr = va;
1420 return SIGBUS;
1421 }
1422 if (__get_user(val, va)) {
1423 MIPS_FPU_EMU_INC_STATS(errors);
1424 *fault_addr = va;
1425 return SIGSEGV;
1426 }
1427 SITOREG(val, MIPSInst_FD(ir));
1428 break;
1429
1430 case swxc1_op:
1431 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1432 xcp->regs[MIPSInst_FT(ir)]);
1433
1434 MIPS_FPU_EMU_INC_STATS(stores);
1435
1436 SIFROMREG(val, MIPSInst_FS(ir));
1437 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1438 MIPS_FPU_EMU_INC_STATS(errors);
1439 *fault_addr = va;
1440 return SIGBUS;
1441 }
1442 if (put_user(val, va)) {
1443 MIPS_FPU_EMU_INC_STATS(errors);
1444 *fault_addr = va;
1445 return SIGSEGV;
1446 }
1447 break;
1448
1449 case madd_s_op:
1450 handler = fpemu_sp_madd;
1451 goto scoptop;
1452 case msub_s_op:
1453 handler = fpemu_sp_msub;
1454 goto scoptop;
1455 case nmadd_s_op:
1456 handler = fpemu_sp_nmadd;
1457 goto scoptop;
1458 case nmsub_s_op:
1459 handler = fpemu_sp_nmsub;
1460 goto scoptop;
1461
1462 scoptop:
1463 SPFROMREG(fr, MIPSInst_FR(ir));
1464 SPFROMREG(fs, MIPSInst_FS(ir));
1465 SPFROMREG(ft, MIPSInst_FT(ir));
1466 fd = (*handler) (fr, fs, ft);
1467 SPTOREG(fd, MIPSInst_FD(ir));
1468
1469 copcsr:
1470 if (ieee754_cxtest(IEEE754_INEXACT))
1471 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1472 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1473 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1474 if (ieee754_cxtest(IEEE754_OVERFLOW))
1475 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1476 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1477 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1478
1479 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1480 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1481 /*printk ("SIGFPE: fpu csr = %08x\n",
1482 ctx->fcr31); */
1483 return SIGFPE;
1484 }
1485
1486 break;
1487
1488 default:
1489 return SIGILL;
1490 }
1491 break;
1492 }
1493
1494 case d_fmt:{ /* 1 */
1495 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
1496 ieee754dp fd, fr, fs, ft;
1497 u64 __user *va;
1498 u64 val;
1499
1500 switch (MIPSInst_FUNC(ir)) {
1501 case ldxc1_op:
1502 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1503 xcp->regs[MIPSInst_FT(ir)]);
1504
1505 MIPS_FPU_EMU_INC_STATS(loads);
1506 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1507 MIPS_FPU_EMU_INC_STATS(errors);
1508 *fault_addr = va;
1509 return SIGBUS;
1510 }
1511 if (__get_user(val, va)) {
1512 MIPS_FPU_EMU_INC_STATS(errors);
1513 *fault_addr = va;
1514 return SIGSEGV;
1515 }
1516 DITOREG(val, MIPSInst_FD(ir));
1517 break;
1518
1519 case sdxc1_op:
1520 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1521 xcp->regs[MIPSInst_FT(ir)]);
1522
1523 MIPS_FPU_EMU_INC_STATS(stores);
1524 DIFROMREG(val, MIPSInst_FS(ir));
1525 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1526 MIPS_FPU_EMU_INC_STATS(errors);
1527 *fault_addr = va;
1528 return SIGBUS;
1529 }
1530 if (__put_user(val, va)) {
1531 MIPS_FPU_EMU_INC_STATS(errors);
1532 *fault_addr = va;
1533 return SIGSEGV;
1534 }
1535 break;
1536
1537 case madd_d_op:
1538 handler = fpemu_dp_madd;
1539 goto dcoptop;
1540 case msub_d_op:
1541 handler = fpemu_dp_msub;
1542 goto dcoptop;
1543 case nmadd_d_op:
1544 handler = fpemu_dp_nmadd;
1545 goto dcoptop;
1546 case nmsub_d_op:
1547 handler = fpemu_dp_nmsub;
1548 goto dcoptop;
1549
1550 dcoptop:
1551 DPFROMREG(fr, MIPSInst_FR(ir));
1552 DPFROMREG(fs, MIPSInst_FS(ir));
1553 DPFROMREG(ft, MIPSInst_FT(ir));
1554 fd = (*handler) (fr, fs, ft);
1555 DPTOREG(fd, MIPSInst_FD(ir));
1556 goto copcsr;
1557
1558 default:
1559 return SIGILL;
1560 }
1561 break;
1562 }
1563
1564 case 0x3:
1565 if (MIPSInst_FUNC(ir) != pfetch_op)
1566 return SIGILL;
1567
1568 /* ignore prefx operation */
1569 break;
1570
1571 default:
1572 return SIGILL;
1573 }
1574
1575 return 0;
1576}
1577#endif
1578
1579
1580
1581/*
1582 * Emulate a single COP1 arithmetic instruction.
1583 */
1584static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1585 mips_instruction ir)
1586{
1587 int rfmt; /* resulting format */
1588 unsigned rcsr = 0; /* resulting csr */
1589 unsigned cond;
1590 union {
1591 ieee754dp d;
1592 ieee754sp s;
1593 int w;
1594#ifdef __mips64
1595 s64 l;
1596#endif
1597 } rv; /* resulting value */
1598
1599 MIPS_FPU_EMU_INC_STATS(cp1ops);
1600 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1601 case s_fmt:{ /* 0 */
1602 union {
1603 ieee754sp(*b) (ieee754sp, ieee754sp);
1604 ieee754sp(*u) (ieee754sp);
1605 } handler;
1606
1607 switch (MIPSInst_FUNC(ir)) {
1608 /* binary ops */
1609 case fadd_op:
1610 handler.b = ieee754sp_add;
1611 goto scopbop;
1612 case fsub_op:
1613 handler.b = ieee754sp_sub;
1614 goto scopbop;
1615 case fmul_op:
1616 handler.b = ieee754sp_mul;
1617 goto scopbop;
1618 case fdiv_op:
1619 handler.b = ieee754sp_div;
1620 goto scopbop;
1621
1622 /* unary ops */
1623#if __mips >= 2 || defined(__mips64)
1624 case fsqrt_op:
1625 handler.u = ieee754sp_sqrt;
1626 goto scopuop;
1627#endif
1628#if __mips >= 4 && __mips != 32
1629 case frsqrt_op:
1630 handler.u = fpemu_sp_rsqrt;
1631 goto scopuop;
1632 case frecip_op:
1633 handler.u = fpemu_sp_recip;
1634 goto scopuop;
1635#endif
1636#if __mips >= 4
1637 case fmovc_op:
1638 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1639 if (((ctx->fcr31 & cond) != 0) !=
1640 ((MIPSInst_FT(ir) & 1) != 0))
1641 return 0;
1642 SPFROMREG(rv.s, MIPSInst_FS(ir));
1643 break;
1644 case fmovz_op:
1645 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1646 return 0;
1647 SPFROMREG(rv.s, MIPSInst_FS(ir));
1648 break;
1649 case fmovn_op:
1650 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1651 return 0;
1652 SPFROMREG(rv.s, MIPSInst_FS(ir));
1653 break;
1654#endif
1655 case fabs_op:
1656 handler.u = ieee754sp_abs;
1657 goto scopuop;
1658 case fneg_op:
1659 handler.u = ieee754sp_neg;
1660 goto scopuop;
1661 case fmov_op:
1662 /* an easy one */
1663 SPFROMREG(rv.s, MIPSInst_FS(ir));
1664 goto copcsr;
1665
1666 /* binary op on handler */
1667 scopbop:
1668 {
1669 ieee754sp fs, ft;
1670
1671 SPFROMREG(fs, MIPSInst_FS(ir));
1672 SPFROMREG(ft, MIPSInst_FT(ir));
1673
1674 rv.s = (*handler.b) (fs, ft);
1675 goto copcsr;
1676 }
1677 scopuop:
1678 {
1679 ieee754sp fs;
1680
1681 SPFROMREG(fs, MIPSInst_FS(ir));
1682 rv.s = (*handler.u) (fs);
1683 goto copcsr;
1684 }
1685 copcsr:
1686 if (ieee754_cxtest(IEEE754_INEXACT))
1687 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1688 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1689 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1690 if (ieee754_cxtest(IEEE754_OVERFLOW))
1691 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1692 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
1693 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1694 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1695 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1696 break;
1697
1698 /* unary conv ops */
1699 case fcvts_op:
1700 return SIGILL; /* not defined */
1701 case fcvtd_op:{
1702 ieee754sp fs;
1703
1704 SPFROMREG(fs, MIPSInst_FS(ir));
1705 rv.d = ieee754dp_fsp(fs);
1706 rfmt = d_fmt;
1707 goto copcsr;
1708 }
1709 case fcvtw_op:{
1710 ieee754sp fs;
1711
1712 SPFROMREG(fs, MIPSInst_FS(ir));
1713 rv.w = ieee754sp_tint(fs);
1714 rfmt = w_fmt;
1715 goto copcsr;
1716 }
1717
1718#if __mips >= 2 || defined(__mips64)
1719 case fround_op:
1720 case ftrunc_op:
1721 case fceil_op:
1722 case ffloor_op:{
1723 unsigned int oldrm = ieee754_csr.rm;
1724 ieee754sp fs;
1725
1726 SPFROMREG(fs, MIPSInst_FS(ir));
1727 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1728 rv.w = ieee754sp_tint(fs);
1729 ieee754_csr.rm = oldrm;
1730 rfmt = w_fmt;
1731 goto copcsr;
1732 }
1733#endif /* __mips >= 2 */
1734
1735#if defined(__mips64)
1736 case fcvtl_op:{
1737 ieee754sp fs;
1738
1739 SPFROMREG(fs, MIPSInst_FS(ir));
1740 rv.l = ieee754sp_tlong(fs);
1741 rfmt = l_fmt;
1742 goto copcsr;
1743 }
1744
1745 case froundl_op:
1746 case ftruncl_op:
1747 case fceill_op:
1748 case ffloorl_op:{
1749 unsigned int oldrm = ieee754_csr.rm;
1750 ieee754sp fs;
1751
1752 SPFROMREG(fs, MIPSInst_FS(ir));
1753 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1754 rv.l = ieee754sp_tlong(fs);
1755 ieee754_csr.rm = oldrm;
1756 rfmt = l_fmt;
1757 goto copcsr;
1758 }
1759#endif /* defined(__mips64) */
1760
1761 default:
1762 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1763 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1764 ieee754sp fs, ft;
1765
1766 SPFROMREG(fs, MIPSInst_FS(ir));
1767 SPFROMREG(ft, MIPSInst_FT(ir));
1768 rv.w = ieee754sp_cmp(fs, ft,
1769 cmptab[cmpop & 0x7], cmpop & 0x8);
1770 rfmt = -1;
1771 if ((cmpop & 0x8) && ieee754_cxtest
1772 (IEEE754_INVALID_OPERATION))
1773 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1774 else
1775 goto copcsr;
1776
1777 }
1778 else {
1779 return SIGILL;
1780 }
1781 break;
1782 }
1783 break;
1784 }
1785
1786 case d_fmt:{
1787 union {
1788 ieee754dp(*b) (ieee754dp, ieee754dp);
1789 ieee754dp(*u) (ieee754dp);
1790 } handler;
1791
1792 switch (MIPSInst_FUNC(ir)) {
1793 /* binary ops */
1794 case fadd_op:
1795 handler.b = ieee754dp_add;
1796 goto dcopbop;
1797 case fsub_op:
1798 handler.b = ieee754dp_sub;
1799 goto dcopbop;
1800 case fmul_op:
1801 handler.b = ieee754dp_mul;
1802 goto dcopbop;
1803 case fdiv_op:
1804 handler.b = ieee754dp_div;
1805 goto dcopbop;
1806
1807 /* unary ops */
1808#if __mips >= 2 || defined(__mips64)
1809 case fsqrt_op:
1810 handler.u = ieee754dp_sqrt;
1811 goto dcopuop;
1812#endif
1813#if __mips >= 4 && __mips != 32
1814 case frsqrt_op:
1815 handler.u = fpemu_dp_rsqrt;
1816 goto dcopuop;
1817 case frecip_op:
1818 handler.u = fpemu_dp_recip;
1819 goto dcopuop;
1820#endif
1821#if __mips >= 4
1822 case fmovc_op:
1823 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1824 if (((ctx->fcr31 & cond) != 0) !=
1825 ((MIPSInst_FT(ir) & 1) != 0))
1826 return 0;
1827 DPFROMREG(rv.d, MIPSInst_FS(ir));
1828 break;
1829 case fmovz_op:
1830 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1831 return 0;
1832 DPFROMREG(rv.d, MIPSInst_FS(ir));
1833 break;
1834 case fmovn_op:
1835 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1836 return 0;
1837 DPFROMREG(rv.d, MIPSInst_FS(ir));
1838 break;
1839#endif
1840 case fabs_op:
1841 handler.u = ieee754dp_abs;
1842 goto dcopuop;
1843
1844 case fneg_op:
1845 handler.u = ieee754dp_neg;
1846 goto dcopuop;
1847
1848 case fmov_op:
1849 /* an easy one */
1850 DPFROMREG(rv.d, MIPSInst_FS(ir));
1851 goto copcsr;
1852
1853 /* binary op on handler */
1854 dcopbop:{
1855 ieee754dp fs, ft;
1856
1857 DPFROMREG(fs, MIPSInst_FS(ir));
1858 DPFROMREG(ft, MIPSInst_FT(ir));
1859
1860 rv.d = (*handler.b) (fs, ft);
1861 goto copcsr;
1862 }
1863 dcopuop:{
1864 ieee754dp fs;
1865
1866 DPFROMREG(fs, MIPSInst_FS(ir));
1867 rv.d = (*handler.u) (fs);
1868 goto copcsr;
1869 }
1870
1871 /* unary conv ops */
1872 case fcvts_op:{
1873 ieee754dp fs;
1874
1875 DPFROMREG(fs, MIPSInst_FS(ir));
1876 rv.s = ieee754sp_fdp(fs);
1877 rfmt = s_fmt;
1878 goto copcsr;
1879 }
1880 case fcvtd_op:
1881 return SIGILL; /* not defined */
1882
1883 case fcvtw_op:{
1884 ieee754dp fs;
1885
1886 DPFROMREG(fs, MIPSInst_FS(ir));
1887 rv.w = ieee754dp_tint(fs); /* wrong */
1888 rfmt = w_fmt;
1889 goto copcsr;
1890 }
1891
1892#if __mips >= 2 || defined(__mips64)
1893 case fround_op:
1894 case ftrunc_op:
1895 case fceil_op:
1896 case ffloor_op:{
1897 unsigned int oldrm = ieee754_csr.rm;
1898 ieee754dp fs;
1899
1900 DPFROMREG(fs, MIPSInst_FS(ir));
1901 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1902 rv.w = ieee754dp_tint(fs);
1903 ieee754_csr.rm = oldrm;
1904 rfmt = w_fmt;
1905 goto copcsr;
1906 }
1907#endif
1908
1909#if defined(__mips64)
1910 case fcvtl_op:{
1911 ieee754dp fs;
1912
1913 DPFROMREG(fs, MIPSInst_FS(ir));
1914 rv.l = ieee754dp_tlong(fs);
1915 rfmt = l_fmt;
1916 goto copcsr;
1917 }
1918
1919 case froundl_op:
1920 case ftruncl_op:
1921 case fceill_op:
1922 case ffloorl_op:{
1923 unsigned int oldrm = ieee754_csr.rm;
1924 ieee754dp fs;
1925
1926 DPFROMREG(fs, MIPSInst_FS(ir));
1927 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1928 rv.l = ieee754dp_tlong(fs);
1929 ieee754_csr.rm = oldrm;
1930 rfmt = l_fmt;
1931 goto copcsr;
1932 }
1933#endif /* __mips >= 3 */
1934
1935 default:
1936 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1937 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1938 ieee754dp fs, ft;
1939
1940 DPFROMREG(fs, MIPSInst_FS(ir));
1941 DPFROMREG(ft, MIPSInst_FT(ir));
1942 rv.w = ieee754dp_cmp(fs, ft,
1943 cmptab[cmpop & 0x7], cmpop & 0x8);
1944 rfmt = -1;
1945 if ((cmpop & 0x8)
1946 &&
1947 ieee754_cxtest
1948 (IEEE754_INVALID_OPERATION))
1949 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1950 else
1951 goto copcsr;
1952
1953 }
1954 else {
1955 return SIGILL;
1956 }
1957 break;
1958 }
1959 break;
1960 }
1961
1962 case w_fmt:{
1963 ieee754sp fs;
1964
1965 switch (MIPSInst_FUNC(ir)) {
1966 case fcvts_op:
1967 /* convert word to single precision real */
1968 SPFROMREG(fs, MIPSInst_FS(ir));
1969 rv.s = ieee754sp_fint(fs.bits);
1970 rfmt = s_fmt;
1971 goto copcsr;
1972 case fcvtd_op:
1973 /* convert word to double precision real */
1974 SPFROMREG(fs, MIPSInst_FS(ir));
1975 rv.d = ieee754dp_fint(fs.bits);
1976 rfmt = d_fmt;
1977 goto copcsr;
1978 default:
1979 return SIGILL;
1980 }
1981 break;
1982 }
1983
1984#if defined(__mips64)
1985 case l_fmt:{
1986 u64 bits;
1987 DIFROMREG(bits, MIPSInst_FS(ir));
1988
1989 switch (MIPSInst_FUNC(ir)) {
1990 case fcvts_op:
1991 /* convert long to single precision real */
1992 rv.s = ieee754sp_flong(bits);
1993 rfmt = s_fmt;
1994 goto copcsr;
1995 case fcvtd_op:
1996 /* convert long to double precision real */
1997 rv.d = ieee754dp_flong(bits);
1998 rfmt = d_fmt;
1999 goto copcsr;
2000 default:
2001 return SIGILL;
2002 }
2003 break;
2004 }
2005#endif
2006
2007 default:
2008 return SIGILL;
2009 }
2010
2011 /*
2012 * Update the fpu CSR register for this operation.
2013 * If an exception is required, generate a tidy SIGFPE exception,
2014 * without updating the result register.
2015 * Note: cause exception bits do not accumulate, they are rewritten
2016 * for each op; only the flag/sticky bits accumulate.
2017 */
2018 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2019 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2020 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
2021 return SIGFPE;
2022 }
2023
2024 /*
2025 * Now we can safely write the result back to the register file.
2026 */
2027 switch (rfmt) {
2028 case -1:{
2029#if __mips >= 4
2030 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
2031#else
2032 cond = FPU_CSR_COND;
2033#endif
2034 if (rv.w)
2035 ctx->fcr31 |= cond;
2036 else
2037 ctx->fcr31 &= ~cond;
2038 break;
2039 }
2040 case d_fmt:
2041 DPTOREG(rv.d, MIPSInst_FD(ir));
2042 break;
2043 case s_fmt:
2044 SPTOREG(rv.s, MIPSInst_FD(ir));
2045 break;
2046 case w_fmt:
2047 SITOREG(rv.w, MIPSInst_FD(ir));
2048 break;
2049#if defined(__mips64)
2050 case l_fmt:
2051 DITOREG(rv.l, MIPSInst_FD(ir));
2052 break;
2053#endif
2054 default:
2055 return SIGILL;
2056 }
2057
2058 return 0;
2059}
2060
2061int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2062 int has_fpu, void *__user *fault_addr)
2063{
2064 unsigned long oldepc, prevepc;
2065 struct mm_decoded_insn dec_insn;
2066 u16 instr[4];
2067 u16 *instr_ptr;
2068 int sig = 0;
2069
2070 oldepc = xcp->cp0_epc;
2071 do {
2072 prevepc = xcp->cp0_epc;
2073
2074 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2075 /*
2076 * Get next 2 microMIPS instructions and convert them
2077 * into 32-bit instructions.
2078 */
2079 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2080 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2081 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2082 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2083 MIPS_FPU_EMU_INC_STATS(errors);
2084 return SIGBUS;
2085 }
2086 instr_ptr = instr;
2087
2088 /* Get first instruction. */
2089 if (mm_insn_16bit(*instr_ptr)) {
2090 /* Duplicate the half-word. */
2091 dec_insn.insn = (*instr_ptr << 16) |
2092 (*instr_ptr);
2093 /* 16-bit instruction. */
2094 dec_insn.pc_inc = 2;
2095 instr_ptr += 1;
2096 } else {
2097 dec_insn.insn = (*instr_ptr << 16) |
2098 *(instr_ptr+1);
2099 /* 32-bit instruction. */
2100 dec_insn.pc_inc = 4;
2101 instr_ptr += 2;
2102 }
2103 /* Get second instruction. */
2104 if (mm_insn_16bit(*instr_ptr)) {
2105 /* Duplicate the half-word. */
2106 dec_insn.next_insn = (*instr_ptr << 16) |
2107 (*instr_ptr);
2108 /* 16-bit instruction. */
2109 dec_insn.next_pc_inc = 2;
2110 } else {
2111 dec_insn.next_insn = (*instr_ptr << 16) |
2112 *(instr_ptr+1);
2113 /* 32-bit instruction. */
2114 dec_insn.next_pc_inc = 4;
2115 }
2116 dec_insn.micro_mips_mode = 1;
2117 } else {
2118 if ((get_user(dec_insn.insn,
2119 (mips_instruction __user *) xcp->cp0_epc)) ||
2120 (get_user(dec_insn.next_insn,
2121 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2122 MIPS_FPU_EMU_INC_STATS(errors);
2123 return SIGBUS;
2124 }
2125 dec_insn.pc_inc = 4;
2126 dec_insn.next_pc_inc = 4;
2127 dec_insn.micro_mips_mode = 0;
2128 }
2129
2130 if ((dec_insn.insn == 0) ||
2131 ((dec_insn.pc_inc == 2) &&
2132 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2133 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2134 else {
2135 /*
2136 * The 'ieee754_csr' is an alias of
2137 * ctx->fcr31. No need to copy ctx->fcr31 to
2138 * ieee754_csr. But ieee754_csr.rm is ieee
2139 * library modes. (not mips rounding mode)
2140 */
2141 /* convert to ieee library modes */
2142 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
2143 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2144 /* revert to mips rounding mode */
2145 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
2146 }
2147
2148 if (has_fpu)
2149 break;
2150 if (sig)
2151 break;
2152
2153 cond_resched();
2154 } while (xcp->cp0_epc > prevepc);
2155
2156 /* SIGILL indicates a non-fpu instruction */
2157 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2158 /* but if epc has advanced, then ignore it */
2159 sig = 0;
2160
2161 return sig;
2162}
2163
2164#ifdef CONFIG_DEBUG_FS
2165
2166static int fpuemu_stat_get(void *data, u64 *val)
2167{
2168 int cpu;
2169 unsigned long sum = 0;
2170 for_each_online_cpu(cpu) {
2171 struct mips_fpu_emulator_stats *ps;
2172 local_t *pv;
2173 ps = &per_cpu(fpuemustats, cpu);
2174 pv = (void *)ps + (unsigned long)data;
2175 sum += local_read(pv);
2176 }
2177 *val = sum;
2178 return 0;
2179}
2180DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
2181
2182extern struct dentry *mips_debugfs_dir;
2183static int __init debugfs_fpuemu(void)
2184{
2185 struct dentry *d, *dir;
2186
2187 if (!mips_debugfs_dir)
2188 return -ENODEV;
2189 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
2190 if (!dir)
2191 return -ENOMEM;
2192
2193#define FPU_STAT_CREATE(M) \
2194 do { \
2195 d = debugfs_create_file(#M , S_IRUGO, dir, \
2196 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
2197 &fops_fpuemu_stat); \
2198 if (!d) \
2199 return -ENOMEM; \
2200 } while (0)
2201
2202 FPU_STAT_CREATE(emulated);
2203 FPU_STAT_CREATE(loads);
2204 FPU_STAT_CREATE(stores);
2205 FPU_STAT_CREATE(cp1ops);
2206 FPU_STAT_CREATE(cp1xops);
2207 FPU_STAT_CREATE(errors);
2208
2209 return 0;
2210}
2211__initcall(debugfs_fpuemu);
2212#endif