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1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32#include <linux/netdevice.h>
33
34#include "ixgbe.h"
35#include "ixgbe_common.h"
36#include "ixgbe_phy.h"
37
38static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
41static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
44 u16 count);
45static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
49
50static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
51static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
52static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
53 u16 words, u16 *data);
54static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
57 u16 offset);
58static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
59
60/**
61 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
62 * control
63 * @hw: pointer to hardware structure
64 *
65 * There are several phys that do not support autoneg flow control. This
66 * function check the device id to see if the associated phy supports
67 * autoneg flow control.
68 **/
69bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
70{
71 bool supported = false;
72 ixgbe_link_speed speed;
73 bool link_up;
74
75 switch (hw->phy.media_type) {
76 case ixgbe_media_type_fiber:
77 hw->mac.ops.check_link(hw, &speed, &link_up, false);
78 /* if link is down, assume supported */
79 if (link_up)
80 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
81 true : false;
82 else
83 supported = true;
84 break;
85 case ixgbe_media_type_backplane:
86 supported = true;
87 break;
88 case ixgbe_media_type_copper:
89 /* only some copper devices support flow control autoneg */
90 switch (hw->device_id) {
91 case IXGBE_DEV_ID_82599_T3_LOM:
92 case IXGBE_DEV_ID_X540T:
93 case IXGBE_DEV_ID_X540T1:
94 supported = true;
95 break;
96 default:
97 break;
98 }
99 default:
100 break;
101 }
102
103 return supported;
104}
105
106/**
107 * ixgbe_setup_fc - Set up flow control
108 * @hw: pointer to hardware structure
109 *
110 * Called at init time to set up flow control.
111 **/
112static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
113{
114 s32 ret_val = 0;
115 u32 reg = 0, reg_bp = 0;
116 u16 reg_cu = 0;
117 bool locked = false;
118
119 /*
120 * Validate the requested mode. Strict IEEE mode does not allow
121 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
122 */
123 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
124 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
125 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
126 goto out;
127 }
128
129 /*
130 * 10gig parts do not have a word in the EEPROM to determine the
131 * default flow control setting, so we explicitly set it to full.
132 */
133 if (hw->fc.requested_mode == ixgbe_fc_default)
134 hw->fc.requested_mode = ixgbe_fc_full;
135
136 /*
137 * Set up the 1G and 10G flow control advertisement registers so the
138 * HW will be able to do fc autoneg once the cable is plugged in. If
139 * we link at 10G, the 1G advertisement is harmless and vice versa.
140 */
141 switch (hw->phy.media_type) {
142 case ixgbe_media_type_backplane:
143 /* some MAC's need RMW protection on AUTOC */
144 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
145 if (ret_val)
146 goto out;
147
148 /* only backplane uses autoc so fall though */
149 case ixgbe_media_type_fiber:
150 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
151
152 break;
153 case ixgbe_media_type_copper:
154 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
155 MDIO_MMD_AN, ®_cu);
156 break;
157 default:
158 break;
159 }
160
161 /*
162 * The possible values of fc.requested_mode are:
163 * 0: Flow control is completely disabled
164 * 1: Rx flow control is enabled (we can receive pause frames,
165 * but not send pause frames).
166 * 2: Tx flow control is enabled (we can send pause frames but
167 * we do not support receiving pause frames).
168 * 3: Both Rx and Tx flow control (symmetric) are enabled.
169 * other: Invalid.
170 */
171 switch (hw->fc.requested_mode) {
172 case ixgbe_fc_none:
173 /* Flow control completely disabled by software override. */
174 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
175 if (hw->phy.media_type == ixgbe_media_type_backplane)
176 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
177 IXGBE_AUTOC_ASM_PAUSE);
178 else if (hw->phy.media_type == ixgbe_media_type_copper)
179 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
180 break;
181 case ixgbe_fc_tx_pause:
182 /*
183 * Tx Flow control is enabled, and Rx Flow control is
184 * disabled by software override.
185 */
186 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
187 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
188 if (hw->phy.media_type == ixgbe_media_type_backplane) {
189 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
190 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
191 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
192 reg_cu |= IXGBE_TAF_ASM_PAUSE;
193 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
194 }
195 break;
196 case ixgbe_fc_rx_pause:
197 /*
198 * Rx Flow control is enabled and Tx Flow control is
199 * disabled by software override. Since there really
200 * isn't a way to advertise that we are capable of RX
201 * Pause ONLY, we will advertise that we support both
202 * symmetric and asymmetric Rx PAUSE, as such we fall
203 * through to the fc_full statement. Later, we will
204 * disable the adapter's ability to send PAUSE frames.
205 */
206 case ixgbe_fc_full:
207 /* Flow control (both Rx and Tx) is enabled by SW override. */
208 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
209 if (hw->phy.media_type == ixgbe_media_type_backplane)
210 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
211 IXGBE_AUTOC_ASM_PAUSE;
212 else if (hw->phy.media_type == ixgbe_media_type_copper)
213 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
214 break;
215 default:
216 hw_dbg(hw, "Flow control param set incorrectly\n");
217 ret_val = IXGBE_ERR_CONFIG;
218 goto out;
219 break;
220 }
221
222 if (hw->mac.type != ixgbe_mac_X540) {
223 /*
224 * Enable auto-negotiation between the MAC & PHY;
225 * the MAC will advertise clause 37 flow control.
226 */
227 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
228 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
229
230 /* Disable AN timeout */
231 if (hw->fc.strict_ieee)
232 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
233
234 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
235 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
236 }
237
238 /*
239 * AUTOC restart handles negotiation of 1G and 10G on backplane
240 * and copper. There is no need to set the PCS1GCTL register.
241 *
242 */
243 if (hw->phy.media_type == ixgbe_media_type_backplane) {
244 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
245 * LESM is on, likewise reset_pipeline requries the lock as
246 * it also writes AUTOC.
247 */
248 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
249 if (ret_val)
250 goto out;
251
252 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
253 ixgbe_device_supports_autoneg_fc(hw)) {
254 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
255 MDIO_MMD_AN, reg_cu);
256 }
257
258 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
259out:
260 return ret_val;
261}
262
263/**
264 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
265 * @hw: pointer to hardware structure
266 *
267 * Starts the hardware by filling the bus info structure and media type, clears
268 * all on chip counters, initializes receive address registers, multicast
269 * table, VLAN filter table, calls routine to set up link and flow control
270 * settings, and leaves transmit and receive units disabled and uninitialized
271 **/
272s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
273{
274 u32 ctrl_ext;
275
276 /* Set the media type */
277 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
278
279 /* Identify the PHY */
280 hw->phy.ops.identify(hw);
281
282 /* Clear the VLAN filter table */
283 hw->mac.ops.clear_vfta(hw);
284
285 /* Clear statistics registers */
286 hw->mac.ops.clear_hw_cntrs(hw);
287
288 /* Set No Snoop Disable */
289 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
290 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
291 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
292 IXGBE_WRITE_FLUSH(hw);
293
294 /* Setup flow control */
295 ixgbe_setup_fc(hw);
296
297 /* Clear adapter stopped flag */
298 hw->adapter_stopped = false;
299
300 return 0;
301}
302
303/**
304 * ixgbe_start_hw_gen2 - Init sequence for common device family
305 * @hw: pointer to hw structure
306 *
307 * Performs the init sequence common to the second generation
308 * of 10 GbE devices.
309 * Devices in the second generation:
310 * 82599
311 * X540
312 **/
313s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
314{
315 u32 i;
316 u32 regval;
317
318 /* Clear the rate limiters */
319 for (i = 0; i < hw->mac.max_tx_queues; i++) {
320 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
321 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
322 }
323 IXGBE_WRITE_FLUSH(hw);
324
325 /* Disable relaxed ordering */
326 for (i = 0; i < hw->mac.max_tx_queues; i++) {
327 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
328 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
329 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
330 }
331
332 for (i = 0; i < hw->mac.max_rx_queues; i++) {
333 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
334 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
335 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
336 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
337 }
338
339 return 0;
340}
341
342/**
343 * ixgbe_init_hw_generic - Generic hardware initialization
344 * @hw: pointer to hardware structure
345 *
346 * Initialize the hardware by resetting the hardware, filling the bus info
347 * structure and media type, clears all on chip counters, initializes receive
348 * address registers, multicast table, VLAN filter table, calls routine to set
349 * up link and flow control settings, and leaves transmit and receive units
350 * disabled and uninitialized
351 **/
352s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
353{
354 s32 status;
355
356 /* Reset the hardware */
357 status = hw->mac.ops.reset_hw(hw);
358
359 if (status == 0) {
360 /* Start the HW */
361 status = hw->mac.ops.start_hw(hw);
362 }
363
364 return status;
365}
366
367/**
368 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
369 * @hw: pointer to hardware structure
370 *
371 * Clears all hardware statistics counters by reading them from the hardware
372 * Statistics counters are clear on read.
373 **/
374s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
375{
376 u16 i = 0;
377
378 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
379 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
380 IXGBE_READ_REG(hw, IXGBE_ERRBC);
381 IXGBE_READ_REG(hw, IXGBE_MSPDC);
382 for (i = 0; i < 8; i++)
383 IXGBE_READ_REG(hw, IXGBE_MPC(i));
384
385 IXGBE_READ_REG(hw, IXGBE_MLFC);
386 IXGBE_READ_REG(hw, IXGBE_MRFC);
387 IXGBE_READ_REG(hw, IXGBE_RLEC);
388 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
389 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
390 if (hw->mac.type >= ixgbe_mac_82599EB) {
391 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
392 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
393 } else {
394 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
395 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
396 }
397
398 for (i = 0; i < 8; i++) {
399 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
400 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
401 if (hw->mac.type >= ixgbe_mac_82599EB) {
402 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
403 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
404 } else {
405 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
406 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
407 }
408 }
409 if (hw->mac.type >= ixgbe_mac_82599EB)
410 for (i = 0; i < 8; i++)
411 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
412 IXGBE_READ_REG(hw, IXGBE_PRC64);
413 IXGBE_READ_REG(hw, IXGBE_PRC127);
414 IXGBE_READ_REG(hw, IXGBE_PRC255);
415 IXGBE_READ_REG(hw, IXGBE_PRC511);
416 IXGBE_READ_REG(hw, IXGBE_PRC1023);
417 IXGBE_READ_REG(hw, IXGBE_PRC1522);
418 IXGBE_READ_REG(hw, IXGBE_GPRC);
419 IXGBE_READ_REG(hw, IXGBE_BPRC);
420 IXGBE_READ_REG(hw, IXGBE_MPRC);
421 IXGBE_READ_REG(hw, IXGBE_GPTC);
422 IXGBE_READ_REG(hw, IXGBE_GORCL);
423 IXGBE_READ_REG(hw, IXGBE_GORCH);
424 IXGBE_READ_REG(hw, IXGBE_GOTCL);
425 IXGBE_READ_REG(hw, IXGBE_GOTCH);
426 if (hw->mac.type == ixgbe_mac_82598EB)
427 for (i = 0; i < 8; i++)
428 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
429 IXGBE_READ_REG(hw, IXGBE_RUC);
430 IXGBE_READ_REG(hw, IXGBE_RFC);
431 IXGBE_READ_REG(hw, IXGBE_ROC);
432 IXGBE_READ_REG(hw, IXGBE_RJC);
433 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
434 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
435 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
436 IXGBE_READ_REG(hw, IXGBE_TORL);
437 IXGBE_READ_REG(hw, IXGBE_TORH);
438 IXGBE_READ_REG(hw, IXGBE_TPR);
439 IXGBE_READ_REG(hw, IXGBE_TPT);
440 IXGBE_READ_REG(hw, IXGBE_PTC64);
441 IXGBE_READ_REG(hw, IXGBE_PTC127);
442 IXGBE_READ_REG(hw, IXGBE_PTC255);
443 IXGBE_READ_REG(hw, IXGBE_PTC511);
444 IXGBE_READ_REG(hw, IXGBE_PTC1023);
445 IXGBE_READ_REG(hw, IXGBE_PTC1522);
446 IXGBE_READ_REG(hw, IXGBE_MPTC);
447 IXGBE_READ_REG(hw, IXGBE_BPTC);
448 for (i = 0; i < 16; i++) {
449 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
450 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
451 if (hw->mac.type >= ixgbe_mac_82599EB) {
452 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
453 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
454 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
455 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
456 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
457 } else {
458 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
459 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
460 }
461 }
462
463 if (hw->mac.type == ixgbe_mac_X540) {
464 if (hw->phy.id == 0)
465 hw->phy.ops.identify(hw);
466 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
467 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
468 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
469 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
470 }
471
472 return 0;
473}
474
475/**
476 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
477 * @hw: pointer to hardware structure
478 * @pba_num: stores the part number string from the EEPROM
479 * @pba_num_size: part number string buffer length
480 *
481 * Reads the part number string from the EEPROM.
482 **/
483s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
484 u32 pba_num_size)
485{
486 s32 ret_val;
487 u16 data;
488 u16 pba_ptr;
489 u16 offset;
490 u16 length;
491
492 if (pba_num == NULL) {
493 hw_dbg(hw, "PBA string buffer was null\n");
494 return IXGBE_ERR_INVALID_ARGUMENT;
495 }
496
497 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
498 if (ret_val) {
499 hw_dbg(hw, "NVM Read Error\n");
500 return ret_val;
501 }
502
503 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
504 if (ret_val) {
505 hw_dbg(hw, "NVM Read Error\n");
506 return ret_val;
507 }
508
509 /*
510 * if data is not ptr guard the PBA must be in legacy format which
511 * means pba_ptr is actually our second data word for the PBA number
512 * and we can decode it into an ascii string
513 */
514 if (data != IXGBE_PBANUM_PTR_GUARD) {
515 hw_dbg(hw, "NVM PBA number is not stored as string\n");
516
517 /* we will need 11 characters to store the PBA */
518 if (pba_num_size < 11) {
519 hw_dbg(hw, "PBA string buffer too small\n");
520 return IXGBE_ERR_NO_SPACE;
521 }
522
523 /* extract hex string from data and pba_ptr */
524 pba_num[0] = (data >> 12) & 0xF;
525 pba_num[1] = (data >> 8) & 0xF;
526 pba_num[2] = (data >> 4) & 0xF;
527 pba_num[3] = data & 0xF;
528 pba_num[4] = (pba_ptr >> 12) & 0xF;
529 pba_num[5] = (pba_ptr >> 8) & 0xF;
530 pba_num[6] = '-';
531 pba_num[7] = 0;
532 pba_num[8] = (pba_ptr >> 4) & 0xF;
533 pba_num[9] = pba_ptr & 0xF;
534
535 /* put a null character on the end of our string */
536 pba_num[10] = '\0';
537
538 /* switch all the data but the '-' to hex char */
539 for (offset = 0; offset < 10; offset++) {
540 if (pba_num[offset] < 0xA)
541 pba_num[offset] += '0';
542 else if (pba_num[offset] < 0x10)
543 pba_num[offset] += 'A' - 0xA;
544 }
545
546 return 0;
547 }
548
549 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
550 if (ret_val) {
551 hw_dbg(hw, "NVM Read Error\n");
552 return ret_val;
553 }
554
555 if (length == 0xFFFF || length == 0) {
556 hw_dbg(hw, "NVM PBA number section invalid length\n");
557 return IXGBE_ERR_PBA_SECTION;
558 }
559
560 /* check if pba_num buffer is big enough */
561 if (pba_num_size < (((u32)length * 2) - 1)) {
562 hw_dbg(hw, "PBA string buffer too small\n");
563 return IXGBE_ERR_NO_SPACE;
564 }
565
566 /* trim pba length from start of string */
567 pba_ptr++;
568 length--;
569
570 for (offset = 0; offset < length; offset++) {
571 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
572 if (ret_val) {
573 hw_dbg(hw, "NVM Read Error\n");
574 return ret_val;
575 }
576 pba_num[offset * 2] = (u8)(data >> 8);
577 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
578 }
579 pba_num[offset * 2] = '\0';
580
581 return 0;
582}
583
584/**
585 * ixgbe_get_mac_addr_generic - Generic get MAC address
586 * @hw: pointer to hardware structure
587 * @mac_addr: Adapter MAC address
588 *
589 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
590 * A reset of the adapter must be performed prior to calling this function
591 * in order for the MAC address to have been loaded from the EEPROM into RAR0
592 **/
593s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
594{
595 u32 rar_high;
596 u32 rar_low;
597 u16 i;
598
599 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
600 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
601
602 for (i = 0; i < 4; i++)
603 mac_addr[i] = (u8)(rar_low >> (i*8));
604
605 for (i = 0; i < 2; i++)
606 mac_addr[i+4] = (u8)(rar_high >> (i*8));
607
608 return 0;
609}
610
611enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
612{
613 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
614 case IXGBE_PCI_LINK_WIDTH_1:
615 return ixgbe_bus_width_pcie_x1;
616 case IXGBE_PCI_LINK_WIDTH_2:
617 return ixgbe_bus_width_pcie_x2;
618 case IXGBE_PCI_LINK_WIDTH_4:
619 return ixgbe_bus_width_pcie_x4;
620 case IXGBE_PCI_LINK_WIDTH_8:
621 return ixgbe_bus_width_pcie_x8;
622 default:
623 return ixgbe_bus_width_unknown;
624 }
625}
626
627enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
628{
629 switch (link_status & IXGBE_PCI_LINK_SPEED) {
630 case IXGBE_PCI_LINK_SPEED_2500:
631 return ixgbe_bus_speed_2500;
632 case IXGBE_PCI_LINK_SPEED_5000:
633 return ixgbe_bus_speed_5000;
634 case IXGBE_PCI_LINK_SPEED_8000:
635 return ixgbe_bus_speed_8000;
636 default:
637 return ixgbe_bus_speed_unknown;
638 }
639}
640
641/**
642 * ixgbe_get_bus_info_generic - Generic set PCI bus info
643 * @hw: pointer to hardware structure
644 *
645 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
646 **/
647s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
648{
649 u16 link_status;
650
651 hw->bus.type = ixgbe_bus_type_pci_express;
652
653 /* Get the negotiated link width and speed from PCI config space */
654 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS);
655
656 hw->bus.width = ixgbe_convert_bus_width(link_status);
657 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
658
659 hw->mac.ops.set_lan_id(hw);
660
661 return 0;
662}
663
664/**
665 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
666 * @hw: pointer to the HW structure
667 *
668 * Determines the LAN function id by reading memory-mapped registers
669 * and swaps the port value if requested.
670 **/
671void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
672{
673 struct ixgbe_bus_info *bus = &hw->bus;
674 u32 reg;
675
676 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
677 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
678 bus->lan_id = bus->func;
679
680 /* check for a port swap */
681 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
682 if (reg & IXGBE_FACTPS_LFS)
683 bus->func ^= 0x1;
684}
685
686/**
687 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
688 * @hw: pointer to hardware structure
689 *
690 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
691 * disables transmit and receive units. The adapter_stopped flag is used by
692 * the shared code and drivers to determine if the adapter is in a stopped
693 * state and should not touch the hardware.
694 **/
695s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
696{
697 u32 reg_val;
698 u16 i;
699
700 /*
701 * Set the adapter_stopped flag so other driver functions stop touching
702 * the hardware
703 */
704 hw->adapter_stopped = true;
705
706 /* Disable the receive unit */
707 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
708
709 /* Clear interrupt mask to stop interrupts from being generated */
710 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
711
712 /* Clear any pending interrupts, flush previous writes */
713 IXGBE_READ_REG(hw, IXGBE_EICR);
714
715 /* Disable the transmit unit. Each queue must be disabled. */
716 for (i = 0; i < hw->mac.max_tx_queues; i++)
717 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
718
719 /* Disable the receive unit by stopping each queue */
720 for (i = 0; i < hw->mac.max_rx_queues; i++) {
721 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
722 reg_val &= ~IXGBE_RXDCTL_ENABLE;
723 reg_val |= IXGBE_RXDCTL_SWFLSH;
724 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
725 }
726
727 /* flush all queues disables */
728 IXGBE_WRITE_FLUSH(hw);
729 usleep_range(1000, 2000);
730
731 /*
732 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
733 * access and verify no pending requests
734 */
735 return ixgbe_disable_pcie_master(hw);
736}
737
738/**
739 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
740 * @hw: pointer to hardware structure
741 * @index: led number to turn on
742 **/
743s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
744{
745 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
746
747 /* To turn on the LED, set mode to ON. */
748 led_reg &= ~IXGBE_LED_MODE_MASK(index);
749 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
750 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
751 IXGBE_WRITE_FLUSH(hw);
752
753 return 0;
754}
755
756/**
757 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
758 * @hw: pointer to hardware structure
759 * @index: led number to turn off
760 **/
761s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
762{
763 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
764
765 /* To turn off the LED, set mode to OFF. */
766 led_reg &= ~IXGBE_LED_MODE_MASK(index);
767 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
768 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
769 IXGBE_WRITE_FLUSH(hw);
770
771 return 0;
772}
773
774/**
775 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
776 * @hw: pointer to hardware structure
777 *
778 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
779 * ixgbe_hw struct in order to set up EEPROM access.
780 **/
781s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
782{
783 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
784 u32 eec;
785 u16 eeprom_size;
786
787 if (eeprom->type == ixgbe_eeprom_uninitialized) {
788 eeprom->type = ixgbe_eeprom_none;
789 /* Set default semaphore delay to 10ms which is a well
790 * tested value */
791 eeprom->semaphore_delay = 10;
792 /* Clear EEPROM page size, it will be initialized as needed */
793 eeprom->word_page_size = 0;
794
795 /*
796 * Check for EEPROM present first.
797 * If not present leave as none
798 */
799 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
800 if (eec & IXGBE_EEC_PRES) {
801 eeprom->type = ixgbe_eeprom_spi;
802
803 /*
804 * SPI EEPROM is assumed here. This code would need to
805 * change if a future EEPROM is not SPI.
806 */
807 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
808 IXGBE_EEC_SIZE_SHIFT);
809 eeprom->word_size = 1 << (eeprom_size +
810 IXGBE_EEPROM_WORD_SIZE_SHIFT);
811 }
812
813 if (eec & IXGBE_EEC_ADDR_SIZE)
814 eeprom->address_bits = 16;
815 else
816 eeprom->address_bits = 8;
817 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
818 "%d\n", eeprom->type, eeprom->word_size,
819 eeprom->address_bits);
820 }
821
822 return 0;
823}
824
825/**
826 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
827 * @hw: pointer to hardware structure
828 * @offset: offset within the EEPROM to write
829 * @words: number of words
830 * @data: 16 bit word(s) to write to EEPROM
831 *
832 * Reads 16 bit word(s) from EEPROM through bit-bang method
833 **/
834s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
835 u16 words, u16 *data)
836{
837 s32 status = 0;
838 u16 i, count;
839
840 hw->eeprom.ops.init_params(hw);
841
842 if (words == 0) {
843 status = IXGBE_ERR_INVALID_ARGUMENT;
844 goto out;
845 }
846
847 if (offset + words > hw->eeprom.word_size) {
848 status = IXGBE_ERR_EEPROM;
849 goto out;
850 }
851
852 /*
853 * The EEPROM page size cannot be queried from the chip. We do lazy
854 * initialization. It is worth to do that when we write large buffer.
855 */
856 if ((hw->eeprom.word_page_size == 0) &&
857 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
858 ixgbe_detect_eeprom_page_size_generic(hw, offset);
859
860 /*
861 * We cannot hold synchronization semaphores for too long
862 * to avoid other entity starvation. However it is more efficient
863 * to read in bursts than synchronizing access for each word.
864 */
865 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
866 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
867 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
868 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
869 count, &data[i]);
870
871 if (status != 0)
872 break;
873 }
874
875out:
876 return status;
877}
878
879/**
880 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
881 * @hw: pointer to hardware structure
882 * @offset: offset within the EEPROM to be written to
883 * @words: number of word(s)
884 * @data: 16 bit word(s) to be written to the EEPROM
885 *
886 * If ixgbe_eeprom_update_checksum is not called after this function, the
887 * EEPROM will most likely contain an invalid checksum.
888 **/
889static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
890 u16 words, u16 *data)
891{
892 s32 status;
893 u16 word;
894 u16 page_size;
895 u16 i;
896 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
897
898 /* Prepare the EEPROM for writing */
899 status = ixgbe_acquire_eeprom(hw);
900
901 if (status == 0) {
902 if (ixgbe_ready_eeprom(hw) != 0) {
903 ixgbe_release_eeprom(hw);
904 status = IXGBE_ERR_EEPROM;
905 }
906 }
907
908 if (status == 0) {
909 for (i = 0; i < words; i++) {
910 ixgbe_standby_eeprom(hw);
911
912 /* Send the WRITE ENABLE command (8 bit opcode ) */
913 ixgbe_shift_out_eeprom_bits(hw,
914 IXGBE_EEPROM_WREN_OPCODE_SPI,
915 IXGBE_EEPROM_OPCODE_BITS);
916
917 ixgbe_standby_eeprom(hw);
918
919 /*
920 * Some SPI eeproms use the 8th address bit embedded
921 * in the opcode
922 */
923 if ((hw->eeprom.address_bits == 8) &&
924 ((offset + i) >= 128))
925 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
926
927 /* Send the Write command (8-bit opcode + addr) */
928 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
929 IXGBE_EEPROM_OPCODE_BITS);
930 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
931 hw->eeprom.address_bits);
932
933 page_size = hw->eeprom.word_page_size;
934
935 /* Send the data in burst via SPI*/
936 do {
937 word = data[i];
938 word = (word >> 8) | (word << 8);
939 ixgbe_shift_out_eeprom_bits(hw, word, 16);
940
941 if (page_size == 0)
942 break;
943
944 /* do not wrap around page */
945 if (((offset + i) & (page_size - 1)) ==
946 (page_size - 1))
947 break;
948 } while (++i < words);
949
950 ixgbe_standby_eeprom(hw);
951 usleep_range(10000, 20000);
952 }
953 /* Done with writing - release the EEPROM */
954 ixgbe_release_eeprom(hw);
955 }
956
957 return status;
958}
959
960/**
961 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
962 * @hw: pointer to hardware structure
963 * @offset: offset within the EEPROM to be written to
964 * @data: 16 bit word to be written to the EEPROM
965 *
966 * If ixgbe_eeprom_update_checksum is not called after this function, the
967 * EEPROM will most likely contain an invalid checksum.
968 **/
969s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
970{
971 s32 status;
972
973 hw->eeprom.ops.init_params(hw);
974
975 if (offset >= hw->eeprom.word_size) {
976 status = IXGBE_ERR_EEPROM;
977 goto out;
978 }
979
980 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
981
982out:
983 return status;
984}
985
986/**
987 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
988 * @hw: pointer to hardware structure
989 * @offset: offset within the EEPROM to be read
990 * @words: number of word(s)
991 * @data: read 16 bit words(s) from EEPROM
992 *
993 * Reads 16 bit word(s) from EEPROM through bit-bang method
994 **/
995s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
996 u16 words, u16 *data)
997{
998 s32 status = 0;
999 u16 i, count;
1000
1001 hw->eeprom.ops.init_params(hw);
1002
1003 if (words == 0) {
1004 status = IXGBE_ERR_INVALID_ARGUMENT;
1005 goto out;
1006 }
1007
1008 if (offset + words > hw->eeprom.word_size) {
1009 status = IXGBE_ERR_EEPROM;
1010 goto out;
1011 }
1012
1013 /*
1014 * We cannot hold synchronization semaphores for too long
1015 * to avoid other entity starvation. However it is more efficient
1016 * to read in bursts than synchronizing access for each word.
1017 */
1018 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1019 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1020 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1021
1022 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1023 count, &data[i]);
1024
1025 if (status != 0)
1026 break;
1027 }
1028
1029out:
1030 return status;
1031}
1032
1033/**
1034 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1035 * @hw: pointer to hardware structure
1036 * @offset: offset within the EEPROM to be read
1037 * @words: number of word(s)
1038 * @data: read 16 bit word(s) from EEPROM
1039 *
1040 * Reads 16 bit word(s) from EEPROM through bit-bang method
1041 **/
1042static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1043 u16 words, u16 *data)
1044{
1045 s32 status;
1046 u16 word_in;
1047 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1048 u16 i;
1049
1050 /* Prepare the EEPROM for reading */
1051 status = ixgbe_acquire_eeprom(hw);
1052
1053 if (status == 0) {
1054 if (ixgbe_ready_eeprom(hw) != 0) {
1055 ixgbe_release_eeprom(hw);
1056 status = IXGBE_ERR_EEPROM;
1057 }
1058 }
1059
1060 if (status == 0) {
1061 for (i = 0; i < words; i++) {
1062 ixgbe_standby_eeprom(hw);
1063 /*
1064 * Some SPI eeproms use the 8th address bit embedded
1065 * in the opcode
1066 */
1067 if ((hw->eeprom.address_bits == 8) &&
1068 ((offset + i) >= 128))
1069 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1070
1071 /* Send the READ command (opcode + addr) */
1072 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1073 IXGBE_EEPROM_OPCODE_BITS);
1074 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1075 hw->eeprom.address_bits);
1076
1077 /* Read the data. */
1078 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1079 data[i] = (word_in >> 8) | (word_in << 8);
1080 }
1081
1082 /* End this read operation */
1083 ixgbe_release_eeprom(hw);
1084 }
1085
1086 return status;
1087}
1088
1089/**
1090 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1091 * @hw: pointer to hardware structure
1092 * @offset: offset within the EEPROM to be read
1093 * @data: read 16 bit value from EEPROM
1094 *
1095 * Reads 16 bit value from EEPROM through bit-bang method
1096 **/
1097s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1098 u16 *data)
1099{
1100 s32 status;
1101
1102 hw->eeprom.ops.init_params(hw);
1103
1104 if (offset >= hw->eeprom.word_size) {
1105 status = IXGBE_ERR_EEPROM;
1106 goto out;
1107 }
1108
1109 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1110
1111out:
1112 return status;
1113}
1114
1115/**
1116 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1117 * @hw: pointer to hardware structure
1118 * @offset: offset of word in the EEPROM to read
1119 * @words: number of word(s)
1120 * @data: 16 bit word(s) from the EEPROM
1121 *
1122 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1123 **/
1124s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1125 u16 words, u16 *data)
1126{
1127 u32 eerd;
1128 s32 status = 0;
1129 u32 i;
1130
1131 hw->eeprom.ops.init_params(hw);
1132
1133 if (words == 0) {
1134 status = IXGBE_ERR_INVALID_ARGUMENT;
1135 goto out;
1136 }
1137
1138 if (offset >= hw->eeprom.word_size) {
1139 status = IXGBE_ERR_EEPROM;
1140 goto out;
1141 }
1142
1143 for (i = 0; i < words; i++) {
1144 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1145 IXGBE_EEPROM_RW_REG_START;
1146
1147 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1148 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1149
1150 if (status == 0) {
1151 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1152 IXGBE_EEPROM_RW_REG_DATA);
1153 } else {
1154 hw_dbg(hw, "Eeprom read timed out\n");
1155 goto out;
1156 }
1157 }
1158out:
1159 return status;
1160}
1161
1162/**
1163 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1164 * @hw: pointer to hardware structure
1165 * @offset: offset within the EEPROM to be used as a scratch pad
1166 *
1167 * Discover EEPROM page size by writing marching data at given offset.
1168 * This function is called only when we are writing a new large buffer
1169 * at given offset so the data would be overwritten anyway.
1170 **/
1171static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1172 u16 offset)
1173{
1174 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1175 s32 status = 0;
1176 u16 i;
1177
1178 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1179 data[i] = i;
1180
1181 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1182 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1183 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1184 hw->eeprom.word_page_size = 0;
1185 if (status != 0)
1186 goto out;
1187
1188 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1189 if (status != 0)
1190 goto out;
1191
1192 /*
1193 * When writing in burst more than the actual page size
1194 * EEPROM address wraps around current page.
1195 */
1196 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1197
1198 hw_dbg(hw, "Detected EEPROM page size = %d words.\n",
1199 hw->eeprom.word_page_size);
1200out:
1201 return status;
1202}
1203
1204/**
1205 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1206 * @hw: pointer to hardware structure
1207 * @offset: offset of word in the EEPROM to read
1208 * @data: word read from the EEPROM
1209 *
1210 * Reads a 16 bit word from the EEPROM using the EERD register.
1211 **/
1212s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1213{
1214 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1215}
1216
1217/**
1218 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1219 * @hw: pointer to hardware structure
1220 * @offset: offset of word in the EEPROM to write
1221 * @words: number of words
1222 * @data: word(s) write to the EEPROM
1223 *
1224 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1225 **/
1226s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1227 u16 words, u16 *data)
1228{
1229 u32 eewr;
1230 s32 status = 0;
1231 u16 i;
1232
1233 hw->eeprom.ops.init_params(hw);
1234
1235 if (words == 0) {
1236 status = IXGBE_ERR_INVALID_ARGUMENT;
1237 goto out;
1238 }
1239
1240 if (offset >= hw->eeprom.word_size) {
1241 status = IXGBE_ERR_EEPROM;
1242 goto out;
1243 }
1244
1245 for (i = 0; i < words; i++) {
1246 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1247 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1248 IXGBE_EEPROM_RW_REG_START;
1249
1250 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1251 if (status != 0) {
1252 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1253 goto out;
1254 }
1255
1256 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1257
1258 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1259 if (status != 0) {
1260 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1261 goto out;
1262 }
1263 }
1264
1265out:
1266 return status;
1267}
1268
1269/**
1270 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1271 * @hw: pointer to hardware structure
1272 * @offset: offset of word in the EEPROM to write
1273 * @data: word write to the EEPROM
1274 *
1275 * Write a 16 bit word to the EEPROM using the EEWR register.
1276 **/
1277s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1278{
1279 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1280}
1281
1282/**
1283 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1284 * @hw: pointer to hardware structure
1285 * @ee_reg: EEPROM flag for polling
1286 *
1287 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1288 * read or write is done respectively.
1289 **/
1290static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1291{
1292 u32 i;
1293 u32 reg;
1294 s32 status = IXGBE_ERR_EEPROM;
1295
1296 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1297 if (ee_reg == IXGBE_NVM_POLL_READ)
1298 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1299 else
1300 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1301
1302 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1303 status = 0;
1304 break;
1305 }
1306 udelay(5);
1307 }
1308 return status;
1309}
1310
1311/**
1312 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1313 * @hw: pointer to hardware structure
1314 *
1315 * Prepares EEPROM for access using bit-bang method. This function should
1316 * be called before issuing a command to the EEPROM.
1317 **/
1318static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1319{
1320 s32 status = 0;
1321 u32 eec;
1322 u32 i;
1323
1324 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
1325 status = IXGBE_ERR_SWFW_SYNC;
1326
1327 if (status == 0) {
1328 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1329
1330 /* Request EEPROM Access */
1331 eec |= IXGBE_EEC_REQ;
1332 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1333
1334 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1335 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1336 if (eec & IXGBE_EEC_GNT)
1337 break;
1338 udelay(5);
1339 }
1340
1341 /* Release if grant not acquired */
1342 if (!(eec & IXGBE_EEC_GNT)) {
1343 eec &= ~IXGBE_EEC_REQ;
1344 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1345 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1346
1347 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1348 status = IXGBE_ERR_EEPROM;
1349 }
1350
1351 /* Setup EEPROM for Read/Write */
1352 if (status == 0) {
1353 /* Clear CS and SK */
1354 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1355 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1356 IXGBE_WRITE_FLUSH(hw);
1357 udelay(1);
1358 }
1359 }
1360 return status;
1361}
1362
1363/**
1364 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1365 * @hw: pointer to hardware structure
1366 *
1367 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1368 **/
1369static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1370{
1371 s32 status = IXGBE_ERR_EEPROM;
1372 u32 timeout = 2000;
1373 u32 i;
1374 u32 swsm;
1375
1376 /* Get SMBI software semaphore between device drivers first */
1377 for (i = 0; i < timeout; i++) {
1378 /*
1379 * If the SMBI bit is 0 when we read it, then the bit will be
1380 * set and we have the semaphore
1381 */
1382 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1383 if (!(swsm & IXGBE_SWSM_SMBI)) {
1384 status = 0;
1385 break;
1386 }
1387 udelay(50);
1388 }
1389
1390 if (i == timeout) {
1391 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
1392 "not granted.\n");
1393 /*
1394 * this release is particularly important because our attempts
1395 * above to get the semaphore may have succeeded, and if there
1396 * was a timeout, we should unconditionally clear the semaphore
1397 * bits to free the driver to make progress
1398 */
1399 ixgbe_release_eeprom_semaphore(hw);
1400
1401 udelay(50);
1402 /*
1403 * one last try
1404 * If the SMBI bit is 0 when we read it, then the bit will be
1405 * set and we have the semaphore
1406 */
1407 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1408 if (!(swsm & IXGBE_SWSM_SMBI))
1409 status = 0;
1410 }
1411
1412 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1413 if (status == 0) {
1414 for (i = 0; i < timeout; i++) {
1415 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1416
1417 /* Set the SW EEPROM semaphore bit to request access */
1418 swsm |= IXGBE_SWSM_SWESMBI;
1419 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1420
1421 /*
1422 * If we set the bit successfully then we got the
1423 * semaphore.
1424 */
1425 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1426 if (swsm & IXGBE_SWSM_SWESMBI)
1427 break;
1428
1429 udelay(50);
1430 }
1431
1432 /*
1433 * Release semaphores and return error if SW EEPROM semaphore
1434 * was not granted because we don't have access to the EEPROM
1435 */
1436 if (i >= timeout) {
1437 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
1438 "not granted.\n");
1439 ixgbe_release_eeprom_semaphore(hw);
1440 status = IXGBE_ERR_EEPROM;
1441 }
1442 } else {
1443 hw_dbg(hw, "Software semaphore SMBI between device drivers "
1444 "not granted.\n");
1445 }
1446
1447 return status;
1448}
1449
1450/**
1451 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1452 * @hw: pointer to hardware structure
1453 *
1454 * This function clears hardware semaphore bits.
1455 **/
1456static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1457{
1458 u32 swsm;
1459
1460 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1461
1462 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1463 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1464 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1465 IXGBE_WRITE_FLUSH(hw);
1466}
1467
1468/**
1469 * ixgbe_ready_eeprom - Polls for EEPROM ready
1470 * @hw: pointer to hardware structure
1471 **/
1472static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1473{
1474 s32 status = 0;
1475 u16 i;
1476 u8 spi_stat_reg;
1477
1478 /*
1479 * Read "Status Register" repeatedly until the LSB is cleared. The
1480 * EEPROM will signal that the command has been completed by clearing
1481 * bit 0 of the internal status register. If it's not cleared within
1482 * 5 milliseconds, then error out.
1483 */
1484 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1485 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1486 IXGBE_EEPROM_OPCODE_BITS);
1487 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1488 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1489 break;
1490
1491 udelay(5);
1492 ixgbe_standby_eeprom(hw);
1493 }
1494
1495 /*
1496 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1497 * devices (and only 0-5mSec on 5V devices)
1498 */
1499 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1500 hw_dbg(hw, "SPI EEPROM Status error\n");
1501 status = IXGBE_ERR_EEPROM;
1502 }
1503
1504 return status;
1505}
1506
1507/**
1508 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1509 * @hw: pointer to hardware structure
1510 **/
1511static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1512{
1513 u32 eec;
1514
1515 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1516
1517 /* Toggle CS to flush commands */
1518 eec |= IXGBE_EEC_CS;
1519 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1520 IXGBE_WRITE_FLUSH(hw);
1521 udelay(1);
1522 eec &= ~IXGBE_EEC_CS;
1523 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1524 IXGBE_WRITE_FLUSH(hw);
1525 udelay(1);
1526}
1527
1528/**
1529 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1530 * @hw: pointer to hardware structure
1531 * @data: data to send to the EEPROM
1532 * @count: number of bits to shift out
1533 **/
1534static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1535 u16 count)
1536{
1537 u32 eec;
1538 u32 mask;
1539 u32 i;
1540
1541 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1542
1543 /*
1544 * Mask is used to shift "count" bits of "data" out to the EEPROM
1545 * one bit at a time. Determine the starting bit based on count
1546 */
1547 mask = 0x01 << (count - 1);
1548
1549 for (i = 0; i < count; i++) {
1550 /*
1551 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1552 * "1", and then raising and then lowering the clock (the SK
1553 * bit controls the clock input to the EEPROM). A "0" is
1554 * shifted out to the EEPROM by setting "DI" to "0" and then
1555 * raising and then lowering the clock.
1556 */
1557 if (data & mask)
1558 eec |= IXGBE_EEC_DI;
1559 else
1560 eec &= ~IXGBE_EEC_DI;
1561
1562 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1563 IXGBE_WRITE_FLUSH(hw);
1564
1565 udelay(1);
1566
1567 ixgbe_raise_eeprom_clk(hw, &eec);
1568 ixgbe_lower_eeprom_clk(hw, &eec);
1569
1570 /*
1571 * Shift mask to signify next bit of data to shift in to the
1572 * EEPROM
1573 */
1574 mask = mask >> 1;
1575 }
1576
1577 /* We leave the "DI" bit set to "0" when we leave this routine. */
1578 eec &= ~IXGBE_EEC_DI;
1579 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1580 IXGBE_WRITE_FLUSH(hw);
1581}
1582
1583/**
1584 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1585 * @hw: pointer to hardware structure
1586 **/
1587static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1588{
1589 u32 eec;
1590 u32 i;
1591 u16 data = 0;
1592
1593 /*
1594 * In order to read a register from the EEPROM, we need to shift
1595 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1596 * the clock input to the EEPROM (setting the SK bit), and then reading
1597 * the value of the "DO" bit. During this "shifting in" process the
1598 * "DI" bit should always be clear.
1599 */
1600 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1601
1602 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1603
1604 for (i = 0; i < count; i++) {
1605 data = data << 1;
1606 ixgbe_raise_eeprom_clk(hw, &eec);
1607
1608 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1609
1610 eec &= ~(IXGBE_EEC_DI);
1611 if (eec & IXGBE_EEC_DO)
1612 data |= 1;
1613
1614 ixgbe_lower_eeprom_clk(hw, &eec);
1615 }
1616
1617 return data;
1618}
1619
1620/**
1621 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1622 * @hw: pointer to hardware structure
1623 * @eec: EEC register's current value
1624 **/
1625static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1626{
1627 /*
1628 * Raise the clock input to the EEPROM
1629 * (setting the SK bit), then delay
1630 */
1631 *eec = *eec | IXGBE_EEC_SK;
1632 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1633 IXGBE_WRITE_FLUSH(hw);
1634 udelay(1);
1635}
1636
1637/**
1638 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1639 * @hw: pointer to hardware structure
1640 * @eecd: EECD's current value
1641 **/
1642static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1643{
1644 /*
1645 * Lower the clock input to the EEPROM (clearing the SK bit), then
1646 * delay
1647 */
1648 *eec = *eec & ~IXGBE_EEC_SK;
1649 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1650 IXGBE_WRITE_FLUSH(hw);
1651 udelay(1);
1652}
1653
1654/**
1655 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1656 * @hw: pointer to hardware structure
1657 **/
1658static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1659{
1660 u32 eec;
1661
1662 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1663
1664 eec |= IXGBE_EEC_CS; /* Pull CS high */
1665 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1666
1667 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1668 IXGBE_WRITE_FLUSH(hw);
1669
1670 udelay(1);
1671
1672 /* Stop requesting EEPROM access */
1673 eec &= ~IXGBE_EEC_REQ;
1674 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1675
1676 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1677
1678 /*
1679 * Delay before attempt to obtain semaphore again to allow FW
1680 * access. semaphore_delay is in ms we need us for usleep_range
1681 */
1682 usleep_range(hw->eeprom.semaphore_delay * 1000,
1683 hw->eeprom.semaphore_delay * 2000);
1684}
1685
1686/**
1687 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1688 * @hw: pointer to hardware structure
1689 **/
1690u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1691{
1692 u16 i;
1693 u16 j;
1694 u16 checksum = 0;
1695 u16 length = 0;
1696 u16 pointer = 0;
1697 u16 word = 0;
1698
1699 /* Include 0x0-0x3F in the checksum */
1700 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1701 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1702 hw_dbg(hw, "EEPROM read failed\n");
1703 break;
1704 }
1705 checksum += word;
1706 }
1707
1708 /* Include all data from pointers except for the fw pointer */
1709 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1710 hw->eeprom.ops.read(hw, i, &pointer);
1711
1712 /* Make sure the pointer seems valid */
1713 if (pointer != 0xFFFF && pointer != 0) {
1714 hw->eeprom.ops.read(hw, pointer, &length);
1715
1716 if (length != 0xFFFF && length != 0) {
1717 for (j = pointer+1; j <= pointer+length; j++) {
1718 hw->eeprom.ops.read(hw, j, &word);
1719 checksum += word;
1720 }
1721 }
1722 }
1723 }
1724
1725 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1726
1727 return checksum;
1728}
1729
1730/**
1731 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1732 * @hw: pointer to hardware structure
1733 * @checksum_val: calculated checksum
1734 *
1735 * Performs checksum calculation and validates the EEPROM checksum. If the
1736 * caller does not need checksum_val, the value can be NULL.
1737 **/
1738s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1739 u16 *checksum_val)
1740{
1741 s32 status;
1742 u16 checksum;
1743 u16 read_checksum = 0;
1744
1745 /*
1746 * Read the first word from the EEPROM. If this times out or fails, do
1747 * not continue or we could be in for a very long wait while every
1748 * EEPROM read fails
1749 */
1750 status = hw->eeprom.ops.read(hw, 0, &checksum);
1751
1752 if (status == 0) {
1753 checksum = hw->eeprom.ops.calc_checksum(hw);
1754
1755 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1756
1757 /*
1758 * Verify read checksum from EEPROM is the same as
1759 * calculated checksum
1760 */
1761 if (read_checksum != checksum)
1762 status = IXGBE_ERR_EEPROM_CHECKSUM;
1763
1764 /* If the user cares, return the calculated checksum */
1765 if (checksum_val)
1766 *checksum_val = checksum;
1767 } else {
1768 hw_dbg(hw, "EEPROM read failed\n");
1769 }
1770
1771 return status;
1772}
1773
1774/**
1775 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1776 * @hw: pointer to hardware structure
1777 **/
1778s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1779{
1780 s32 status;
1781 u16 checksum;
1782
1783 /*
1784 * Read the first word from the EEPROM. If this times out or fails, do
1785 * not continue or we could be in for a very long wait while every
1786 * EEPROM read fails
1787 */
1788 status = hw->eeprom.ops.read(hw, 0, &checksum);
1789
1790 if (status == 0) {
1791 checksum = hw->eeprom.ops.calc_checksum(hw);
1792 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1793 checksum);
1794 } else {
1795 hw_dbg(hw, "EEPROM read failed\n");
1796 }
1797
1798 return status;
1799}
1800
1801/**
1802 * ixgbe_set_rar_generic - Set Rx address register
1803 * @hw: pointer to hardware structure
1804 * @index: Receive address register to write
1805 * @addr: Address to put into receive address register
1806 * @vmdq: VMDq "set" or "pool" index
1807 * @enable_addr: set flag that address is active
1808 *
1809 * Puts an ethernet address into a receive address register.
1810 **/
1811s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1812 u32 enable_addr)
1813{
1814 u32 rar_low, rar_high;
1815 u32 rar_entries = hw->mac.num_rar_entries;
1816
1817 /* Make sure we are using a valid rar index range */
1818 if (index >= rar_entries) {
1819 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1820 return IXGBE_ERR_INVALID_ARGUMENT;
1821 }
1822
1823 /* setup VMDq pool selection before this RAR gets enabled */
1824 hw->mac.ops.set_vmdq(hw, index, vmdq);
1825
1826 /*
1827 * HW expects these in little endian so we reverse the byte
1828 * order from network order (big endian) to little endian
1829 */
1830 rar_low = ((u32)addr[0] |
1831 ((u32)addr[1] << 8) |
1832 ((u32)addr[2] << 16) |
1833 ((u32)addr[3] << 24));
1834 /*
1835 * Some parts put the VMDq setting in the extra RAH bits,
1836 * so save everything except the lower 16 bits that hold part
1837 * of the address and the address valid bit.
1838 */
1839 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1840 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1841 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1842
1843 if (enable_addr != 0)
1844 rar_high |= IXGBE_RAH_AV;
1845
1846 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1847 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1848
1849 return 0;
1850}
1851
1852/**
1853 * ixgbe_clear_rar_generic - Remove Rx address register
1854 * @hw: pointer to hardware structure
1855 * @index: Receive address register to write
1856 *
1857 * Clears an ethernet address from a receive address register.
1858 **/
1859s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1860{
1861 u32 rar_high;
1862 u32 rar_entries = hw->mac.num_rar_entries;
1863
1864 /* Make sure we are using a valid rar index range */
1865 if (index >= rar_entries) {
1866 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1867 return IXGBE_ERR_INVALID_ARGUMENT;
1868 }
1869
1870 /*
1871 * Some parts put the VMDq setting in the extra RAH bits,
1872 * so save everything except the lower 16 bits that hold part
1873 * of the address and the address valid bit.
1874 */
1875 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1876 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1877
1878 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1879 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1880
1881 /* clear VMDq pool/queue selection for this RAR */
1882 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1883
1884 return 0;
1885}
1886
1887/**
1888 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1889 * @hw: pointer to hardware structure
1890 *
1891 * Places the MAC address in receive address register 0 and clears the rest
1892 * of the receive address registers. Clears the multicast table. Assumes
1893 * the receiver is in reset when the routine is called.
1894 **/
1895s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1896{
1897 u32 i;
1898 u32 rar_entries = hw->mac.num_rar_entries;
1899
1900 /*
1901 * If the current mac address is valid, assume it is a software override
1902 * to the permanent address.
1903 * Otherwise, use the permanent address from the eeprom.
1904 */
1905 if (!is_valid_ether_addr(hw->mac.addr)) {
1906 /* Get the MAC address from the RAR0 for later reference */
1907 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1908
1909 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
1910 } else {
1911 /* Setup the receive address. */
1912 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1913 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
1914
1915 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1916
1917 /* clear VMDq pool/queue selection for RAR 0 */
1918 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
1919 }
1920 hw->addr_ctrl.overflow_promisc = 0;
1921
1922 hw->addr_ctrl.rar_used_count = 1;
1923
1924 /* Zero out the other receive addresses. */
1925 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1926 for (i = 1; i < rar_entries; i++) {
1927 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1928 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1929 }
1930
1931 /* Clear the MTA */
1932 hw->addr_ctrl.mta_in_use = 0;
1933 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1934
1935 hw_dbg(hw, " Clearing MTA\n");
1936 for (i = 0; i < hw->mac.mcft_size; i++)
1937 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1938
1939 if (hw->mac.ops.init_uta_tables)
1940 hw->mac.ops.init_uta_tables(hw);
1941
1942 return 0;
1943}
1944
1945/**
1946 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1947 * @hw: pointer to hardware structure
1948 * @mc_addr: the multicast address
1949 *
1950 * Extracts the 12 bits, from a multicast address, to determine which
1951 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1952 * incoming rx multicast addresses, to determine the bit-vector to check in
1953 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1954 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1955 * to mc_filter_type.
1956 **/
1957static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1958{
1959 u32 vector = 0;
1960
1961 switch (hw->mac.mc_filter_type) {
1962 case 0: /* use bits [47:36] of the address */
1963 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1964 break;
1965 case 1: /* use bits [46:35] of the address */
1966 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1967 break;
1968 case 2: /* use bits [45:34] of the address */
1969 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1970 break;
1971 case 3: /* use bits [43:32] of the address */
1972 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1973 break;
1974 default: /* Invalid mc_filter_type */
1975 hw_dbg(hw, "MC filter type param set incorrectly\n");
1976 break;
1977 }
1978
1979 /* vector can only be 12-bits or boundary will be exceeded */
1980 vector &= 0xFFF;
1981 return vector;
1982}
1983
1984/**
1985 * ixgbe_set_mta - Set bit-vector in multicast table
1986 * @hw: pointer to hardware structure
1987 * @hash_value: Multicast address hash value
1988 *
1989 * Sets the bit-vector in the multicast table.
1990 **/
1991static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1992{
1993 u32 vector;
1994 u32 vector_bit;
1995 u32 vector_reg;
1996
1997 hw->addr_ctrl.mta_in_use++;
1998
1999 vector = ixgbe_mta_vector(hw, mc_addr);
2000 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
2001
2002 /*
2003 * The MTA is a register array of 128 32-bit registers. It is treated
2004 * like an array of 4096 bits. We want to set bit
2005 * BitArray[vector_value]. So we figure out what register the bit is
2006 * in, read it, OR in the new bit, then write back the new value. The
2007 * register is determined by the upper 7 bits of the vector value and
2008 * the bit within that register are determined by the lower 5 bits of
2009 * the value.
2010 */
2011 vector_reg = (vector >> 5) & 0x7F;
2012 vector_bit = vector & 0x1F;
2013 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2014}
2015
2016/**
2017 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2018 * @hw: pointer to hardware structure
2019 * @netdev: pointer to net device structure
2020 *
2021 * The given list replaces any existing list. Clears the MC addrs from receive
2022 * address registers and the multicast table. Uses unused receive address
2023 * registers for the first multicast addresses, and hashes the rest into the
2024 * multicast table.
2025 **/
2026s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
2027 struct net_device *netdev)
2028{
2029 struct netdev_hw_addr *ha;
2030 u32 i;
2031
2032 /*
2033 * Set the new number of MC addresses that we are being requested to
2034 * use.
2035 */
2036 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
2037 hw->addr_ctrl.mta_in_use = 0;
2038
2039 /* Clear mta_shadow */
2040 hw_dbg(hw, " Clearing MTA\n");
2041 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2042
2043 /* Update mta shadow */
2044 netdev_for_each_mc_addr(ha, netdev) {
2045 hw_dbg(hw, " Adding the multicast addresses:\n");
2046 ixgbe_set_mta(hw, ha->addr);
2047 }
2048
2049 /* Enable mta */
2050 for (i = 0; i < hw->mac.mcft_size; i++)
2051 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2052 hw->mac.mta_shadow[i]);
2053
2054 if (hw->addr_ctrl.mta_in_use > 0)
2055 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2056 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2057
2058 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
2059 return 0;
2060}
2061
2062/**
2063 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2064 * @hw: pointer to hardware structure
2065 *
2066 * Enables multicast address in RAR and the use of the multicast hash table.
2067 **/
2068s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2069{
2070 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2071
2072 if (a->mta_in_use > 0)
2073 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2074 hw->mac.mc_filter_type);
2075
2076 return 0;
2077}
2078
2079/**
2080 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2081 * @hw: pointer to hardware structure
2082 *
2083 * Disables multicast address in RAR and the use of the multicast hash table.
2084 **/
2085s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2086{
2087 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2088
2089 if (a->mta_in_use > 0)
2090 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2091
2092 return 0;
2093}
2094
2095/**
2096 * ixgbe_fc_enable_generic - Enable flow control
2097 * @hw: pointer to hardware structure
2098 *
2099 * Enable flow control according to the current settings.
2100 **/
2101s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2102{
2103 s32 ret_val = 0;
2104 u32 mflcn_reg, fccfg_reg;
2105 u32 reg;
2106 u32 fcrtl, fcrth;
2107 int i;
2108
2109 /*
2110 * Validate the water mark configuration for packet buffer 0. Zero
2111 * water marks indicate that the packet buffer was not configured
2112 * and the watermarks for packet buffer 0 should always be configured.
2113 */
2114 if (!hw->fc.low_water ||
2115 !hw->fc.high_water[0] ||
2116 !hw->fc.pause_time) {
2117 hw_dbg(hw, "Invalid water mark configuration\n");
2118 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2119 goto out;
2120 }
2121
2122 /* Negotiate the fc mode to use */
2123 ixgbe_fc_autoneg(hw);
2124
2125 /* Disable any previous flow control settings */
2126 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2127 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2128
2129 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2130 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2131
2132 /*
2133 * The possible values of fc.current_mode are:
2134 * 0: Flow control is completely disabled
2135 * 1: Rx flow control is enabled (we can receive pause frames,
2136 * but not send pause frames).
2137 * 2: Tx flow control is enabled (we can send pause frames but
2138 * we do not support receiving pause frames).
2139 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2140 * other: Invalid.
2141 */
2142 switch (hw->fc.current_mode) {
2143 case ixgbe_fc_none:
2144 /*
2145 * Flow control is disabled by software override or autoneg.
2146 * The code below will actually disable it in the HW.
2147 */
2148 break;
2149 case ixgbe_fc_rx_pause:
2150 /*
2151 * Rx Flow control is enabled and Tx Flow control is
2152 * disabled by software override. Since there really
2153 * isn't a way to advertise that we are capable of RX
2154 * Pause ONLY, we will advertise that we support both
2155 * symmetric and asymmetric Rx PAUSE. Later, we will
2156 * disable the adapter's ability to send PAUSE frames.
2157 */
2158 mflcn_reg |= IXGBE_MFLCN_RFCE;
2159 break;
2160 case ixgbe_fc_tx_pause:
2161 /*
2162 * Tx Flow control is enabled, and Rx Flow control is
2163 * disabled by software override.
2164 */
2165 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2166 break;
2167 case ixgbe_fc_full:
2168 /* Flow control (both Rx and Tx) is enabled by SW override. */
2169 mflcn_reg |= IXGBE_MFLCN_RFCE;
2170 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2171 break;
2172 default:
2173 hw_dbg(hw, "Flow control param set incorrectly\n");
2174 ret_val = IXGBE_ERR_CONFIG;
2175 goto out;
2176 break;
2177 }
2178
2179 /* Set 802.3x based flow control settings. */
2180 mflcn_reg |= IXGBE_MFLCN_DPF;
2181 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2182 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2183
2184 fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE;
2185
2186 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2187 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2188 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2189 hw->fc.high_water[i]) {
2190 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2191 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2192 } else {
2193 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2194 /*
2195 * In order to prevent Tx hangs when the internal Tx
2196 * switch is enabled we must set the high water mark
2197 * to the maximum FCRTH value. This allows the Tx
2198 * switch to function even under heavy Rx workloads.
2199 */
2200 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2201 }
2202
2203 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2204 }
2205
2206 /* Configure pause time (2 TCs per register) */
2207 reg = hw->fc.pause_time * 0x00010001;
2208 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2209 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2210
2211 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2212
2213out:
2214 return ret_val;
2215}
2216
2217/**
2218 * ixgbe_negotiate_fc - Negotiate flow control
2219 * @hw: pointer to hardware structure
2220 * @adv_reg: flow control advertised settings
2221 * @lp_reg: link partner's flow control settings
2222 * @adv_sym: symmetric pause bit in advertisement
2223 * @adv_asm: asymmetric pause bit in advertisement
2224 * @lp_sym: symmetric pause bit in link partner advertisement
2225 * @lp_asm: asymmetric pause bit in link partner advertisement
2226 *
2227 * Find the intersection between advertised settings and link partner's
2228 * advertised settings
2229 **/
2230static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2231 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2232{
2233 if ((!(adv_reg)) || (!(lp_reg)))
2234 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2235
2236 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2237 /*
2238 * Now we need to check if the user selected Rx ONLY
2239 * of pause frames. In this case, we had to advertise
2240 * FULL flow control because we could not advertise RX
2241 * ONLY. Hence, we must now check to see if we need to
2242 * turn OFF the TRANSMISSION of PAUSE frames.
2243 */
2244 if (hw->fc.requested_mode == ixgbe_fc_full) {
2245 hw->fc.current_mode = ixgbe_fc_full;
2246 hw_dbg(hw, "Flow Control = FULL.\n");
2247 } else {
2248 hw->fc.current_mode = ixgbe_fc_rx_pause;
2249 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2250 }
2251 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2252 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2253 hw->fc.current_mode = ixgbe_fc_tx_pause;
2254 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2255 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2256 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2257 hw->fc.current_mode = ixgbe_fc_rx_pause;
2258 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2259 } else {
2260 hw->fc.current_mode = ixgbe_fc_none;
2261 hw_dbg(hw, "Flow Control = NONE.\n");
2262 }
2263 return 0;
2264}
2265
2266/**
2267 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2268 * @hw: pointer to hardware structure
2269 *
2270 * Enable flow control according on 1 gig fiber.
2271 **/
2272static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2273{
2274 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2275 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2276
2277 /*
2278 * On multispeed fiber at 1g, bail out if
2279 * - link is up but AN did not complete, or if
2280 * - link is up and AN completed but timed out
2281 */
2282
2283 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2284 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2285 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2286 goto out;
2287
2288 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2289 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2290
2291 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2292 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2293 IXGBE_PCS1GANA_ASM_PAUSE,
2294 IXGBE_PCS1GANA_SYM_PAUSE,
2295 IXGBE_PCS1GANA_ASM_PAUSE);
2296
2297out:
2298 return ret_val;
2299}
2300
2301/**
2302 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2303 * @hw: pointer to hardware structure
2304 *
2305 * Enable flow control according to IEEE clause 37.
2306 **/
2307static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2308{
2309 u32 links2, anlp1_reg, autoc_reg, links;
2310 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2311
2312 /*
2313 * On backplane, bail out if
2314 * - backplane autoneg was not completed, or if
2315 * - we are 82599 and link partner is not AN enabled
2316 */
2317 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2318 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2319 goto out;
2320
2321 if (hw->mac.type == ixgbe_mac_82599EB) {
2322 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2323 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2324 goto out;
2325 }
2326 /*
2327 * Read the 10g AN autoc and LP ability registers and resolve
2328 * local flow control settings accordingly
2329 */
2330 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2331 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2332
2333 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2334 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2335 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2336
2337out:
2338 return ret_val;
2339}
2340
2341/**
2342 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2343 * @hw: pointer to hardware structure
2344 *
2345 * Enable flow control according to IEEE clause 37.
2346 **/
2347static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2348{
2349 u16 technology_ability_reg = 0;
2350 u16 lp_technology_ability_reg = 0;
2351
2352 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2353 MDIO_MMD_AN,
2354 &technology_ability_reg);
2355 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2356 MDIO_MMD_AN,
2357 &lp_technology_ability_reg);
2358
2359 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2360 (u32)lp_technology_ability_reg,
2361 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2362 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2363}
2364
2365/**
2366 * ixgbe_fc_autoneg - Configure flow control
2367 * @hw: pointer to hardware structure
2368 *
2369 * Compares our advertised flow control capabilities to those advertised by
2370 * our link partner, and determines the proper flow control mode to use.
2371 **/
2372void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2373{
2374 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2375 ixgbe_link_speed speed;
2376 bool link_up;
2377
2378 /*
2379 * AN should have completed when the cable was plugged in.
2380 * Look for reasons to bail out. Bail out if:
2381 * - FC autoneg is disabled, or if
2382 * - link is not up.
2383 *
2384 * Since we're being called from an LSC, link is already known to be up.
2385 * So use link_up_wait_to_complete=false.
2386 */
2387 if (hw->fc.disable_fc_autoneg)
2388 goto out;
2389
2390 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2391 if (!link_up)
2392 goto out;
2393
2394 switch (hw->phy.media_type) {
2395 /* Autoneg flow control on fiber adapters */
2396 case ixgbe_media_type_fiber:
2397 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2398 ret_val = ixgbe_fc_autoneg_fiber(hw);
2399 break;
2400
2401 /* Autoneg flow control on backplane adapters */
2402 case ixgbe_media_type_backplane:
2403 ret_val = ixgbe_fc_autoneg_backplane(hw);
2404 break;
2405
2406 /* Autoneg flow control on copper adapters */
2407 case ixgbe_media_type_copper:
2408 if (ixgbe_device_supports_autoneg_fc(hw))
2409 ret_val = ixgbe_fc_autoneg_copper(hw);
2410 break;
2411
2412 default:
2413 break;
2414 }
2415
2416out:
2417 if (ret_val == 0) {
2418 hw->fc.fc_was_autonegged = true;
2419 } else {
2420 hw->fc.fc_was_autonegged = false;
2421 hw->fc.current_mode = hw->fc.requested_mode;
2422 }
2423}
2424
2425/**
2426 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
2427 * @hw: pointer to hardware structure
2428 *
2429 * System-wide timeout range is encoded in PCIe Device Control2 register.
2430 *
2431 * Add 10% to specified maximum and return the number of times to poll for
2432 * completion timeout, in units of 100 microsec. Never return less than
2433 * 800 = 80 millisec.
2434 **/
2435static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
2436{
2437 s16 devctl2;
2438 u32 pollcnt;
2439
2440 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
2441 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
2442
2443 switch (devctl2) {
2444 case IXGBE_PCIDEVCTRL2_65_130ms:
2445 pollcnt = 1300; /* 130 millisec */
2446 break;
2447 case IXGBE_PCIDEVCTRL2_260_520ms:
2448 pollcnt = 5200; /* 520 millisec */
2449 break;
2450 case IXGBE_PCIDEVCTRL2_1_2s:
2451 pollcnt = 20000; /* 2 sec */
2452 break;
2453 case IXGBE_PCIDEVCTRL2_4_8s:
2454 pollcnt = 80000; /* 8 sec */
2455 break;
2456 case IXGBE_PCIDEVCTRL2_17_34s:
2457 pollcnt = 34000; /* 34 sec */
2458 break;
2459 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
2460 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
2461 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
2462 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
2463 default:
2464 pollcnt = 800; /* 80 millisec minimum */
2465 break;
2466 }
2467
2468 /* add 10% to spec maximum */
2469 return (pollcnt * 11) / 10;
2470}
2471
2472/**
2473 * ixgbe_disable_pcie_master - Disable PCI-express master access
2474 * @hw: pointer to hardware structure
2475 *
2476 * Disables PCI-Express master access and verifies there are no pending
2477 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2478 * bit hasn't caused the master requests to be disabled, else 0
2479 * is returned signifying master requests disabled.
2480 **/
2481static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2482{
2483 s32 status = 0;
2484 u32 i, poll;
2485 u16 value;
2486
2487 /* Always set this bit to ensure any future transactions are blocked */
2488 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2489
2490 /* Exit if master requests are blocked */
2491 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
2492 ixgbe_removed(hw->hw_addr))
2493 goto out;
2494
2495 /* Poll for master request bit to clear */
2496 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2497 udelay(100);
2498 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2499 goto out;
2500 }
2501
2502 /*
2503 * Two consecutive resets are required via CTRL.RST per datasheet
2504 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2505 * of this need. The first reset prevents new master requests from
2506 * being issued by our device. We then must wait 1usec or more for any
2507 * remaining completions from the PCIe bus to trickle in, and then reset
2508 * again to clear out any effects they may have had on our device.
2509 */
2510 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2511 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2512
2513 /*
2514 * Before proceeding, make sure that the PCIe block does not have
2515 * transactions pending.
2516 */
2517 poll = ixgbe_pcie_timeout_poll(hw);
2518 for (i = 0; i < poll; i++) {
2519 udelay(100);
2520 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
2521 if (ixgbe_removed(hw->hw_addr))
2522 goto out;
2523 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2524 goto out;
2525 }
2526
2527 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2528 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2529
2530out:
2531 return status;
2532}
2533
2534/**
2535 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2536 * @hw: pointer to hardware structure
2537 * @mask: Mask to specify which semaphore to acquire
2538 *
2539 * Acquires the SWFW semaphore through the GSSR register for the specified
2540 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2541 **/
2542s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2543{
2544 u32 gssr = 0;
2545 u32 swmask = mask;
2546 u32 fwmask = mask << 5;
2547 u32 timeout = 200;
2548 u32 i;
2549
2550 for (i = 0; i < timeout; i++) {
2551 /*
2552 * SW NVM semaphore bit is used for access to all
2553 * SW_FW_SYNC bits (not just NVM)
2554 */
2555 if (ixgbe_get_eeprom_semaphore(hw))
2556 return IXGBE_ERR_SWFW_SYNC;
2557
2558 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2559 if (!(gssr & (fwmask | swmask))) {
2560 gssr |= swmask;
2561 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2562 ixgbe_release_eeprom_semaphore(hw);
2563 return 0;
2564 } else {
2565 /* Resource is currently in use by FW or SW */
2566 ixgbe_release_eeprom_semaphore(hw);
2567 usleep_range(5000, 10000);
2568 }
2569 }
2570
2571 /* If time expired clear the bits holding the lock and retry */
2572 if (gssr & (fwmask | swmask))
2573 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
2574
2575 usleep_range(5000, 10000);
2576 return IXGBE_ERR_SWFW_SYNC;
2577}
2578
2579/**
2580 * ixgbe_release_swfw_sync - Release SWFW semaphore
2581 * @hw: pointer to hardware structure
2582 * @mask: Mask to specify which semaphore to release
2583 *
2584 * Releases the SWFW semaphore through the GSSR register for the specified
2585 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2586 **/
2587void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2588{
2589 u32 gssr;
2590 u32 swmask = mask;
2591
2592 ixgbe_get_eeprom_semaphore(hw);
2593
2594 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2595 gssr &= ~swmask;
2596 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2597
2598 ixgbe_release_eeprom_semaphore(hw);
2599}
2600
2601/**
2602 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
2603 * @hw: pointer to hardware structure
2604 * @reg_val: Value we read from AUTOC
2605 * @locked: bool to indicate whether the SW/FW lock should be taken. Never
2606 * true in this the generic case.
2607 *
2608 * The default case requires no protection so just to the register read.
2609 **/
2610s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
2611{
2612 *locked = false;
2613 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2614 return 0;
2615}
2616
2617/**
2618 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
2619 * @hw: pointer to hardware structure
2620 * @reg_val: value to write to AUTOC
2621 * @locked: bool to indicate whether the SW/FW lock was already taken by
2622 * previous read.
2623 **/
2624s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
2625{
2626 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
2627 return 0;
2628}
2629
2630/**
2631 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2632 * @hw: pointer to hardware structure
2633 *
2634 * Stops the receive data path and waits for the HW to internally
2635 * empty the Rx security block.
2636 **/
2637s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2638{
2639#define IXGBE_MAX_SECRX_POLL 40
2640 int i;
2641 int secrxreg;
2642
2643 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2644 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2645 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2646 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2647 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2648 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2649 break;
2650 else
2651 /* Use interrupt-safe sleep just in case */
2652 udelay(1000);
2653 }
2654
2655 /* For informational purposes only */
2656 if (i >= IXGBE_MAX_SECRX_POLL)
2657 hw_dbg(hw, "Rx unit being enabled before security "
2658 "path fully disabled. Continuing with init.\n");
2659
2660 return 0;
2661
2662}
2663
2664/**
2665 * ixgbe_enable_rx_buff - Enables the receive data path
2666 * @hw: pointer to hardware structure
2667 *
2668 * Enables the receive data path
2669 **/
2670s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2671{
2672 int secrxreg;
2673
2674 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2675 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2676 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2677 IXGBE_WRITE_FLUSH(hw);
2678
2679 return 0;
2680}
2681
2682/**
2683 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2684 * @hw: pointer to hardware structure
2685 * @regval: register value to write to RXCTRL
2686 *
2687 * Enables the Rx DMA unit
2688 **/
2689s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2690{
2691 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2692
2693 return 0;
2694}
2695
2696/**
2697 * ixgbe_blink_led_start_generic - Blink LED based on index.
2698 * @hw: pointer to hardware structure
2699 * @index: led number to blink
2700 **/
2701s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2702{
2703 ixgbe_link_speed speed = 0;
2704 bool link_up = false;
2705 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2706 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2707 s32 ret_val = 0;
2708 bool locked = false;
2709
2710 /*
2711 * Link must be up to auto-blink the LEDs;
2712 * Force it if link is down.
2713 */
2714 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2715
2716 if (!link_up) {
2717 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
2718 if (ret_val)
2719 goto out;
2720
2721 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2722 autoc_reg |= IXGBE_AUTOC_FLU;
2723
2724 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
2725 if (ret_val)
2726 goto out;
2727
2728 IXGBE_WRITE_FLUSH(hw);
2729
2730 usleep_range(10000, 20000);
2731 }
2732
2733 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2734 led_reg |= IXGBE_LED_BLINK(index);
2735 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2736 IXGBE_WRITE_FLUSH(hw);
2737
2738out:
2739 return ret_val;
2740}
2741
2742/**
2743 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2744 * @hw: pointer to hardware structure
2745 * @index: led number to stop blinking
2746 **/
2747s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2748{
2749 u32 autoc_reg = 0;
2750 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2751 s32 ret_val = 0;
2752 bool locked = false;
2753
2754 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
2755 if (ret_val)
2756 goto out;
2757
2758 autoc_reg &= ~IXGBE_AUTOC_FLU;
2759 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2760
2761 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
2762 if (ret_val)
2763 goto out;
2764
2765 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2766 led_reg &= ~IXGBE_LED_BLINK(index);
2767 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2768 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2769 IXGBE_WRITE_FLUSH(hw);
2770
2771out:
2772 return ret_val;
2773}
2774
2775/**
2776 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2777 * @hw: pointer to hardware structure
2778 * @san_mac_offset: SAN MAC address offset
2779 *
2780 * This function will read the EEPROM location for the SAN MAC address
2781 * pointer, and returns the value at that location. This is used in both
2782 * get and set mac_addr routines.
2783 **/
2784static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2785 u16 *san_mac_offset)
2786{
2787 s32 ret_val;
2788
2789 /*
2790 * First read the EEPROM pointer to see if the MAC addresses are
2791 * available.
2792 */
2793 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
2794 san_mac_offset);
2795 if (ret_val)
2796 hw_err(hw, "eeprom read at offset %d failed\n",
2797 IXGBE_SAN_MAC_ADDR_PTR);
2798
2799 return ret_val;
2800}
2801
2802/**
2803 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2804 * @hw: pointer to hardware structure
2805 * @san_mac_addr: SAN MAC address
2806 *
2807 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2808 * per-port, so set_lan_id() must be called before reading the addresses.
2809 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2810 * upon for non-SFP connections, so we must call it here.
2811 **/
2812s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2813{
2814 u16 san_mac_data, san_mac_offset;
2815 u8 i;
2816 s32 ret_val;
2817
2818 /*
2819 * First read the EEPROM pointer to see if the MAC addresses are
2820 * available. If they're not, no point in calling set_lan_id() here.
2821 */
2822 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2823 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
2824
2825 goto san_mac_addr_clr;
2826
2827 /* make sure we know which port we need to program */
2828 hw->mac.ops.set_lan_id(hw);
2829 /* apply the port offset to the address offset */
2830 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2831 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2832 for (i = 0; i < 3; i++) {
2833 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
2834 &san_mac_data);
2835 if (ret_val) {
2836 hw_err(hw, "eeprom read at offset %d failed\n",
2837 san_mac_offset);
2838 goto san_mac_addr_clr;
2839 }
2840 san_mac_addr[i * 2] = (u8)(san_mac_data);
2841 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2842 san_mac_offset++;
2843 }
2844 return 0;
2845
2846san_mac_addr_clr:
2847 /* No addresses available in this EEPROM. It's not necessarily an
2848 * error though, so just wipe the local address and return.
2849 */
2850 for (i = 0; i < 6; i++)
2851 san_mac_addr[i] = 0xFF;
2852 return ret_val;
2853}
2854
2855/**
2856 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2857 * @hw: pointer to hardware structure
2858 *
2859 * Read PCIe configuration space, and get the MSI-X vector count from
2860 * the capabilities table.
2861 **/
2862u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2863{
2864 u16 msix_count = 1;
2865 u16 max_msix_count;
2866 u16 pcie_offset;
2867
2868 switch (hw->mac.type) {
2869 case ixgbe_mac_82598EB:
2870 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2871 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2872 break;
2873 case ixgbe_mac_82599EB:
2874 case ixgbe_mac_X540:
2875 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2876 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2877 break;
2878 default:
2879 return msix_count;
2880 }
2881
2882 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset);
2883 if (ixgbe_removed(hw->hw_addr))
2884 msix_count = 0;
2885 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2886
2887 /* MSI-X count is zero-based in HW */
2888 msix_count++;
2889
2890 if (msix_count > max_msix_count)
2891 msix_count = max_msix_count;
2892
2893 return msix_count;
2894}
2895
2896/**
2897 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2898 * @hw: pointer to hardware struct
2899 * @rar: receive address register index to disassociate
2900 * @vmdq: VMDq pool index to remove from the rar
2901 **/
2902s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2903{
2904 u32 mpsar_lo, mpsar_hi;
2905 u32 rar_entries = hw->mac.num_rar_entries;
2906
2907 /* Make sure we are using a valid rar index range */
2908 if (rar >= rar_entries) {
2909 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2910 return IXGBE_ERR_INVALID_ARGUMENT;
2911 }
2912
2913 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2914 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2915
2916 if (ixgbe_removed(hw->hw_addr))
2917 goto done;
2918
2919 if (!mpsar_lo && !mpsar_hi)
2920 goto done;
2921
2922 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2923 if (mpsar_lo) {
2924 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2925 mpsar_lo = 0;
2926 }
2927 if (mpsar_hi) {
2928 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2929 mpsar_hi = 0;
2930 }
2931 } else if (vmdq < 32) {
2932 mpsar_lo &= ~(1 << vmdq);
2933 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2934 } else {
2935 mpsar_hi &= ~(1 << (vmdq - 32));
2936 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2937 }
2938
2939 /* was that the last pool using this rar? */
2940 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2941 hw->mac.ops.clear_rar(hw, rar);
2942done:
2943 return 0;
2944}
2945
2946/**
2947 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2948 * @hw: pointer to hardware struct
2949 * @rar: receive address register index to associate with a VMDq index
2950 * @vmdq: VMDq pool index
2951 **/
2952s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2953{
2954 u32 mpsar;
2955 u32 rar_entries = hw->mac.num_rar_entries;
2956
2957 /* Make sure we are using a valid rar index range */
2958 if (rar >= rar_entries) {
2959 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2960 return IXGBE_ERR_INVALID_ARGUMENT;
2961 }
2962
2963 if (vmdq < 32) {
2964 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2965 mpsar |= 1 << vmdq;
2966 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2967 } else {
2968 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2969 mpsar |= 1 << (vmdq - 32);
2970 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2971 }
2972 return 0;
2973}
2974
2975/**
2976 * This function should only be involved in the IOV mode.
2977 * In IOV mode, Default pool is next pool after the number of
2978 * VFs advertized and not 0.
2979 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
2980 *
2981 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
2982 * @hw: pointer to hardware struct
2983 * @vmdq: VMDq pool index
2984 **/
2985s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
2986{
2987 u32 rar = hw->mac.san_mac_rar_index;
2988
2989 if (vmdq < 32) {
2990 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
2991 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2992 } else {
2993 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2994 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
2995 }
2996
2997 return 0;
2998}
2999
3000/**
3001 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3002 * @hw: pointer to hardware structure
3003 **/
3004s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3005{
3006 int i;
3007
3008 for (i = 0; i < 128; i++)
3009 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3010
3011 return 0;
3012}
3013
3014/**
3015 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3016 * @hw: pointer to hardware structure
3017 * @vlan: VLAN id to write to VLAN filter
3018 *
3019 * return the VLVF index where this VLAN id should be placed
3020 *
3021 **/
3022static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3023{
3024 u32 bits = 0;
3025 u32 first_empty_slot = 0;
3026 s32 regindex;
3027
3028 /* short cut the special case */
3029 if (vlan == 0)
3030 return 0;
3031
3032 /*
3033 * Search for the vlan id in the VLVF entries. Save off the first empty
3034 * slot found along the way
3035 */
3036 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3037 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3038 if (!bits && !(first_empty_slot))
3039 first_empty_slot = regindex;
3040 else if ((bits & 0x0FFF) == vlan)
3041 break;
3042 }
3043
3044 /*
3045 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3046 * in the VLVF. Else use the first empty VLVF register for this
3047 * vlan id.
3048 */
3049 if (regindex >= IXGBE_VLVF_ENTRIES) {
3050 if (first_empty_slot)
3051 regindex = first_empty_slot;
3052 else {
3053 hw_dbg(hw, "No space in VLVF.\n");
3054 regindex = IXGBE_ERR_NO_SPACE;
3055 }
3056 }
3057
3058 return regindex;
3059}
3060
3061/**
3062 * ixgbe_set_vfta_generic - Set VLAN filter table
3063 * @hw: pointer to hardware structure
3064 * @vlan: VLAN id to write to VLAN filter
3065 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3066 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3067 *
3068 * Turn on/off specified VLAN in the VLAN filter table.
3069 **/
3070s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3071 bool vlan_on)
3072{
3073 s32 regindex;
3074 u32 bitindex;
3075 u32 vfta;
3076 u32 bits;
3077 u32 vt;
3078 u32 targetbit;
3079 bool vfta_changed = false;
3080
3081 if (vlan > 4095)
3082 return IXGBE_ERR_PARAM;
3083
3084 /*
3085 * this is a 2 part operation - first the VFTA, then the
3086 * VLVF and VLVFB if VT Mode is set
3087 * We don't write the VFTA until we know the VLVF part succeeded.
3088 */
3089
3090 /* Part 1
3091 * The VFTA is a bitstring made up of 128 32-bit registers
3092 * that enable the particular VLAN id, much like the MTA:
3093 * bits[11-5]: which register
3094 * bits[4-0]: which bit in the register
3095 */
3096 regindex = (vlan >> 5) & 0x7F;
3097 bitindex = vlan & 0x1F;
3098 targetbit = (1 << bitindex);
3099 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3100
3101 if (vlan_on) {
3102 if (!(vfta & targetbit)) {
3103 vfta |= targetbit;
3104 vfta_changed = true;
3105 }
3106 } else {
3107 if ((vfta & targetbit)) {
3108 vfta &= ~targetbit;
3109 vfta_changed = true;
3110 }
3111 }
3112
3113 /* Part 2
3114 * If VT Mode is set
3115 * Either vlan_on
3116 * make sure the vlan is in VLVF
3117 * set the vind bit in the matching VLVFB
3118 * Or !vlan_on
3119 * clear the pool bit and possibly the vind
3120 */
3121 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3122 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3123 s32 vlvf_index;
3124
3125 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3126 if (vlvf_index < 0)
3127 return vlvf_index;
3128
3129 if (vlan_on) {
3130 /* set the pool bit */
3131 if (vind < 32) {
3132 bits = IXGBE_READ_REG(hw,
3133 IXGBE_VLVFB(vlvf_index*2));
3134 bits |= (1 << vind);
3135 IXGBE_WRITE_REG(hw,
3136 IXGBE_VLVFB(vlvf_index*2),
3137 bits);
3138 } else {
3139 bits = IXGBE_READ_REG(hw,
3140 IXGBE_VLVFB((vlvf_index*2)+1));
3141 bits |= (1 << (vind-32));
3142 IXGBE_WRITE_REG(hw,
3143 IXGBE_VLVFB((vlvf_index*2)+1),
3144 bits);
3145 }
3146 } else {
3147 /* clear the pool bit */
3148 if (vind < 32) {
3149 bits = IXGBE_READ_REG(hw,
3150 IXGBE_VLVFB(vlvf_index*2));
3151 bits &= ~(1 << vind);
3152 IXGBE_WRITE_REG(hw,
3153 IXGBE_VLVFB(vlvf_index*2),
3154 bits);
3155 bits |= IXGBE_READ_REG(hw,
3156 IXGBE_VLVFB((vlvf_index*2)+1));
3157 } else {
3158 bits = IXGBE_READ_REG(hw,
3159 IXGBE_VLVFB((vlvf_index*2)+1));
3160 bits &= ~(1 << (vind-32));
3161 IXGBE_WRITE_REG(hw,
3162 IXGBE_VLVFB((vlvf_index*2)+1),
3163 bits);
3164 bits |= IXGBE_READ_REG(hw,
3165 IXGBE_VLVFB(vlvf_index*2));
3166 }
3167 }
3168
3169 /*
3170 * If there are still bits set in the VLVFB registers
3171 * for the VLAN ID indicated we need to see if the
3172 * caller is requesting that we clear the VFTA entry bit.
3173 * If the caller has requested that we clear the VFTA
3174 * entry bit but there are still pools/VFs using this VLAN
3175 * ID entry then ignore the request. We're not worried
3176 * about the case where we're turning the VFTA VLAN ID
3177 * entry bit on, only when requested to turn it off as
3178 * there may be multiple pools and/or VFs using the
3179 * VLAN ID entry. In that case we cannot clear the
3180 * VFTA bit until all pools/VFs using that VLAN ID have also
3181 * been cleared. This will be indicated by "bits" being
3182 * zero.
3183 */
3184 if (bits) {
3185 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3186 (IXGBE_VLVF_VIEN | vlan));
3187 if (!vlan_on) {
3188 /* someone wants to clear the vfta entry
3189 * but some pools/VFs are still using it.
3190 * Ignore it. */
3191 vfta_changed = false;
3192 }
3193 }
3194 else
3195 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3196 }
3197
3198 if (vfta_changed)
3199 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3200
3201 return 0;
3202}
3203
3204/**
3205 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3206 * @hw: pointer to hardware structure
3207 *
3208 * Clears the VLAN filer table, and the VMDq index associated with the filter
3209 **/
3210s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3211{
3212 u32 offset;
3213
3214 for (offset = 0; offset < hw->mac.vft_size; offset++)
3215 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3216
3217 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3218 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3219 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3220 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3221 }
3222
3223 return 0;
3224}
3225
3226/**
3227 * ixgbe_check_mac_link_generic - Determine link and speed status
3228 * @hw: pointer to hardware structure
3229 * @speed: pointer to link speed
3230 * @link_up: true when link is up
3231 * @link_up_wait_to_complete: bool used to wait for link up or not
3232 *
3233 * Reads the links register to determine if link is up and the current speed
3234 **/
3235s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3236 bool *link_up, bool link_up_wait_to_complete)
3237{
3238 u32 links_reg, links_orig;
3239 u32 i;
3240
3241 /* clear the old state */
3242 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3243
3244 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3245
3246 if (links_orig != links_reg) {
3247 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3248 links_orig, links_reg);
3249 }
3250
3251 if (link_up_wait_to_complete) {
3252 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3253 if (links_reg & IXGBE_LINKS_UP) {
3254 *link_up = true;
3255 break;
3256 } else {
3257 *link_up = false;
3258 }
3259 msleep(100);
3260 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3261 }
3262 } else {
3263 if (links_reg & IXGBE_LINKS_UP)
3264 *link_up = true;
3265 else
3266 *link_up = false;
3267 }
3268
3269 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3270 IXGBE_LINKS_SPEED_10G_82599)
3271 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3272 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3273 IXGBE_LINKS_SPEED_1G_82599)
3274 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3275 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3276 IXGBE_LINKS_SPEED_100_82599)
3277 *speed = IXGBE_LINK_SPEED_100_FULL;
3278 else
3279 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3280
3281 return 0;
3282}
3283
3284/**
3285 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3286 * the EEPROM
3287 * @hw: pointer to hardware structure
3288 * @wwnn_prefix: the alternative WWNN prefix
3289 * @wwpn_prefix: the alternative WWPN prefix
3290 *
3291 * This function will read the EEPROM from the alternative SAN MAC address
3292 * block to check the support for the alternative WWNN/WWPN prefix support.
3293 **/
3294s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3295 u16 *wwpn_prefix)
3296{
3297 u16 offset, caps;
3298 u16 alt_san_mac_blk_offset;
3299
3300 /* clear output first */
3301 *wwnn_prefix = 0xFFFF;
3302 *wwpn_prefix = 0xFFFF;
3303
3304 /* check if alternative SAN MAC is supported */
3305 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
3306 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
3307 goto wwn_prefix_err;
3308
3309 if ((alt_san_mac_blk_offset == 0) ||
3310 (alt_san_mac_blk_offset == 0xFFFF))
3311 goto wwn_prefix_out;
3312
3313 /* check capability in alternative san mac address block */
3314 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3315 if (hw->eeprom.ops.read(hw, offset, &caps))
3316 goto wwn_prefix_err;
3317 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3318 goto wwn_prefix_out;
3319
3320 /* get the corresponding prefix for WWNN/WWPN */
3321 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3322 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
3323 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3324
3325 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3326 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
3327 goto wwn_prefix_err;
3328
3329wwn_prefix_out:
3330 return 0;
3331
3332wwn_prefix_err:
3333 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3334 return 0;
3335}
3336
3337/**
3338 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3339 * @hw: pointer to hardware structure
3340 * @enable: enable or disable switch for anti-spoofing
3341 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3342 *
3343 **/
3344void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3345{
3346 int j;
3347 int pf_target_reg = pf >> 3;
3348 int pf_target_shift = pf % 8;
3349 u32 pfvfspoof = 0;
3350
3351 if (hw->mac.type == ixgbe_mac_82598EB)
3352 return;
3353
3354 if (enable)
3355 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3356
3357 /*
3358 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3359 * MAC anti-spoof enables in each register array element.
3360 */
3361 for (j = 0; j < pf_target_reg; j++)
3362 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3363
3364 /*
3365 * The PF should be allowed to spoof so that it can support
3366 * emulation mode NICs. Do not set the bits assigned to the PF
3367 */
3368 pfvfspoof &= (1 << pf_target_shift) - 1;
3369 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3370
3371 /*
3372 * Remaining pools belong to the PF so they do not need to have
3373 * anti-spoofing enabled.
3374 */
3375 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3376 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
3377}
3378
3379/**
3380 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3381 * @hw: pointer to hardware structure
3382 * @enable: enable or disable switch for VLAN anti-spoofing
3383 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3384 *
3385 **/
3386void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3387{
3388 int vf_target_reg = vf >> 3;
3389 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3390 u32 pfvfspoof;
3391
3392 if (hw->mac.type == ixgbe_mac_82598EB)
3393 return;
3394
3395 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3396 if (enable)
3397 pfvfspoof |= (1 << vf_target_shift);
3398 else
3399 pfvfspoof &= ~(1 << vf_target_shift);
3400 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3401}
3402
3403/**
3404 * ixgbe_get_device_caps_generic - Get additional device capabilities
3405 * @hw: pointer to hardware structure
3406 * @device_caps: the EEPROM word with the extra device capabilities
3407 *
3408 * This function will read the EEPROM location for the device capabilities,
3409 * and return the word through device_caps.
3410 **/
3411s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3412{
3413 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3414
3415 return 0;
3416}
3417
3418/**
3419 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3420 * @hw: pointer to hardware structure
3421 * @num_pb: number of packet buffers to allocate
3422 * @headroom: reserve n KB of headroom
3423 * @strategy: packet buffer allocation strategy
3424 **/
3425void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3426 int num_pb,
3427 u32 headroom,
3428 int strategy)
3429{
3430 u32 pbsize = hw->mac.rx_pb_size;
3431 int i = 0;
3432 u32 rxpktsize, txpktsize, txpbthresh;
3433
3434 /* Reserve headroom */
3435 pbsize -= headroom;
3436
3437 if (!num_pb)
3438 num_pb = 1;
3439
3440 /* Divide remaining packet buffer space amongst the number
3441 * of packet buffers requested using supplied strategy.
3442 */
3443 switch (strategy) {
3444 case (PBA_STRATEGY_WEIGHTED):
3445 /* pba_80_48 strategy weight first half of packet buffer with
3446 * 5/8 of the packet buffer space.
3447 */
3448 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3449 pbsize -= rxpktsize * (num_pb / 2);
3450 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3451 for (; i < (num_pb / 2); i++)
3452 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3453 /* Fall through to configure remaining packet buffers */
3454 case (PBA_STRATEGY_EQUAL):
3455 /* Divide the remaining Rx packet buffer evenly among the TCs */
3456 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3457 for (; i < num_pb; i++)
3458 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3459 break;
3460 default:
3461 break;
3462 }
3463
3464 /*
3465 * Setup Tx packet buffer and threshold equally for all TCs
3466 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3467 * 10 since the largest packet we support is just over 9K.
3468 */
3469 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3470 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3471 for (i = 0; i < num_pb; i++) {
3472 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3473 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3474 }
3475
3476 /* Clear unused TCs, if any, to zero buffer size*/
3477 for (; i < IXGBE_MAX_PB; i++) {
3478 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3479 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3480 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3481 }
3482}
3483
3484/**
3485 * ixgbe_calculate_checksum - Calculate checksum for buffer
3486 * @buffer: pointer to EEPROM
3487 * @length: size of EEPROM to calculate a checksum for
3488 *
3489 * Calculates the checksum for some buffer on a specified length. The
3490 * checksum calculated is returned.
3491 **/
3492static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3493{
3494 u32 i;
3495 u8 sum = 0;
3496
3497 if (!buffer)
3498 return 0;
3499
3500 for (i = 0; i < length; i++)
3501 sum += buffer[i];
3502
3503 return (u8) (0 - sum);
3504}
3505
3506/**
3507 * ixgbe_host_interface_command - Issue command to manageability block
3508 * @hw: pointer to the HW structure
3509 * @buffer: contains the command to write and where the return status will
3510 * be placed
3511 * @length: length of buffer, must be multiple of 4 bytes
3512 *
3513 * Communicates with the manageability block. On success return 0
3514 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3515 **/
3516static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3517 u32 length)
3518{
3519 u32 hicr, i, bi;
3520 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3521 u8 buf_len, dword_len;
3522
3523 s32 ret_val = 0;
3524
3525 if (length == 0 || length & 0x3 ||
3526 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3527 hw_dbg(hw, "Buffer length failure.\n");
3528 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3529 goto out;
3530 }
3531
3532 /* Check that the host interface is enabled. */
3533 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3534 if ((hicr & IXGBE_HICR_EN) == 0) {
3535 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3536 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3537 goto out;
3538 }
3539
3540 /* Calculate length in DWORDs */
3541 dword_len = length >> 2;
3542
3543 /*
3544 * The device driver writes the relevant command block
3545 * into the ram area.
3546 */
3547 for (i = 0; i < dword_len; i++)
3548 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3549 i, cpu_to_le32(buffer[i]));
3550
3551 /* Setting this bit tells the ARC that a new command is pending. */
3552 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3553
3554 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3555 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3556 if (!(hicr & IXGBE_HICR_C))
3557 break;
3558 usleep_range(1000, 2000);
3559 }
3560
3561 /* Check command successful completion. */
3562 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3563 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3564 hw_dbg(hw, "Command has failed with no status valid.\n");
3565 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3566 goto out;
3567 }
3568
3569 /* Calculate length in DWORDs */
3570 dword_len = hdr_size >> 2;
3571
3572 /* first pull in the header so we know the buffer length */
3573 for (bi = 0; bi < dword_len; bi++) {
3574 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3575 le32_to_cpus(&buffer[bi]);
3576 }
3577
3578 /* If there is any thing in data position pull it in */
3579 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3580 if (buf_len == 0)
3581 goto out;
3582
3583 if (length < (buf_len + hdr_size)) {
3584 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3585 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3586 goto out;
3587 }
3588
3589 /* Calculate length in DWORDs, add 3 for odd lengths */
3590 dword_len = (buf_len + 3) >> 2;
3591
3592 /* Pull in the rest of the buffer (bi is where we left off)*/
3593 for (; bi <= dword_len; bi++) {
3594 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3595 le32_to_cpus(&buffer[bi]);
3596 }
3597
3598out:
3599 return ret_val;
3600}
3601
3602/**
3603 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3604 * @hw: pointer to the HW structure
3605 * @maj: driver version major number
3606 * @min: driver version minor number
3607 * @build: driver version build number
3608 * @sub: driver version sub build number
3609 *
3610 * Sends driver version number to firmware through the manageability
3611 * block. On success return 0
3612 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3613 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3614 **/
3615s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3616 u8 build, u8 sub)
3617{
3618 struct ixgbe_hic_drv_info fw_cmd;
3619 int i;
3620 s32 ret_val = 0;
3621
3622 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) {
3623 ret_val = IXGBE_ERR_SWFW_SYNC;
3624 goto out;
3625 }
3626
3627 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3628 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3629 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3630 fw_cmd.port_num = (u8)hw->bus.func;
3631 fw_cmd.ver_maj = maj;
3632 fw_cmd.ver_min = min;
3633 fw_cmd.ver_build = build;
3634 fw_cmd.ver_sub = sub;
3635 fw_cmd.hdr.checksum = 0;
3636 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3637 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3638 fw_cmd.pad = 0;
3639 fw_cmd.pad2 = 0;
3640
3641 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
3642 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3643 sizeof(fw_cmd));
3644 if (ret_val != 0)
3645 continue;
3646
3647 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3648 FW_CEM_RESP_STATUS_SUCCESS)
3649 ret_val = 0;
3650 else
3651 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3652
3653 break;
3654 }
3655
3656 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3657out:
3658 return ret_val;
3659}
3660
3661/**
3662 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3663 * @hw: pointer to the hardware structure
3664 *
3665 * The 82599 and x540 MACs can experience issues if TX work is still pending
3666 * when a reset occurs. This function prevents this by flushing the PCIe
3667 * buffers on the system.
3668 **/
3669void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3670{
3671 u32 gcr_ext, hlreg0;
3672
3673 /*
3674 * If double reset is not requested then all transactions should
3675 * already be clear and as such there is no work to do
3676 */
3677 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3678 return;
3679
3680 /*
3681 * Set loopback enable to prevent any transmits from being sent
3682 * should the link come up. This assumes that the RXCTRL.RXEN bit
3683 * has already been cleared.
3684 */
3685 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3686 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3687
3688 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3689 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3690 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3691 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3692
3693 /* Flush all writes and allow 20usec for all transactions to clear */
3694 IXGBE_WRITE_FLUSH(hw);
3695 udelay(20);
3696
3697 /* restore previous register values */
3698 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3699 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3700}
3701
3702static const u8 ixgbe_emc_temp_data[4] = {
3703 IXGBE_EMC_INTERNAL_DATA,
3704 IXGBE_EMC_DIODE1_DATA,
3705 IXGBE_EMC_DIODE2_DATA,
3706 IXGBE_EMC_DIODE3_DATA
3707};
3708static const u8 ixgbe_emc_therm_limit[4] = {
3709 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3710 IXGBE_EMC_DIODE1_THERM_LIMIT,
3711 IXGBE_EMC_DIODE2_THERM_LIMIT,
3712 IXGBE_EMC_DIODE3_THERM_LIMIT
3713};
3714
3715/**
3716 * ixgbe_get_ets_data - Extracts the ETS bit data
3717 * @hw: pointer to hardware structure
3718 * @ets_cfg: extected ETS data
3719 * @ets_offset: offset of ETS data
3720 *
3721 * Returns error code.
3722 **/
3723static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3724 u16 *ets_offset)
3725{
3726 s32 status = 0;
3727
3728 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3729 if (status)
3730 goto out;
3731
3732 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) {
3733 status = IXGBE_NOT_IMPLEMENTED;
3734 goto out;
3735 }
3736
3737 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3738 if (status)
3739 goto out;
3740
3741 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) {
3742 status = IXGBE_NOT_IMPLEMENTED;
3743 goto out;
3744 }
3745
3746out:
3747 return status;
3748}
3749
3750/**
3751 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3752 * @hw: pointer to hardware structure
3753 *
3754 * Returns the thermal sensor data structure
3755 **/
3756s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3757{
3758 s32 status = 0;
3759 u16 ets_offset;
3760 u16 ets_cfg;
3761 u16 ets_sensor;
3762 u8 num_sensors;
3763 u8 i;
3764 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3765
3766 /* Only support thermal sensors attached to physical port 0 */
3767 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
3768 status = IXGBE_NOT_IMPLEMENTED;
3769 goto out;
3770 }
3771
3772 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3773 if (status)
3774 goto out;
3775
3776 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3777 if (num_sensors > IXGBE_MAX_SENSORS)
3778 num_sensors = IXGBE_MAX_SENSORS;
3779
3780 for (i = 0; i < num_sensors; i++) {
3781 u8 sensor_index;
3782 u8 sensor_location;
3783
3784 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3785 &ets_sensor);
3786 if (status)
3787 goto out;
3788
3789 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3790 IXGBE_ETS_DATA_INDEX_SHIFT);
3791 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3792 IXGBE_ETS_DATA_LOC_SHIFT);
3793
3794 if (sensor_location != 0) {
3795 status = hw->phy.ops.read_i2c_byte(hw,
3796 ixgbe_emc_temp_data[sensor_index],
3797 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3798 &data->sensor[i].temp);
3799 if (status)
3800 goto out;
3801 }
3802 }
3803out:
3804 return status;
3805}
3806
3807/**
3808 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3809 * @hw: pointer to hardware structure
3810 *
3811 * Inits the thermal sensor thresholds according to the NVM map
3812 * and save off the threshold and location values into mac.thermal_sensor_data
3813 **/
3814s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3815{
3816 s32 status = 0;
3817 u16 ets_offset;
3818 u16 ets_cfg;
3819 u16 ets_sensor;
3820 u8 low_thresh_delta;
3821 u8 num_sensors;
3822 u8 therm_limit;
3823 u8 i;
3824 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3825
3826 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3827
3828 /* Only support thermal sensors attached to physical port 0 */
3829 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
3830 status = IXGBE_NOT_IMPLEMENTED;
3831 goto out;
3832 }
3833
3834 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3835 if (status)
3836 goto out;
3837
3838 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3839 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3840 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3841 if (num_sensors > IXGBE_MAX_SENSORS)
3842 num_sensors = IXGBE_MAX_SENSORS;
3843
3844 for (i = 0; i < num_sensors; i++) {
3845 u8 sensor_index;
3846 u8 sensor_location;
3847
3848 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
3849 hw_err(hw, "eeprom read at offset %d failed\n",
3850 ets_offset + 1 + i);
3851 continue;
3852 }
3853 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3854 IXGBE_ETS_DATA_INDEX_SHIFT);
3855 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3856 IXGBE_ETS_DATA_LOC_SHIFT);
3857 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3858
3859 hw->phy.ops.write_i2c_byte(hw,
3860 ixgbe_emc_therm_limit[sensor_index],
3861 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3862
3863 if (sensor_location == 0)
3864 continue;
3865
3866 data->sensor[i].location = sensor_location;
3867 data->sensor[i].caution_thresh = therm_limit;
3868 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
3869 }
3870out:
3871 return status;
3872}
3873