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1#ifndef _INTEL_RINGBUFFER_H_
2#define _INTEL_RINGBUFFER_H_
3
4enum {
5 RCS = 0x0,
6 VCS,
7 BCS,
8 I915_NUM_RINGS,
9};
10
11struct intel_hw_status_page {
12 u32 __iomem *page_addr;
13 unsigned int gfx_addr;
14 struct drm_i915_gem_object *obj;
15};
16
17#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
18#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
19
20#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
21#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
22
23#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
24#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
25
26#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
27#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
28
29#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
30#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
31
32#define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
33#define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
34#define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
35
36struct intel_ring_buffer {
37 const char *name;
38 enum intel_ring_id {
39 RING_RENDER = 0x1,
40 RING_BSD = 0x2,
41 RING_BLT = 0x4,
42 } id;
43 u32 mmio_base;
44 void __iomem *virtual_start;
45 struct drm_device *dev;
46 struct drm_i915_gem_object *obj;
47
48 u32 head;
49 u32 tail;
50 int space;
51 int size;
52 int effective_size;
53 struct intel_hw_status_page status_page;
54
55 spinlock_t irq_lock;
56 u32 irq_refcount;
57 u32 irq_mask;
58 u32 irq_seqno; /* last seq seem at irq time */
59 u32 trace_irq_seqno;
60 u32 waiting_seqno;
61 u32 sync_seqno[I915_NUM_RINGS-1];
62 bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
63 void (*irq_put)(struct intel_ring_buffer *ring);
64
65 int (*init)(struct intel_ring_buffer *ring);
66
67 void (*write_tail)(struct intel_ring_buffer *ring,
68 u32 value);
69 int __must_check (*flush)(struct intel_ring_buffer *ring,
70 u32 invalidate_domains,
71 u32 flush_domains);
72 int (*add_request)(struct intel_ring_buffer *ring,
73 u32 *seqno);
74 u32 (*get_seqno)(struct intel_ring_buffer *ring);
75 int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
76 u32 offset, u32 length);
77 void (*cleanup)(struct intel_ring_buffer *ring);
78
79 /**
80 * List of objects currently involved in rendering from the
81 * ringbuffer.
82 *
83 * Includes buffers having the contents of their GPU caches
84 * flushed, not necessarily primitives. last_rendering_seqno
85 * represents when the rendering involved will be completed.
86 *
87 * A reference is held on the buffer while on this list.
88 */
89 struct list_head active_list;
90
91 /**
92 * List of breadcrumbs associated with GPU requests currently
93 * outstanding.
94 */
95 struct list_head request_list;
96
97 /**
98 * List of objects currently pending a GPU write flush.
99 *
100 * All elements on this list will belong to either the
101 * active_list or flushing_list, last_rendering_seqno can
102 * be used to differentiate between the two elements.
103 */
104 struct list_head gpu_write_list;
105
106 /**
107 * Do we have some not yet emitted requests outstanding?
108 */
109 u32 outstanding_lazy_request;
110
111 wait_queue_head_t irq_queue;
112 drm_local_map_t map;
113
114 void *private;
115};
116
117static inline u32
118intel_ring_sync_index(struct intel_ring_buffer *ring,
119 struct intel_ring_buffer *other)
120{
121 int idx;
122
123 /*
124 * cs -> 0 = vcs, 1 = bcs
125 * vcs -> 0 = bcs, 1 = cs,
126 * bcs -> 0 = cs, 1 = vcs.
127 */
128
129 idx = (other - ring) - 1;
130 if (idx < 0)
131 idx += I915_NUM_RINGS;
132
133 return idx;
134}
135
136static inline u32
137intel_read_status_page(struct intel_ring_buffer *ring,
138 int reg)
139{
140 return ioread32(ring->status_page.page_addr + reg);
141}
142
143/**
144 * Reads a dword out of the status page, which is written to from the command
145 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
146 * MI_STORE_DATA_IMM.
147 *
148 * The following dwords have a reserved meaning:
149 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
150 * 0x04: ring 0 head pointer
151 * 0x05: ring 1 head pointer (915-class)
152 * 0x06: ring 2 head pointer (915-class)
153 * 0x10-0x1b: Context status DWords (GM45)
154 * 0x1f: Last written status offset. (GM45)
155 *
156 * The area from dword 0x20 to 0x3ff is available for driver usage.
157 */
158#define READ_HWSP(dev_priv, reg) intel_read_status_page(LP_RING(dev_priv), reg)
159#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
160#define I915_GEM_HWS_INDEX 0x20
161#define I915_BREADCRUMB_INDEX 0x21
162
163void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
164
165int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
166static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring)
167{
168 return intel_wait_ring_buffer(ring, ring->size - 8);
169}
170
171int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
172
173static inline void intel_ring_emit(struct intel_ring_buffer *ring,
174 u32 data)
175{
176 iowrite32(data, ring->virtual_start + ring->tail);
177 ring->tail += 4;
178}
179
180void intel_ring_advance(struct intel_ring_buffer *ring);
181
182u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
183int intel_ring_sync(struct intel_ring_buffer *ring,
184 struct intel_ring_buffer *to,
185 u32 seqno);
186
187int intel_init_render_ring_buffer(struct drm_device *dev);
188int intel_init_bsd_ring_buffer(struct drm_device *dev);
189int intel_init_blt_ring_buffer(struct drm_device *dev);
190
191u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
192void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
193
194static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
195{
196 if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
197 ring->trace_irq_seqno = seqno;
198}
199
200/* DRI warts */
201int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
202
203#endif /* _INTEL_RINGBUFFER_H_ */
1#ifndef _INTEL_RINGBUFFER_H_
2#define _INTEL_RINGBUFFER_H_
3
4/*
5 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
6 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
7 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
8 *
9 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
10 * cacheline, the Head Pointer must not be greater than the Tail
11 * Pointer."
12 */
13#define I915_RING_FREE_SPACE 64
14
15struct intel_hw_status_page {
16 u32 *page_addr;
17 unsigned int gfx_addr;
18 struct drm_i915_gem_object *obj;
19};
20
21#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
22#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
23
24#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
25#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
26
27#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
28#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
29
30#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
31#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
32
33#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
34#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
35
36#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
37#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
38
39enum intel_ring_hangcheck_action {
40 HANGCHECK_IDLE = 0,
41 HANGCHECK_WAIT,
42 HANGCHECK_ACTIVE,
43 HANGCHECK_KICK,
44 HANGCHECK_HUNG,
45};
46
47#define HANGCHECK_SCORE_RING_HUNG 31
48
49struct intel_ring_hangcheck {
50 u64 acthd;
51 u32 seqno;
52 int score;
53 enum intel_ring_hangcheck_action action;
54 bool deadlock;
55};
56
57struct intel_ring_buffer {
58 const char *name;
59 enum intel_ring_id {
60 RCS = 0x0,
61 VCS,
62 BCS,
63 VECS,
64 } id;
65#define I915_NUM_RINGS 4
66 u32 mmio_base;
67 void __iomem *virtual_start;
68 struct drm_device *dev;
69 struct drm_i915_gem_object *obj;
70
71 u32 head;
72 u32 tail;
73 int space;
74 int size;
75 int effective_size;
76 struct intel_hw_status_page status_page;
77
78 /** We track the position of the requests in the ring buffer, and
79 * when each is retired we increment last_retired_head as the GPU
80 * must have finished processing the request and so we know we
81 * can advance the ringbuffer up to that position.
82 *
83 * last_retired_head is set to -1 after the value is consumed so
84 * we can detect new retirements.
85 */
86 u32 last_retired_head;
87
88 unsigned irq_refcount; /* protected by dev_priv->irq_lock */
89 u32 irq_enable_mask; /* bitmask to enable ring interrupt */
90 u32 trace_irq_seqno;
91 u32 sync_seqno[I915_NUM_RINGS-1];
92 bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
93 void (*irq_put)(struct intel_ring_buffer *ring);
94
95 int (*init)(struct intel_ring_buffer *ring);
96
97 void (*write_tail)(struct intel_ring_buffer *ring,
98 u32 value);
99 int __must_check (*flush)(struct intel_ring_buffer *ring,
100 u32 invalidate_domains,
101 u32 flush_domains);
102 int (*add_request)(struct intel_ring_buffer *ring);
103 /* Some chipsets are not quite as coherent as advertised and need
104 * an expensive kick to force a true read of the up-to-date seqno.
105 * However, the up-to-date seqno is not always required and the last
106 * seen value is good enough. Note that the seqno will always be
107 * monotonic, even if not coherent.
108 */
109 u32 (*get_seqno)(struct intel_ring_buffer *ring,
110 bool lazy_coherency);
111 void (*set_seqno)(struct intel_ring_buffer *ring,
112 u32 seqno);
113 int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
114 u32 offset, u32 length,
115 unsigned flags);
116#define I915_DISPATCH_SECURE 0x1
117#define I915_DISPATCH_PINNED 0x2
118 void (*cleanup)(struct intel_ring_buffer *ring);
119 int (*sync_to)(struct intel_ring_buffer *ring,
120 struct intel_ring_buffer *to,
121 u32 seqno);
122
123 /* our mbox written by others */
124 u32 semaphore_register[I915_NUM_RINGS];
125 /* mboxes this ring signals to */
126 u32 signal_mbox[I915_NUM_RINGS];
127
128 /**
129 * List of objects currently involved in rendering from the
130 * ringbuffer.
131 *
132 * Includes buffers having the contents of their GPU caches
133 * flushed, not necessarily primitives. last_rendering_seqno
134 * represents when the rendering involved will be completed.
135 *
136 * A reference is held on the buffer while on this list.
137 */
138 struct list_head active_list;
139
140 /**
141 * List of breadcrumbs associated with GPU requests currently
142 * outstanding.
143 */
144 struct list_head request_list;
145
146 /**
147 * Do we have some not yet emitted requests outstanding?
148 */
149 struct drm_i915_gem_request *preallocated_lazy_request;
150 u32 outstanding_lazy_seqno;
151 bool gpu_caches_dirty;
152 bool fbc_dirty;
153
154 wait_queue_head_t irq_queue;
155
156 /**
157 * Do an explicit TLB flush before MI_SET_CONTEXT
158 */
159 bool itlb_before_ctx_switch;
160 struct i915_hw_context *default_context;
161 struct i915_hw_context *last_context;
162
163 struct intel_ring_hangcheck hangcheck;
164
165 struct {
166 struct drm_i915_gem_object *obj;
167 u32 gtt_offset;
168 volatile u32 *cpu_page;
169 } scratch;
170
171 /*
172 * Tables of commands the command parser needs to know about
173 * for this ring.
174 */
175 const struct drm_i915_cmd_table *cmd_tables;
176 int cmd_table_count;
177
178 /*
179 * Table of registers allowed in commands that read/write registers.
180 */
181 const u32 *reg_table;
182 int reg_count;
183
184 /*
185 * Table of registers allowed in commands that read/write registers, but
186 * only from the DRM master.
187 */
188 const u32 *master_reg_table;
189 int master_reg_count;
190
191 /*
192 * Returns the bitmask for the length field of the specified command.
193 * Return 0 for an unrecognized/invalid command.
194 *
195 * If the command parser finds an entry for a command in the ring's
196 * cmd_tables, it gets the command's length based on the table entry.
197 * If not, it calls this function to determine the per-ring length field
198 * encoding for the command (i.e. certain opcode ranges use certain bits
199 * to encode the command length in the header).
200 */
201 u32 (*get_cmd_length_mask)(u32 cmd_header);
202};
203
204static inline bool
205intel_ring_initialized(struct intel_ring_buffer *ring)
206{
207 return ring->obj != NULL;
208}
209
210static inline unsigned
211intel_ring_flag(struct intel_ring_buffer *ring)
212{
213 return 1 << ring->id;
214}
215
216static inline u32
217intel_ring_sync_index(struct intel_ring_buffer *ring,
218 struct intel_ring_buffer *other)
219{
220 int idx;
221
222 /*
223 * cs -> 0 = vcs, 1 = bcs
224 * vcs -> 0 = bcs, 1 = cs,
225 * bcs -> 0 = cs, 1 = vcs.
226 */
227
228 idx = (other - ring) - 1;
229 if (idx < 0)
230 idx += I915_NUM_RINGS;
231
232 return idx;
233}
234
235static inline u32
236intel_read_status_page(struct intel_ring_buffer *ring,
237 int reg)
238{
239 /* Ensure that the compiler doesn't optimize away the load. */
240 barrier();
241 return ring->status_page.page_addr[reg];
242}
243
244static inline void
245intel_write_status_page(struct intel_ring_buffer *ring,
246 int reg, u32 value)
247{
248 ring->status_page.page_addr[reg] = value;
249}
250
251/**
252 * Reads a dword out of the status page, which is written to from the command
253 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
254 * MI_STORE_DATA_IMM.
255 *
256 * The following dwords have a reserved meaning:
257 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
258 * 0x04: ring 0 head pointer
259 * 0x05: ring 1 head pointer (915-class)
260 * 0x06: ring 2 head pointer (915-class)
261 * 0x10-0x1b: Context status DWords (GM45)
262 * 0x1f: Last written status offset. (GM45)
263 *
264 * The area from dword 0x20 to 0x3ff is available for driver usage.
265 */
266#define I915_GEM_HWS_INDEX 0x20
267#define I915_GEM_HWS_SCRATCH_INDEX 0x30
268#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
269
270void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
271
272int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
273int __must_check intel_ring_cacheline_align(struct intel_ring_buffer *ring);
274static inline void intel_ring_emit(struct intel_ring_buffer *ring,
275 u32 data)
276{
277 iowrite32(data, ring->virtual_start + ring->tail);
278 ring->tail += 4;
279}
280static inline void intel_ring_advance(struct intel_ring_buffer *ring)
281{
282 ring->tail &= ring->size - 1;
283}
284void __intel_ring_advance(struct intel_ring_buffer *ring);
285
286int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
287void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno);
288int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
289int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
290
291int intel_init_render_ring_buffer(struct drm_device *dev);
292int intel_init_bsd_ring_buffer(struct drm_device *dev);
293int intel_init_blt_ring_buffer(struct drm_device *dev);
294int intel_init_vebox_ring_buffer(struct drm_device *dev);
295
296u64 intel_ring_get_active_head(struct intel_ring_buffer *ring);
297void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
298
299static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
300{
301 return ring->tail;
302}
303
304static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
305{
306 BUG_ON(ring->outstanding_lazy_seqno == 0);
307 return ring->outstanding_lazy_seqno;
308}
309
310static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
311{
312 if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
313 ring->trace_irq_seqno = seqno;
314}
315
316/* DRI warts */
317int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
318
319#endif /* _INTEL_RINGBUFFER_H_ */