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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * RISC-V processor specific defines
4 *
5 * Copyright (C) 2021 Western Digital Corporation or its affiliates.
6 */
7#ifndef SELFTEST_KVM_PROCESSOR_H
8#define SELFTEST_KVM_PROCESSOR_H
9
10#include <linux/stringify.h>
11#include <asm/csr.h>
12#include "kvm_util.h"
13
14static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t subtype,
15 uint64_t idx, uint64_t size)
16{
17 return KVM_REG_RISCV | type | subtype | idx | size;
18}
19
20#if __riscv_xlen == 64
21#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U64
22#else
23#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32
24#endif
25
26#define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, 0, \
27 KVM_REG_RISCV_CONFIG_REG(name), \
28 KVM_REG_SIZE_ULONG)
29
30#define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, 0, \
31 KVM_REG_RISCV_CORE_REG(name), \
32 KVM_REG_SIZE_ULONG)
33
34#define RISCV_GENERAL_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \
35 KVM_REG_RISCV_CSR_GENERAL, \
36 KVM_REG_RISCV_CSR_REG(name), \
37 KVM_REG_SIZE_ULONG)
38
39#define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, 0, \
40 KVM_REG_RISCV_TIMER_REG(name), \
41 KVM_REG_SIZE_U64)
42
43#define RISCV_ISA_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \
44 KVM_REG_RISCV_ISA_SINGLE, \
45 idx, KVM_REG_SIZE_ULONG)
46
47#define RISCV_SBI_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_SBI_EXT, \
48 KVM_REG_RISCV_SBI_SINGLE, \
49 idx, KVM_REG_SIZE_ULONG)
50
51bool __vcpu_has_ext(struct kvm_vcpu *vcpu, uint64_t ext);
52
53struct ex_regs {
54 unsigned long ra;
55 unsigned long sp;
56 unsigned long gp;
57 unsigned long tp;
58 unsigned long t0;
59 unsigned long t1;
60 unsigned long t2;
61 unsigned long s0;
62 unsigned long s1;
63 unsigned long a0;
64 unsigned long a1;
65 unsigned long a2;
66 unsigned long a3;
67 unsigned long a4;
68 unsigned long a5;
69 unsigned long a6;
70 unsigned long a7;
71 unsigned long s2;
72 unsigned long s3;
73 unsigned long s4;
74 unsigned long s5;
75 unsigned long s6;
76 unsigned long s7;
77 unsigned long s8;
78 unsigned long s9;
79 unsigned long s10;
80 unsigned long s11;
81 unsigned long t3;
82 unsigned long t4;
83 unsigned long t5;
84 unsigned long t6;
85 unsigned long epc;
86 unsigned long status;
87 unsigned long cause;
88};
89
90#define NR_VECTORS 2
91#define NR_EXCEPTIONS 32
92#define EC_MASK (NR_EXCEPTIONS - 1)
93
94typedef void(*exception_handler_fn)(struct ex_regs *);
95
96void vm_init_vector_tables(struct kvm_vm *vm);
97void vcpu_init_vector_tables(struct kvm_vcpu *vcpu);
98
99void vm_install_exception_handler(struct kvm_vm *vm, int vector, exception_handler_fn handler);
100
101void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn handler);
102
103/* L3 index Bit[47:39] */
104#define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL
105#define PGTBL_L3_INDEX_SHIFT 39
106#define PGTBL_L3_BLOCK_SHIFT 39
107#define PGTBL_L3_BLOCK_SIZE 0x0000008000000000ULL
108#define PGTBL_L3_MAP_MASK (~(PGTBL_L3_BLOCK_SIZE - 1))
109/* L2 index Bit[38:30] */
110#define PGTBL_L2_INDEX_MASK 0x0000007FC0000000ULL
111#define PGTBL_L2_INDEX_SHIFT 30
112#define PGTBL_L2_BLOCK_SHIFT 30
113#define PGTBL_L2_BLOCK_SIZE 0x0000000040000000ULL
114#define PGTBL_L2_MAP_MASK (~(PGTBL_L2_BLOCK_SIZE - 1))
115/* L1 index Bit[29:21] */
116#define PGTBL_L1_INDEX_MASK 0x000000003FE00000ULL
117#define PGTBL_L1_INDEX_SHIFT 21
118#define PGTBL_L1_BLOCK_SHIFT 21
119#define PGTBL_L1_BLOCK_SIZE 0x0000000000200000ULL
120#define PGTBL_L1_MAP_MASK (~(PGTBL_L1_BLOCK_SIZE - 1))
121/* L0 index Bit[20:12] */
122#define PGTBL_L0_INDEX_MASK 0x00000000001FF000ULL
123#define PGTBL_L0_INDEX_SHIFT 12
124#define PGTBL_L0_BLOCK_SHIFT 12
125#define PGTBL_L0_BLOCK_SIZE 0x0000000000001000ULL
126#define PGTBL_L0_MAP_MASK (~(PGTBL_L0_BLOCK_SIZE - 1))
127
128#define PGTBL_PTE_ADDR_MASK 0x003FFFFFFFFFFC00ULL
129#define PGTBL_PTE_ADDR_SHIFT 10
130#define PGTBL_PTE_RSW_MASK 0x0000000000000300ULL
131#define PGTBL_PTE_RSW_SHIFT 8
132#define PGTBL_PTE_DIRTY_MASK 0x0000000000000080ULL
133#define PGTBL_PTE_DIRTY_SHIFT 7
134#define PGTBL_PTE_ACCESSED_MASK 0x0000000000000040ULL
135#define PGTBL_PTE_ACCESSED_SHIFT 6
136#define PGTBL_PTE_GLOBAL_MASK 0x0000000000000020ULL
137#define PGTBL_PTE_GLOBAL_SHIFT 5
138#define PGTBL_PTE_USER_MASK 0x0000000000000010ULL
139#define PGTBL_PTE_USER_SHIFT 4
140#define PGTBL_PTE_EXECUTE_MASK 0x0000000000000008ULL
141#define PGTBL_PTE_EXECUTE_SHIFT 3
142#define PGTBL_PTE_WRITE_MASK 0x0000000000000004ULL
143#define PGTBL_PTE_WRITE_SHIFT 2
144#define PGTBL_PTE_READ_MASK 0x0000000000000002ULL
145#define PGTBL_PTE_READ_SHIFT 1
146#define PGTBL_PTE_PERM_MASK (PGTBL_PTE_ACCESSED_MASK | \
147 PGTBL_PTE_DIRTY_MASK | \
148 PGTBL_PTE_EXECUTE_MASK | \
149 PGTBL_PTE_WRITE_MASK | \
150 PGTBL_PTE_READ_MASK)
151#define PGTBL_PTE_VALID_MASK 0x0000000000000001ULL
152#define PGTBL_PTE_VALID_SHIFT 0
153
154#define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE
155#define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT
156
157/* SBI return error codes */
158#define SBI_SUCCESS 0
159#define SBI_ERR_FAILURE -1
160#define SBI_ERR_NOT_SUPPORTED -2
161#define SBI_ERR_INVALID_PARAM -3
162#define SBI_ERR_DENIED -4
163#define SBI_ERR_INVALID_ADDRESS -5
164#define SBI_ERR_ALREADY_AVAILABLE -6
165#define SBI_ERR_ALREADY_STARTED -7
166#define SBI_ERR_ALREADY_STOPPED -8
167
168#define SBI_EXT_EXPERIMENTAL_START 0x08000000
169#define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF
170
171#define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END
172#define KVM_RISCV_SELFTESTS_SBI_UCALL 0
173#define KVM_RISCV_SELFTESTS_SBI_UNEXP 1
174
175enum sbi_ext_id {
176 SBI_EXT_BASE = 0x10,
177 SBI_EXT_STA = 0x535441,
178};
179
180enum sbi_ext_base_fid {
181 SBI_EXT_BASE_PROBE_EXT = 3,
182};
183
184struct sbiret {
185 long error;
186 long value;
187};
188
189struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
190 unsigned long arg1, unsigned long arg2,
191 unsigned long arg3, unsigned long arg4,
192 unsigned long arg5);
193
194bool guest_sbi_probe_extension(int extid, long *out_val);
195
196static inline void local_irq_enable(void)
197{
198 csr_set(CSR_SSTATUS, SR_SIE);
199}
200
201static inline void local_irq_disable(void)
202{
203 csr_clear(CSR_SSTATUS, SR_SIE);
204}
205
206#endif /* SELFTEST_KVM_PROCESSOR_H */