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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 | /* SPDX-License-Identifier: GPL-2.0 */ /* * ARM Generic Timer specific interface */ #ifndef SELFTEST_KVM_ARCH_TIMER_H #define SELFTEST_KVM_ARCH_TIMER_H #include "processor.h" enum arch_timer { VIRTUAL, PHYSICAL, }; #define CTL_ENABLE (1 << 0) #define CTL_IMASK (1 << 1) #define CTL_ISTATUS (1 << 2) #define msec_to_cycles(msec) \ (timer_get_cntfrq() * (uint64_t)(msec) / 1000) #define usec_to_cycles(usec) \ (timer_get_cntfrq() * (uint64_t)(usec) / 1000000) #define cycles_to_usec(cycles) \ ((uint64_t)(cycles) * 1000000 / timer_get_cntfrq()) static inline uint32_t timer_get_cntfrq(void) { return read_sysreg(cntfrq_el0); } static inline uint64_t timer_get_cntct(enum arch_timer timer) { isb(); switch (timer) { case VIRTUAL: return read_sysreg(cntvct_el0); case PHYSICAL: return read_sysreg(cntpct_el0); default: GUEST_FAIL("Unexpected timer type = %u", timer); } /* We should not reach here */ return 0; } static inline void timer_set_cval(enum arch_timer timer, uint64_t cval) { switch (timer) { case VIRTUAL: write_sysreg(cval, cntv_cval_el0); break; case PHYSICAL: write_sysreg(cval, cntp_cval_el0); break; default: GUEST_FAIL("Unexpected timer type = %u", timer); } isb(); } static inline uint64_t timer_get_cval(enum arch_timer timer) { switch (timer) { case VIRTUAL: return read_sysreg(cntv_cval_el0); case PHYSICAL: return read_sysreg(cntp_cval_el0); default: GUEST_FAIL("Unexpected timer type = %u", timer); } /* We should not reach here */ return 0; } static inline void timer_set_tval(enum arch_timer timer, uint32_t tval) { switch (timer) { case VIRTUAL: write_sysreg(tval, cntv_tval_el0); break; case PHYSICAL: write_sysreg(tval, cntp_tval_el0); break; default: GUEST_FAIL("Unexpected timer type = %u", timer); } isb(); } static inline void timer_set_ctl(enum arch_timer timer, uint32_t ctl) { switch (timer) { case VIRTUAL: write_sysreg(ctl, cntv_ctl_el0); break; case PHYSICAL: write_sysreg(ctl, cntp_ctl_el0); break; default: GUEST_FAIL("Unexpected timer type = %u", timer); } isb(); } static inline uint32_t timer_get_ctl(enum arch_timer timer) { switch (timer) { case VIRTUAL: return read_sysreg(cntv_ctl_el0); case PHYSICAL: return read_sysreg(cntp_ctl_el0); default: GUEST_FAIL("Unexpected timer type = %u", timer); } /* We should not reach here */ return 0; } static inline void timer_set_next_cval_ms(enum arch_timer timer, uint32_t msec) { uint64_t now_ct = timer_get_cntct(timer); uint64_t next_ct = now_ct + msec_to_cycles(msec); timer_set_cval(timer, next_ct); } static inline void timer_set_next_tval_ms(enum arch_timer timer, uint32_t msec) { timer_set_tval(timer, msec_to_cycles(msec)); } #endif /* SELFTEST_KVM_ARCH_TIMER_H */ |