Loading...
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
2 *
3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#ifndef QAIC_ACCEL_H_
8#define QAIC_ACCEL_H_
9
10#include "drm.h"
11
12#if defined(__cplusplus)
13extern "C" {
14#endif
15
16/* The length(4K) includes len and count fields of qaic_manage_msg */
17#define QAIC_MANAGE_MAX_MSG_LENGTH SZ_4K
18
19/* semaphore flags */
20#define QAIC_SEM_INSYNCFENCE 2
21#define QAIC_SEM_OUTSYNCFENCE 1
22
23/* Semaphore commands */
24#define QAIC_SEM_NOP 0
25#define QAIC_SEM_INIT 1
26#define QAIC_SEM_INC 2
27#define QAIC_SEM_DEC 3
28#define QAIC_SEM_WAIT_EQUAL 4
29#define QAIC_SEM_WAIT_GT_EQ 5 /* Greater than or equal */
30#define QAIC_SEM_WAIT_GT_0 6 /* Greater than 0 */
31
32#define QAIC_TRANS_UNDEFINED 0
33#define QAIC_TRANS_PASSTHROUGH_FROM_USR 1
34#define QAIC_TRANS_PASSTHROUGH_TO_USR 2
35#define QAIC_TRANS_PASSTHROUGH_FROM_DEV 3
36#define QAIC_TRANS_PASSTHROUGH_TO_DEV 4
37#define QAIC_TRANS_DMA_XFER_FROM_USR 5
38#define QAIC_TRANS_DMA_XFER_TO_DEV 6
39#define QAIC_TRANS_ACTIVATE_FROM_USR 7
40#define QAIC_TRANS_ACTIVATE_FROM_DEV 8
41#define QAIC_TRANS_ACTIVATE_TO_DEV 9
42#define QAIC_TRANS_DEACTIVATE_FROM_USR 10
43#define QAIC_TRANS_DEACTIVATE_FROM_DEV 11
44#define QAIC_TRANS_STATUS_FROM_USR 12
45#define QAIC_TRANS_STATUS_TO_USR 13
46#define QAIC_TRANS_STATUS_FROM_DEV 14
47#define QAIC_TRANS_STATUS_TO_DEV 15
48#define QAIC_TRANS_TERMINATE_FROM_DEV 16
49#define QAIC_TRANS_TERMINATE_TO_DEV 17
50#define QAIC_TRANS_DMA_XFER_CONT 18
51#define QAIC_TRANS_VALIDATE_PARTITION_FROM_DEV 19
52#define QAIC_TRANS_VALIDATE_PARTITION_TO_DEV 20
53
54/**
55 * struct qaic_manage_trans_hdr - Header for a transaction in a manage message.
56 * @type: In. Identifies this transaction. See QAIC_TRANS_* defines.
57 * @len: In. Length of this transaction, including this header.
58 */
59struct qaic_manage_trans_hdr {
60 __u32 type;
61 __u32 len;
62};
63
64/**
65 * struct qaic_manage_trans_passthrough - Defines a passthrough transaction.
66 * @hdr: In. Header to identify this transaction.
67 * @data: In. Payload of this ransaction. Opaque to the driver. Userspace must
68 * encode in little endian and align/pad to 64-bit.
69 */
70struct qaic_manage_trans_passthrough {
71 struct qaic_manage_trans_hdr hdr;
72 __u8 data[];
73};
74
75/**
76 * struct qaic_manage_trans_dma_xfer - Defines a DMA transfer transaction.
77 * @hdr: In. Header to identify this transaction.
78 * @tag: In. Identified this transfer in other transactions. Opaque to the
79 * driver.
80 * @pad: Structure padding.
81 * @addr: In. Address of the data to DMA to the device.
82 * @size: In. Length of the data to DMA to the device.
83 */
84struct qaic_manage_trans_dma_xfer {
85 struct qaic_manage_trans_hdr hdr;
86 __u32 tag;
87 __u32 pad;
88 __u64 addr;
89 __u64 size;
90};
91
92/**
93 * struct qaic_manage_trans_activate_to_dev - Defines an activate request.
94 * @hdr: In. Header to identify this transaction.
95 * @queue_size: In. Number of elements for DBC request and response queues.
96 * @eventfd: Unused.
97 * @options: In. Device specific options for this activate.
98 * @pad: Structure padding. Must be 0.
99 */
100struct qaic_manage_trans_activate_to_dev {
101 struct qaic_manage_trans_hdr hdr;
102 __u32 queue_size;
103 __u32 eventfd;
104 __u32 options;
105 __u32 pad;
106};
107
108/**
109 * struct qaic_manage_trans_activate_from_dev - Defines an activate response.
110 * @hdr: Out. Header to identify this transaction.
111 * @status: Out. Return code of the request from the device.
112 * @dbc_id: Out. Id of the assigned DBC for successful request.
113 * @options: Out. Device specific options for this activate.
114 */
115struct qaic_manage_trans_activate_from_dev {
116 struct qaic_manage_trans_hdr hdr;
117 __u32 status;
118 __u32 dbc_id;
119 __u64 options;
120};
121
122/**
123 * struct qaic_manage_trans_deactivate - Defines a deactivate request.
124 * @hdr: In. Header to identify this transaction.
125 * @dbc_id: In. Id of assigned DBC.
126 * @pad: Structure padding. Must be 0.
127 */
128struct qaic_manage_trans_deactivate {
129 struct qaic_manage_trans_hdr hdr;
130 __u32 dbc_id;
131 __u32 pad;
132};
133
134/**
135 * struct qaic_manage_trans_status_to_dev - Defines a status request.
136 * @hdr: In. Header to identify this transaction.
137 */
138struct qaic_manage_trans_status_to_dev {
139 struct qaic_manage_trans_hdr hdr;
140};
141
142/**
143 * struct qaic_manage_trans_status_from_dev - Defines a status response.
144 * @hdr: Out. Header to identify this transaction.
145 * @major: Out. NNC protocol version major number.
146 * @minor: Out. NNC protocol version minor number.
147 * @status: Out. Return code from device.
148 * @status_flags: Out. Flags from device. Bit 0 indicates if CRCs are required.
149 */
150struct qaic_manage_trans_status_from_dev {
151 struct qaic_manage_trans_hdr hdr;
152 __u16 major;
153 __u16 minor;
154 __u32 status;
155 __u64 status_flags;
156};
157
158/**
159 * struct qaic_manage_msg - Defines a message to the device.
160 * @len: In. Length of all the transactions contained within this message.
161 * @count: In. Number of transactions in this message.
162 * @data: In. Address to an array where the transactions can be found.
163 */
164struct qaic_manage_msg {
165 __u32 len;
166 __u32 count;
167 __u64 data;
168};
169
170/**
171 * struct qaic_create_bo - Defines a request to create a buffer object.
172 * @size: In. Size of the buffer in bytes.
173 * @handle: Out. GEM handle for the BO.
174 * @pad: Structure padding. Must be 0.
175 */
176struct qaic_create_bo {
177 __u64 size;
178 __u32 handle;
179 __u32 pad;
180};
181
182/**
183 * struct qaic_mmap_bo - Defines a request to prepare a BO for mmap().
184 * @handle: In. Handle of the GEM BO to prepare for mmap().
185 * @pad: Structure padding. Must be 0.
186 * @offset: Out. Offset value to provide to mmap().
187 */
188struct qaic_mmap_bo {
189 __u32 handle;
190 __u32 pad;
191 __u64 offset;
192};
193
194/**
195 * struct qaic_sem - Defines a semaphore command for a BO slice.
196 * @val: In. Only lower 12 bits are valid.
197 * @index: In. Only lower 5 bits are valid.
198 * @presync: In. 1 if presync operation, 0 if postsync.
199 * @cmd: In. One of QAIC_SEM_*.
200 * @flags: In. Bitfield. See QAIC_SEM_INSYNCFENCE and QAIC_SEM_OUTSYNCFENCE
201 * @pad: Structure padding. Must be 0.
202 */
203struct qaic_sem {
204 __u16 val;
205 __u8 index;
206 __u8 presync;
207 __u8 cmd;
208 __u8 flags;
209 __u16 pad;
210};
211
212/**
213 * struct qaic_attach_slice_entry - Defines a single BO slice.
214 * @size: In. Size of this slice in bytes.
215 * @sem0: In. Semaphore command 0. Must be 0 is not valid.
216 * @sem1: In. Semaphore command 1. Must be 0 is not valid.
217 * @sem2: In. Semaphore command 2. Must be 0 is not valid.
218 * @sem3: In. Semaphore command 3. Must be 0 is not valid.
219 * @dev_addr: In. Device address this slice pushes to or pulls from.
220 * @db_addr: In. Address of the doorbell to ring.
221 * @db_data: In. Data to write to the doorbell.
222 * @db_len: In. Size of the doorbell data in bits - 32, 16, or 8. 0 is for
223 * inactive doorbells.
224 * @offset: In. Start of this slice as an offset from the start of the BO.
225 */
226struct qaic_attach_slice_entry {
227 __u64 size;
228 struct qaic_sem sem0;
229 struct qaic_sem sem1;
230 struct qaic_sem sem2;
231 struct qaic_sem sem3;
232 __u64 dev_addr;
233 __u64 db_addr;
234 __u32 db_data;
235 __u32 db_len;
236 __u64 offset;
237};
238
239/**
240 * struct qaic_attach_slice_hdr - Defines metadata for a set of BO slices.
241 * @count: In. Number of slices for this BO.
242 * @dbc_id: In. Associate the sliced BO with this DBC.
243 * @handle: In. GEM handle of the BO to slice.
244 * @dir: In. Direction of data flow. 1 = DMA_TO_DEVICE, 2 = DMA_FROM_DEVICE
245 * @size: Deprecated. This value is ignored and size of @handle is used instead.
246 */
247struct qaic_attach_slice_hdr {
248 __u32 count;
249 __u32 dbc_id;
250 __u32 handle;
251 __u32 dir;
252 __u64 size;
253};
254
255/**
256 * struct qaic_attach_slice - Defines a set of BO slices.
257 * @hdr: In. Metadata of the set of slices.
258 * @data: In. Pointer to an array containing the slice definitions.
259 */
260struct qaic_attach_slice {
261 struct qaic_attach_slice_hdr hdr;
262 __u64 data;
263};
264
265/**
266 * struct qaic_execute_entry - Defines a BO to submit to the device.
267 * @handle: In. GEM handle of the BO to commit to the device.
268 * @dir: In. Direction of data. 1 = to device, 2 = from device.
269 */
270struct qaic_execute_entry {
271 __u32 handle;
272 __u32 dir;
273};
274
275/**
276 * struct qaic_partial_execute_entry - Defines a BO to resize and submit.
277 * @handle: In. GEM handle of the BO to commit to the device.
278 * @dir: In. Direction of data. 1 = to device, 2 = from device.
279 * @resize: In. New size of the BO. Must be <= the original BO size.
280 * @resize as 0 would be interpreted as no DMA transfer is
281 * involved.
282 */
283struct qaic_partial_execute_entry {
284 __u32 handle;
285 __u32 dir;
286 __u64 resize;
287};
288
289/**
290 * struct qaic_execute_hdr - Defines metadata for BO submission.
291 * @count: In. Number of BOs to submit.
292 * @dbc_id: In. DBC to submit the BOs on.
293 */
294struct qaic_execute_hdr {
295 __u32 count;
296 __u32 dbc_id;
297};
298
299/**
300 * struct qaic_execute - Defines a list of BOs to submit to the device.
301 * @hdr: In. BO list metadata.
302 * @data: In. Pointer to an array of BOs to submit.
303 */
304struct qaic_execute {
305 struct qaic_execute_hdr hdr;
306 __u64 data;
307};
308
309/**
310 * struct qaic_wait - Defines a blocking wait for BO execution.
311 * @handle: In. GEM handle of the BO to wait on.
312 * @timeout: In. Maximum time in ms to wait for the BO.
313 * @dbc_id: In. DBC the BO is submitted to.
314 * @pad: Structure padding. Must be 0.
315 */
316struct qaic_wait {
317 __u32 handle;
318 __u32 timeout;
319 __u32 dbc_id;
320 __u32 pad;
321};
322
323/**
324 * struct qaic_perf_stats_hdr - Defines metadata for getting BO perf info.
325 * @count: In. Number of BOs requested.
326 * @pad: Structure padding. Must be 0.
327 * @dbc_id: In. DBC the BO are associated with.
328 */
329struct qaic_perf_stats_hdr {
330 __u16 count;
331 __u16 pad;
332 __u32 dbc_id;
333};
334
335/**
336 * struct qaic_perf_stats - Defines a request for getting BO perf info.
337 * @hdr: In. Request metadata
338 * @data: In. Pointer to array of stats structures that will receive the data.
339 */
340struct qaic_perf_stats {
341 struct qaic_perf_stats_hdr hdr;
342 __u64 data;
343};
344
345/**
346 * struct qaic_perf_stats_entry - Defines a BO perf info.
347 * @handle: In. GEM handle of the BO to get perf stats for.
348 * @queue_level_before: Out. Number of elements in the queue before this BO
349 * was submitted.
350 * @num_queue_element: Out. Number of elements added to the queue to submit
351 * this BO.
352 * @submit_latency_us: Out. Time taken by the driver to submit this BO.
353 * @device_latency_us: Out. Time taken by the device to execute this BO.
354 * @pad: Structure padding. Must be 0.
355 */
356struct qaic_perf_stats_entry {
357 __u32 handle;
358 __u32 queue_level_before;
359 __u32 num_queue_element;
360 __u32 submit_latency_us;
361 __u32 device_latency_us;
362 __u32 pad;
363};
364
365/**
366 * struct qaic_detach_slice - Detaches slicing configuration from BO.
367 * @handle: In. GEM handle of the BO to detach slicing configuration.
368 * @pad: Structure padding. Must be 0.
369 */
370struct qaic_detach_slice {
371 __u32 handle;
372 __u32 pad;
373};
374
375#define DRM_QAIC_MANAGE 0x00
376#define DRM_QAIC_CREATE_BO 0x01
377#define DRM_QAIC_MMAP_BO 0x02
378#define DRM_QAIC_ATTACH_SLICE_BO 0x03
379#define DRM_QAIC_EXECUTE_BO 0x04
380#define DRM_QAIC_PARTIAL_EXECUTE_BO 0x05
381#define DRM_QAIC_WAIT_BO 0x06
382#define DRM_QAIC_PERF_STATS_BO 0x07
383#define DRM_QAIC_DETACH_SLICE_BO 0x08
384
385#define DRM_IOCTL_QAIC_MANAGE DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg)
386#define DRM_IOCTL_QAIC_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo)
387#define DRM_IOCTL_QAIC_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo)
388#define DRM_IOCTL_QAIC_ATTACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, struct qaic_attach_slice)
389#define DRM_IOCTL_QAIC_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_EXECUTE_BO, struct qaic_execute)
390#define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, struct qaic_execute)
391#define DRM_IOCTL_QAIC_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait)
392#define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, struct qaic_perf_stats)
393#define DRM_IOCTL_QAIC_DETACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_DETACH_SLICE_BO, struct qaic_detach_slice)
394
395#if defined(__cplusplus)
396}
397#endif
398
399#endif /* QAIC_ACCEL_H_ */