1/* SPDX-License-Identifier: GPL-2.0 */
  2
  3#ifndef __TI_SYSC_DATA_H__
  4#define __TI_SYSC_DATA_H__
  5
  6enum ti_sysc_module_type {
  7	TI_SYSC_OMAP2,
  8	TI_SYSC_OMAP2_TIMER,
  9	TI_SYSC_OMAP3_SHAM,
 10	TI_SYSC_OMAP3_AES,
 11	TI_SYSC_OMAP4,
 12	TI_SYSC_OMAP4_TIMER,
 13	TI_SYSC_OMAP4_SIMPLE,
 14	TI_SYSC_OMAP34XX_SR,
 15	TI_SYSC_OMAP36XX_SR,
 16	TI_SYSC_OMAP4_SR,
 17	TI_SYSC_OMAP4_MCASP,
 18	TI_SYSC_OMAP4_USB_HOST_FS,
 19	TI_SYSC_DRA7_MCAN,
 20	TI_SYSC_PRUSS,
 21};
 22
 23struct ti_sysc_cookie {
 24	void *data;
 25	void *clkdm;
 26};
 27
 28/**
 29 * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets
 30 * @midle_shift: Offset of the midle bit
 31 * @clkact_shift: Offset of the clockactivity bit
 32 * @sidle_shift: Offset of the sidle bit
 33 * @enwkup_shift: Offset of the enawakeup bit
 34 * @srst_shift: Offset of the softreset bit
 35 * @autoidle_shift: Offset of the autoidle bit
 36 * @dmadisable_shift: Offset of the dmadisable bit
 37 * @emufree_shift; Offset of the emufree bit
 38 *
 39 * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a
 40 * feature is not available.
 41 */
 42struct sysc_regbits {
 43	s8 midle_shift;
 44	s8 clkact_shift;
 45	s8 sidle_shift;
 46	s8 enwkup_shift;
 47	s8 srst_shift;
 48	s8 autoidle_shift;
 49	s8 dmadisable_shift;
 50	s8 emufree_shift;
 51};
 52
 53#define SYSC_MODULE_QUIRK_OTG		BIT(30)
 54#define SYSC_QUIRK_RESET_ON_CTX_LOST	BIT(29)
 55#define SYSC_QUIRK_REINIT_ON_CTX_LOST	BIT(28)
 56#define SYSC_QUIRK_REINIT_ON_RESUME	BIT(27)
 57#define SYSC_QUIRK_GPMC_DEBUG		BIT(26)
 58#define SYSC_MODULE_QUIRK_ENA_RESETDONE	BIT(25)
 59#define SYSC_MODULE_QUIRK_PRUSS		BIT(24)
 60#define SYSC_MODULE_QUIRK_DSS_RESET	BIT(23)
 61#define SYSC_MODULE_QUIRK_RTC_UNLOCK	BIT(22)
 62#define SYSC_QUIRK_CLKDM_NOAUTO		BIT(21)
 63#define SYSC_QUIRK_FORCE_MSTANDBY	BIT(20)
 64#define SYSC_MODULE_QUIRK_AESS		BIT(19)
 65#define SYSC_MODULE_QUIRK_SGX		BIT(18)
 66#define SYSC_MODULE_QUIRK_HDQ1W		BIT(17)
 67#define SYSC_MODULE_QUIRK_I2C		BIT(16)
 68#define SYSC_MODULE_QUIRK_WDT		BIT(15)
 69#define SYSS_QUIRK_RESETDONE_INVERTED	BIT(14)
 70#define SYSC_QUIRK_SWSUP_MSTANDBY	BIT(13)
 71#define SYSC_QUIRK_SWSUP_SIDLE_ACT	BIT(12)
 72#define SYSC_QUIRK_SWSUP_SIDLE		BIT(11)
 73#define SYSC_QUIRK_EXT_OPT_CLOCK	BIT(10)
 74#define SYSC_QUIRK_LEGACY_IDLE		BIT(9)
 75#define SYSC_QUIRK_RESET_STATUS		BIT(8)
 76#define SYSC_QUIRK_NO_IDLE		BIT(7)
 77#define SYSC_QUIRK_NO_IDLE_ON_INIT	BIT(6)
 78#define SYSC_QUIRK_NO_RESET_ON_INIT	BIT(5)
 79#define SYSC_QUIRK_OPT_CLKS_NEEDED	BIT(4)
 80#define SYSC_QUIRK_OPT_CLKS_IN_RESET	BIT(3)
 81#define SYSC_QUIRK_16BIT		BIT(2)
 82#define SYSC_QUIRK_UNCACHED		BIT(1)
 83#define SYSC_QUIRK_USE_CLOCKACT		BIT(0)
 84
 85#define SYSC_NR_IDLEMODES		4
 86
 87/**
 88 * struct sysc_capabilities - capabilities for an interconnect target module
 89 * @type: sysc type identifier for the module
 90 * @sysc_mask: bitmask of supported SYSCONFIG register bits
 91 * @regbits: bitmask of SYSCONFIG register bits
 92 * @mod_quirks: bitmask of module specific quirks
 93 */
 94struct sysc_capabilities {
 95	const enum ti_sysc_module_type type;
 96	const u32 sysc_mask;
 97	const struct sysc_regbits *regbits;
 98	const u32 mod_quirks;
 99};
100
101/**
102 * struct sysc_config - configuration for an interconnect target module
103 * @sysc_val: configured value for sysc register
104 * @syss_mask: configured mask value for SYSSTATUS register
105 * @midlemodes: bitmask of supported master idle modes
106 * @sidlemodes: bitmask of supported slave idle modes
107 * @srst_udelay: optional delay needed after OCP soft reset
108 * @quirks: bitmask of enabled quirks
109 */
110struct sysc_config {
111	u32 sysc_val;
112	u32 syss_mask;
113	u8 midlemodes;
114	u8 sidlemodes;
115	u8 srst_udelay;
116	u32 quirks;
117};
118
119enum sysc_registers {
120	SYSC_REVISION,
121	SYSC_SYSCONFIG,
122	SYSC_SYSSTATUS,
123	SYSC_MAX_REGS,
124};
125
126/**
127 * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module
128 * @name: legacy "ti,hwmods" module name
129 * @module_pa: physical address of the interconnect target module
130 * @module_size: size of the interconnect target module
131 * @offsets: array of register offsets as listed in enum sysc_registers
132 * @nr_offsets: number of registers
133 * @cap: interconnect target module capabilities
134 * @cfg: interconnect target module configuration
135 *
136 * This data is enough to allocate a new struct omap_hwmod_class_sysconfig
137 * based on device tree data parsed by ti-sysc driver.
138 */
139struct ti_sysc_module_data {
140	const char *name;
141	u64 module_pa;
142	u32 module_size;
143	int *offsets;
144	int nr_offsets;
145	const struct sysc_capabilities *cap;
146	struct sysc_config *cfg;
147};
148
149struct device;
150struct clk;
151
152struct ti_sysc_platform_data {
153	struct of_dev_auxdata *auxdata;
154	bool (*soc_type_gp)(void);
155	int (*init_clockdomain)(struct device *dev, struct clk *fck,
156				struct clk *ick, struct ti_sysc_cookie *cookie);
157	void (*clkdm_deny_idle)(struct device *dev,
158				const struct ti_sysc_cookie *cookie);
159	void (*clkdm_allow_idle)(struct device *dev,
160				 const struct ti_sysc_cookie *cookie);
161	int (*init_module)(struct device *dev,
162			   const struct ti_sysc_module_data *data,
163			   struct ti_sysc_cookie *cookie);
164	int (*enable_module)(struct device *dev,
165			     const struct ti_sysc_cookie *cookie);
166	int (*idle_module)(struct device *dev,
167			   const struct ti_sysc_cookie *cookie);
168	int (*shutdown_module)(struct device *dev,
169			       const struct ti_sysc_cookie *cookie);
170};
171
172#endif	/* __TI_SYSC_DATA_H__ */