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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * USBSS device controller driver header file
4 *
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
7 *
8 * Author: Pawel Laszczak <pawell@cadence.com>
9 * Pawel Jez <pjez@cadence.com>
10 * Peter Chen <peter.chen@nxp.com>
11 */
12#ifndef __LINUX_CDNS3_GADGET
13#define __LINUX_CDNS3_GADGET
14#include <linux/usb/gadget.h>
15#include <linux/dma-direction.h>
16
17/*
18 * USBSS-DEV register interface.
19 * This corresponds to the USBSS Device Controller Interface
20 */
21
22/**
23 * struct cdns3_usb_regs - device controller registers.
24 * @usb_conf: Global Configuration.
25 * @usb_sts: Global Status.
26 * @usb_cmd: Global Command.
27 * @usb_itpn: ITP/SOF number.
28 * @usb_lpm: Global Command.
29 * @usb_ien: USB Interrupt Enable.
30 * @usb_ists: USB Interrupt Status.
31 * @ep_sel: Endpoint Select.
32 * @ep_traddr: Endpoint Transfer Ring Address.
33 * @ep_cfg: Endpoint Configuration.
34 * @ep_cmd: Endpoint Command.
35 * @ep_sts: Endpoint Status.
36 * @ep_sts_sid: Endpoint Status.
37 * @ep_sts_en: Endpoint Status Enable.
38 * @drbl: Doorbell.
39 * @ep_ien: EP Interrupt Enable.
40 * @ep_ists: EP Interrupt Status.
41 * @usb_pwr: Global Power Configuration.
42 * @usb_conf2: Global Configuration 2.
43 * @usb_cap1: Capability 1.
44 * @usb_cap2: Capability 2.
45 * @usb_cap3: Capability 3.
46 * @usb_cap4: Capability 4.
47 * @usb_cap5: Capability 5.
48 * @usb_cap6: Capability 6.
49 * @usb_cpkt1: Custom Packet 1.
50 * @usb_cpkt2: Custom Packet 2.
51 * @usb_cpkt3: Custom Packet 3.
52 * @ep_dma_ext_addr: Upper address for DMA operations.
53 * @buf_addr: Address for On-chip Buffer operations.
54 * @buf_data: Data for On-chip Buffer operations.
55 * @buf_ctrl: On-chip Buffer Access Control.
56 * @dtrans: DMA Transfer Mode.
57 * @tdl_from_trb: Source of TD Configuration.
58 * @tdl_beh: TDL Behavior Configuration.
59 * @ep_tdl: Endpoint TDL.
60 * @tdl_beh2: TDL Behavior 2 Configuration.
61 * @dma_adv_td: DMA Advance TD Configuration.
62 * @reserved1: Reserved.
63 * @cfg_regs: Configuration.
64 * @reserved2: Reserved.
65 * @dma_axi_ctrl: AXI Control.
66 * @dma_axi_id: AXI ID register.
67 * @dma_axi_cap: AXI Capability.
68 * @dma_axi_ctrl0: AXI Control 0.
69 * @dma_axi_ctrl1: AXI Control 1.
70 */
71struct cdns3_usb_regs {
72 __le32 usb_conf;
73 __le32 usb_sts;
74 __le32 usb_cmd;
75 __le32 usb_itpn;
76 __le32 usb_lpm;
77 __le32 usb_ien;
78 __le32 usb_ists;
79 __le32 ep_sel;
80 __le32 ep_traddr;
81 __le32 ep_cfg;
82 __le32 ep_cmd;
83 __le32 ep_sts;
84 __le32 ep_sts_sid;
85 __le32 ep_sts_en;
86 __le32 drbl;
87 __le32 ep_ien;
88 __le32 ep_ists;
89 __le32 usb_pwr;
90 __le32 usb_conf2;
91 __le32 usb_cap1;
92 __le32 usb_cap2;
93 __le32 usb_cap3;
94 __le32 usb_cap4;
95 __le32 usb_cap5;
96 __le32 usb_cap6;
97 __le32 usb_cpkt1;
98 __le32 usb_cpkt2;
99 __le32 usb_cpkt3;
100 __le32 ep_dma_ext_addr;
101 __le32 buf_addr;
102 __le32 buf_data;
103 __le32 buf_ctrl;
104 __le32 dtrans;
105 __le32 tdl_from_trb;
106 __le32 tdl_beh;
107 __le32 ep_tdl;
108 __le32 tdl_beh2;
109 __le32 dma_adv_td;
110 __le32 reserved1[26];
111 __le32 cfg_reg1;
112 __le32 dbg_link1;
113 __le32 dbg_link2;
114 __le32 cfg_regs[74];
115 __le32 reserved2[51];
116 __le32 dma_axi_ctrl;
117 __le32 dma_axi_id;
118 __le32 dma_axi_cap;
119 __le32 dma_axi_ctrl0;
120 __le32 dma_axi_ctrl1;
121};
122
123/* USB_CONF - bitmasks */
124/* Reset USB device configuration. */
125#define USB_CONF_CFGRST BIT(0)
126/* Set Configuration. */
127#define USB_CONF_CFGSET BIT(1)
128/* Disconnect USB device in SuperSpeed. */
129#define USB_CONF_USB3DIS BIT(3)
130/* Disconnect USB device in HS/FS */
131#define USB_CONF_USB2DIS BIT(4)
132/* Little Endian access - default */
133#define USB_CONF_LENDIAN BIT(5)
134/*
135 * Big Endian access. Driver assume that byte order for
136 * SFRs access always is as Little Endian so this bit
137 * is not used.
138 */
139#define USB_CONF_BENDIAN BIT(6)
140/* Device software reset. */
141#define USB_CONF_SWRST BIT(7)
142/* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/
143#define USB_CONF_DSING BIT(8)
144/* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */
145#define USB_CONF_DMULT BIT(9)
146/* DMA clock turn-off enable. */
147#define USB_CONF_DMAOFFEN BIT(10)
148/* DMA clock turn-off disable. */
149#define USB_CONF_DMAOFFDS BIT(11)
150/* Clear Force Full Speed. */
151#define USB_CONF_CFORCE_FS BIT(12)
152/* Set Force Full Speed. */
153#define USB_CONF_SFORCE_FS BIT(13)
154/* Device enable. */
155#define USB_CONF_DEVEN BIT(14)
156/* Device disable. */
157#define USB_CONF_DEVDS BIT(15)
158/* L1 LPM state entry enable (used in HS/FS mode). */
159#define USB_CONF_L1EN BIT(16)
160/* L1 LPM state entry disable (used in HS/FS mode). */
161#define USB_CONF_L1DS BIT(17)
162/* USB 2.0 clock gate disable. */
163#define USB_CONF_CLK2OFFEN BIT(18)
164/* USB 2.0 clock gate enable. */
165#define USB_CONF_CLK2OFFDS BIT(19)
166/* L0 LPM state entry request (used in HS/FS mode). */
167#define USB_CONF_LGO_L0 BIT(20)
168/* USB 3.0 clock gate disable. */
169#define USB_CONF_CLK3OFFEN BIT(21)
170/* USB 3.0 clock gate enable. */
171#define USB_CONF_CLK3OFFDS BIT(22)
172/* Bit 23 is reserved*/
173/* U1 state entry enable (used in SS mode). */
174#define USB_CONF_U1EN BIT(24)
175/* U1 state entry disable (used in SS mode). */
176#define USB_CONF_U1DS BIT(25)
177/* U2 state entry enable (used in SS mode). */
178#define USB_CONF_U2EN BIT(26)
179/* U2 state entry disable (used in SS mode). */
180#define USB_CONF_U2DS BIT(27)
181/* U0 state entry request (used in SS mode). */
182#define USB_CONF_LGO_U0 BIT(28)
183/* U1 state entry request (used in SS mode). */
184#define USB_CONF_LGO_U1 BIT(29)
185/* U2 state entry request (used in SS mode). */
186#define USB_CONF_LGO_U2 BIT(30)
187/* SS.Inactive state entry request (used in SS mode) */
188#define USB_CONF_LGO_SSINACT BIT(31)
189
190/* USB_STS - bitmasks */
191/*
192 * Configuration status.
193 * 1 - device is in the configured state.
194 * 0 - device is not configured.
195 */
196#define USB_STS_CFGSTS_MASK BIT(0)
197#define USB_STS_CFGSTS(p) ((p) & USB_STS_CFGSTS_MASK)
198/*
199 * On-chip memory overflow.
200 * 0 - On-chip memory status OK.
201 * 1 - On-chip memory overflow.
202 */
203#define USB_STS_OV_MASK BIT(1)
204#define USB_STS_OV(p) ((p) & USB_STS_OV_MASK)
205/*
206 * SuperSpeed connection status.
207 * 0 - USB in SuperSpeed mode disconnected.
208 * 1 - USB in SuperSpeed mode connected.
209 */
210#define USB_STS_USB3CONS_MASK BIT(2)
211#define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK)
212/*
213 * DMA transfer configuration status.
214 * 0 - single request.
215 * 1 - multiple TRB chain
216 * Supported only for controller version < DEV_VER_V3
217 */
218#define USB_STS_DTRANS_MASK BIT(3)
219#define USB_STS_DTRANS(p) ((p) & USB_STS_DTRANS_MASK)
220/*
221 * Device speed.
222 * 0 - Undefined (value after reset).
223 * 1 - Low speed
224 * 2 - Full speed
225 * 3 - High speed
226 * 4 - Super speed
227 */
228#define USB_STS_USBSPEED_MASK GENMASK(6, 4)
229#define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4)
230#define USB_STS_LS (0x1 << 4)
231#define USB_STS_FS (0x2 << 4)
232#define USB_STS_HS (0x3 << 4)
233#define USB_STS_SS (0x4 << 4)
234#define DEV_UNDEFSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4))
235#define DEV_LOWSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS)
236#define DEV_FULLSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS)
237#define DEV_HIGHSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS)
238#define DEV_SUPERSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS)
239/*
240 * Endianness for SFR access.
241 * 0 - Little Endian order (default after hardware reset).
242 * 1 - Big Endian order
243 */
244#define USB_STS_ENDIAN_MASK BIT(7)
245#define USB_STS_ENDIAN(p) ((p) & USB_STS_ENDIAN_MASK)
246/*
247 * HS/FS clock turn-off status.
248 * 0 - hsfs clock is always on.
249 * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
250 * (default after hardware reset).
251 */
252#define USB_STS_CLK2OFF_MASK BIT(8)
253#define USB_STS_CLK2OFF(p) ((p) & USB_STS_CLK2OFF_MASK)
254/*
255 * PCLK clock turn-off status.
256 * 0 - pclk clock is always on.
257 * 1 - pclk clock turn-off in U3 (SS mode) is enabled
258 * (default after hardware reset).
259 */
260#define USB_STS_CLK3OFF_MASK BIT(9)
261#define USB_STS_CLK3OFF(p) ((p) & USB_STS_CLK3OFF_MASK)
262/*
263 * Controller in reset state.
264 * 0 - Internal reset is active.
265 * 1 - Internal reset is not active and controller is fully operational.
266 */
267#define USB_STS_IN_RST_MASK BIT(10)
268#define USB_STS_IN_RST(p) ((p) & USB_STS_IN_RST_MASK)
269/*
270 * Status of the "TDL calculation basing on TRB" feature.
271 * 0 - disabled
272 * 1 - enabled
273 * Supported only for DEV_VER_V2 controller version.
274 */
275#define USB_STS_TDL_TRB_ENABLED BIT(11)
276/*
277 * Device enable Status.
278 * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
279 * 1 - USB device is enabled (VBUS input is connected to the internal logic).
280 */
281#define USB_STS_DEVS_MASK BIT(14)
282#define USB_STS_DEVS(p) ((p) & USB_STS_DEVS_MASK)
283/*
284 * Address status.
285 * 0 - USB device is default state.
286 * 1 - USB device is at least in address state.
287 */
288#define USB_STS_ADDRESSED_MASK BIT(15)
289#define USB_STS_ADDRESSED(p) ((p) & USB_STS_ADDRESSED_MASK)
290/*
291 * L1 LPM state enable status (used in HS/FS mode).
292 * 0 - Entering to L1 LPM state disabled.
293 * 1 - Entering to L1 LPM state enabled.
294 */
295#define USB_STS_L1ENS_MASK BIT(16)
296#define USB_STS_L1ENS(p) ((p) & USB_STS_L1ENS_MASK)
297/*
298 * Internal VBUS connection status (used both in HS/FS and SS mode).
299 * 0 - internal VBUS is not detected.
300 * 1 - internal VBUS is detected.
301 */
302#define USB_STS_VBUSS_MASK BIT(17)
303#define USB_STS_VBUSS(p) ((p) & USB_STS_VBUSS_MASK)
304/*
305 * HS/FS LPM state (used in FS/HS mode).
306 * 0 - L0 State
307 * 1 - L1 State
308 * 2 - L2 State
309 * 3 - L3 State
310 */
311#define USB_STS_LPMST_MASK GENMASK(19, 18)
312#define DEV_L0_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x0 << 18))
313#define DEV_L1_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x1 << 18))
314#define DEV_L2_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x2 << 18))
315#define DEV_L3_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x3 << 18))
316/*
317 * Disable HS status (used in FS/HS mode).
318 * 0 - the disconnect bit for HS/FS mode is set .
319 * 1 - the disconnect bit for HS/FS mode is not set.
320 */
321#define USB_STS_USB2CONS_MASK BIT(20)
322#define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK)
323/*
324 * HS/FS mode connection status (used in FS/HS mode).
325 * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
326 * 1 - High Speed operations in USB2.0 (FS/HS).
327 */
328#define USB_STS_DISABLE_HS_MASK BIT(21)
329#define USB_STS_DISABLE_HS(p) ((p) & USB_STS_DISABLE_HS_MASK)
330/*
331 * U1 state enable status (used in SS mode).
332 * 0 - Entering to U1 state disabled.
333 * 1 - Entering to U1 state enabled.
334 */
335#define USB_STS_U1ENS_MASK BIT(24)
336#define USB_STS_U1ENS(p) ((p) & USB_STS_U1ENS_MASK)
337/*
338 * U2 state enable status (used in SS mode).
339 * 0 - Entering to U2 state disabled.
340 * 1 - Entering to U2 state enabled.
341 */
342#define USB_STS_U2ENS_MASK BIT(25)
343#define USB_STS_U2ENS(p) ((p) & USB_STS_U2ENS_MASK)
344/*
345 * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
346 * SuperSpeed link state
347 */
348#define USB_STS_LST_MASK GENMASK(29, 26)
349#define DEV_LST_U0 (((p) & USB_STS_LST_MASK) == (0x0 << 26))
350#define DEV_LST_U1 (((p) & USB_STS_LST_MASK) == (0x1 << 26))
351#define DEV_LST_U2 (((p) & USB_STS_LST_MASK) == (0x2 << 26))
352#define DEV_LST_U3 (((p) & USB_STS_LST_MASK) == (0x3 << 26))
353#define DEV_LST_DISABLED (((p) & USB_STS_LST_MASK) == (0x4 << 26))
354#define DEV_LST_RXDETECT (((p) & USB_STS_LST_MASK) == (0x5 << 26))
355#define DEV_LST_INACTIVE (((p) & USB_STS_LST_MASK) == (0x6 << 26))
356#define DEV_LST_POLLING (((p) & USB_STS_LST_MASK) == (0x7 << 26))
357#define DEV_LST_RECOVERY (((p) & USB_STS_LST_MASK) == (0x8 << 26))
358#define DEV_LST_HOT_RESET (((p) & USB_STS_LST_MASK) == (0x9 << 26))
359#define DEV_LST_COMP_MODE (((p) & USB_STS_LST_MASK) == (0xa << 26))
360#define DEV_LST_LB_STATE (((p) & USB_STS_LST_MASK) == (0xb << 26))
361/*
362 * DMA clock turn-off status.
363 * 0 - DMA clock is always on (default after hardware reset).
364 * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
365 */
366#define USB_STS_DMAOFF_MASK BIT(30)
367#define USB_STS_DMAOFF(p) ((p) & USB_STS_DMAOFF_MASK)
368/*
369 * SFR Endian status.
370 * 0 - Little Endian order (default after hardware reset).
371 * 1 - Big Endian order.
372 */
373#define USB_STS_ENDIAN2_MASK BIT(31)
374#define USB_STS_ENDIAN2(p) ((p) & USB_STS_ENDIAN2_MASK)
375
376/* USB_CMD - bitmasks */
377/* Set Function Address */
378#define USB_CMD_SET_ADDR BIT(0)
379/*
380 * Function Address This field is saved to the device only when the field
381 * SET_ADDR is set '1 ' during write to USB_CMD register.
382 * Software is responsible for entering the address of the device during
383 * SET_ADDRESS request service. This field should be set immediately after
384 * the SETUP packet is decoded, and prior to confirmation of the status phase
385 */
386#define USB_CMD_FADDR_MASK GENMASK(7, 1)
387#define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK)
388/* Send Function Wake Device Notification TP (used only in SS mode). */
389#define USB_CMD_SDNFW BIT(8)
390/* Set Test Mode (used only in HS/FS mode). */
391#define USB_CMD_STMODE BIT(9)
392/* Test mode selector (used only in HS/FS mode) */
393#define USB_STS_TMODE_SEL_MASK GENMASK(11, 10)
394#define USB_STS_TMODE_SEL(p) (((p) << 10) & USB_STS_TMODE_SEL_MASK)
395/*
396 * Send Latency Tolerance Message Device Notification TP (used only
397 * in SS mode).
398 */
399#define USB_CMD_SDNLTM BIT(12)
400/* Send Custom Transaction Packet (used only in SS mode) */
401#define USB_CMD_SPKT BIT(13)
402/*Device Notification 'Function Wake' - Interface value (only in SS mode. */
403#define USB_CMD_DNFW_INT_MASK GENMASK(23, 16)
404#define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK)
405/*
406 * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
407 * (used only in SS mode).
408 */
409#define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16)
410#define USB_STS_DNLTM_BELT(p) (((p) << 16) & USB_CMD_DNLTM_BELT_MASK)
411
412/* USB_ITPN - bitmasks */
413/*
414 * ITP(SS) / SOF (HS/FS) number
415 * In SS mode this field represent number of last ITP received from host.
416 * In HS/FS mode this field represent number of last SOF received from host.
417 */
418#define USB_ITPN_MASK GENMASK(13, 0)
419#define USB_ITPN(p) ((p) & USB_ITPN_MASK)
420
421/* USB_LPM - bitmasks */
422/* Host Initiated Resume Duration. */
423#define USB_LPM_HIRD_MASK GENMASK(3, 0)
424#define USB_LPM_HIRD(p) ((p) & USB_LPM_HIRD_MASK)
425/* Remote Wakeup Enable (bRemoteWake). */
426#define USB_LPM_BRW BIT(4)
427
428/* USB_IEN - bitmasks */
429/* SS connection interrupt enable */
430#define USB_IEN_CONIEN BIT(0)
431/* SS disconnection interrupt enable. */
432#define USB_IEN_DISIEN BIT(1)
433/* USB SS warm reset interrupt enable. */
434#define USB_IEN_UWRESIEN BIT(2)
435/* USB SS hot reset interrupt enable */
436#define USB_IEN_UHRESIEN BIT(3)
437/* SS link U3 state enter interrupt enable (suspend).*/
438#define USB_IEN_U3ENTIEN BIT(4)
439/* SS link U3 state exit interrupt enable (wakeup). */
440#define USB_IEN_U3EXTIEN BIT(5)
441/* SS link U2 state enter interrupt enable.*/
442#define USB_IEN_U2ENTIEN BIT(6)
443/* SS link U2 state exit interrupt enable.*/
444#define USB_IEN_U2EXTIEN BIT(7)
445/* SS link U1 state enter interrupt enable.*/
446#define USB_IEN_U1ENTIEN BIT(8)
447/* SS link U1 state exit interrupt enable.*/
448#define USB_IEN_U1EXTIEN BIT(9)
449/* ITP/SOF packet detected interrupt enable.*/
450#define USB_IEN_ITPIEN BIT(10)
451/* Wakeup interrupt enable.*/
452#define USB_IEN_WAKEIEN BIT(11)
453/* Send Custom Packet interrupt enable.*/
454#define USB_IEN_SPKTIEN BIT(12)
455/* HS/FS mode connection interrupt enable.*/
456#define USB_IEN_CON2IEN BIT(16)
457/* HS/FS mode disconnection interrupt enable.*/
458#define USB_IEN_DIS2IEN BIT(17)
459/* USB reset (HS/FS mode) interrupt enable.*/
460#define USB_IEN_U2RESIEN BIT(18)
461/* LPM L2 state enter interrupt enable.*/
462#define USB_IEN_L2ENTIEN BIT(20)
463/* LPM L2 state exit interrupt enable.*/
464#define USB_IEN_L2EXTIEN BIT(21)
465/* LPM L1 state enter interrupt enable.*/
466#define USB_IEN_L1ENTIEN BIT(24)
467/* LPM L1 state exit interrupt enable.*/
468#define USB_IEN_L1EXTIEN BIT(25)
469/* Configuration reset interrupt enable.*/
470#define USB_IEN_CFGRESIEN BIT(26)
471/* Start of the USB SS warm reset interrupt enable.*/
472#define USB_IEN_UWRESSIEN BIT(28)
473/* End of the USB SS warm reset interrupt enable.*/
474#define USB_IEN_UWRESEIEN BIT(29)
475
476#define USB_IEN_INIT (USB_IEN_U2RESIEN | USB_ISTS_DIS2I | USB_IEN_CON2IEN \
477 | USB_IEN_UHRESIEN | USB_IEN_UWRESIEN | USB_IEN_DISIEN \
478 | USB_IEN_CONIEN | USB_IEN_U3EXTIEN | USB_IEN_L2ENTIEN \
479 | USB_IEN_L2EXTIEN | USB_IEN_L1ENTIEN | USB_IEN_U3ENTIEN)
480
481/* USB_ISTS - bitmasks */
482/* SS Connection detected. */
483#define USB_ISTS_CONI BIT(0)
484/* SS Disconnection detected. */
485#define USB_ISTS_DISI BIT(1)
486/* UUSB warm reset detectede. */
487#define USB_ISTS_UWRESI BIT(2)
488/* USB hot reset detected. */
489#define USB_ISTS_UHRESI BIT(3)
490/* U3 link state enter detected (suspend).*/
491#define USB_ISTS_U3ENTI BIT(4)
492/* U3 link state exit detected (wakeup). */
493#define USB_ISTS_U3EXTI BIT(5)
494/* U2 link state enter detected.*/
495#define USB_ISTS_U2ENTI BIT(6)
496/* U2 link state exit detected.*/
497#define USB_ISTS_U2EXTI BIT(7)
498/* U1 link state enter detected.*/
499#define USB_ISTS_U1ENTI BIT(8)
500/* U1 link state exit detected.*/
501#define USB_ISTS_U1EXTI BIT(9)
502/* ITP/SOF packet detected.*/
503#define USB_ISTS_ITPI BIT(10)
504/* Wakeup detected.*/
505#define USB_ISTS_WAKEI BIT(11)
506/* Send Custom Packet detected.*/
507#define USB_ISTS_SPKTI BIT(12)
508/* HS/FS mode connection detected.*/
509#define USB_ISTS_CON2I BIT(16)
510/* HS/FS mode disconnection detected.*/
511#define USB_ISTS_DIS2I BIT(17)
512/* USB reset (HS/FS mode) detected.*/
513#define USB_ISTS_U2RESI BIT(18)
514/* LPM L2 state enter detected.*/
515#define USB_ISTS_L2ENTI BIT(20)
516/* LPM L2 state exit detected.*/
517#define USB_ISTS_L2EXTI BIT(21)
518/* LPM L1 state enter detected.*/
519#define USB_ISTS_L1ENTI BIT(24)
520/* LPM L1 state exit detected.*/
521#define USB_ISTS_L1EXTI BIT(25)
522/* USB configuration reset detected.*/
523#define USB_ISTS_CFGRESI BIT(26)
524/* Start of the USB warm reset detected.*/
525#define USB_ISTS_UWRESSI BIT(28)
526/* End of the USB warm reset detected.*/
527#define USB_ISTS_UWRESEI BIT(29)
528
529/* USB_SEL - bitmasks */
530#define EP_SEL_EPNO_MASK GENMASK(3, 0)
531/* Endpoint number. */
532#define EP_SEL_EPNO(p) ((p) & EP_SEL_EPNO_MASK)
533/* Endpoint direction bit - 0 - OUT, 1 - IN. */
534#define EP_SEL_DIR BIT(7)
535
536#define select_ep_in(nr) (EP_SEL_EPNO(p) | EP_SEL_DIR)
537#define select_ep_out (EP_SEL_EPNO(p))
538
539/* EP_TRADDR - bitmasks */
540/* Transfer Ring address. */
541#define EP_TRADDR_TRADDR(p) ((p))
542
543/* EP_CFG - bitmasks */
544/* Endpoint enable */
545#define EP_CFG_ENABLE BIT(0)
546/*
547 * Endpoint type.
548 * 1 - isochronous
549 * 2 - bulk
550 * 3 - interrupt
551 */
552#define EP_CFG_EPTYPE_MASK GENMASK(2, 1)
553#define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK)
554/* Stream support enable (only in SS mode). */
555#define EP_CFG_STREAM_EN BIT(3)
556/* TDL check (only in SS mode for BULK EP). */
557#define EP_CFG_TDL_CHK BIT(4)
558/* SID check (only in SS mode for BULK OUT EP). */
559#define EP_CFG_SID_CHK BIT(5)
560/* DMA transfer endianness. */
561#define EP_CFG_EPENDIAN BIT(7)
562/* Max burst size (used only in SS mode). */
563#define EP_CFG_MAXBURST_MASK GENMASK(11, 8)
564#define EP_CFG_MAXBURST(p) (((p) << 8) & EP_CFG_MAXBURST_MASK)
565#define EP_CFG_MAXBURST_MAX 15
566/* ISO max burst. */
567#define EP_CFG_MULT_MASK GENMASK(15, 14)
568#define EP_CFG_MULT(p) (((p) << 14) & EP_CFG_MULT_MASK)
569#define EP_CFG_MULT_MAX 2
570/* ISO max burst. */
571#define EP_CFG_MAXPKTSIZE_MASK GENMASK(26, 16)
572#define EP_CFG_MAXPKTSIZE(p) (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK)
573/* Max number of buffered packets. */
574#define EP_CFG_BUFFERING_MASK GENMASK(31, 27)
575#define EP_CFG_BUFFERING(p) (((p) << 27) & EP_CFG_BUFFERING_MASK)
576#define EP_CFG_BUFFERING_MAX 15
577
578/* EP_CMD - bitmasks */
579/* Endpoint reset. */
580#define EP_CMD_EPRST BIT(0)
581/* Endpoint STALL set. */
582#define EP_CMD_SSTALL BIT(1)
583/* Endpoint STALL clear. */
584#define EP_CMD_CSTALL BIT(2)
585/* Send ERDY TP. */
586#define EP_CMD_ERDY BIT(3)
587/* Request complete. */
588#define EP_CMD_REQ_CMPL BIT(5)
589/* Transfer descriptor ready. */
590#define EP_CMD_DRDY BIT(6)
591/* Data flush. */
592#define EP_CMD_DFLUSH BIT(7)
593/*
594 * Transfer Descriptor Length write (used only for Bulk Stream capable
595 * endpoints in SS mode).
596 * Bit Removed from DEV_VER_V3 controller version.
597 */
598#define EP_CMD_STDL BIT(8)
599/*
600 * Transfer Descriptor Length (used only in SS mode for bulk endpoints).
601 * Bits Removed from DEV_VER_V3 controller version.
602 */
603#define EP_CMD_TDL_MASK GENMASK(15, 9)
604#define EP_CMD_TDL_SET(p) (((p) << 9) & EP_CMD_TDL_MASK)
605#define EP_CMD_TDL_GET(p) (((p) & EP_CMD_TDL_MASK) >> 9)
606#define EP_CMD_TDL_MAX (EP_CMD_TDL_MASK >> 9)
607
608/* ERDY Stream ID value (used in SS mode). */
609#define EP_CMD_ERDY_SID_MASK GENMASK(31, 16)
610#define EP_CMD_ERDY_SID(p) (((p) << 16) & EP_CMD_ERDY_SID_MASK)
611
612/* EP_STS - bitmasks */
613/* Setup transfer complete. */
614#define EP_STS_SETUP BIT(0)
615/* Endpoint STALL status. */
616#define EP_STS_STALL(p) ((p) & BIT(1))
617/* Interrupt On Complete. */
618#define EP_STS_IOC BIT(2)
619/* Interrupt on Short Packet. */
620#define EP_STS_ISP BIT(3)
621/* Transfer descriptor missing. */
622#define EP_STS_DESCMIS BIT(4)
623/* Stream Rejected (used only in SS mode) */
624#define EP_STS_STREAMR BIT(5)
625/* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */
626#define EP_STS_MD_EXIT BIT(6)
627/* TRB error. */
628#define EP_STS_TRBERR BIT(7)
629/* Not ready (used only in SS mode). */
630#define EP_STS_NRDY BIT(8)
631/* DMA busy bit. */
632#define EP_STS_DBUSY BIT(9)
633/* Endpoint Buffer Empty */
634#define EP_STS_BUFFEMPTY(p) ((p) & BIT(10))
635/* Current Cycle Status */
636#define EP_STS_CCS(p) ((p) & BIT(11))
637/* Prime (used only in SS mode. */
638#define EP_STS_PRIME BIT(12)
639/* Stream error (used only in SS mode). */
640#define EP_STS_SIDERR BIT(13)
641/* OUT size mismatch. */
642#define EP_STS_OUTSMM BIT(14)
643/* ISO transmission error. */
644#define EP_STS_ISOERR BIT(15)
645/* Host Packet Pending (only for SS mode). */
646#define EP_STS_HOSTPP(p) ((p) & BIT(16))
647/* Stream Protocol State Machine State (only for Bulk stream endpoints). */
648#define EP_STS_SPSMST_MASK GENMASK(18, 17)
649#define EP_STS_SPSMST_DISABLED(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
650#define EP_STS_SPSMST_IDLE(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
651#define EP_STS_SPSMST_START_STREAM(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
652#define EP_STS_SPSMST_MOVE_DATA(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
653/* Interrupt On Transfer complete. */
654#define EP_STS_IOT BIT(19)
655/* OUT queue endpoint number. */
656#define EP_STS_OUTQ_NO_MASK GENMASK(27, 24)
657#define EP_STS_OUTQ_NO(p) (((p) & EP_STS_OUTQ_NO_MASK) >> 24)
658/* OUT queue valid flag. */
659#define EP_STS_OUTQ_VAL_MASK BIT(28)
660#define EP_STS_OUTQ_VAL(p) ((p) & EP_STS_OUTQ_VAL_MASK)
661/* SETUP WAIT. */
662#define EP_STS_STPWAIT BIT(31)
663
664/* EP_STS_SID - bitmasks */
665/* Stream ID (used only in SS mode). */
666#define EP_STS_SID_MASK GENMASK(15, 0)
667#define EP_STS_SID(p) ((p) & EP_STS_SID_MASK)
668
669/* EP_STS_EN - bitmasks */
670/* SETUP interrupt enable. */
671#define EP_STS_EN_SETUPEN BIT(0)
672/* OUT transfer missing descriptor enable. */
673#define EP_STS_EN_DESCMISEN BIT(4)
674/* Stream Rejected enable. */
675#define EP_STS_EN_STREAMREN BIT(5)
676/* Move Data Exit enable.*/
677#define EP_STS_EN_MD_EXITEN BIT(6)
678/* TRB enable. */
679#define EP_STS_EN_TRBERREN BIT(7)
680/* NRDY enable. */
681#define EP_STS_EN_NRDYEN BIT(8)
682/* Prime enable. */
683#define EP_STS_EN_PRIMEEEN BIT(12)
684/* Stream error enable. */
685#define EP_STS_EN_SIDERREN BIT(13)
686/* OUT size mismatch enable. */
687#define EP_STS_EN_OUTSMMEN BIT(14)
688/* ISO transmission error enable. */
689#define EP_STS_EN_ISOERREN BIT(15)
690/* Interrupt on Transmission complete enable. */
691#define EP_STS_EN_IOTEN BIT(19)
692/* Setup Wait interrupt enable. */
693#define EP_STS_EN_STPWAITEN BIT(31)
694
695/* DRBL- bitmasks */
696#define DB_VALUE_BY_INDEX(index) (1 << (index))
697#define DB_VALUE_EP0_OUT BIT(0)
698#define DB_VALUE_EP0_IN BIT(16)
699
700/* EP_IEN - bitmasks */
701#define EP_IEN(index) (1 << (index))
702#define EP_IEN_EP_OUT0 BIT(0)
703#define EP_IEN_EP_IN0 BIT(16)
704
705/* EP_ISTS - bitmasks */
706#define EP_ISTS(index) (1 << (index))
707#define EP_ISTS_EP_OUT0 BIT(0)
708#define EP_ISTS_EP_IN0 BIT(16)
709
710/* USB_PWR- bitmasks */
711/*Power Shut Off capability enable*/
712#define PUSB_PWR_PSO_EN BIT(0)
713/*Power Shut Off capability disable*/
714#define PUSB_PWR_PSO_DS BIT(1)
715/*
716 * Enables turning-off Reference Clock.
717 * This bit is optional and implemented only when support for OTG is
718 * implemented (indicated by OTG_READY bit set to '1').
719 */
720#define PUSB_PWR_STB_CLK_SWITCH_EN BIT(8)
721/*
722 * Status bit indicating that operation required by STB_CLK_SWITCH_EN write
723 * is completed
724 */
725#define PUSB_PWR_STB_CLK_SWITCH_DONE BIT(9)
726/* This bit informs if Fast Registers Access is enabled. */
727#define PUSB_PWR_FST_REG_ACCESS_STAT BIT(30)
728/* Fast Registers Access Enable. */
729#define PUSB_PWR_FST_REG_ACCESS BIT(31)
730
731/* USB_CONF2- bitmasks */
732/*
733 * Writing 1 disables TDL calculation basing on TRB feature in controller
734 * for DMULT mode.
735 * Bit supported only for DEV_VER_V2 version.
736 */
737#define USB_CONF2_DIS_TDL_TRB BIT(1)
738/*
739 * Writing 1 enables TDL calculation basing on TRB feature in controller
740 * for DMULT mode.
741 * Bit supported only for DEV_VER_V2 version.
742 */
743#define USB_CONF2_EN_TDL_TRB BIT(2)
744
745/* USB_CAP1- bitmasks */
746/*
747 * SFR Interface type
748 * These field reflects type of SFR interface implemented:
749 * 0x0 - OCP
750 * 0x1 - AHB,
751 * 0x2 - PLB
752 * 0x3 - AXI
753 * 0x4-0xF - reserved
754 */
755#define USB_CAP1_SFR_TYPE_MASK GENMASK(3, 0)
756#define DEV_SFR_TYPE_OCP(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0)
757#define DEV_SFR_TYPE_AHB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1)
758#define DEV_SFR_TYPE_PLB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2)
759#define DEV_SFR_TYPE_AXI(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3)
760/*
761 * SFR Interface width
762 * These field reflects width of SFR interface implemented:
763 * 0x0 - 8 bit interface,
764 * 0x1 - 16 bit interface,
765 * 0x2 - 32 bit interface
766 * 0x3 - 64 bit interface
767 * 0x4-0xF - reserved
768 */
769#define USB_CAP1_SFR_WIDTH_MASK GENMASK(7, 4)
770#define DEV_SFR_WIDTH_8(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4))
771#define DEV_SFR_WIDTH_16(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4))
772#define DEV_SFR_WIDTH_32(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4))
773#define DEV_SFR_WIDTH_64(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4))
774/*
775 * DMA Interface type
776 * These field reflects type of DMA interface implemented:
777 * 0x0 - OCP
778 * 0x1 - AHB,
779 * 0x2 - PLB
780 * 0x3 - AXI
781 * 0x4-0xF - reserved
782 */
783#define USB_CAP1_DMA_TYPE_MASK GENMASK(11, 8)
784#define DEV_DMA_TYPE_OCP(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8))
785#define DEV_DMA_TYPE_AHB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8))
786#define DEV_DMA_TYPE_PLB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8))
787#define DEV_DMA_TYPE_AXI(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8))
788/*
789 * DMA Interface width
790 * These field reflects width of DMA interface implemented:
791 * 0x0 - reserved,
792 * 0x1 - reserved,
793 * 0x2 - 32 bit interface
794 * 0x3 - 64 bit interface
795 * 0x4-0xF - reserved
796 */
797#define USB_CAP1_DMA_WIDTH_MASK GENMASK(15, 12)
798#define DEV_DMA_WIDTH_32(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12))
799#define DEV_DMA_WIDTH_64(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12))
800/*
801 * USB3 PHY Interface type
802 * These field reflects type of USB3 PHY interface implemented:
803 * 0x0 - USB PIPE,
804 * 0x1 - RMMI,
805 * 0x2-0xF - reserved
806 */
807#define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16)
808#define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16))
809#define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16))
810/*
811 * USB3 PHY Interface width
812 * These field reflects width of USB3 PHY interface implemented:
813 * 0x0 - 8 bit PIPE interface,
814 * 0x1 - 16 bit PIPE interface,
815 * 0x2 - 32 bit PIPE interface,
816 * 0x3 - 64 bit PIPE interface
817 * 0x4-0xF - reserved
818 * Note: When SSIC interface is implemented this field shows the width of
819 * internal PIPE interface. The RMMI interface is always 20bit wide.
820 */
821#define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20)
822#define DEV_U3PHY_WIDTH_8(p) \
823 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20))
824#define DEV_U3PHY_WIDTH_16(p) \
825 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16))
826#define DEV_U3PHY_WIDTH_32(p) \
827 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20))
828#define DEV_U3PHY_WIDTH_64(p) \
829 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16))
830
831/*
832 * USB2 PHY Interface enable
833 * These field informs if USB2 PHY interface is implemented:
834 * 0x0 - interface NOT implemented,
835 * 0x1 - interface implemented
836 */
837#define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24))
838/*
839 * USB2 PHY Interface type
840 * These field reflects type of USB2 PHY interface implemented:
841 * 0x0 - UTMI,
842 * 0x1 - ULPI
843 */
844#define DEV_U2PHY_ULPI(p) ((p) & BIT(25))
845/*
846 * USB2 PHY Interface width
847 * These field reflects width of USB2 PHY interface implemented:
848 * 0x0 - 8 bit interface,
849 * 0x1 - 16 bit interface,
850 * Note: The ULPI interface is always 8bit wide.
851 */
852#define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26))
853/*
854 * OTG Ready
855 * 0x0 - pure device mode
856 * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
857 */
858#define USB_CAP1_OTG_READY(p) ((p) & BIT(27))
859
860/*
861 * When set, indicates that controller supports automatic internal TDL
862 * calculation basing on the size provided in TRB (TRB[22:17]) for DMULT mode
863 * Supported only for DEV_VER_V2 controller version.
864 */
865#define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28))
866
867/* USB_CAP2- bitmasks */
868/*
869 * The actual size of the connected On-chip RAM memory in kB:
870 * - 0 means 256 kB (max supported mem size)
871 * - value other than 0 reflects the mem size in kB
872 */
873#define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0))
874/*
875 * Max supported mem size
876 * These field reflects width of on-chip RAM address bus width,
877 * which determines max supported mem size:
878 * 0x0-0x7 - reserved,
879 * 0x8 - support for 4kB mem,
880 * 0x9 - support for 8kB mem,
881 * 0xA - support for 16kB mem,
882 * 0xB - support for 32kB mem,
883 * 0xC - support for 64kB mem,
884 * 0xD - support for 128kB mem,
885 * 0xE - support for 256kB mem,
886 * 0xF - reserved
887 */
888#define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8))
889
890/* USB_CAP3- bitmasks */
891#define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index)))
892
893/* USB_CAP4- bitmasks */
894#define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index)))
895
896/* USB_CAP5- bitmasks */
897#define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index)))
898
899/* USB_CAP6- bitmasks */
900/* The USBSS-DEV Controller Internal build number. */
901#define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0))
902/* The USBSS-DEV Controller version number. */
903#define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24))
904
905#define DEV_VER_NXP_V1 0x00024502
906#define DEV_VER_TI_V1 0x00024509
907#define DEV_VER_V2 0x0002450C
908#define DEV_VER_V3 0x0002450d
909
910/* DBG_LINK1- bitmasks */
911/*
912 * LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum
913 * time required for decoding the received LFPS as an LFPS.U1_Exit.
914 */
915#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0))
916/*
917 * LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for
918 * phytxelecidle deassertion when LFPS.U1_Exit
919 */
920#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK GENMASK(15, 8)
921#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8))
922/*
923 * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
924 * Receiver termination detection sequence:
925 * 0: it is possible that USBSS_DEV will terminate Farend receiver
926 * termination detection sequence
927 * 1: USBSS_DEV will not terminate Far-end receiver termination
928 * detection sequence
929 */
930#define DBG_LINK1_RXDET_BREAK_DIS BIT(16)
931/* LFPS_GEN_PING value This parameter configures the LFPS.Ping generation */
932#define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17))
933/*
934 * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the
935 * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically
936 * cleared. Writing '0' has no effect
937 */
938#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET BIT(24)
939/*
940 * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the
941 * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically
942 * cleared. Writing '0' has no effect
943 */
944#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET BIT(25)
945/*
946 * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes
947 * the RXDET_BREAK_DIS field value to the device. This bit is automatically
948 * cleared. Writing '0' has no effect
949 */
950#define DBG_LINK1_RXDET_BREAK_DIS_SET BIT(26)
951/*
952 * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes
953 * the LFPS_GEN_PING field value to the device. This bit is automatically
954 * cleared. Writing '0' has no effect."
955 */
956#define DBG_LINK1_LFPS_GEN_PING_SET BIT(27)
957
958/* DMA_AXI_CTRL- bitmasks */
959/* The mawprot pin configuration. */
960#define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0))
961/* The marprot pin configuration. */
962#define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16)
963#define DMA_AXI_CTRL_NON_SECURE 0x02
964
965#define gadget_to_cdns3_device(g) (container_of(g, struct cdns3_device, gadget))
966
967#define ep_to_cdns3_ep(ep) (container_of(ep, struct cdns3_endpoint, endpoint))
968
969/*-------------------------------------------------------------------------*/
970/*
971 * USBSS-DEV DMA interface.
972 */
973#define TRBS_PER_SEGMENT 600
974
975#define ISO_MAX_INTERVAL 10
976
977#define MAX_TRB_LENGTH BIT(16)
978
979#if TRBS_PER_SEGMENT < 2
980#error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2."
981#endif
982
983#define TRBS_PER_STREAM_SEGMENT 2
984
985#if TRBS_PER_STREAM_SEGMENT < 2
986#error "Incorrect TRBS_PER_STREAMS_SEGMENT. Minimal Transfer Ring size is 2."
987#endif
988
989/*
990 *Only for ISOC endpoints - maximum number of TRBs is calculated as
991 * pow(2, bInterval-1) * number of usb requests. It is limitation made by
992 * driver to save memory. Controller must prepare TRB for each ITP even
993 * if bInterval > 1. It's the reason why driver needs so many TRBs for
994 * isochronous endpoints.
995 */
996#define TRBS_PER_ISOC_SEGMENT (ISO_MAX_INTERVAL * 8)
997
998#define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \
999 TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT)
1000/**
1001 * struct cdns3_trb - represent Transfer Descriptor block.
1002 * @buffer: pointer to buffer data
1003 * @length: length of data
1004 * @control: control flags.
1005 *
1006 * This structure describes transfer block serviced by DMA module.
1007 */
1008struct cdns3_trb {
1009 __le32 buffer;
1010 __le32 length;
1011 __le32 control;
1012};
1013
1014#define TRB_SIZE (sizeof(struct cdns3_trb))
1015#define TRB_RING_SIZE (TRB_SIZE * TRBS_PER_SEGMENT)
1016#define TRB_STREAM_RING_SIZE (TRB_SIZE * TRBS_PER_STREAM_SEGMENT)
1017#define TRB_ISO_RING_SIZE (TRB_SIZE * TRBS_PER_ISOC_SEGMENT)
1018#define TRB_CTRL_RING_SIZE (TRB_SIZE * 2)
1019
1020/* TRB bit mask */
1021#define TRB_TYPE_BITMASK GENMASK(15, 10)
1022#define TRB_TYPE(p) ((p) << 10)
1023#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1024
1025/* TRB type IDs */
1026/* bulk, interrupt, isoc , and control data stage */
1027#define TRB_NORMAL 1
1028/* TRB for linking ring segments */
1029#define TRB_LINK 6
1030
1031/* Cycle bit - indicates TRB ownership by driver or hw*/
1032#define TRB_CYCLE BIT(0)
1033/*
1034 * When set to '1', the device will toggle its interpretation of the Cycle bit
1035 */
1036#define TRB_TOGGLE BIT(1)
1037/*
1038 * The controller will set it if OUTSMM (OUT size mismatch) is detected,
1039 * this bit is for normal TRB
1040 */
1041#define TRB_SMM BIT(1)
1042
1043/*
1044 * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was
1045 * processed while USB short packet was received. No more buffers defined by
1046 * the TD will be used. DMA will automatically advance to next TD.
1047 * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
1048 * - Shall be set to 1 by Controller when Short Packet condition for this TRB
1049 * is detected independent if ISP is set or not.
1050 */
1051#define TRB_SP BIT(1)
1052
1053/* Interrupt on short packet*/
1054#define TRB_ISP BIT(2)
1055/*Setting this bit enables FIFO DMA operation mode*/
1056#define TRB_FIFO_MODE BIT(3)
1057/* Set PCIe no snoop attribute */
1058#define TRB_CHAIN BIT(4)
1059/* Interrupt on completion */
1060#define TRB_IOC BIT(5)
1061
1062/* stream ID bitmasks. */
1063#define TRB_STREAM_ID_BITMASK GENMASK(31, 16)
1064#define TRB_STREAM_ID(p) ((p) << 16)
1065#define TRB_FIELD_TO_STREAMID(p) (((p) & TRB_STREAM_ID_BITMASK) >> 16)
1066
1067/* Size of TD expressed in USB packets for HS/FS mode. */
1068#define TRB_TDL_HS_SIZE(p) (((p) << 16) & GENMASK(31, 16))
1069#define TRB_TDL_HS_SIZE_GET(p) (((p) & GENMASK(31, 16)) >> 16)
1070
1071/* transfer_len bitmasks. */
1072#define TRB_LEN(p) ((p) & GENMASK(16, 0))
1073
1074/* Size of TD expressed in USB packets for SS mode. */
1075#define TRB_TDL_SS_SIZE(p) (((p) << 17) & GENMASK(23, 17))
1076#define TRB_TDL_SS_SIZE_GET(p) (((p) & GENMASK(23, 17)) >> 17)
1077
1078/* transfer_len bitmasks - bits 31:24 */
1079#define TRB_BURST_LEN(p) ((unsigned int)((p) << 24) & GENMASK(31, 24))
1080#define TRB_BURST_LEN_GET(p) (((p) & GENMASK(31, 24)) >> 24)
1081
1082/* Data buffer pointer bitmasks*/
1083#define TRB_BUFFER(p) ((p) & GENMASK(31, 0))
1084
1085/*-------------------------------------------------------------------------*/
1086/* Driver numeric constants */
1087
1088/* Such declaration should be added to ch9.h */
1089#define USB_DEVICE_MAX_ADDRESS 127
1090
1091/* Endpoint init values */
1092#define CDNS3_EP_MAX_PACKET_LIMIT 1024
1093#define CDNS3_EP_MAX_STREAMS 15
1094#define CDNS3_EP0_MAX_PACKET_LIMIT 512
1095
1096/* All endpoints including EP0 */
1097#define CDNS3_ENDPOINTS_MAX_COUNT 32
1098#define CDNS3_EP_ZLP_BUF_SIZE 1024
1099
1100#define CDNS3_MAX_NUM_DESCMISS_BUF 32
1101#define CDNS3_DESCMIS_BUF_SIZE 2048 /* Bytes */
1102#define CDNS3_WA2_NUM_BUFFERS 128
1103/*-------------------------------------------------------------------------*/
1104/* Used structs */
1105
1106struct cdns3_device;
1107
1108/**
1109 * struct cdns3_endpoint - extended device side representation of USB endpoint.
1110 * @endpoint: usb endpoint
1111 * @pending_req_list: list of requests queuing on transfer ring.
1112 * @deferred_req_list: list of requests waiting for queuing on transfer ring.
1113 * @wa2_descmiss_req_list: list of requests internally allocated by driver.
1114 * @trb_pool: transfer ring - array of transaction buffers
1115 * @trb_pool_dma: dma address of transfer ring
1116 * @cdns3_dev: device associated with this endpoint
1117 * @name: a human readable name e.g. ep1out
1118 * @flags: specify the current state of endpoint
1119 * @descmis_req: internal transfer object used for getting data from on-chip
1120 * buffer. It can happen only if function driver doesn't send usb_request
1121 * object on time.
1122 * @dir: endpoint direction
1123 * @num: endpoint number (1 - 15)
1124 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
1125 * @interval: interval between packets used for ISOC endpoint.
1126 * @free_trbs: number of free TRBs in transfer ring
1127 * @num_trbs: number of all TRBs in transfer ring
1128 * @alloc_ring_size: size of the allocated TRB ring
1129 * @pcs: producer cycle state
1130 * @ccs: consumer cycle state
1131 * @enqueue: enqueue index in transfer ring
1132 * @dequeue: dequeue index in transfer ring
1133 * @trb_burst_size: number of burst used in trb.
1134 */
1135struct cdns3_endpoint {
1136 struct usb_ep endpoint;
1137 struct list_head pending_req_list;
1138 struct list_head deferred_req_list;
1139 struct list_head wa2_descmiss_req_list;
1140 int wa2_counter;
1141
1142 struct cdns3_trb *trb_pool;
1143 dma_addr_t trb_pool_dma;
1144
1145 struct cdns3_device *cdns3_dev;
1146 char name[20];
1147
1148#define EP_ENABLED BIT(0)
1149#define EP_STALLED BIT(1)
1150#define EP_STALL_PENDING BIT(2)
1151#define EP_WEDGE BIT(3)
1152#define EP_TRANSFER_STARTED BIT(4)
1153#define EP_UPDATE_EP_TRBADDR BIT(5)
1154#define EP_PENDING_REQUEST BIT(6)
1155#define EP_RING_FULL BIT(7)
1156#define EP_CLAIMED BIT(8)
1157#define EP_DEFERRED_DRDY BIT(9)
1158#define EP_QUIRK_ISO_OUT_EN BIT(10)
1159#define EP_QUIRK_END_TRANSFER BIT(11)
1160#define EP_QUIRK_EXTRA_BUF_DET BIT(12)
1161#define EP_QUIRK_EXTRA_BUF_EN BIT(13)
1162#define EP_TDLCHK_EN BIT(15)
1163#define EP_CONFIGURED BIT(16)
1164 u32 flags;
1165
1166 struct cdns3_request *descmis_req;
1167
1168 u8 dir;
1169 u8 num;
1170 u8 type;
1171 u8 mult;
1172 u8 bMaxBurst;
1173 u16 wMaxPacketSize;
1174 int interval;
1175
1176 int free_trbs;
1177 int num_trbs;
1178 int alloc_ring_size;
1179 u8 pcs;
1180 u8 ccs;
1181 int enqueue;
1182 int dequeue;
1183 u8 trb_burst_size;
1184
1185 unsigned int wa1_set:1;
1186 struct cdns3_trb *wa1_trb;
1187 unsigned int wa1_trb_index;
1188 unsigned int wa1_cycle_bit:1;
1189
1190 /* Stream related */
1191 unsigned int use_streams:1;
1192 unsigned int prime_flag:1;
1193 u32 ep_sts_pending;
1194 u16 last_stream_id;
1195 u16 pending_tdl;
1196 unsigned int stream_sg_idx;
1197};
1198
1199/**
1200 * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
1201 * @buf: aligned to 8 bytes data buffer. Buffer address used in
1202 * TRB shall be aligned to 8.
1203 * @dma: dma address
1204 * @size: size of buffer
1205 * @in_use: inform if this buffer is associated with usb_request
1206 * @list: used to adding instance of this object to list
1207 */
1208struct cdns3_aligned_buf {
1209 void *buf;
1210 dma_addr_t dma;
1211 u32 size;
1212 enum dma_data_direction dir;
1213 unsigned in_use:1;
1214 struct list_head list;
1215};
1216
1217/**
1218 * struct cdns3_request - extended device side representation of usb_request
1219 * object .
1220 * @request: generic usb_request object describing single I/O request.
1221 * @priv_ep: extended representation of usb_ep object
1222 * @trb: the first TRB association with this request
1223 * @start_trb: number of the first TRB in transfer ring
1224 * @end_trb: number of the last TRB in transfer ring
1225 * @aligned_buf: object holds information about aligned buffer associated whit
1226 * this endpoint
1227 * @flags: flag specifying special usage of request
1228 * @list: used by internally allocated request to add to wa2_descmiss_req_list.
1229 * @finished_trb: number of trb has already finished per request
1230 * @num_of_trb: how many trbs in this request
1231 */
1232struct cdns3_request {
1233 struct usb_request request;
1234 struct cdns3_endpoint *priv_ep;
1235 struct cdns3_trb *trb;
1236 int start_trb;
1237 int end_trb;
1238 struct cdns3_aligned_buf *aligned_buf;
1239#define REQUEST_PENDING BIT(0)
1240#define REQUEST_INTERNAL BIT(1)
1241#define REQUEST_INTERNAL_CH BIT(2)
1242#define REQUEST_ZLP BIT(3)
1243#define REQUEST_UNALIGNED BIT(4)
1244 u32 flags;
1245 struct list_head list;
1246 int finished_trb;
1247 int num_of_trb;
1248};
1249
1250#define to_cdns3_request(r) (container_of(r, struct cdns3_request, request))
1251
1252/*Stages used during enumeration process.*/
1253#define CDNS3_SETUP_STAGE 0x0
1254#define CDNS3_DATA_STAGE 0x1
1255#define CDNS3_STATUS_STAGE 0x2
1256
1257/**
1258 * struct cdns3_device - represent USB device.
1259 * @dev: pointer to device structure associated whit this controller
1260 * @sysdev: pointer to the DMA capable device
1261 * @gadget: device side representation of the peripheral controller
1262 * @gadget_driver: pointer to the gadget driver
1263 * @dev_ver: device controller version.
1264 * @lock: for synchronizing
1265 * @regs: base address for device side registers
1266 * @setup_buf: used while processing usb control requests
1267 * @setup_dma: dma address for setup_buf
1268 * @zlp_buf - zlp buffer
1269 * @ep0_stage: ep0 stage during enumeration process.
1270 * @ep0_data_dir: direction for control transfer
1271 * @eps: array of pointers to all endpoints with exclusion ep0
1272 * @aligned_buf_list: list of aligned buffers internally allocated by driver
1273 * @aligned_buf_wq: workqueue freeing no longer used aligned buf.
1274 * @selected_ep: actually selected endpoint. It's used only to improve
1275 * performance.
1276 * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP.
1277 * @u1_allowed: allow device transition to u1 state
1278 * @u2_allowed: allow device transition to u2 state
1279 * @is_selfpowered: device is self powered
1280 * @setup_pending: setup packet is processing by gadget driver
1281 * @hw_configured_flag: hardware endpoint configuration was set.
1282 * @wake_up_flag: allow device to remote up the host
1283 * @status_completion_no_call: indicate that driver is waiting for status s
1284 * stage completion. It's used in deferred SET_CONFIGURATION request.
1285 * @onchip_buffers: number of available on-chip buffers.
1286 * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
1287 * @pending_status_wq: workqueue handling status stage for deferred requests.
1288 * @pending_status_request: request for which status stage was deferred
1289 */
1290struct cdns3_device {
1291 struct device *dev;
1292 struct device *sysdev;
1293
1294 struct usb_gadget gadget;
1295 struct usb_gadget_driver *gadget_driver;
1296
1297#define CDNS_REVISION_V0 0x00024501
1298#define CDNS_REVISION_V1 0x00024509
1299 u32 dev_ver;
1300
1301 /* generic spin-lock for drivers */
1302 spinlock_t lock;
1303
1304 struct cdns3_usb_regs __iomem *regs;
1305
1306 struct dma_pool *eps_dma_pool;
1307 struct usb_ctrlrequest *setup_buf;
1308 dma_addr_t setup_dma;
1309 void *zlp_buf;
1310
1311 u8 ep0_stage;
1312 int ep0_data_dir;
1313
1314 struct cdns3_endpoint *eps[CDNS3_ENDPOINTS_MAX_COUNT];
1315
1316 struct list_head aligned_buf_list;
1317 struct work_struct aligned_buf_wq;
1318
1319 u32 selected_ep;
1320 u16 isoch_delay;
1321
1322 unsigned wait_for_setup:1;
1323 unsigned u1_allowed:1;
1324 unsigned u2_allowed:1;
1325 unsigned is_selfpowered:1;
1326 unsigned setup_pending:1;
1327 unsigned hw_configured_flag:1;
1328 unsigned wake_up_flag:1;
1329 unsigned status_completion_no_call:1;
1330 unsigned using_streams:1;
1331 int out_mem_is_allocated;
1332
1333 struct work_struct pending_status_wq;
1334 struct usb_request *pending_status_request;
1335
1336 /*in KB */
1337 u16 onchip_buffers;
1338 u16 onchip_used_size;
1339
1340 u16 ep_buf_size;
1341 u16 ep_iso_burst;
1342};
1343
1344void cdns3_set_register_bit(void __iomem *ptr, u32 mask);
1345dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
1346 struct cdns3_trb *trb);
1347enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev);
1348void cdns3_pending_setup_status_handler(struct work_struct *work);
1349void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev);
1350void cdns3_set_hw_configuration(struct cdns3_device *priv_dev);
1351void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep);
1352void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable);
1353struct usb_request *cdns3_next_request(struct list_head *list);
1354void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm);
1355int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep);
1356u8 cdns3_ep_addr_to_index(u8 ep_addr);
1357int cdns3_gadget_ep_set_wedge(struct usb_ep *ep);
1358int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value);
1359void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep);
1360int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep);
1361struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
1362 gfp_t gfp_flags);
1363void cdns3_gadget_ep_free_request(struct usb_ep *ep,
1364 struct usb_request *request);
1365int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request);
1366void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
1367 struct cdns3_request *priv_req,
1368 int status);
1369
1370int cdns3_init_ep0(struct cdns3_device *priv_dev,
1371 struct cdns3_endpoint *priv_ep);
1372void cdns3_ep0_config(struct cdns3_device *priv_dev);
1373int cdns3_ep_config(struct cdns3_endpoint *priv_ep, bool enable);
1374void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir);
1375int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev);
1376
1377#endif /* __LINUX_CDNS3_GADGET */