Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/module.h>
17#include <linux/platform_device.h>
18
19#include <dt-bindings/thermal/tegra124-soctherm.h>
20
21#include "soctherm.h"
22
23#define TEGRA124_THERMTRIP_ANY_EN_MASK (0x1 << 28)
24#define TEGRA124_THERMTRIP_MEM_EN_MASK (0x1 << 27)
25#define TEGRA124_THERMTRIP_GPU_EN_MASK (0x1 << 26)
26#define TEGRA124_THERMTRIP_CPU_EN_MASK (0x1 << 25)
27#define TEGRA124_THERMTRIP_TSENSE_EN_MASK (0x1 << 24)
28#define TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16)
29#define TEGRA124_THERMTRIP_CPU_THRESH_MASK (0xff << 8)
30#define TEGRA124_THERMTRIP_TSENSE_THRESH_MASK 0xff
31
32#define TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17)
33#define TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9)
34
35#define TEGRA124_THRESH_GRAIN 1000
36#define TEGRA124_BPTT 8
37
38static const struct tegra_tsensor_configuration tegra124_tsensor_config = {
39 .tall = 16300,
40 .tiddq_en = 1,
41 .ten_count = 1,
42 .tsample = 120,
43 .tsample_ate = 480,
44};
45
46static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = {
47 .id = TEGRA124_SOCTHERM_SENSOR_CPU,
48 .name = "cpu",
49 .sensor_temp_offset = SENSOR_TEMP1,
50 .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
51 .pdiv = 8,
52 .pdiv_ate = 8,
53 .pdiv_mask = SENSOR_PDIV_CPU_MASK,
54 .pllx_hotspot_diff = 10,
55 .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
56 .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
57 .thermtrip_enable_mask = TEGRA124_THERMTRIP_CPU_EN_MASK,
58 .thermtrip_threshold_mask = TEGRA124_THERMTRIP_CPU_THRESH_MASK,
59 .thermctl_isr_mask = THERM_IRQ_CPU_MASK,
60 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
61 .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
62 .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
63};
64
65static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
66 .id = TEGRA124_SOCTHERM_SENSOR_GPU,
67 .name = "gpu",
68 .sensor_temp_offset = SENSOR_TEMP1,
69 .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
70 .pdiv = 8,
71 .pdiv_ate = 8,
72 .pdiv_mask = SENSOR_PDIV_GPU_MASK,
73 .pllx_hotspot_diff = 5,
74 .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
75 .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
76 .thermtrip_enable_mask = TEGRA124_THERMTRIP_GPU_EN_MASK,
77 .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK,
78 .thermctl_isr_mask = THERM_IRQ_GPU_MASK,
79 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
80 .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
81 .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
82};
83
84static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
85 .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
86 .name = "pll",
87 .sensor_temp_offset = SENSOR_TEMP2,
88 .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
89 .pdiv = 8,
90 .pdiv_ate = 8,
91 .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
92 .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
93 .thermtrip_enable_mask = TEGRA124_THERMTRIP_TSENSE_EN_MASK,
94 .thermtrip_threshold_mask = TEGRA124_THERMTRIP_TSENSE_THRESH_MASK,
95 .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
96 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
97 .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
98 .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
99};
100
101static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
102 .id = TEGRA124_SOCTHERM_SENSOR_MEM,
103 .name = "mem",
104 .sensor_temp_offset = SENSOR_TEMP2,
105 .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
106 .pdiv = 8,
107 .pdiv_ate = 8,
108 .pdiv_mask = SENSOR_PDIV_MEM_MASK,
109 .pllx_hotspot_diff = 0,
110 .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
111 .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
112 .thermtrip_enable_mask = TEGRA124_THERMTRIP_MEM_EN_MASK,
113 .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK,
114 .thermctl_isr_mask = THERM_IRQ_MEM_MASK,
115 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
116 .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
117 .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
118};
119
120static const struct tegra_tsensor_group *tegra124_tsensor_groups[] = {
121 &tegra124_tsensor_group_cpu,
122 &tegra124_tsensor_group_gpu,
123 &tegra124_tsensor_group_pll,
124 &tegra124_tsensor_group_mem,
125};
126
127static const struct tegra_tsensor tegra124_tsensors[] = {
128 {
129 .name = "cpu0",
130 .base = 0xc0,
131 .config = &tegra124_tsensor_config,
132 .calib_fuse_offset = 0x098,
133 .fuse_corr_alpha = 1135400,
134 .fuse_corr_beta = -6266900,
135 .group = &tegra124_tsensor_group_cpu,
136 }, {
137 .name = "cpu1",
138 .base = 0xe0,
139 .config = &tegra124_tsensor_config,
140 .calib_fuse_offset = 0x084,
141 .fuse_corr_alpha = 1122220,
142 .fuse_corr_beta = -5700700,
143 .group = &tegra124_tsensor_group_cpu,
144 }, {
145 .name = "cpu2",
146 .base = 0x100,
147 .config = &tegra124_tsensor_config,
148 .calib_fuse_offset = 0x088,
149 .fuse_corr_alpha = 1127000,
150 .fuse_corr_beta = -6768200,
151 .group = &tegra124_tsensor_group_cpu,
152 }, {
153 .name = "cpu3",
154 .base = 0x120,
155 .config = &tegra124_tsensor_config,
156 .calib_fuse_offset = 0x12c,
157 .fuse_corr_alpha = 1110900,
158 .fuse_corr_beta = -6232000,
159 .group = &tegra124_tsensor_group_cpu,
160 }, {
161 .name = "mem0",
162 .base = 0x140,
163 .config = &tegra124_tsensor_config,
164 .calib_fuse_offset = 0x158,
165 .fuse_corr_alpha = 1122300,
166 .fuse_corr_beta = -5936400,
167 .group = &tegra124_tsensor_group_mem,
168 }, {
169 .name = "mem1",
170 .base = 0x160,
171 .config = &tegra124_tsensor_config,
172 .calib_fuse_offset = 0x15c,
173 .fuse_corr_alpha = 1145700,
174 .fuse_corr_beta = -7124600,
175 .group = &tegra124_tsensor_group_mem,
176 }, {
177 .name = "gpu",
178 .base = 0x180,
179 .config = &tegra124_tsensor_config,
180 .calib_fuse_offset = 0x154,
181 .fuse_corr_alpha = 1120100,
182 .fuse_corr_beta = -6000500,
183 .group = &tegra124_tsensor_group_gpu,
184 }, {
185 .name = "pllx",
186 .base = 0x1a0,
187 .config = &tegra124_tsensor_config,
188 .calib_fuse_offset = 0x160,
189 .fuse_corr_alpha = 1106500,
190 .fuse_corr_beta = -6729300,
191 .group = &tegra124_tsensor_group_pll,
192 },
193};
194
195/*
196 * Mask/shift bits in FUSE_TSENSOR_COMMON and
197 * FUSE_TSENSOR_COMMON, which are described in
198 * tegra_soctherm_fuse.c
199 */
200static const struct tegra_soctherm_fuse tegra124_soctherm_fuse = {
201 .fuse_base_cp_mask = 0x3ff,
202 .fuse_base_cp_shift = 0,
203 .fuse_base_ft_mask = 0x7ff << 10,
204 .fuse_base_ft_shift = 10,
205 .fuse_shift_ft_mask = 0x1f << 21,
206 .fuse_shift_ft_shift = 21,
207 .fuse_spare_realignment = 0x1fc,
208};
209
210const struct tegra_soctherm_soc tegra124_soctherm = {
211 .tsensors = tegra124_tsensors,
212 .num_tsensors = ARRAY_SIZE(tegra124_tsensors),
213 .ttgs = tegra124_tsensor_groups,
214 .num_ttgs = ARRAY_SIZE(tegra124_tsensor_groups),
215 .tfuse = &tegra124_soctherm_fuse,
216 .thresh_grain = TEGRA124_THRESH_GRAIN,
217 .bptt = TEGRA124_BPTT,
218 .use_ccroc = false,
219};