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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 | // SPDX-License-Identifier: GPL-2.0 /* * Allwinner H6 SoC pinctrl driver. * * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> */ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" static const struct sunxi_desc_pin h6_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), SUNXI_FUNCTION(0x2, "emac")), /* ERXD1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), SUNXI_FUNCTION(0x2, "emac")), /* ERXD0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), SUNXI_FUNCTION(0x2, "emac")), /* ECRS_DV */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), SUNXI_FUNCTION(0x2, "emac")), /* ERXERR */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), SUNXI_FUNCTION(0x2, "emac")), /* ETXD1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), SUNXI_FUNCTION(0x2, "emac")), /* ETXD0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), SUNXI_FUNCTION(0x2, "emac")), /* ETXCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), SUNXI_FUNCTION(0x2, "emac")), /* ETXEN */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), SUNXI_FUNCTION(0x2, "emac")), /* EMDC */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), SUNXI_FUNCTION(0x2, "emac")), /* EMDIO */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), SUNXI_FUNCTION(0x2, "ccir"), /* CLK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), SUNXI_FUNCTION(0x2, "ccir"), /* DE */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), SUNXI_FUNCTION(0x2, "ccir"), /* HSYNC */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), SUNXI_FUNCTION(0x2, "ccir"), /* VSYNC */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), SUNXI_FUNCTION(0x2, "ccir"), /* DO0 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), SUNXI_FUNCTION(0x2, "ccir"), /* DO1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), SUNXI_FUNCTION(0x2, "ccir"), /* DO2 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), SUNXI_FUNCTION(0x2, "ccir"), /* DO3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), SUNXI_FUNCTION(0x2, "ccir"), /* DO4 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), SUNXI_FUNCTION(0x2, "ccir"), /* DO5 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), SUNXI_FUNCTION(0x2, "ccir"), /* DO6 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), SUNXI_FUNCTION(0x2, "ccir"), /* DO7 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), SUNXI_FUNCTION(0x2, "i2s3"), /* SYNC */ SUNXI_FUNCTION(0x4, "h_i2s3"), /* SYNC */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), SUNXI_FUNCTION(0x2, "i2s3"), /* CLK */ SUNXI_FUNCTION(0x4, "h_i2s3"), /* CLK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), SUNXI_FUNCTION(0x2, "i2s3"), /* DOUT */ SUNXI_FUNCTION(0x4, "h_i2s3"), /* DOUT */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), SUNXI_FUNCTION(0x2, "i2s3"), /* DIN */ SUNXI_FUNCTION(0x4, "h_i2s3"), /* DIN */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), SUNXI_FUNCTION(0x2, "i2s3"), /* MCLK */ SUNXI_FUNCTION(0x4, "h_i2s3"), /* MCLK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17), SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18), SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19), SUNXI_FUNCTION(0x2, "pwm1"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* WE */ SUNXI_FUNCTION(0x4, "spi0")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ SUNXI_FUNCTION(0x3, "mmc2")), /* DS */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ SUNXI_FUNCTION(0x4, "spi0")), /* MISO */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* RE */ SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */ SUNXI_FUNCTION(0x4, "spi0")), /* CS */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */ SUNXI_FUNCTION(0x4, "spi0")), /* HOLD */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */ SUNXI_FUNCTION(0x4, "spi0")), /* WP */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ SUNXI_FUNCTION(0x3, "ts0"), /* CLK */ SUNXI_FUNCTION(0x4, "csi"), /* PCLK */ SUNXI_FUNCTION(0x5, "emac")), /* ERXD3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ SUNXI_FUNCTION(0x3, "ts0"), /* ERR */ SUNXI_FUNCTION(0x4, "csi"), /* MCLK */ SUNXI_FUNCTION(0x5, "emac")), /* ERXD2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */ SUNXI_FUNCTION(0x4, "csi"), /* HSYNC */ SUNXI_FUNCTION(0x5, "emac")), /* ERXD1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ SUNXI_FUNCTION(0x3, "ts0"), /* DVLD */ SUNXI_FUNCTION(0x4, "csi"), /* VSYNC */ SUNXI_FUNCTION(0x5, "emac")), /* ERXD0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ SUNXI_FUNCTION(0x3, "ts0"), /* D0 */ SUNXI_FUNCTION(0x4, "csi"), /* D0 */ SUNXI_FUNCTION(0x5, "emac")), /* ERXCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ SUNXI_FUNCTION(0x3, "ts0"), /* D1 */ SUNXI_FUNCTION(0x4, "csi"), /* D1 */ SUNXI_FUNCTION(0x5, "emac")), /* ERXCTL */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ SUNXI_FUNCTION(0x3, "ts0"), /* D2 */ SUNXI_FUNCTION(0x4, "csi"), /* D2 */ SUNXI_FUNCTION(0x5, "emac")), /* ENULL */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ SUNXI_FUNCTION(0x3, "ts0"), /* D3 */ SUNXI_FUNCTION(0x4, "csi"), /* D3 */ SUNXI_FUNCTION(0x5, "emac")), /* ETXD3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ SUNXI_FUNCTION(0x3, "ts0"), /* D4 */ SUNXI_FUNCTION(0x4, "csi"), /* D4 */ SUNXI_FUNCTION(0x5, "emac")), /* ETXD2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ SUNXI_FUNCTION(0x3, "ts0"), /* D5 */ SUNXI_FUNCTION(0x4, "csi"), /* D5 */ SUNXI_FUNCTION(0x5, "emac")), /* ETXD1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ SUNXI_FUNCTION(0x3, "ts0"), /* D6 */ SUNXI_FUNCTION(0x4, "csi"), /* D6 */ SUNXI_FUNCTION(0x5, "emac")), /* ETXD0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ SUNXI_FUNCTION(0x3, "ts0"), /* D7 */ SUNXI_FUNCTION(0x4, "csi"), /* D7 */ SUNXI_FUNCTION(0x5, "emac")), /* ETXCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ SUNXI_FUNCTION(0x3, "ts1"), /* CLK */ SUNXI_FUNCTION(0x4, "csi"), /* SCK */ SUNXI_FUNCTION(0x5, "emac")), /* ETXCTL */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ SUNXI_FUNCTION(0x3, "ts1"), /* ERR */ SUNXI_FUNCTION(0x4, "csi"), /* SDA */ SUNXI_FUNCTION(0x5, "emac")), /* ECLKIN */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ SUNXI_FUNCTION(0x3, "ts1"), /* SYNC */ SUNXI_FUNCTION(0x4, "dmic"), /* CLK */ SUNXI_FUNCTION(0x5, "csi")), /* D8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ SUNXI_FUNCTION(0x3, "ts1"), /* DVLD */ SUNXI_FUNCTION(0x4, "dmic"), /* DATA0 */ SUNXI_FUNCTION(0x5, "csi")), /* D9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ SUNXI_FUNCTION(0x3, "ts1"), /* D0 */ SUNXI_FUNCTION(0x4, "dmic")), /* DATA1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ SUNXI_FUNCTION(0x3, "ts2"), /* CLK */ SUNXI_FUNCTION(0x4, "dmic")), /* DATA2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ SUNXI_FUNCTION(0x3, "ts2"), /* ERR */ SUNXI_FUNCTION(0x4, "dmic")), /* DATA3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ SUNXI_FUNCTION(0x3, "ts2"), /* SYNC */ SUNXI_FUNCTION(0x4, "uart2"), /* TX */ SUNXI_FUNCTION(0x5, "emac")), /* EMDC */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ SUNXI_FUNCTION(0x3, "ts2"), /* DVLD */ SUNXI_FUNCTION(0x4, "uart2"), /* RX */ SUNXI_FUNCTION(0x5, "emac")), /* EMDIO */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ SUNXI_FUNCTION(0x3, "ts2"), /* D0 */ SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */ SUNXI_FUNCTION(0x3, "ts3"), /* CLK */ SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */ SUNXI_FUNCTION(0x3, "ts3"), /* ERR */ SUNXI_FUNCTION(0x4, "uart3"), /* TX */ SUNXI_FUNCTION(0x5, "jtag")), /* MS */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */ SUNXI_FUNCTION(0x3, "ts3"), /* SYNC */ SUNXI_FUNCTION(0x4, "uart3"), /* RX */ SUNXI_FUNCTION(0x5, "jtag")), /* CK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ SUNXI_FUNCTION(0x3, "ts3"), /* DVLD */ SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ SUNXI_FUNCTION(0x5, "jtag")), /* DO */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ SUNXI_FUNCTION(0x3, "ts3"), /* D0 */ SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ SUNXI_FUNCTION(0x5, "jtag")), /* DI */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ SUNXI_FUNCTION(0x3, "jtag"), /* MS */ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ SUNXI_FUNCTION(0x3, "jtag"), /* DI */ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ SUNXI_FUNCTION(0x3, "uart0"), /* TX */ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ SUNXI_FUNCTION(0x3, "jtag"), /* DO */ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ SUNXI_FUNCTION(0x3, "uart0"), /* RX */ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ SUNXI_FUNCTION(0x3, "jtag"), /* CK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart1"), /* TX */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart1"), /* RX */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ SUNXI_FUNCTION(0x4, "sim0"), /* VPPEN */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ SUNXI_FUNCTION(0x4, "sim0"), /* VPPPP */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s2"), /* SYNC */ SUNXI_FUNCTION(0x3, "h_i2s2"), /* SYNC */ SUNXI_FUNCTION(0x4, "sim0"), /* PWREN */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s2"), /* CLK */ SUNXI_FUNCTION(0x3, "h_i2s2"), /* CLK */ SUNXI_FUNCTION(0x4, "sim0"), /* CLK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s2"), /* DOUT */ SUNXI_FUNCTION(0x3, "h_i2s2"), /* DOUT */ SUNXI_FUNCTION(0x4, "sim0"), /* DATA */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s2"), /* DIN */ SUNXI_FUNCTION(0x3, "h_i2s2"), /* DIN */ SUNXI_FUNCTION(0x4, "sim0"), /* RST */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s2"), /* MCLK */ SUNXI_FUNCTION(0x3, "h_i2s2"), /* MCLK */ SUNXI_FUNCTION(0x4, "sim0"), /* DET */ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PG_EINT14 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart0"), /* TX */ SUNXI_FUNCTION(0x3, "i2s0"), /* SYNC */ SUNXI_FUNCTION(0x4, "h_i2s0"), /* SYNC */ SUNXI_FUNCTION(0x5, "sim1"), /* VPPEN */ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PH_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart0"), /* RX */ SUNXI_FUNCTION(0x3, "i2s0"), /* CLK */ SUNXI_FUNCTION(0x4, "h_i2s0"), /* CLK */ SUNXI_FUNCTION(0x5, "sim1"), /* VPPPP */ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PH_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "ir_tx"), SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */ SUNXI_FUNCTION(0x4, "h_i2s0"), /* DOUT */ SUNXI_FUNCTION(0x5, "sim1"), /* PWREN */ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PH_EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* CS */ SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */ SUNXI_FUNCTION(0x4, "h_i2s0"), /* DIN */ SUNXI_FUNCTION(0x5, "sim1"), /* CLK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PH_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */ SUNXI_FUNCTION(0x4, "h_i2s0"), /* MCLK */ SUNXI_FUNCTION(0x5, "sim1"), /* DATA */ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PH_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ SUNXI_FUNCTION(0x3, "spdif"), /* MCLK */ SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */ SUNXI_FUNCTION(0x5, "sim1"), /* RST */ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PH_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ SUNXI_FUNCTION(0x3, "spdif"), /* IN */ SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */ SUNXI_FUNCTION(0x5, "sim1"), /* DET */ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PH_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x3, "spdif"), /* OUT */ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PH_EINT7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PH_EINT8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PH_EINT9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PH_EINT10 */ }; static const unsigned int h6_irq_bank_map[] = { 1, 5, 6, 7 }; static const struct sunxi_pinctrl_desc h6_pinctrl_data = { .pins = h6_pins, .npins = ARRAY_SIZE(h6_pins), .irq_banks = 4, .irq_bank_map = h6_irq_bank_map, .irq_read_needs_mux = true, .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, }; static int h6_pinctrl_probe(struct platform_device *pdev) { return sunxi_pinctrl_init(pdev, &h6_pinctrl_data); } static const struct of_device_id h6_pinctrl_match[] = { { .compatible = "allwinner,sun50i-h6-pinctrl", }, {} }; static struct platform_driver h6_pinctrl_driver = { .probe = h6_pinctrl_probe, .driver = { .name = "sun50i-h6-pinctrl", .of_match_table = h6_pinctrl_match, }, }; builtin_platform_driver(h6_pinctrl_driver); |