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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 | // SPDX-License-Identifier: GPL-2.0 /* * PCI Express Precision Time Measurement * Copyright (c) 2016, Intel Corporation. */ #include <linux/bitfield.h> #include <linux/module.h> #include <linux/init.h> #include <linux/pci.h> #include "../pci.h" /* * If the next upstream device supports PTM, return it; otherwise return * NULL. PTM Messages are local, so both link partners must support it. */ static struct pci_dev *pci_upstream_ptm(struct pci_dev *dev) { struct pci_dev *ups = pci_upstream_bridge(dev); /* * Switch Downstream Ports are not permitted to have a PTM * capability; their PTM behavior is controlled by the Upstream * Port (PCIe r5.0, sec 7.9.16), so if the upstream bridge is a * Switch Downstream Port, look up one more level. */ if (ups && pci_pcie_type(ups) == PCI_EXP_TYPE_DOWNSTREAM) ups = pci_upstream_bridge(ups); if (ups && ups->ptm_cap) return ups; return NULL; } /* * Find the PTM Capability (if present) and extract the information we need * to use it. */ void pci_ptm_init(struct pci_dev *dev) { u16 ptm; u32 cap; struct pci_dev *ups; if (!pci_is_pcie(dev)) return; ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); if (!ptm) return; dev->ptm_cap = ptm; pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u32)); pci_read_config_dword(dev, ptm + PCI_PTM_CAP, &cap); dev->ptm_granularity = FIELD_GET(PCI_PTM_GRANULARITY_MASK, cap); /* * Per the spec recommendation (PCIe r6.0, sec 7.9.15.3), select the * furthest upstream Time Source as the PTM Root. For Endpoints, * "the Effective Granularity is the maximum Local Clock Granularity * reported by the PTM Root and all intervening PTM Time Sources." */ ups = pci_upstream_ptm(dev); if (ups) { if (ups->ptm_granularity == 0) dev->ptm_granularity = 0; else if (ups->ptm_granularity > dev->ptm_granularity) dev->ptm_granularity = ups->ptm_granularity; } else if (cap & PCI_PTM_CAP_ROOT) { dev->ptm_root = 1; } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { /* * Per sec 7.9.15.3, this should be the Local Clock * Granularity of the associated Time Source. But it * doesn't say how to find that Time Source. */ dev->ptm_granularity = 0; } if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM) pci_enable_ptm(dev, NULL); } void pci_save_ptm_state(struct pci_dev *dev) { u16 ptm = dev->ptm_cap; struct pci_cap_saved_state *save_state; u32 *cap; if (!ptm) return; save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM); if (!save_state) return; cap = (u32 *)&save_state->cap.data[0]; pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, cap); } void pci_restore_ptm_state(struct pci_dev *dev) { u16 ptm = dev->ptm_cap; struct pci_cap_saved_state *save_state; u32 *cap; if (!ptm) return; save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM); if (!save_state) return; cap = (u32 *)&save_state->cap.data[0]; pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, *cap); } /* Enable PTM in the Control register if possible */ static int __pci_enable_ptm(struct pci_dev *dev) { u16 ptm = dev->ptm_cap; struct pci_dev *ups; u32 ctrl; if (!ptm) return -EINVAL; /* * A device uses local PTM Messages to request time information * from a PTM Root that's farther upstream. Every device along the * path must support PTM and have it enabled so it can handle the * messages. Therefore, if this device is not a PTM Root, the * upstream link partner must have PTM enabled before we can enable * PTM. */ if (!dev->ptm_root) { ups = pci_upstream_ptm(dev); if (!ups || !ups->ptm_enabled) return -EINVAL; } pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, &ctrl); ctrl |= PCI_PTM_CTRL_ENABLE; ctrl &= ~PCI_PTM_GRANULARITY_MASK; ctrl |= FIELD_PREP(PCI_PTM_GRANULARITY_MASK, dev->ptm_granularity); if (dev->ptm_root) ctrl |= PCI_PTM_CTRL_ROOT; pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, ctrl); return 0; } /** * pci_enable_ptm() - Enable Precision Time Measurement * @dev: PCI device * @granularity: pointer to return granularity * * Enable Precision Time Measurement for @dev. If successful and * @granularity is non-NULL, return the Effective Granularity. * * Return: zero if successful, or -EINVAL if @dev lacks a PTM Capability or * is not a PTM Root and lacks an upstream path of PTM-enabled devices. */ int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) { int rc; char clock_desc[8]; rc = __pci_enable_ptm(dev); if (rc) return rc; dev->ptm_enabled = 1; if (granularity) *granularity = dev->ptm_granularity; switch (dev->ptm_granularity) { case 0: snprintf(clock_desc, sizeof(clock_desc), "unknown"); break; case 255: snprintf(clock_desc, sizeof(clock_desc), ">254ns"); break; default: snprintf(clock_desc, sizeof(clock_desc), "%uns", dev->ptm_granularity); break; } pci_info(dev, "PTM enabled%s, %s granularity\n", dev->ptm_root ? " (root)" : "", clock_desc); return 0; } EXPORT_SYMBOL(pci_enable_ptm); static void __pci_disable_ptm(struct pci_dev *dev) { u16 ptm = dev->ptm_cap; u32 ctrl; if (!ptm) return; pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, &ctrl); ctrl &= ~(PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT); pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, ctrl); } /** * pci_disable_ptm() - Disable Precision Time Measurement * @dev: PCI device * * Disable Precision Time Measurement for @dev. */ void pci_disable_ptm(struct pci_dev *dev) { if (dev->ptm_enabled) { __pci_disable_ptm(dev); dev->ptm_enabled = 0; } } EXPORT_SYMBOL(pci_disable_ptm); /* * Disable PTM, but preserve dev->ptm_enabled so we silently re-enable it on * resume if necessary. */ void pci_suspend_ptm(struct pci_dev *dev) { if (dev->ptm_enabled) __pci_disable_ptm(dev); } /* If PTM was enabled before suspend, re-enable it when resuming */ void pci_resume_ptm(struct pci_dev *dev) { if (dev->ptm_enabled) __pci_enable_ptm(dev); } bool pcie_ptm_enabled(struct pci_dev *dev) { if (!dev) return false; return dev->ptm_enabled; } EXPORT_SYMBOL(pcie_ptm_enabled); |