1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright(c) 2009-2012  Realtek Corporation.*/
  3
  4#ifndef __RTL92C_PHY_H__
  5#define __RTL92C_PHY_H__
  6
  7#define MAX_PRECMD_CNT				16
  8#define MAX_RFDEPENDCMD_CNT			16
  9#define MAX_POSTCMD_CNT				16
 10
 11#define MAX_DOZE_WAITING_TIMES_9x		64
 12
 13#define RT_CANNOT_IO(hw)			false
 14#define HIGHPOWER_RADIOA_ARRAYLEN		22
 15
 16#define IQK_ADDA_REG_NUM			16
 17#define MAX_TOLERANCE				5
 18#define	IQK_DELAY_TIME				1
 19
 20#define	APK_BB_REG_NUM				5
 21#define	APK_AFE_REG_NUM				16
 22#define	APK_CURVE_REG_NUM			4
 23#define	PATH_NUM				2
 24
 25#define LOOP_LIMIT				5
 26#define MAX_STALL_TIME				50
 27#define ANTENNADIVERSITYVALUE			0x80
 28#define MAX_TXPWR_IDX_NMODE_92S			63
 29#define reset_cnt_limit				3
 30
 31#define IQK_ADDA_REG_NUM			16
 32#define IQK_MAC_REG_NUM				4
 33
 34#define IQK_DELAY_TIME				1
 35
 36#define RF6052_MAX_PATH				2
 37
 38#define CT_OFFSET_MAC_ADDR			0X16
 39
 40#define CT_OFFSET_CCK_TX_PWR_IDX		0x5A
 41#define CT_OFFSET_HT401S_TX_PWR_IDX		0x60
 42#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF	0x66
 43#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF		0x69
 44#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF		0x6C
 45
 46#define CT_OFFSET_HT40_MAX_PWR_OFFSET		0x6F
 47#define CT_OFFSET_HT20_MAX_PWR_OFFSET		0x72
 48
 49#define CT_OFFSET_CHANNEL_PLAH			0x75
 50#define CT_OFFSET_THERMAL_METER			0x78
 51#define CT_OFFSET_RF_OPTION			0x79
 52#define CT_OFFSET_VERSION			0x7E
 53#define CT_OFFSET_CUSTOMER_ID			0x7F
 54
 55#define RTL92C_MAX_PATH_NUM			2
 56
 57enum hw90_block_e {
 58	HW90_BLOCK_MAC = 0,
 59	HW90_BLOCK_PHY0 = 1,
 60	HW90_BLOCK_PHY1 = 2,
 61	HW90_BLOCK_RF = 3,
 62	HW90_BLOCK_MAXIMUM = 4,
 63};
 64
 65enum baseband_config_type {
 66	BASEBAND_CONFIG_PHY_REG = 0,
 67	BASEBAND_CONFIG_AGC_TAB = 1,
 68};
 69
 70enum ra_offset_area {
 71	RA_OFFSET_LEGACY_OFDM1,
 72	RA_OFFSET_LEGACY_OFDM2,
 73	RA_OFFSET_HT_OFDM1,
 74	RA_OFFSET_HT_OFDM2,
 75	RA_OFFSET_HT_OFDM3,
 76	RA_OFFSET_HT_OFDM4,
 77	RA_OFFSET_HT_CCK,
 78};
 79
 80enum antenna_path {
 81	ANTENNA_NONE,
 82	ANTENNA_D,
 83	ANTENNA_C,
 84	ANTENNA_CD,
 85	ANTENNA_B,
 86	ANTENNA_BD,
 87	ANTENNA_BC,
 88	ANTENNA_BCD,
 89	ANTENNA_A,
 90	ANTENNA_AD,
 91	ANTENNA_AC,
 92	ANTENNA_ACD,
 93	ANTENNA_AB,
 94	ANTENNA_ABD,
 95	ANTENNA_ABC,
 96	ANTENNA_ABCD
 97};
 98
 99struct r_antenna_select_ofdm {
100	u32 r_tx_antenna:4;
101	u32 r_ant_l:4;
102	u32 r_ant_non_ht:4;
103	u32 r_ant_ht1:4;
104	u32 r_ant_ht2:4;
105	u32 r_ant_ht_s1:4;
106	u32 r_ant_non_ht_s1:4;
107	u32 ofdm_txsc:2;
108	u32 reserved:2;
109};
110
111struct r_antenna_select_cck {
112	u8 r_cckrx_enable_2:2;
113	u8 r_cckrx_enable:2;
114	u8 r_ccktx_enable:4;
115};
116
117struct efuse_contents {
118	u8 mac_addr[ETH_ALEN];
119	u8 cck_tx_power_idx[6];
120	u8 ht40_1s_tx_power_idx[6];
121	u8 ht40_2s_tx_power_idx_diff[3];
122	u8 ht20_tx_power_idx_diff[3];
123	u8 ofdm_tx_power_idx_diff[3];
124	u8 ht40_max_power_offset[3];
125	u8 ht20_max_power_offset[3];
126	u8 channel_plan;
127	u8 thermal_meter;
128	u8 rf_option[5];
129	u8 version;
130	u8 oem_id;
131	u8 regulatory;
132};
133
134struct tx_power_struct {
135	u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
136	u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
137	u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
138	u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
139	u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
140	u8 legacy_ht_txpowerdiff;
141	u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
142	u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
143	u8 pwrgroup_cnt;
144	u32 mcs_original_offset[4][16];
145};
146
147u32 rtl8723e_phy_query_rf_reg(struct ieee80211_hw *hw,
148			      enum radio_path rfpath, u32 regaddr,
149			      u32 bitmask);
150void rtl8723e_phy_set_rf_reg(struct ieee80211_hw *hw,
151			     enum radio_path rfpath, u32 regaddr,
152			     u32 bitmask, u32 data);
153bool rtl8723e_phy_mac_config(struct ieee80211_hw *hw);
154bool rtl8723e_phy_bb_config(struct ieee80211_hw *hw);
155bool rtl8723e_phy_rf_config(struct ieee80211_hw *hw);
156bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
157					  enum radio_path rfpath);
158void rtl8723e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
159void rtl8723e_phy_get_txpower_level(struct ieee80211_hw *hw,
160				    long *powerlevel);
161void rtl8723e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
162bool rtl8723e_phy_update_txpower_dbm(struct ieee80211_hw *hw,
163				     long power_indbm);
164void rtl8723e_phy_scan_operation_backup(struct ieee80211_hw *hw,
165					u8 operation);
166void rtl8723e_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
167void rtl8723e_phy_set_bw_mode(struct ieee80211_hw *hw,
168			      enum nl80211_channel_type ch_type);
169void rtl8723e_phy_sw_chnl_callback(struct ieee80211_hw *hw);
170u8 rtl8723e_phy_sw_chnl(struct ieee80211_hw *hw);
171void rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
172void rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw);
173void rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
174bool rtl8723e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
175					    enum radio_path rfpath);
176bool rtl8723e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
177bool rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw,
178				     enum rf_pwrstate rfpwr_state);
179
180#endif