1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
  4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
  5 */
  6
  7#ifndef __MT76_MAC_H
  8#define __MT76_MAC_H
  9
 10struct mt76_tx_status {
 11	u8 valid:1;
 12	u8 success:1;
 13	u8 aggr:1;
 14	u8 ack_req:1;
 15	u8 is_probe:1;
 16	u8 wcid;
 17	u8 pktid;
 18	u8 retry;
 19	u16 rate;
 20} __packed __aligned(2);
 21
 22/* Note: values in original "RSSI" and "SNR" fields are not actually what they
 23 *	 are called for MT7601U, names used by this driver are educated guesses
 24 *	 (see vendor mac/ral_omac.c).
 25 */
 26struct mt7601u_rxwi {
 27	__le32 rxinfo;
 28
 29	__le32 ctl;
 30
 31	__le16 frag_sn;
 32	__le16 rate;
 33
 34	u8 unknown;
 35	u8 zero[3];
 36
 37	u8 snr;
 38	u8 ant;
 39	u8 gain;
 40	u8 freq_off;
 41
 42	__le32 resv2;
 43	__le32 expert_ant;
 44} __packed __aligned(4);
 45
 46#define MT_RXINFO_BA			BIT(0)
 47#define MT_RXINFO_DATA			BIT(1)
 48#define MT_RXINFO_NULL			BIT(2)
 49#define MT_RXINFO_FRAG			BIT(3)
 50#define MT_RXINFO_U2M			BIT(4)
 51#define MT_RXINFO_MULTICAST		BIT(5)
 52#define MT_RXINFO_BROADCAST		BIT(6)
 53#define MT_RXINFO_MYBSS			BIT(7)
 54#define MT_RXINFO_CRCERR		BIT(8)
 55#define MT_RXINFO_ICVERR		BIT(9)
 56#define MT_RXINFO_MICERR		BIT(10)
 57#define MT_RXINFO_AMSDU			BIT(11)
 58#define MT_RXINFO_HTC			BIT(12)
 59#define MT_RXINFO_RSSI			BIT(13)
 60#define MT_RXINFO_L2PAD			BIT(14)
 61#define MT_RXINFO_AMPDU			BIT(15)
 62#define MT_RXINFO_DECRYPT		BIT(16)
 63#define MT_RXINFO_BSSIDX3		BIT(17)
 64#define MT_RXINFO_WAPI_KEY		BIT(18)
 65#define MT_RXINFO_PN_LEN		GENMASK(21, 19)
 66#define MT_RXINFO_SW_PKT_80211		BIT(22)
 67#define MT_RXINFO_TCP_SUM_BYPASS	BIT(28)
 68#define MT_RXINFO_IP_SUM_BYPASS		BIT(29)
 69#define MT_RXINFO_TCP_SUM_ERR		BIT(30)
 70#define MT_RXINFO_IP_SUM_ERR		BIT(31)
 71
 72#define MT_RXWI_CTL_WCID		GENMASK(7, 0)
 73#define MT_RXWI_CTL_KEY_IDX		GENMASK(9, 8)
 74#define MT_RXWI_CTL_BSS_IDX		GENMASK(12, 10)
 75#define MT_RXWI_CTL_UDF			GENMASK(15, 13)
 76#define MT_RXWI_CTL_MPDU_LEN		GENMASK(27, 16)
 77#define MT_RXWI_CTL_TID			GENMASK(31, 28)
 78
 79#define MT_RXWI_FRAG			GENMASK(3, 0)
 80#define MT_RXWI_SN			GENMASK(15, 4)
 81
 82#define MT_RXWI_RATE_MCS		GENMASK(6, 0)
 83#define MT_RXWI_RATE_BW			BIT(7)
 84#define MT_RXWI_RATE_SGI		BIT(8)
 85#define MT_RXWI_RATE_STBC		GENMASK(10, 9)
 86#define MT_RXWI_RATE_ETXBF		BIT(11)
 87#define MT_RXWI_RATE_SND		BIT(12)
 88#define MT_RXWI_RATE_ITXBF		BIT(13)
 89#define MT_RXWI_RATE_PHY		GENMASK(15, 14)
 90
 91#define MT_RXWI_GAIN_RSSI_VAL		GENMASK(5, 0)
 92#define MT_RXWI_GAIN_RSSI_LNA_ID	GENMASK(7, 6)
 93#define MT_RXWI_ANT_AUX_LNA		BIT(7)
 94
 95#define MT_RXWI_EANT_ENC_ANT_ID		GENMASK(7, 0)
 96
 97enum mt76_phy_type {
 98	MT_PHY_TYPE_CCK,
 99	MT_PHY_TYPE_OFDM,
100	MT_PHY_TYPE_HT,
101	MT_PHY_TYPE_HT_GF,
102};
103
104enum mt76_phy_bandwidth {
105	MT_PHY_BW_20,
106	MT_PHY_BW_40,
107};
108
109struct mt76_txwi {
110	__le16 flags;
111	__le16 rate_ctl;
112
113	u8 ack_ctl;
114	u8 wcid;
115	__le16 len_ctl;
116
117	__le32 iv;
118
119	__le32 eiv;
120
121	u8 aid;
122	u8 txstream;
123	__le16 ctl;
124} __packed __aligned(4);
125
126#define MT_TXWI_FLAGS_FRAG		BIT(0)
127#define MT_TXWI_FLAGS_MMPS		BIT(1)
128#define MT_TXWI_FLAGS_CFACK		BIT(2)
129#define MT_TXWI_FLAGS_TS		BIT(3)
130#define MT_TXWI_FLAGS_AMPDU		BIT(4)
131#define MT_TXWI_FLAGS_MPDU_DENSITY	GENMASK(7, 5)
132#define MT_TXWI_FLAGS_TXOP		GENMASK(9, 8)
133#define MT_TXWI_FLAGS_CWMIN		GENMASK(12, 10)
134#define MT_TXWI_FLAGS_NO_RATE_FALLBACK	BIT(13)
135#define MT_TXWI_FLAGS_TX_RPT		BIT(14)
136#define MT_TXWI_FLAGS_TX_RATE_LUT	BIT(15)
137
138#define MT_TXWI_RATE_MCS		GENMASK(6, 0)
139#define MT_TXWI_RATE_BW			BIT(7)
140#define MT_TXWI_RATE_SGI		BIT(8)
141#define MT_TXWI_RATE_STBC		GENMASK(10, 9)
142#define MT_TXWI_RATE_PHY_MODE		GENMASK(15, 14)
143
144#define MT_TXWI_ACK_CTL_REQ		BIT(0)
145#define MT_TXWI_ACK_CTL_NSEQ		BIT(1)
146#define MT_TXWI_ACK_CTL_BA_WINDOW	GENMASK(7, 2)
147
148#define MT_TXWI_LEN_BYTE_CNT		GENMASK(11, 0)
149#define MT_TXWI_LEN_PKTID		GENMASK(15, 12)
150
151#define MT_TXWI_CTL_TX_POWER_ADJ	GENMASK(3, 0)
152#define MT_TXWI_CTL_CHAN_CHECK_PKT	BIT(4)
153#define MT_TXWI_CTL_PIFS_REV		BIT(6)
154
155u32 mt76_mac_process_rx(struct mt7601u_dev *dev, struct sk_buff *skb,
156			u8 *data, void *rxi);
157int mt76_mac_wcid_set_key(struct mt7601u_dev *dev, u8 idx,
158			  struct ieee80211_key_conf *key);
159void mt76_mac_wcid_set_rate(struct mt7601u_dev *dev, struct mt76_wcid *wcid,
160			    const struct ieee80211_tx_rate *rate);
161
162int mt76_mac_shared_key_setup(struct mt7601u_dev *dev, u8 vif_idx, u8 key_idx,
163			      struct ieee80211_key_conf *key);
164u16 mt76_mac_tx_rate_val(struct mt7601u_dev *dev,
165			 const struct ieee80211_tx_rate *rate, u8 *nss_val);
166struct mt76_tx_status
167mt7601u_mac_fetch_tx_status(struct mt7601u_dev *dev);
168void mt76_send_tx_status(struct mt7601u_dev *dev, struct mt76_tx_status *stat);
169void mt7601u_set_macaddr(struct mt7601u_dev *dev, const u8 *addr);
170
171#endif