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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef B43_PIO_H_
3#define B43_PIO_H_
4
5#include "b43.h"
6
7#include <linux/interrupt.h>
8#include <linux/io.h>
9#include <linux/list.h>
10#include <linux/skbuff.h>
11
12
13/*** Registers for PIO queues up to revision 7. ***/
14/* TX queue. */
15#define B43_PIO_TXCTL 0x00
16#define B43_PIO_TXCTL_WRITELO 0x0001
17#define B43_PIO_TXCTL_WRITEHI 0x0002
18#define B43_PIO_TXCTL_EOF 0x0004
19#define B43_PIO_TXCTL_FREADY 0x0008
20#define B43_PIO_TXCTL_FLUSHREQ 0x0020
21#define B43_PIO_TXCTL_FLUSHPEND 0x0040
22#define B43_PIO_TXCTL_SUSPREQ 0x0080
23#define B43_PIO_TXCTL_QSUSP 0x0100
24#define B43_PIO_TXCTL_COMMCNT 0xFC00
25#define B43_PIO_TXCTL_COMMCNT_SHIFT 10
26#define B43_PIO_TXDATA 0x02
27#define B43_PIO_TXQBUFSIZE 0x04
28/* RX queue. */
29#define B43_PIO_RXCTL 0x00
30#define B43_PIO_RXCTL_FRAMERDY 0x0001
31#define B43_PIO_RXCTL_DATARDY 0x0002
32#define B43_PIO_RXDATA 0x02
33
34/*** Registers for PIO queues revision 8 and later. ***/
35/* TX queue */
36#define B43_PIO8_TXCTL 0x00
37#define B43_PIO8_TXCTL_0_7 0x00000001
38#define B43_PIO8_TXCTL_8_15 0x00000002
39#define B43_PIO8_TXCTL_16_23 0x00000004
40#define B43_PIO8_TXCTL_24_31 0x00000008
41#define B43_PIO8_TXCTL_EOF 0x00000010
42#define B43_PIO8_TXCTL_FREADY 0x00000080
43#define B43_PIO8_TXCTL_SUSPREQ 0x00000100
44#define B43_PIO8_TXCTL_QSUSP 0x00000200
45#define B43_PIO8_TXCTL_FLUSHREQ 0x00000400
46#define B43_PIO8_TXCTL_FLUSHPEND 0x00000800
47#define B43_PIO8_TXDATA 0x04
48/* RX queue */
49#define B43_PIO8_RXCTL 0x00
50#define B43_PIO8_RXCTL_FRAMERDY 0x00000001
51#define B43_PIO8_RXCTL_DATARDY 0x00000002
52#define B43_PIO8_RXDATA 0x04
53
54
55/* The maximum number of TX-packets the HW can handle. */
56#define B43_PIO_MAX_NR_TXPACKETS 32
57
58
59struct b43_pio_txpacket {
60 /* Pointer to the TX queue we belong to. */
61 struct b43_pio_txqueue *queue;
62 /* The TX data packet. */
63 struct sk_buff *skb;
64 /* Index in the (struct b43_pio_txqueue)->packets array. */
65 u8 index;
66
67 struct list_head list;
68};
69
70struct b43_pio_txqueue {
71 struct b43_wldev *dev;
72 u16 mmio_base;
73
74 /* The device queue buffer size in bytes. */
75 u16 buffer_size;
76 /* The number of used bytes in the device queue buffer. */
77 u16 buffer_used;
78 /* The number of packets that can still get queued.
79 * This is decremented on queueing a packet and incremented
80 * after receiving the transmit status. */
81 u16 free_packet_slots;
82
83 /* True, if the mac80211 queue was stopped due to overflow at TX. */
84 bool stopped;
85 /* Our b43 queue index number */
86 u8 index;
87 /* The mac80211 QoS queue priority. */
88 u8 queue_prio;
89
90 /* Buffer for TX packet meta data. */
91 struct b43_pio_txpacket packets[B43_PIO_MAX_NR_TXPACKETS];
92 struct list_head packets_list;
93
94 /* Shortcut to the 802.11 core revision. This is to
95 * avoid horrible pointer dereferencing in the fastpaths. */
96 u8 rev;
97};
98
99struct b43_pio_rxqueue {
100 struct b43_wldev *dev;
101 u16 mmio_base;
102
103 /* Shortcut to the 802.11 core revision. This is to
104 * avoid horrible pointer dereferencing in the fastpaths. */
105 u8 rev;
106};
107
108
109static inline u16 b43_piotx_read16(struct b43_pio_txqueue *q, u16 offset)
110{
111 return b43_read16(q->dev, q->mmio_base + offset);
112}
113
114static inline u32 b43_piotx_read32(struct b43_pio_txqueue *q, u16 offset)
115{
116 return b43_read32(q->dev, q->mmio_base + offset);
117}
118
119static inline void b43_piotx_write16(struct b43_pio_txqueue *q,
120 u16 offset, u16 value)
121{
122 b43_write16(q->dev, q->mmio_base + offset, value);
123}
124
125static inline void b43_piotx_write32(struct b43_pio_txqueue *q,
126 u16 offset, u32 value)
127{
128 b43_write32(q->dev, q->mmio_base + offset, value);
129}
130
131
132static inline u16 b43_piorx_read16(struct b43_pio_rxqueue *q, u16 offset)
133{
134 return b43_read16(q->dev, q->mmio_base + offset);
135}
136
137static inline u32 b43_piorx_read32(struct b43_pio_rxqueue *q, u16 offset)
138{
139 return b43_read32(q->dev, q->mmio_base + offset);
140}
141
142static inline void b43_piorx_write16(struct b43_pio_rxqueue *q,
143 u16 offset, u16 value)
144{
145 b43_write16(q->dev, q->mmio_base + offset, value);
146}
147
148static inline void b43_piorx_write32(struct b43_pio_rxqueue *q,
149 u16 offset, u32 value)
150{
151 b43_write32(q->dev, q->mmio_base + offset, value);
152}
153
154
155int b43_pio_init(struct b43_wldev *dev);
156void b43_pio_free(struct b43_wldev *dev);
157
158int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb);
159void b43_pio_handle_txstatus(struct b43_wldev *dev,
160 const struct b43_txstatus *status);
161void b43_pio_rx(struct b43_pio_rxqueue *q);
162
163void b43_pio_tx_suspend(struct b43_wldev *dev);
164void b43_pio_tx_resume(struct b43_wldev *dev);
165
166#endif /* B43_PIO_H_ */