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1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#ifndef ATH11K_CORE_H
8#define ATH11K_CORE_H
9
10#include <linux/types.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/bitfield.h>
14#include <linux/dmi.h>
15#include <linux/ctype.h>
16#include <linux/rhashtable.h>
17#include <linux/average.h>
18#include <linux/firmware.h>
19
20#include "qmi.h"
21#include "htc.h"
22#include "wmi.h"
23#include "hal.h"
24#include "dp.h"
25#include "ce.h"
26#include "mac.h"
27#include "hw.h"
28#include "hal_rx.h"
29#include "reg.h"
30#include "thermal.h"
31#include "dbring.h"
32#include "spectral.h"
33#include "wow.h"
34#include "fw.h"
35
36#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
37
38#define ATH11K_TX_MGMT_NUM_PENDING_MAX 512
39
40#define ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
41
42/* Pending management packets threshold for dropping probe responses */
43#define ATH11K_PRB_RSP_DROP_THRESHOLD ((ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
44
45#define ATH11K_INVALID_HW_MAC_ID 0xFF
46#define ATH11K_CONNECTION_LOSS_HZ (3 * HZ)
47
48/* SMBIOS type containing Board Data File Name Extension */
49#define ATH11K_SMBIOS_BDF_EXT_TYPE 0xF8
50
51/* SMBIOS type structure length (excluding strings-set) */
52#define ATH11K_SMBIOS_BDF_EXT_LENGTH 0x9
53
54/* The magic used by QCA spec */
55#define ATH11K_SMBIOS_BDF_EXT_MAGIC "BDF_"
56
57extern unsigned int ath11k_frame_mode;
58extern bool ath11k_ftm_mode;
59
60#define ATH11K_SCAN_TIMEOUT_HZ (20 * HZ)
61
62#define ATH11K_MON_TIMER_INTERVAL 10
63#define ATH11K_RESET_TIMEOUT_HZ (20 * HZ)
64#define ATH11K_RESET_MAX_FAIL_COUNT_FIRST 3
65#define ATH11K_RESET_MAX_FAIL_COUNT_FINAL 5
66#define ATH11K_RESET_FAIL_TIMEOUT_HZ (20 * HZ)
67#define ATH11K_RECONFIGURE_TIMEOUT_HZ (10 * HZ)
68#define ATH11K_RECOVER_START_TIMEOUT_HZ (20 * HZ)
69
70enum ath11k_supported_bw {
71 ATH11K_BW_20 = 0,
72 ATH11K_BW_40 = 1,
73 ATH11K_BW_80 = 2,
74 ATH11K_BW_160 = 3,
75};
76
77enum ath11k_bdf_search {
78 ATH11K_BDF_SEARCH_DEFAULT,
79 ATH11K_BDF_SEARCH_BUS_AND_BOARD,
80};
81
82enum wme_ac {
83 WME_AC_BE,
84 WME_AC_BK,
85 WME_AC_VI,
86 WME_AC_VO,
87 WME_NUM_AC
88};
89
90#define ATH11K_HT_MCS_MAX 7
91#define ATH11K_VHT_MCS_MAX 9
92#define ATH11K_HE_MCS_MAX 11
93
94enum ath11k_crypt_mode {
95 /* Only use hardware crypto engine */
96 ATH11K_CRYPT_MODE_HW,
97 /* Only use software crypto */
98 ATH11K_CRYPT_MODE_SW,
99};
100
101static inline enum wme_ac ath11k_tid_to_ac(u32 tid)
102{
103 return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
104 ((tid == 1) || (tid == 2)) ? WME_AC_BK :
105 ((tid == 4) || (tid == 5)) ? WME_AC_VI :
106 WME_AC_VO);
107}
108
109enum ath11k_skb_flags {
110 ATH11K_SKB_HW_80211_ENCAP = BIT(0),
111 ATH11K_SKB_CIPHER_SET = BIT(1),
112};
113
114struct ath11k_skb_cb {
115 dma_addr_t paddr;
116 u8 eid;
117 u8 flags;
118 u32 cipher;
119 struct ath11k *ar;
120 struct ieee80211_vif *vif;
121} __packed;
122
123struct ath11k_skb_rxcb {
124 dma_addr_t paddr;
125 bool is_first_msdu;
126 bool is_last_msdu;
127 bool is_continuation;
128 bool is_mcbc;
129 bool is_eapol;
130 struct hal_rx_desc *rx_desc;
131 u8 err_rel_src;
132 u8 err_code;
133 u8 mac_id;
134 u8 unmapped;
135 u8 is_frag;
136 u8 tid;
137 u16 peer_id;
138 u16 seq_no;
139};
140
141enum ath11k_hw_rev {
142 ATH11K_HW_IPQ8074,
143 ATH11K_HW_QCA6390_HW20,
144 ATH11K_HW_IPQ6018_HW10,
145 ATH11K_HW_QCN9074_HW10,
146 ATH11K_HW_WCN6855_HW20,
147 ATH11K_HW_WCN6855_HW21,
148 ATH11K_HW_WCN6750_HW10,
149 ATH11K_HW_IPQ5018_HW10,
150 ATH11K_HW_QCA2066_HW21,
151};
152
153enum ath11k_firmware_mode {
154 /* the default mode, standard 802.11 functionality */
155 ATH11K_FIRMWARE_MODE_NORMAL,
156
157 /* factory tests etc */
158 ATH11K_FIRMWARE_MODE_FTM,
159
160 /* Cold boot calibration */
161 ATH11K_FIRMWARE_MODE_COLD_BOOT = 7,
162};
163
164extern bool ath11k_cold_boot_cal;
165
166#define ATH11K_IRQ_NUM_MAX 52
167#define ATH11K_EXT_IRQ_NUM_MAX 16
168
169struct ath11k_ext_irq_grp {
170 struct ath11k_base *ab;
171 u32 irqs[ATH11K_EXT_IRQ_NUM_MAX];
172 u32 num_irq;
173 u32 grp_id;
174 u64 timestamp;
175 bool napi_enabled;
176 struct napi_struct napi;
177 struct net_device napi_ndev;
178};
179
180enum ath11k_smbios_cc_type {
181 /* disable country code setting from SMBIOS */
182 ATH11K_SMBIOS_CC_DISABLE = 0,
183
184 /* set country code by ANSI country name, based on ISO3166-1 alpha2 */
185 ATH11K_SMBIOS_CC_ISO = 1,
186
187 /* worldwide regdomain */
188 ATH11K_SMBIOS_CC_WW = 2,
189};
190
191struct ath11k_smbios_bdf {
192 struct dmi_header hdr;
193
194 u8 features_disabled;
195
196 /* enum ath11k_smbios_cc_type */
197 u8 country_code_flag;
198
199 /* To set specific country, you need to set country code
200 * flag=ATH11K_SMBIOS_CC_ISO first, then if country is United
201 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'=
202 * 0x53). To set country to INDONESIA, then country code value =
203 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag =
204 * ATH11K_SMBIOS_CC_WW, then you can use worldwide regulatory
205 * setting.
206 */
207 u16 cc_code;
208
209 u8 bdf_enabled;
210 u8 bdf_ext[];
211} __packed;
212
213#define HEHANDLE_CAP_PHYINFO_SIZE 3
214#define HECAP_PHYINFO_SIZE 9
215#define HECAP_MACINFO_SIZE 5
216#define HECAP_TXRX_MCS_NSS_SIZE 2
217#define HECAP_PPET16_PPET8_MAX_SIZE 25
218
219#define HE_PPET16_PPET8_SIZE 8
220
221/* 802.11ax PPE (PPDU packet Extension) threshold */
222struct he_ppe_threshold {
223 u32 numss_m1;
224 u32 ru_mask;
225 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
226};
227
228struct ath11k_he {
229 u8 hecap_macinfo[HECAP_MACINFO_SIZE];
230 u32 hecap_rxmcsnssmap;
231 u32 hecap_txmcsnssmap;
232 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
233 struct he_ppe_threshold hecap_ppet;
234 u32 heop_param;
235};
236
237#define MAX_RADIOS 3
238
239/* ipq5018 hw param macros */
240#define MAX_RADIOS_5018 1
241#define CE_CNT_5018 6
242#define TARGET_CE_CNT_5018 9
243#define SVC_CE_MAP_LEN_5018 17
244#define RXDMA_PER_PDEV_5018 1
245
246enum {
247 WMI_HOST_TP_SCALE_MAX = 0,
248 WMI_HOST_TP_SCALE_50 = 1,
249 WMI_HOST_TP_SCALE_25 = 2,
250 WMI_HOST_TP_SCALE_12 = 3,
251 WMI_HOST_TP_SCALE_MIN = 4,
252 WMI_HOST_TP_SCALE_SIZE = 5,
253};
254
255enum ath11k_scan_state {
256 ATH11K_SCAN_IDLE,
257 ATH11K_SCAN_STARTING,
258 ATH11K_SCAN_RUNNING,
259 ATH11K_SCAN_ABORTING,
260};
261
262enum ath11k_11d_state {
263 ATH11K_11D_IDLE,
264 ATH11K_11D_PREPARING,
265 ATH11K_11D_RUNNING,
266};
267
268enum ath11k_dev_flags {
269 ATH11K_CAC_RUNNING,
270 ATH11K_FLAG_CORE_REGISTERED,
271 ATH11K_FLAG_CRASH_FLUSH,
272 ATH11K_FLAG_RAW_MODE,
273 ATH11K_FLAG_HW_CRYPTO_DISABLED,
274 ATH11K_FLAG_BTCOEX,
275 ATH11K_FLAG_RECOVERY,
276 ATH11K_FLAG_UNREGISTERING,
277 ATH11K_FLAG_REGISTERED,
278 ATH11K_FLAG_QMI_FAIL,
279 ATH11K_FLAG_HTC_SUSPEND_COMPLETE,
280 ATH11K_FLAG_CE_IRQ_ENABLED,
281 ATH11K_FLAG_EXT_IRQ_ENABLED,
282 ATH11K_FLAG_FIXED_MEM_RGN,
283 ATH11K_FLAG_DEVICE_INIT_DONE,
284 ATH11K_FLAG_MULTI_MSI_VECTORS,
285 ATH11K_FLAG_FTM_SEGMENTED,
286};
287
288enum ath11k_monitor_flags {
289 ATH11K_FLAG_MONITOR_CONF_ENABLED,
290 ATH11K_FLAG_MONITOR_STARTED,
291 ATH11K_FLAG_MONITOR_VDEV_CREATED,
292};
293
294#define ATH11K_IPV6_UC_TYPE 0
295#define ATH11K_IPV6_AC_TYPE 1
296
297#define ATH11K_IPV6_MAX_COUNT 16
298#define ATH11K_IPV4_MAX_COUNT 2
299
300struct ath11k_arp_ns_offload {
301 u8 ipv4_addr[ATH11K_IPV4_MAX_COUNT][4];
302 u32 ipv4_count;
303 u32 ipv6_count;
304 u8 ipv6_addr[ATH11K_IPV6_MAX_COUNT][16];
305 u8 self_ipv6_addr[ATH11K_IPV6_MAX_COUNT][16];
306 u8 ipv6_type[ATH11K_IPV6_MAX_COUNT];
307 bool ipv6_valid[ATH11K_IPV6_MAX_COUNT];
308 u8 mac_addr[ETH_ALEN];
309};
310
311struct ath11k_rekey_data {
312 u8 kck[NL80211_KCK_LEN];
313 u8 kek[NL80211_KCK_LEN];
314 u64 replay_ctr;
315 bool enable_offload;
316};
317
318/**
319 * struct ath11k_chan_power_info - TPE containing power info per channel chunk
320 * @chan_cfreq: channel center freq (MHz)
321 * e.g.
322 * channel 37/20 MHz, it is 6135
323 * channel 37/40 MHz, it is 6125
324 * channel 37/80 MHz, it is 6145
325 * channel 37/160 MHz, it is 6185
326 * @tx_power: transmit power (dBm)
327 */
328struct ath11k_chan_power_info {
329 u16 chan_cfreq;
330 s8 tx_power;
331};
332
333/**
334 * struct ath11k_reg_tpc_power_info - regulatory TPC power info
335 * @is_psd_power: is PSD power or not
336 * @eirp_power: Maximum EIRP power (dBm), valid only if power is PSD
337 * @ap_power_type: type of power (SP/LPI/VLP)
338 * @num_pwr_levels: number of power levels
339 * @reg_max: Array of maximum TX power (dBm) per PSD value
340 * @ap_constraint_power: AP constraint power (dBm)
341 * @tpe: TPE values processed from TPE IE
342 * @chan_power_info: power info to send to firmware
343 */
344struct ath11k_reg_tpc_power_info {
345 bool is_psd_power;
346 u8 eirp_power;
347 enum wmi_reg_6ghz_ap_type ap_power_type;
348 u8 num_pwr_levels;
349 u8 reg_max[IEEE80211_MAX_NUM_PWR_LEVEL];
350 u8 ap_constraint_power;
351 s8 tpe[IEEE80211_MAX_NUM_PWR_LEVEL];
352 struct ath11k_chan_power_info chan_power_info[IEEE80211_MAX_NUM_PWR_LEVEL];
353};
354
355struct ath11k_vif {
356 u32 vdev_id;
357 enum wmi_vdev_type vdev_type;
358 enum wmi_vdev_subtype vdev_subtype;
359 u32 beacon_interval;
360 u32 dtim_period;
361 u16 ast_hash;
362 u16 ast_idx;
363 u16 tcl_metadata;
364 u8 hal_addr_search_flags;
365 u8 search_type;
366
367 struct ath11k *ar;
368 struct ieee80211_vif *vif;
369
370 u16 tx_seq_no;
371 struct wmi_wmm_params_all_arg wmm_params;
372 struct list_head list;
373 union {
374 struct {
375 u32 uapsd;
376 } sta;
377 struct {
378 /* 127 stations; wmi limit */
379 u8 tim_bitmap[16];
380 u8 tim_len;
381 u32 ssid_len;
382 u8 ssid[IEEE80211_MAX_SSID_LEN];
383 bool hidden_ssid;
384 /* P2P_IE with NoA attribute for P2P_GO case */
385 u32 noa_len;
386 u8 *noa_data;
387 } ap;
388 } u;
389
390 bool is_started;
391 bool is_up;
392 bool ftm_responder;
393 bool spectral_enabled;
394 bool ps;
395 u32 aid;
396 u8 bssid[ETH_ALEN];
397 struct cfg80211_bitrate_mask bitrate_mask;
398 struct delayed_work connection_loss_work;
399 int num_legacy_stations;
400 int rtscts_prot_mode;
401 int txpower;
402 bool rsnie_present;
403 bool wpaie_present;
404 bool bcca_zero_sent;
405 bool do_not_send_tmpl;
406 struct ieee80211_chanctx_conf chanctx;
407 struct ath11k_arp_ns_offload arp_ns_offload;
408 struct ath11k_rekey_data rekey_data;
409
410 struct ath11k_reg_tpc_power_info reg_tpc_info;
411};
412
413struct ath11k_vif_iter {
414 u32 vdev_id;
415 struct ath11k_vif *arvif;
416};
417
418struct ath11k_rx_peer_stats {
419 u64 num_msdu;
420 u64 num_mpdu_fcs_ok;
421 u64 num_mpdu_fcs_err;
422 u64 tcp_msdu_count;
423 u64 udp_msdu_count;
424 u64 other_msdu_count;
425 u64 ampdu_msdu_count;
426 u64 non_ampdu_msdu_count;
427 u64 stbc_count;
428 u64 beamformed_count;
429 u64 mcs_count[HAL_RX_MAX_MCS + 1];
430 u64 nss_count[HAL_RX_MAX_NSS];
431 u64 bw_count[HAL_RX_BW_MAX];
432 u64 gi_count[HAL_RX_GI_MAX];
433 u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
434 u64 tid_count[IEEE80211_NUM_TIDS + 1];
435 u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
436 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
437 u64 rx_duration;
438 u64 dcm_count;
439 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX];
440};
441
442#define ATH11K_HE_MCS_NUM 12
443#define ATH11K_VHT_MCS_NUM 10
444#define ATH11K_BW_NUM 4
445#define ATH11K_NSS_NUM 4
446#define ATH11K_LEGACY_NUM 12
447#define ATH11K_GI_NUM 4
448#define ATH11K_HT_MCS_NUM 32
449
450enum ath11k_pkt_rx_err {
451 ATH11K_PKT_RX_ERR_FCS,
452 ATH11K_PKT_RX_ERR_TKIP,
453 ATH11K_PKT_RX_ERR_CRYPT,
454 ATH11K_PKT_RX_ERR_PEER_IDX_INVAL,
455 ATH11K_PKT_RX_ERR_MAX,
456};
457
458enum ath11k_ampdu_subfrm_num {
459 ATH11K_AMPDU_SUBFRM_NUM_10,
460 ATH11K_AMPDU_SUBFRM_NUM_20,
461 ATH11K_AMPDU_SUBFRM_NUM_30,
462 ATH11K_AMPDU_SUBFRM_NUM_40,
463 ATH11K_AMPDU_SUBFRM_NUM_50,
464 ATH11K_AMPDU_SUBFRM_NUM_60,
465 ATH11K_AMPDU_SUBFRM_NUM_MORE,
466 ATH11K_AMPDU_SUBFRM_NUM_MAX,
467};
468
469enum ath11k_amsdu_subfrm_num {
470 ATH11K_AMSDU_SUBFRM_NUM_1,
471 ATH11K_AMSDU_SUBFRM_NUM_2,
472 ATH11K_AMSDU_SUBFRM_NUM_3,
473 ATH11K_AMSDU_SUBFRM_NUM_4,
474 ATH11K_AMSDU_SUBFRM_NUM_MORE,
475 ATH11K_AMSDU_SUBFRM_NUM_MAX,
476};
477
478enum ath11k_counter_type {
479 ATH11K_COUNTER_TYPE_BYTES,
480 ATH11K_COUNTER_TYPE_PKTS,
481 ATH11K_COUNTER_TYPE_MAX,
482};
483
484enum ath11k_stats_type {
485 ATH11K_STATS_TYPE_SUCC,
486 ATH11K_STATS_TYPE_FAIL,
487 ATH11K_STATS_TYPE_RETRY,
488 ATH11K_STATS_TYPE_AMPDU,
489 ATH11K_STATS_TYPE_MAX,
490};
491
492struct ath11k_htt_data_stats {
493 u64 legacy[ATH11K_COUNTER_TYPE_MAX][ATH11K_LEGACY_NUM];
494 u64 ht[ATH11K_COUNTER_TYPE_MAX][ATH11K_HT_MCS_NUM];
495 u64 vht[ATH11K_COUNTER_TYPE_MAX][ATH11K_VHT_MCS_NUM];
496 u64 he[ATH11K_COUNTER_TYPE_MAX][ATH11K_HE_MCS_NUM];
497 u64 bw[ATH11K_COUNTER_TYPE_MAX][ATH11K_BW_NUM];
498 u64 nss[ATH11K_COUNTER_TYPE_MAX][ATH11K_NSS_NUM];
499 u64 gi[ATH11K_COUNTER_TYPE_MAX][ATH11K_GI_NUM];
500};
501
502struct ath11k_htt_tx_stats {
503 struct ath11k_htt_data_stats stats[ATH11K_STATS_TYPE_MAX];
504 u64 tx_duration;
505 u64 ba_fails;
506 u64 ack_fails;
507};
508
509struct ath11k_per_ppdu_tx_stats {
510 u16 succ_pkts;
511 u16 failed_pkts;
512 u16 retry_pkts;
513 u32 succ_bytes;
514 u32 failed_bytes;
515 u32 retry_bytes;
516};
517
518DECLARE_EWMA(avg_rssi, 10, 8)
519
520struct ath11k_sta {
521 struct ath11k_vif *arvif;
522
523 /* the following are protected by ar->data_lock */
524 u32 changed; /* IEEE80211_RC_* */
525 u32 bw;
526 u32 nss;
527 u32 smps;
528 enum hal_pn_type pn_type;
529
530 struct work_struct update_wk;
531 struct work_struct set_4addr_wk;
532 struct rate_info txrate;
533 u32 peer_nss;
534 struct rate_info last_txrate;
535 u64 rx_duration;
536 u64 tx_duration;
537 u8 rssi_comb;
538 struct ewma_avg_rssi avg_rssi;
539 s8 rssi_beacon;
540 s8 chain_signal[IEEE80211_MAX_CHAINS];
541 struct ath11k_htt_tx_stats *tx_stats;
542 struct ath11k_rx_peer_stats *rx_stats;
543
544#ifdef CONFIG_MAC80211_DEBUGFS
545 /* protected by conf_mutex */
546 bool aggr_mode;
547#endif
548
549 bool use_4addr_set;
550 u16 tcl_metadata;
551
552 /* Protected with ar->data_lock */
553 enum ath11k_wmi_peer_ps_state peer_ps_state;
554 u64 ps_start_time;
555 u64 ps_start_jiffies;
556 u64 ps_total_duration;
557 bool peer_current_ps_valid;
558
559 u32 bw_prev;
560};
561
562#define ATH11K_MIN_5G_FREQ 4150
563#define ATH11K_MIN_6G_FREQ 5925
564#define ATH11K_MAX_6G_FREQ 7115
565#define ATH11K_NUM_CHANS 102
566#define ATH11K_MAX_5G_CHAN 177
567
568enum ath11k_state {
569 ATH11K_STATE_OFF,
570 ATH11K_STATE_ON,
571 ATH11K_STATE_RESTARTING,
572 ATH11K_STATE_RESTARTED,
573 ATH11K_STATE_WEDGED,
574 ATH11K_STATE_FTM,
575 /* Add other states as required */
576};
577
578/* Antenna noise floor */
579#define ATH11K_DEFAULT_NOISE_FLOOR -95
580
581#define ATH11K_INVALID_RSSI_FULL -1
582
583#define ATH11K_INVALID_RSSI_EMPTY -128
584
585struct ath11k_fw_stats {
586 struct dentry *debugfs_fwstats;
587 u32 pdev_id;
588 u32 stats_id;
589 struct list_head pdevs;
590 struct list_head vdevs;
591 struct list_head bcn;
592};
593
594struct ath11k_dbg_htt_stats {
595 u8 type;
596 u8 reset;
597 struct debug_htt_stats_req *stats_req;
598 /* protects shared stats req buffer */
599 spinlock_t lock;
600};
601
602#define MAX_MODULE_ID_BITMAP_WORDS 16
603
604struct ath11k_debug {
605 struct dentry *debugfs_pdev;
606 struct ath11k_dbg_htt_stats htt_stats;
607 u32 extd_tx_stats;
608 u32 extd_rx_stats;
609 u32 pktlog_filter;
610 u32 pktlog_mode;
611 u32 pktlog_peer_valid;
612 u8 pktlog_peer_addr[ETH_ALEN];
613 u32 rx_filter;
614 u32 mem_offset;
615 u32 module_id_bitmap[MAX_MODULE_ID_BITMAP_WORDS];
616 struct ath11k_debug_dbr *dbr_debug[WMI_DIRECT_BUF_MAX];
617};
618
619struct ath11k_per_peer_tx_stats {
620 u32 succ_bytes;
621 u32 retry_bytes;
622 u32 failed_bytes;
623 u16 succ_pkts;
624 u16 retry_pkts;
625 u16 failed_pkts;
626 u32 duration;
627 u8 ba_fails;
628 bool is_ampdu;
629};
630
631#define ATH11K_FLUSH_TIMEOUT (5 * HZ)
632#define ATH11K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
633
634struct ath11k {
635 struct ath11k_base *ab;
636 struct ath11k_pdev *pdev;
637 struct ieee80211_hw *hw;
638 struct ath11k_pdev_wmi *wmi;
639 struct ath11k_pdev_dp dp;
640 u8 mac_addr[ETH_ALEN];
641 struct ath11k_he ar_he;
642 enum ath11k_state state;
643 bool supports_6ghz;
644 struct {
645 struct completion started;
646 struct completion completed;
647 struct completion on_channel;
648 struct delayed_work timeout;
649 enum ath11k_scan_state state;
650 bool is_roc;
651 int vdev_id;
652 int roc_freq;
653 bool roc_notify;
654 } scan;
655
656 struct {
657 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
658 struct ieee80211_sband_iftype_data
659 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
660 } mac;
661
662 unsigned long dev_flags;
663 unsigned int filter_flags;
664 unsigned long monitor_flags;
665 u32 min_tx_power;
666 u32 max_tx_power;
667 u32 txpower_limit_2g;
668 u32 txpower_limit_5g;
669 u32 txpower_scale;
670 u32 power_scale;
671 u32 chan_tx_pwr;
672 u32 num_stations;
673 u32 max_num_stations;
674 /* To synchronize concurrent synchronous mac80211 callback operations,
675 * concurrent debugfs configuration and concurrent FW statistics events.
676 */
677 struct mutex conf_mutex;
678 /* protects the radio specific data like debug stats, ppdu_stats_info stats,
679 * vdev_stop_status info, scan data, ath11k_sta info, ath11k_vif info,
680 * channel context data, survey info, test mode data.
681 */
682 spinlock_t data_lock;
683
684 struct list_head arvifs;
685 /* should never be NULL; needed for regular htt rx */
686 struct ieee80211_channel *rx_channel;
687
688 /* valid during scan; needed for mgmt rx during scan */
689 struct ieee80211_channel *scan_channel;
690
691 u8 cfg_tx_chainmask;
692 u8 cfg_rx_chainmask;
693 u8 num_rx_chains;
694 u8 num_tx_chains;
695 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
696 u8 pdev_idx;
697 u8 lmac_id;
698
699 struct completion peer_assoc_done;
700 struct completion peer_delete_done;
701
702 int install_key_status;
703 struct completion install_key_done;
704
705 int last_wmi_vdev_start_status;
706 struct completion vdev_setup_done;
707 struct completion vdev_delete_done;
708
709 int num_peers;
710 int max_num_peers;
711 u32 num_started_vdevs;
712 u32 num_created_vdevs;
713 unsigned long long allocated_vdev_map;
714
715 struct idr txmgmt_idr;
716 /* protects txmgmt_idr data */
717 spinlock_t txmgmt_idr_lock;
718 atomic_t num_pending_mgmt_tx;
719 wait_queue_head_t txmgmt_empty_waitq;
720
721 /* cycle count is reported twice for each visited channel during scan.
722 * access protected by data_lock
723 */
724 u32 survey_last_rx_clear_count;
725 u32 survey_last_cycle_count;
726
727 /* Channel info events are expected to come in pairs without and with
728 * COMPLETE flag set respectively for each channel visit during scan.
729 *
730 * However there are deviations from this rule. This flag is used to
731 * avoid reporting garbage data.
732 */
733 bool ch_info_can_report_survey;
734 struct survey_info survey[ATH11K_NUM_CHANS];
735 struct completion bss_survey_done;
736
737 struct work_struct regd_update_work;
738
739 struct work_struct wmi_mgmt_tx_work;
740 struct sk_buff_head wmi_mgmt_tx_queue;
741
742 struct ath11k_wow wow;
743 struct completion target_suspend;
744 bool target_suspend_ack;
745 struct ath11k_per_peer_tx_stats peer_tx_stats;
746 struct list_head ppdu_stats_info;
747 u32 ppdu_stat_list_depth;
748
749 struct ath11k_per_peer_tx_stats cached_stats;
750 u32 last_ppdu_id;
751 u32 cached_ppdu_id;
752 int monitor_vdev_id;
753 struct completion fw_mode_reset;
754 u8 ftm_msgref;
755#ifdef CONFIG_ATH11K_DEBUGFS
756 struct ath11k_debug debug;
757#endif
758#ifdef CONFIG_ATH11K_SPECTRAL
759 struct ath11k_spectral spectral;
760#endif
761 bool dfs_block_radar_events;
762 struct ath11k_thermal thermal;
763 u32 vdev_id_11d_scan;
764 struct completion completed_11d_scan;
765 enum ath11k_11d_state state_11d;
766 bool regdom_set_by_user;
767 int hw_rate_code;
768 u8 twt_enabled;
769 bool nlo_enabled;
770 u8 alpha2[REG_ALPHA2_LEN + 1];
771 struct ath11k_fw_stats fw_stats;
772 struct completion fw_stats_complete;
773 bool fw_stats_done;
774
775 /* protected by conf_mutex */
776 bool ps_state_enable;
777 bool ps_timekeeper_enable;
778 s8 max_allowed_tx_power;
779};
780
781struct ath11k_band_cap {
782 u32 phy_id;
783 u32 max_bw_supported;
784 u32 ht_cap_info;
785 u32 he_cap_info[2];
786 u32 he_mcs;
787 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
788 struct ath11k_ppe_threshold he_ppet;
789 u16 he_6ghz_capa;
790};
791
792struct ath11k_pdev_cap {
793 u32 supported_bands;
794 u32 ampdu_density;
795 u32 vht_cap;
796 u32 vht_mcs;
797 u32 he_mcs;
798 u32 tx_chain_mask;
799 u32 rx_chain_mask;
800 u32 tx_chain_mask_shift;
801 u32 rx_chain_mask_shift;
802 struct ath11k_band_cap band[NUM_NL80211_BANDS];
803 bool nss_ratio_enabled;
804 u8 nss_ratio_info;
805};
806
807struct ath11k_pdev {
808 struct ath11k *ar;
809 u32 pdev_id;
810 struct ath11k_pdev_cap cap;
811 u8 mac_addr[ETH_ALEN];
812};
813
814struct ath11k_board_data {
815 const struct firmware *fw;
816 const void *data;
817 size_t len;
818};
819
820struct ath11k_pci_ops {
821 int (*wakeup)(struct ath11k_base *ab);
822 void (*release)(struct ath11k_base *ab);
823 int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector);
824 void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value);
825 u32 (*window_read32)(struct ath11k_base *ab, u32 offset);
826};
827
828/* IPQ8074 HW channel counters frequency value in hertz */
829#define IPQ8074_CC_FREQ_HERTZ 320000
830
831struct ath11k_bp_stats {
832 /* Head Pointer reported by the last HTT Backpressure event for the ring */
833 u16 hp;
834
835 /* Tail Pointer reported by the last HTT Backpressure event for the ring */
836 u16 tp;
837
838 /* Number of Backpressure events received for the ring */
839 u32 count;
840
841 /* Last recorded event timestamp */
842 unsigned long jiffies;
843};
844
845struct ath11k_dp_ring_bp_stats {
846 struct ath11k_bp_stats umac_ring_bp_stats[HTT_SW_UMAC_RING_IDX_MAX];
847 struct ath11k_bp_stats lmac_ring_bp_stats[HTT_SW_LMAC_RING_IDX_MAX][MAX_RADIOS];
848};
849
850struct ath11k_soc_dp_tx_err_stats {
851 /* TCL Ring Descriptor unavailable */
852 u32 desc_na[DP_TCL_NUM_RING_MAX];
853 /* Other failures during dp_tx due to mem allocation failure
854 * idr unavailable etc.
855 */
856 atomic_t misc_fail;
857};
858
859struct ath11k_soc_dp_stats {
860 u32 err_ring_pkts;
861 u32 invalid_rbm;
862 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
863 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
864 u32 hal_reo_error[DP_REO_DST_RING_MAX];
865 struct ath11k_soc_dp_tx_err_stats tx_err;
866 struct ath11k_dp_ring_bp_stats bp_stats;
867};
868
869struct ath11k_msi_user {
870 char *name;
871 int num_vectors;
872 u32 base_vector;
873};
874
875struct ath11k_msi_config {
876 int total_vectors;
877 int total_users;
878 struct ath11k_msi_user *users;
879 u16 hw_rev;
880};
881
882/* Master structure to hold the hw data which may be used in core module */
883struct ath11k_base {
884 enum ath11k_hw_rev hw_rev;
885 enum ath11k_firmware_mode fw_mode;
886 struct platform_device *pdev;
887 struct device *dev;
888 struct ath11k_qmi qmi;
889 struct ath11k_wmi_base wmi_ab;
890 struct completion fw_ready;
891 int num_radios;
892 /* HW channel counters frequency value in hertz common to all MACs */
893 u32 cc_freq_hz;
894
895 struct ath11k_htc htc;
896
897 struct ath11k_dp dp;
898
899 void __iomem *mem;
900 void __iomem *mem_ce;
901 unsigned long mem_len;
902
903 struct {
904 enum ath11k_bus bus;
905 const struct ath11k_hif_ops *ops;
906 } hif;
907
908 struct {
909 struct completion wakeup_completed;
910 } wow;
911
912 struct ath11k_ce ce;
913 struct timer_list rx_replenish_retry;
914 struct ath11k_hal hal;
915 /* To synchronize core_start/core_stop */
916 struct mutex core_lock;
917 /* Protects data like peers */
918 spinlock_t base_lock;
919 struct ath11k_pdev pdevs[MAX_RADIOS];
920 struct {
921 enum WMI_HOST_WLAN_BAND supported_bands;
922 u32 pdev_id;
923 } target_pdev_ids[MAX_RADIOS];
924 u8 target_pdev_count;
925 struct ath11k_pdev __rcu *pdevs_active[MAX_RADIOS];
926 struct ath11k_hal_reg_capabilities_ext hal_reg_cap[MAX_RADIOS];
927 unsigned long long free_vdev_map;
928
929 /* To synchronize rhash tbl write operation */
930 struct mutex tbl_mtx_lock;
931
932 /* The rhashtable containing struct ath11k_peer keyed by mac addr */
933 struct rhashtable *rhead_peer_addr;
934 struct rhashtable_params rhash_peer_addr_param;
935
936 /* The rhashtable containing struct ath11k_peer keyed by id */
937 struct rhashtable *rhead_peer_id;
938 struct rhashtable_params rhash_peer_id_param;
939
940 struct list_head peers;
941 wait_queue_head_t peer_mapping_wq;
942 u8 mac_addr[ETH_ALEN];
943 int irq_num[ATH11K_IRQ_NUM_MAX];
944 struct ath11k_ext_irq_grp ext_irq_grp[ATH11K_EXT_IRQ_GRP_NUM_MAX];
945 struct ath11k_targ_cap target_caps;
946 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
947 bool pdevs_macaddr_valid;
948
949 struct ath11k_hw_params hw_params;
950
951 const struct firmware *cal_file;
952
953 /* Below regd's are protected by ab->data_lock */
954 /* This is the regd set for every radio
955 * by the firmware during initialization
956 */
957 struct ieee80211_regdomain *default_regd[MAX_RADIOS];
958 /* This regd is set during dynamic country setting
959 * This may or may not be used during the runtime
960 */
961 struct ieee80211_regdomain *new_regd[MAX_RADIOS];
962 struct cur_regulatory_info *reg_info_store;
963
964 /* Current DFS Regulatory */
965 enum ath11k_dfs_region dfs_region;
966#ifdef CONFIG_ATH11K_DEBUGFS
967 struct dentry *debugfs_soc;
968#endif
969 struct ath11k_soc_dp_stats soc_stats;
970
971 unsigned long dev_flags;
972 struct completion driver_recovery;
973 struct workqueue_struct *workqueue;
974 struct work_struct restart_work;
975 struct work_struct update_11d_work;
976 u8 new_alpha2[3];
977 struct workqueue_struct *workqueue_aux;
978 struct work_struct reset_work;
979 atomic_t reset_count;
980 atomic_t recovery_count;
981 atomic_t recovery_start_count;
982 bool is_reset;
983 struct completion reset_complete;
984 struct completion reconfigure_complete;
985 struct completion recovery_start;
986 /* continuous recovery fail count */
987 atomic_t fail_cont_count;
988 unsigned long reset_fail_timeout;
989 struct {
990 /* protected by data_lock */
991 u32 fw_crash_counter;
992 } stats;
993 u32 pktlog_defs_checksum;
994
995 struct ath11k_dbring_cap *db_caps;
996 u32 num_db_cap;
997
998 /* To synchronize 11d scan vdev id */
999 struct mutex vdev_id_11d_lock;
1000 struct timer_list mon_reap_timer;
1001
1002 struct completion htc_suspend;
1003
1004 struct {
1005 enum ath11k_bdf_search bdf_search;
1006 u32 vendor;
1007 u32 device;
1008 u32 subsystem_vendor;
1009 u32 subsystem_device;
1010 } id;
1011
1012 struct {
1013 struct {
1014 const struct ath11k_msi_config *config;
1015 u32 ep_base_data;
1016 u32 irqs[32];
1017 u32 addr_lo;
1018 u32 addr_hi;
1019 } msi;
1020
1021 const struct ath11k_pci_ops *ops;
1022 } pci;
1023
1024 struct {
1025 u32 api_version;
1026
1027 const struct firmware *fw;
1028 const u8 *amss_data;
1029 size_t amss_len;
1030 const u8 *m3_data;
1031 size_t m3_len;
1032
1033 DECLARE_BITMAP(fw_features, ATH11K_FW_FEATURE_COUNT);
1034 } fw;
1035
1036#ifdef CONFIG_NL80211_TESTMODE
1037 struct {
1038 u32 data_pos;
1039 u32 expected_seq;
1040 u8 *eventdata;
1041 } testmode;
1042#endif
1043
1044 /* must be last */
1045 u8 drv_priv[] __aligned(sizeof(void *));
1046};
1047
1048struct ath11k_fw_stats_pdev {
1049 struct list_head list;
1050
1051 /* PDEV stats */
1052 s32 ch_noise_floor;
1053 /* Cycles spent transmitting frames */
1054 u32 tx_frame_count;
1055 /* Cycles spent receiving frames */
1056 u32 rx_frame_count;
1057 /* Total channel busy time, evidently */
1058 u32 rx_clear_count;
1059 /* Total on-channel time */
1060 u32 cycle_count;
1061 u32 phy_err_count;
1062 u32 chan_tx_power;
1063 u32 ack_rx_bad;
1064 u32 rts_bad;
1065 u32 rts_good;
1066 u32 fcs_bad;
1067 u32 no_beacons;
1068 u32 mib_int_count;
1069
1070 /* PDEV TX stats */
1071 /* Num HTT cookies queued to dispatch list */
1072 s32 comp_queued;
1073 /* Num HTT cookies dispatched */
1074 s32 comp_delivered;
1075 /* Num MSDU queued to WAL */
1076 s32 msdu_enqued;
1077 /* Num MPDU queue to WAL */
1078 s32 mpdu_enqued;
1079 /* Num MSDUs dropped by WMM limit */
1080 s32 wmm_drop;
1081 /* Num Local frames queued */
1082 s32 local_enqued;
1083 /* Num Local frames done */
1084 s32 local_freed;
1085 /* Num queued to HW */
1086 s32 hw_queued;
1087 /* Num PPDU reaped from HW */
1088 s32 hw_reaped;
1089 /* Num underruns */
1090 s32 underrun;
1091 /* Num hw paused */
1092 u32 hw_paused;
1093 /* Num PPDUs cleaned up in TX abort */
1094 s32 tx_abort;
1095 /* Num MPDUs requeued by SW */
1096 s32 mpdus_requeued;
1097 /* excessive retries */
1098 u32 tx_ko;
1099 u32 tx_xretry;
1100 /* data hw rate code */
1101 u32 data_rc;
1102 /* Scheduler self triggers */
1103 u32 self_triggers;
1104 /* frames dropped due to excessive sw retries */
1105 u32 sw_retry_failure;
1106 /* illegal rate phy errors */
1107 u32 illgl_rate_phy_err;
1108 /* wal pdev continuous xretry */
1109 u32 pdev_cont_xretry;
1110 /* wal pdev tx timeouts */
1111 u32 pdev_tx_timeout;
1112 /* wal pdev resets */
1113 u32 pdev_resets;
1114 /* frames dropped due to non-availability of stateless TIDs */
1115 u32 stateless_tid_alloc_failure;
1116 /* PhY/BB underrun */
1117 u32 phy_underrun;
1118 /* MPDU is more than txop limit */
1119 u32 txop_ovf;
1120 /* Num sequences posted */
1121 u32 seq_posted;
1122 /* Num sequences failed in queueing */
1123 u32 seq_failed_queueing;
1124 /* Num sequences completed */
1125 u32 seq_completed;
1126 /* Num sequences restarted */
1127 u32 seq_restarted;
1128 /* Num of MU sequences posted */
1129 u32 mu_seq_posted;
1130 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT
1131 * (Reset,channel change)
1132 */
1133 s32 mpdus_sw_flush;
1134 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */
1135 s32 mpdus_hw_filter;
1136 /* Num MPDUs truncated by PDG (TXOP, TBTT,
1137 * PPDU_duration based on rate, dyn_bw)
1138 */
1139 s32 mpdus_truncated;
1140 /* Num MPDUs that was tried but didn't receive ACK or BA */
1141 s32 mpdus_ack_failed;
1142 /* Num MPDUs that was dropped du to expiry. */
1143 s32 mpdus_expired;
1144
1145 /* PDEV RX stats */
1146 /* Cnts any change in ring routing mid-ppdu */
1147 s32 mid_ppdu_route_change;
1148 /* Total number of statuses processed */
1149 s32 status_rcvd;
1150 /* Extra frags on rings 0-3 */
1151 s32 r0_frags;
1152 s32 r1_frags;
1153 s32 r2_frags;
1154 s32 r3_frags;
1155 /* MSDUs / MPDUs delivered to HTT */
1156 s32 htt_msdus;
1157 s32 htt_mpdus;
1158 /* MSDUs / MPDUs delivered to local stack */
1159 s32 loc_msdus;
1160 s32 loc_mpdus;
1161 /* AMSDUs that have more MSDUs than the status ring size */
1162 s32 oversize_amsdu;
1163 /* Number of PHY errors */
1164 s32 phy_errs;
1165 /* Number of PHY errors drops */
1166 s32 phy_err_drop;
1167 /* Number of mpdu errors - FCS, MIC, ENC etc. */
1168 s32 mpdu_errs;
1169 /* Num overflow errors */
1170 s32 rx_ovfl_errs;
1171};
1172
1173struct ath11k_fw_stats_vdev {
1174 struct list_head list;
1175
1176 u32 vdev_id;
1177 u32 beacon_snr;
1178 u32 data_snr;
1179 u32 num_tx_frames[WLAN_MAX_AC];
1180 u32 num_rx_frames;
1181 u32 num_tx_frames_retries[WLAN_MAX_AC];
1182 u32 num_tx_frames_failures[WLAN_MAX_AC];
1183 u32 num_rts_fail;
1184 u32 num_rts_success;
1185 u32 num_rx_err;
1186 u32 num_rx_discard;
1187 u32 num_tx_not_acked;
1188 u32 tx_rate_history[MAX_TX_RATE_VALUES];
1189 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
1190};
1191
1192struct ath11k_fw_stats_bcn {
1193 struct list_head list;
1194
1195 u32 vdev_id;
1196 u32 tx_bcn_succ_cnt;
1197 u32 tx_bcn_outage_cnt;
1198};
1199
1200void ath11k_fw_stats_init(struct ath11k *ar);
1201void ath11k_fw_stats_pdevs_free(struct list_head *head);
1202void ath11k_fw_stats_vdevs_free(struct list_head *head);
1203void ath11k_fw_stats_bcn_free(struct list_head *head);
1204void ath11k_fw_stats_free(struct ath11k_fw_stats *stats);
1205
1206extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[];
1207extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[];
1208extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[];
1209
1210extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[];
1211extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[];
1212
1213extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[];
1214extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[];
1215
1216extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[];
1217extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[];
1218int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab);
1219int ath11k_core_pre_init(struct ath11k_base *ab);
1220int ath11k_core_init(struct ath11k_base *ath11k);
1221void ath11k_core_deinit(struct ath11k_base *ath11k);
1222struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
1223 enum ath11k_bus bus);
1224void ath11k_core_free(struct ath11k_base *ath11k);
1225int ath11k_core_fetch_bdf(struct ath11k_base *ath11k,
1226 struct ath11k_board_data *bd);
1227int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd);
1228int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1229 struct ath11k_board_data *bd,
1230 const char *name);
1231void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd);
1232int ath11k_core_check_dt(struct ath11k_base *ath11k);
1233int ath11k_core_check_smbios(struct ath11k_base *ab);
1234void ath11k_core_halt(struct ath11k *ar);
1235int ath11k_core_resume(struct ath11k_base *ab);
1236int ath11k_core_suspend(struct ath11k_base *ab);
1237void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab);
1238bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab);
1239
1240const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1241 const char *filename);
1242
1243static inline const char *ath11k_scan_state_str(enum ath11k_scan_state state)
1244{
1245 switch (state) {
1246 case ATH11K_SCAN_IDLE:
1247 return "idle";
1248 case ATH11K_SCAN_STARTING:
1249 return "starting";
1250 case ATH11K_SCAN_RUNNING:
1251 return "running";
1252 case ATH11K_SCAN_ABORTING:
1253 return "aborting";
1254 }
1255
1256 return "unknown";
1257}
1258
1259static inline struct ath11k_skb_cb *ATH11K_SKB_CB(struct sk_buff *skb)
1260{
1261 BUILD_BUG_ON(sizeof(struct ath11k_skb_cb) >
1262 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
1263 return (struct ath11k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
1264}
1265
1266static inline struct ath11k_skb_rxcb *ATH11K_SKB_RXCB(struct sk_buff *skb)
1267{
1268 BUILD_BUG_ON(sizeof(struct ath11k_skb_rxcb) > sizeof(skb->cb));
1269 return (struct ath11k_skb_rxcb *)skb->cb;
1270}
1271
1272static inline struct ath11k_vif *ath11k_vif_to_arvif(struct ieee80211_vif *vif)
1273{
1274 return (struct ath11k_vif *)vif->drv_priv;
1275}
1276
1277static inline struct ath11k_sta *ath11k_sta_to_arsta(struct ieee80211_sta *sta)
1278{
1279 return (struct ath11k_sta *)sta->drv_priv;
1280}
1281
1282static inline struct ath11k *ath11k_ab_to_ar(struct ath11k_base *ab,
1283 int mac_id)
1284{
1285 return ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
1286}
1287
1288static inline void ath11k_core_create_firmware_path(struct ath11k_base *ab,
1289 const char *filename,
1290 void *buf, size_t buf_len)
1291{
1292 snprintf(buf, buf_len, "%s/%s/%s", ATH11K_FW_DIR,
1293 ab->hw_params.fw.dir, filename);
1294}
1295
1296static inline const char *ath11k_bus_str(enum ath11k_bus bus)
1297{
1298 switch (bus) {
1299 case ATH11K_BUS_PCI:
1300 return "pci";
1301 case ATH11K_BUS_AHB:
1302 return "ahb";
1303 }
1304
1305 return "unknown";
1306}
1307
1308#endif /* _CORE_H_ */