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1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2// Copyright (c) 2017 Synopsys, Inc. and/or its affiliates.
3// stmmac Support for 5.xx Ethernet QoS cores
4
5#ifndef __DWMAC5_H__
6#define __DWMAC5_H__
7
8#define MAC_DPP_FSM_INT_STATUS 0x00000140
9#define MAC_AXI_SLV_DPE_ADDR_STATUS 0x00000144
10#define MAC_FSM_CONTROL 0x00000148
11#define PRTYEN BIT(1)
12#define TMOUTEN BIT(0)
13
14#define MAC_FPE_CTRL_STS 0x00000234
15#define TRSP BIT(19)
16#define TVER BIT(18)
17#define RRSP BIT(17)
18#define RVER BIT(16)
19#define SRSP BIT(2)
20#define SVER BIT(1)
21#define EFPE BIT(0)
22
23#define MAC_PPS_CONTROL 0x00000b70
24#define PPS_MAXIDX(x) ((((x) + 1) * 8) - 1)
25#define PPS_MINIDX(x) ((x) * 8)
26#define PPSx_MASK(x) GENMASK(PPS_MAXIDX(x), PPS_MINIDX(x))
27#define MCGRENx(x) BIT(PPS_MAXIDX(x))
28#define TRGTMODSELx(x, val) \
29 GENMASK(PPS_MAXIDX(x) - 1, PPS_MAXIDX(x) - 2) & \
30 ((val) << (PPS_MAXIDX(x) - 2))
31#define PPSCMDx(x, val) \
32 GENMASK(PPS_MINIDX(x) + 3, PPS_MINIDX(x)) & \
33 ((val) << PPS_MINIDX(x))
34#define PPSEN0 BIT(4)
35#define MAC_PPSx_TARGET_TIME_SEC(x) (0x00000b80 + ((x) * 0x10))
36#define MAC_PPSx_TARGET_TIME_NSEC(x) (0x00000b84 + ((x) * 0x10))
37#define TRGTBUSY0 BIT(31)
38#define TTSL0 GENMASK(30, 0)
39#define MAC_PPSx_INTERVAL(x) (0x00000b88 + ((x) * 0x10))
40#define MAC_PPSx_WIDTH(x) (0x00000b8c + ((x) * 0x10))
41
42#define MTL_RXP_CONTROL_STATUS 0x00000ca0
43#define RXPI BIT(31)
44#define NPE GENMASK(23, 16)
45#define NVE GENMASK(7, 0)
46#define MTL_RXP_IACC_CTRL_STATUS 0x00000cb0
47#define STARTBUSY BIT(31)
48#define RXPEIEC GENMASK(22, 21)
49#define RXPEIEE BIT(20)
50#define WRRDN BIT(16)
51#define ADDR GENMASK(15, 0)
52#define MTL_RXP_IACC_DATA 0x00000cb4
53#define MTL_ECC_CONTROL 0x00000cc0
54#define MEEAO BIT(8)
55#define TSOEE BIT(4)
56#define MRXPEE BIT(3)
57#define MESTEE BIT(2)
58#define MRXEE BIT(1)
59#define MTXEE BIT(0)
60
61#define MTL_SAFETY_INT_STATUS 0x00000cc4
62#define MCSIS BIT(31)
63#define MEUIS BIT(1)
64#define MECIS BIT(0)
65#define MTL_ECC_INT_ENABLE 0x00000cc8
66#define RPCEIE BIT(12)
67#define ECEIE BIT(8)
68#define RXCEIE BIT(4)
69#define TXCEIE BIT(0)
70#define MTL_ECC_INT_STATUS 0x00000ccc
71#define MTL_DPP_CONTROL 0x00000ce0
72#define EPSI BIT(2)
73#define OPE BIT(1)
74#define EDPP BIT(0)
75
76#define DMA_SAFETY_INT_STATUS 0x00001080
77#define MSUIS BIT(29)
78#define MSCIS BIT(28)
79#define DEUIS BIT(1)
80#define DECIS BIT(0)
81#define DMA_ECC_INT_ENABLE 0x00001084
82#define TCEIE BIT(0)
83#define DMA_ECC_INT_STATUS 0x00001088
84
85/* EQoS version 5.xx VLAN Tag Filter Fail Packets Queuing */
86#define GMAC_RXQ_CTRL4 0x00000094
87#define GMAC_RXQCTRL_VFFQ_MASK GENMASK(19, 17)
88#define GMAC_RXQCTRL_VFFQ_SHIFT 17
89#define GMAC_RXQCTRL_VFFQE BIT(16)
90
91#define GMAC_INT_FPE_EN BIT(17)
92
93int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp,
94 struct stmmac_safety_feature_cfg *safety_cfg);
95int dwmac5_safety_feat_irq_status(struct net_device *ndev,
96 void __iomem *ioaddr, unsigned int asp,
97 struct stmmac_safety_stats *stats);
98int dwmac5_safety_feat_dump(struct stmmac_safety_stats *stats,
99 int index, unsigned long *count, const char **desc);
100int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries,
101 unsigned int count);
102int dwmac5_flex_pps_config(void __iomem *ioaddr, int index,
103 struct stmmac_pps_cfg *cfg, bool enable,
104 u32 sub_second_inc, u32 systime_flags);
105void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
106 u32 num_txq, u32 num_rxq,
107 bool enable);
108void dwmac5_fpe_send_mpacket(void __iomem *ioaddr,
109 struct stmmac_fpe_cfg *cfg,
110 enum stmmac_mpacket_type type);
111int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev);
112
113#endif /* __DWMAC5_H__ */