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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#ifndef __IXGBE_VF_H__
5#define __IXGBE_VF_H__
6
7#include <linux/pci.h>
8#include <linux/delay.h>
9#include <linux/interrupt.h>
10#include <linux/if_ether.h>
11#include <linux/netdevice.h>
12
13#include "defines.h"
14#include "regs.h"
15#include "mbx.h"
16
17struct ixgbe_hw;
18
19struct ixgbe_mac_operations {
20 s32 (*init_hw)(struct ixgbe_hw *);
21 s32 (*reset_hw)(struct ixgbe_hw *);
22 s32 (*start_hw)(struct ixgbe_hw *);
23 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
24 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
25 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
26 s32 (*stop_adapter)(struct ixgbe_hw *);
27 s32 (*get_bus_info)(struct ixgbe_hw *);
28 s32 (*negotiate_api_version)(struct ixgbe_hw *hw, int api);
29
30 /* Link */
31 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
32 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
33 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
34 bool *);
35
36 /* RAR, Multicast, VLAN */
37 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32);
38 s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
39 s32 (*init_rx_addrs)(struct ixgbe_hw *);
40 s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
41 s32 (*update_xcast_mode)(struct ixgbe_hw *, int);
42 s32 (*get_link_state)(struct ixgbe_hw *hw, bool *link_state);
43 s32 (*enable_mc)(struct ixgbe_hw *);
44 s32 (*disable_mc)(struct ixgbe_hw *);
45 s32 (*clear_vfta)(struct ixgbe_hw *);
46 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
47 s32 (*set_rlpml)(struct ixgbe_hw *, u16);
48};
49
50enum ixgbe_mac_type {
51 ixgbe_mac_unknown = 0,
52 ixgbe_mac_82599_vf,
53 ixgbe_mac_X540_vf,
54 ixgbe_mac_X550_vf,
55 ixgbe_mac_X550EM_x_vf,
56 ixgbe_mac_x550em_a_vf,
57 ixgbe_num_macs
58};
59
60struct ixgbe_mac_info {
61 struct ixgbe_mac_operations ops;
62 u8 addr[6];
63 u8 perm_addr[6];
64
65 enum ixgbe_mac_type type;
66
67 s32 mc_filter_type;
68
69 bool get_link_status;
70 u32 max_tx_queues;
71 u32 max_rx_queues;
72 u32 max_msix_vectors;
73};
74
75struct ixgbe_mbx_operations {
76 s32 (*init_params)(struct ixgbe_hw *hw);
77 void (*release)(struct ixgbe_hw *hw);
78 s32 (*read)(struct ixgbe_hw *, u32 *, u16);
79 s32 (*write)(struct ixgbe_hw *, u32 *, u16);
80 s32 (*check_for_msg)(struct ixgbe_hw *);
81 s32 (*check_for_ack)(struct ixgbe_hw *);
82 s32 (*check_for_rst)(struct ixgbe_hw *);
83};
84
85struct ixgbe_mbx_stats {
86 u32 msgs_tx;
87 u32 msgs_rx;
88
89 u32 acks;
90 u32 reqs;
91 u32 rsts;
92};
93
94struct ixgbe_mbx_info {
95 struct ixgbe_mbx_operations ops;
96 struct ixgbe_mbx_stats stats;
97 u32 timeout;
98 u32 udelay;
99 u32 vf_mailbox;
100 u16 size;
101};
102
103struct ixgbe_hw {
104 void *back;
105
106 u8 __iomem *hw_addr;
107
108 struct ixgbe_mac_info mac;
109 struct ixgbe_mbx_info mbx;
110
111 u16 device_id;
112 u16 subsystem_vendor_id;
113 u16 subsystem_device_id;
114 u16 vendor_id;
115
116 u8 revision_id;
117 bool adapter_stopped;
118
119 int api_version;
120};
121
122struct ixgbevf_hw_stats {
123 u64 base_vfgprc;
124 u64 base_vfgptc;
125 u64 base_vfgorc;
126 u64 base_vfgotc;
127 u64 base_vfmprc;
128
129 u64 last_vfgprc;
130 u64 last_vfgptc;
131 u64 last_vfgorc;
132 u64 last_vfgotc;
133 u64 last_vfmprc;
134
135 u64 vfgprc;
136 u64 vfgptc;
137 u64 vfgorc;
138 u64 vfgotc;
139 u64 vfmprc;
140
141 u64 saved_reset_vfgprc;
142 u64 saved_reset_vfgptc;
143 u64 saved_reset_vfgorc;
144 u64 saved_reset_vfgotc;
145 u64 saved_reset_vfmprc;
146};
147
148struct ixgbevf_info {
149 enum ixgbe_mac_type mac;
150 const struct ixgbe_mac_operations *mac_ops;
151};
152
153#define IXGBE_FAILED_READ_REG 0xffffffffU
154
155#define IXGBE_REMOVED(a) unlikely(!(a))
156
157static inline void ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 value)
158{
159 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
160
161 if (IXGBE_REMOVED(reg_addr))
162 return;
163 writel(value, reg_addr + reg);
164}
165
166#define IXGBE_WRITE_REG(h, r, v) ixgbe_write_reg(h, r, v)
167
168u32 ixgbevf_read_reg(struct ixgbe_hw *hw, u32 reg);
169#define IXGBE_READ_REG(h, r) ixgbevf_read_reg(h, r)
170
171static inline void ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg,
172 u32 offset, u32 value)
173{
174 ixgbe_write_reg(hw, reg + (offset << 2), value);
175}
176
177#define IXGBE_WRITE_REG_ARRAY(h, r, o, v) ixgbe_write_reg_array(h, r, o, v)
178
179static inline u32 ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg,
180 u32 offset)
181{
182 return ixgbevf_read_reg(hw, reg + (offset << 2));
183}
184
185#define IXGBE_READ_REG_ARRAY(h, r, o) ixgbe_read_reg_array(h, r, o)
186
187int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs,
188 unsigned int *default_tc);
189int ixgbevf_get_reta_locked(struct ixgbe_hw *hw, u32 *reta, int num_rx_queues);
190int ixgbevf_get_rss_key_locked(struct ixgbe_hw *hw, u8 *rss_key);
191#endif /* __IXGBE_VF_H__ */