1/* Broadcom NetXtreme-C/E network driver.
  2 *
  3 * Copyright (c) 2021 Broadcom Inc.
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License as published by
  7 * the Free Software Foundation.
  8 */
  9
 10#ifndef BNXT_PTP_H
 11#define BNXT_PTP_H
 12
 13#include <linux/ptp_clock_kernel.h>
 14#include <linux/timecounter.h>
 15
 16#define BNXT_PTP_GRC_WIN	6
 17#define BNXT_PTP_GRC_WIN_BASE	0x6000
 18
 19#define BNXT_MAX_PHC_DRIFT	31000000
 20#define BNXT_CYCLES_SHIFT	23
 21#define BNXT_DEVCLK_FREQ	1000000
 22#define BNXT_LO_TIMER_MASK	0x0000ffffffffUL
 23#define BNXT_HI_TIMER_MASK	0xffff00000000UL
 24
 25#define BNXT_PTP_QTS_TIMEOUT	1000
 26#define BNXT_PTP_QTS_TX_ENABLES	(PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID |	\
 27				 PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT | \
 28				 PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET)
 29
 30struct pps_pin {
 31	u8 event;
 32	u8 usage;
 33	u8 state;
 34};
 35
 36#define TSIO_PIN_VALID(pin) ((pin) >= 0 && (pin) < (BNXT_MAX_TSIO_PINS))
 37
 38#define EVENT_DATA2_PPS_EVENT_TYPE(data2)				\
 39	((data2) & ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE)
 40
 41#define EVENT_DATA2_PPS_PIN_NUM(data2)					\
 42	(((data2) &							\
 43	  ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK) >>\
 44	 ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT)
 45
 46#define BNXT_DATA2_UPPER_MSK						\
 47	ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK
 48
 49#define BNXT_DATA2_UPPER_SFT						\
 50	(32 -								\
 51	 ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT)
 52
 53#define BNXT_DATA1_LOWER_MSK						\
 54	ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK
 55
 56#define BNXT_DATA1_LOWER_SFT						\
 57	  ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT
 58
 59#define EVENT_PPS_TS(data2, data1)					\
 60	(((u64)((data2) & BNXT_DATA2_UPPER_MSK) << BNXT_DATA2_UPPER_SFT) |\
 61	 (((data1) & BNXT_DATA1_LOWER_MSK) >> BNXT_DATA1_LOWER_SFT))
 62
 63#define BNXT_PPS_PIN_DISABLE	0
 64#define BNXT_PPS_PIN_ENABLE	1
 65#define BNXT_PPS_PIN_NONE	0
 66#define BNXT_PPS_PIN_PPS_IN	1
 67#define BNXT_PPS_PIN_PPS_OUT	2
 68#define BNXT_PPS_PIN_SYNC_IN	3
 69#define BNXT_PPS_PIN_SYNC_OUT	4
 70
 71#define BNXT_PPS_EVENT_INTERNAL	1
 72#define BNXT_PPS_EVENT_EXTERNAL	2
 73
 74struct bnxt_pps {
 75	u8 num_pins;
 76#define BNXT_MAX_TSIO_PINS	4
 77	struct pps_pin pins[BNXT_MAX_TSIO_PINS];
 78};
 79
 80struct bnxt_ptp_cfg {
 81	struct ptp_clock_info	ptp_info;
 82	struct ptp_clock	*ptp_clock;
 83	struct cyclecounter	cc;
 84	struct timecounter	tc;
 85	struct bnxt_pps		pps_info;
 86	/* serialize timecounter access */
 87	spinlock_t		ptp_lock;
 88	struct sk_buff		*tx_skb;
 89	u64			current_time;
 90	u64			old_time;
 91	unsigned long		next_period;
 92	unsigned long		next_overflow_check;
 93	u32			cmult;
 94	/* a 23b shift cyclecounter will overflow in ~36 mins.  Check overflow every 18 mins. */
 95	#define BNXT_PHC_OVERFLOW_PERIOD	(18 * 60 * HZ)
 96
 97	u16			tx_seqid;
 98	u16			tx_hdr_off;
 99	struct bnxt		*bp;
100	atomic_t		tx_avail;
101#define BNXT_MAX_TX_TS	1
102	u16			rxctl;
103#define BNXT_PTP_MSG_SYNC			(1 << 0)
104#define BNXT_PTP_MSG_DELAY_REQ			(1 << 1)
105#define BNXT_PTP_MSG_PDELAY_REQ			(1 << 2)
106#define BNXT_PTP_MSG_PDELAY_RESP		(1 << 3)
107#define BNXT_PTP_MSG_FOLLOW_UP			(1 << 8)
108#define BNXT_PTP_MSG_DELAY_RESP			(1 << 9)
109#define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP	(1 << 10)
110#define BNXT_PTP_MSG_ANNOUNCE			(1 << 11)
111#define BNXT_PTP_MSG_SIGNALING			(1 << 12)
112#define BNXT_PTP_MSG_MANAGEMENT			(1 << 13)
113#define BNXT_PTP_MSG_EVENTS		(BNXT_PTP_MSG_SYNC |		\
114					 BNXT_PTP_MSG_DELAY_REQ |	\
115					 BNXT_PTP_MSG_PDELAY_REQ |	\
116					 BNXT_PTP_MSG_PDELAY_RESP)
117	u8			tx_tstamp_en:1;
118	int			rx_filter;
119	u32			tstamp_filters;
120
121	u32			refclk_regs[2];
122	u32			refclk_mapped_regs[2];
123};
124
125#if BITS_PER_LONG == 32
126#define BNXT_READ_TIME64(ptp, dst, src)		\
127do {						\
128	spin_lock_bh(&(ptp)->ptp_lock);		\
129	(dst) = (src);				\
130	spin_unlock_bh(&(ptp)->ptp_lock);	\
131} while (0)
132#else
133#define BNXT_READ_TIME64(ptp, dst, src)		\
134	((dst) = READ_ONCE(src))
135#endif
136
137int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off);
138void bnxt_ptp_update_current_time(struct bnxt *bp);
139void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2);
140int bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp);
141void bnxt_ptp_reapply_pps(struct bnxt *bp);
142int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr);
143int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr);
144int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb);
145int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts);
146void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns);
147int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg);
148int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg);
149void bnxt_ptp_clear(struct bnxt *bp);
150#endif