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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __BCMASP_H
3#define __BCMASP_H
4
5#include <linux/netdevice.h>
6#include <linux/phy.h>
7#include <linux/io-64-nonatomic-hi-lo.h>
8#include <uapi/linux/ethtool.h>
9
10#define ASP_INTR2_OFFSET 0x1000
11#define ASP_INTR2_STATUS 0x0
12#define ASP_INTR2_SET 0x4
13#define ASP_INTR2_CLEAR 0x8
14#define ASP_INTR2_MASK_STATUS 0xc
15#define ASP_INTR2_MASK_SET 0x10
16#define ASP_INTR2_MASK_CLEAR 0x14
17
18#define ASP_INTR2_RX_ECH(intr) BIT(intr)
19#define ASP_INTR2_TX_DESC(intr) BIT((intr) + 14)
20#define ASP_INTR2_UMC0_WAKE BIT(22)
21#define ASP_INTR2_UMC1_WAKE BIT(28)
22#define ASP_INTR2_PHY_EVENT(intr) ((intr) ? BIT(30) | BIT(31) : \
23 BIT(24) | BIT(25))
24
25#define ASP_WAKEUP_INTR2_OFFSET 0x1200
26#define ASP_WAKEUP_INTR2_STATUS 0x0
27#define ASP_WAKEUP_INTR2_SET 0x4
28#define ASP_WAKEUP_INTR2_CLEAR 0x8
29#define ASP_WAKEUP_INTR2_MASK_STATUS 0xc
30#define ASP_WAKEUP_INTR2_MASK_SET 0x10
31#define ASP_WAKEUP_INTR2_MASK_CLEAR 0x14
32#define ASP_WAKEUP_INTR2_MPD_0 BIT(0)
33#define ASP_WAKEUP_INTR2_MPD_1 BIT(1)
34#define ASP_WAKEUP_INTR2_FILT_0 BIT(2)
35#define ASP_WAKEUP_INTR2_FILT_1 BIT(3)
36#define ASP_WAKEUP_INTR2_FW BIT(4)
37
38#define ASP_CTRL2_OFFSET 0x2000
39#define ASP_CTRL2_CORE_CLOCK_SELECT 0x0
40#define ASP_CTRL2_CORE_CLOCK_SELECT_MAIN BIT(0)
41#define ASP_CTRL2_CPU_CLOCK_SELECT 0x4
42#define ASP_CTRL2_CPU_CLOCK_SELECT_MAIN BIT(0)
43
44#define ASP_TX_ANALYTICS_OFFSET 0x4c000
45#define ASP_TX_ANALYTICS_CTRL 0x0
46
47#define ASP_RX_ANALYTICS_OFFSET 0x98000
48#define ASP_RX_ANALYTICS_CTRL 0x0
49
50#define ASP_RX_CTRL_OFFSET 0x9f000
51#define ASP_RX_CTRL_UMAC_0_FRAME_COUNT 0x8
52#define ASP_RX_CTRL_UMAC_1_FRAME_COUNT 0xc
53#define ASP_RX_CTRL_FB_0_FRAME_COUNT 0x14
54#define ASP_RX_CTRL_FB_1_FRAME_COUNT 0x18
55#define ASP_RX_CTRL_FB_8_FRAME_COUNT 0x1c
56/* asp2.1 diverges offsets here */
57/* ASP2.0 */
58#define ASP_RX_CTRL_FB_OUT_FRAME_COUNT 0x20
59#define ASP_RX_CTRL_FB_FILT_OUT_FRAME_COUNT 0x24
60#define ASP_RX_CTRL_FLUSH 0x28
61#define ASP_CTRL_UMAC0_FLUSH_MASK (BIT(0) | BIT(12))
62#define ASP_CTRL_UMAC1_FLUSH_MASK (BIT(1) | BIT(13))
63#define ASP_CTRL_SPB_FLUSH_MASK (BIT(8) | BIT(20))
64#define ASP_RX_CTRL_FB_RX_FIFO_DEPTH 0x30
65/* ASP2.1 */
66#define ASP_RX_CTRL_FB_9_FRAME_COUNT_2_1 0x20
67#define ASP_RX_CTRL_FB_10_FRAME_COUNT_2_1 0x24
68#define ASP_RX_CTRL_FB_OUT_FRAME_COUNT_2_1 0x28
69#define ASP_RX_CTRL_FB_FILT_OUT_FRAME_COUNT_2_1 0x2c
70#define ASP_RX_CTRL_FLUSH_2_1 0x30
71#define ASP_RX_CTRL_FB_RX_FIFO_DEPTH_2_1 0x38
72
73#define ASP_RX_FILTER_OFFSET 0x80000
74#define ASP_RX_FILTER_BLK_CTRL 0x0
75#define ASP_RX_FILTER_OPUT_EN BIT(0)
76#define ASP_RX_FILTER_MDA_EN BIT(1)
77#define ASP_RX_FILTER_LNR_MD BIT(2)
78#define ASP_RX_FILTER_GEN_WK_EN BIT(3)
79#define ASP_RX_FILTER_GEN_WK_CLR BIT(4)
80#define ASP_RX_FILTER_NT_FLT_EN BIT(5)
81#define ASP_RX_FILTER_MDA_CFG(sel) (((sel) * 0x14) + 0x100)
82#define ASP_RX_FILTER_MDA_CFG_EN_SHIFT 8
83#define ASP_RX_FILTER_MDA_CFG_UMC_SEL(sel) ((sel) > 1 ? BIT(17) : \
84 BIT((sel) + 9))
85#define ASP_RX_FILTER_MDA_PAT_H(sel) (((sel) * 0x14) + 0x104)
86#define ASP_RX_FILTER_MDA_PAT_L(sel) (((sel) * 0x14) + 0x108)
87#define ASP_RX_FILTER_MDA_MSK_H(sel) (((sel) * 0x14) + 0x10c)
88#define ASP_RX_FILTER_MDA_MSK_L(sel) (((sel) * 0x14) + 0x110)
89#define ASP_RX_FILTER_MDA_CFG(sel) (((sel) * 0x14) + 0x100)
90#define ASP_RX_FILTER_MDA_PAT_H(sel) (((sel) * 0x14) + 0x104)
91#define ASP_RX_FILTER_MDA_PAT_L(sel) (((sel) * 0x14) + 0x108)
92#define ASP_RX_FILTER_MDA_MSK_H(sel) (((sel) * 0x14) + 0x10c)
93#define ASP_RX_FILTER_MDA_MSK_L(sel) (((sel) * 0x14) + 0x110)
94#define ASP_RX_FILTER_NET_CFG(sel) (((sel) * 0xa04) + 0x400)
95#define ASP_RX_FILTER_NET_CFG_CH(sel) ((sel) << 0)
96#define ASP_RX_FILTER_NET_CFG_EN BIT(9)
97#define ASP_RX_FILTER_NET_CFG_L2_EN BIT(10)
98#define ASP_RX_FILTER_NET_CFG_L3_EN BIT(11)
99#define ASP_RX_FILTER_NET_CFG_L4_EN BIT(12)
100#define ASP_RX_FILTER_NET_CFG_L3_FRM(sel) ((sel) << 13)
101#define ASP_RX_FILTER_NET_CFG_L4_FRM(sel) ((sel) << 15)
102#define ASP_RX_FILTER_NET_CFG_UMC(sel) BIT((sel) + 19)
103#define ASP_RX_FILTER_NET_CFG_DMA_EN BIT(27)
104
105#define ASP_RX_FILTER_NET_OFFSET_MAX 32
106#define ASP_RX_FILTER_NET_PAT(sel, block, off) \
107 (((sel) * 0xa04) + ((block) * 0x200) + (off) + 0x600)
108#define ASP_RX_FILTER_NET_MASK(sel, block, off) \
109 (((sel) * 0xa04) + ((block) * 0x200) + (off) + 0x700)
110
111#define ASP_RX_FILTER_NET_OFFSET(sel) (((sel) * 0xa04) + 0xe00)
112#define ASP_RX_FILTER_NET_OFFSET_L2(val) ((val) << 0)
113#define ASP_RX_FILTER_NET_OFFSET_L3_0(val) ((val) << 8)
114#define ASP_RX_FILTER_NET_OFFSET_L3_1(val) ((val) << 16)
115#define ASP_RX_FILTER_NET_OFFSET_L4(val) ((val) << 24)
116
117enum asp_rx_net_filter_block {
118 ASP_RX_FILTER_NET_L2 = 0,
119 ASP_RX_FILTER_NET_L3_0,
120 ASP_RX_FILTER_NET_L3_1,
121 ASP_RX_FILTER_NET_L4,
122 ASP_RX_FILTER_NET_BLOCK_MAX
123};
124
125#define ASP_EDPKT_OFFSET 0x9c000
126#define ASP_EDPKT_ENABLE 0x4
127#define ASP_EDPKT_ENABLE_EN BIT(0)
128#define ASP_EDPKT_HDR_CFG 0xc
129#define ASP_EDPKT_HDR_SZ_SHIFT 2
130#define ASP_EDPKT_HDR_SZ_32 0
131#define ASP_EDPKT_HDR_SZ_64 1
132#define ASP_EDPKT_HDR_SZ_96 2
133#define ASP_EDPKT_HDR_SZ_128 3
134#define ASP_EDPKT_BURST_BUF_PSCAL_TOUT 0x10
135#define ASP_EDPKT_BURST_BUF_WRITE_TOUT 0x14
136#define ASP_EDPKT_BURST_BUF_READ_TOUT 0x18
137#define ASP_EDPKT_RX_TS_COUNTER 0x38
138#define ASP_EDPKT_ENDI 0x48
139#define ASP_EDPKT_ENDI_DESC_SHIFT 8
140#define ASP_EDPKT_ENDI_NO_BT_SWP 0
141#define ASP_EDPKT_ENDI_BT_SWP_WD 1
142#define ASP_EDPKT_RX_PKT_CNT 0x138
143#define ASP_EDPKT_HDR_EXTR_CNT 0x13c
144#define ASP_EDPKT_HDR_OUT_CNT 0x140
145#define ASP_EDPKT_SPARE_REG 0x174
146#define ASP_EDPKT_SPARE_REG_EPHY_LPI BIT(4)
147#define ASP_EDPKT_SPARE_REG_GPHY_LPI BIT(3)
148
149#define ASP_CTRL_OFFSET 0x101000
150#define ASP_CTRL_ASP_SW_INIT 0x04
151#define ASP_CTRL_ASP_SW_INIT_ACPUSS_CORE BIT(0)
152#define ASP_CTRL_ASP_SW_INIT_ASP_TX BIT(1)
153#define ASP_CTRL_ASP_SW_INIT_AS_RX BIT(2)
154#define ASP_CTRL_ASP_SW_INIT_ASP_RGMII_UMAC0 BIT(3)
155#define ASP_CTRL_ASP_SW_INIT_ASP_RGMII_UMAC1 BIT(4)
156#define ASP_CTRL_ASP_SW_INIT_ASP_XMEMIF BIT(5)
157#define ASP_CTRL_CLOCK_CTRL 0x04
158#define ASP_CTRL_CLOCK_CTRL_ASP_TX_DISABLE BIT(0)
159#define ASP_CTRL_CLOCK_CTRL_ASP_RX_DISABLE BIT(1)
160#define ASP_CTRL_CLOCK_CTRL_ASP_RGMII_SHIFT 2
161#define ASP_CTRL_CLOCK_CTRL_ASP_RGMII_MASK (0x7 << ASP_CTRL_CLOCK_CTRL_ASP_RGMII_SHIFT)
162#define ASP_CTRL_CLOCK_CTRL_ASP_RGMII_DIS(x) BIT(ASP_CTRL_CLOCK_CTRL_ASP_RGMII_SHIFT + (x))
163#define ASP_CTRL_CLOCK_CTRL_ASP_ALL_DISABLE GENMASK(4, 0)
164#define ASP_CTRL_CORE_CLOCK_SELECT 0x08
165#define ASP_CTRL_CORE_CLOCK_SELECT_MAIN BIT(0)
166#define ASP_CTRL_SCRATCH_0 0x0c
167
168struct bcmasp_tx_cb {
169 struct sk_buff *skb;
170 unsigned int bytes_sent;
171 bool last;
172
173 DEFINE_DMA_UNMAP_ADDR(dma_addr);
174 DEFINE_DMA_UNMAP_LEN(dma_len);
175};
176
177struct bcmasp_res {
178 /* Per interface resources */
179 /* Port */
180 void __iomem *umac;
181 void __iomem *umac2fb;
182 void __iomem *rgmii;
183
184 /* TX slowpath/configuration */
185 void __iomem *tx_spb_ctrl;
186 void __iomem *tx_spb_top;
187 void __iomem *tx_epkt_core;
188 void __iomem *tx_pause_ctrl;
189};
190
191#define DESC_ADDR(x) ((x) & GENMASK_ULL(39, 0))
192#define DESC_FLAGS(x) ((x) & GENMASK_ULL(63, 40))
193
194struct bcmasp_desc {
195 u64 buf;
196 #define DESC_CHKSUM BIT_ULL(40)
197 #define DESC_CRC_ERR BIT_ULL(41)
198 #define DESC_RX_SYM_ERR BIT_ULL(42)
199 #define DESC_NO_OCT_ALN BIT_ULL(43)
200 #define DESC_PKT_TRUC BIT_ULL(44)
201 /* 39:0 (TX/RX) bits 0-39 of buf addr
202 * 40 (RX) checksum
203 * 41 (RX) crc_error
204 * 42 (RX) rx_symbol_error
205 * 43 (RX) non_octet_aligned
206 * 44 (RX) pkt_truncated
207 * 45 Reserved
208 * 56:46 (RX) mac_filter_id
209 * 60:57 (RX) rx_port_num (0-unicmac0, 1-unimac1)
210 * 61 Reserved
211 * 63:62 (TX) forward CRC, overwrite CRC
212 */
213 u32 size;
214 u32 flags;
215 #define DESC_INT_EN BIT(0)
216 #define DESC_SOF BIT(1)
217 #define DESC_EOF BIT(2)
218 #define DESC_EPKT_CMD BIT(3)
219 #define DESC_SCRAM_ST BIT(8)
220 #define DESC_SCRAM_END BIT(9)
221 #define DESC_PCPP BIT(10)
222 #define DESC_PPPP BIT(11)
223 /* 0 (TX) tx_int_en
224 * 1 (TX/RX) SOF
225 * 2 (TX/RX) EOF
226 * 3 (TX) epkt_command
227 * 6:4 (TX) PA
228 * 7 (TX) pause at desc end
229 * 8 (TX) scram_start
230 * 9 (TX) scram_end
231 * 10 (TX) PCPP
232 * 11 (TX) PPPP
233 * 14:12 Reserved
234 * 15 (TX) pid ch Valid
235 * 19:16 (TX) data_pkt_type
236 * 32:20 (TX) pid_channel (RX) nw_filter_id
237 */
238};
239
240struct bcmasp_intf;
241
242struct bcmasp_intf_stats64 {
243 /* Rx Stats */
244 u64_stats_t rx_packets;
245 u64_stats_t rx_bytes;
246 u64_stats_t rx_errors;
247 u64_stats_t rx_dropped;
248 u64_stats_t rx_crc_errs;
249 u64_stats_t rx_sym_errs;
250
251 /* Tx Stats*/
252 u64_stats_t tx_packets;
253 u64_stats_t tx_bytes;
254
255 struct u64_stats_sync syncp;
256};
257
258struct bcmasp_mib_counters {
259 u32 edpkt_ts;
260 u32 edpkt_rx_pkt_cnt;
261 u32 edpkt_hdr_ext_cnt;
262 u32 edpkt_hdr_out_cnt;
263 u32 umac_frm_cnt;
264 u32 fb_frm_cnt;
265 u32 fb_rx_fifo_depth;
266 u32 fb_out_frm_cnt;
267 u32 fb_filt_out_frm_cnt;
268 u32 alloc_rx_skb_failed;
269 u32 tx_dma_failed;
270 u32 mc_filters_full_cnt;
271 u32 uc_filters_full_cnt;
272 u32 filters_combine_cnt;
273 u32 promisc_filters_cnt;
274 u32 tx_realloc_offload_failed;
275 u32 tx_timeout_cnt;
276};
277
278struct bcmasp_intf_ops {
279 unsigned long (*rx_desc_read)(struct bcmasp_intf *intf);
280 void (*rx_buffer_write)(struct bcmasp_intf *intf, dma_addr_t addr);
281 void (*rx_desc_write)(struct bcmasp_intf *intf, dma_addr_t addr);
282 unsigned long (*tx_read)(struct bcmasp_intf *intf);
283 void (*tx_write)(struct bcmasp_intf *intf, dma_addr_t addr);
284};
285
286struct bcmasp_priv;
287
288struct bcmasp_intf {
289 struct list_head list;
290 struct net_device *ndev;
291 struct bcmasp_priv *parent;
292
293 /* ASP Ch */
294 int channel;
295 int port;
296 const struct bcmasp_intf_ops *ops;
297
298 /* Used for splitting shared resources */
299 int index;
300
301 struct napi_struct tx_napi;
302 /* TX ring, starts on a new cacheline boundary */
303 void __iomem *tx_spb_dma;
304 int tx_spb_index;
305 int tx_spb_clean_index;
306 struct bcmasp_desc *tx_spb_cpu;
307 dma_addr_t tx_spb_dma_addr;
308 dma_addr_t tx_spb_dma_valid;
309 dma_addr_t tx_spb_dma_read;
310 struct bcmasp_tx_cb *tx_cbs;
311
312 /* RX ring, starts on a new cacheline boundary */
313 void __iomem *rx_edpkt_cfg;
314 void __iomem *rx_edpkt_dma;
315 int rx_edpkt_index;
316 int rx_buf_order;
317 struct bcmasp_desc *rx_edpkt_cpu;
318 dma_addr_t rx_edpkt_dma_addr;
319 dma_addr_t rx_edpkt_dma_read;
320 dma_addr_t rx_edpkt_dma_valid;
321
322 /* RX buffer prefetcher ring*/
323 void *rx_ring_cpu;
324 dma_addr_t rx_ring_dma;
325 dma_addr_t rx_ring_dma_valid;
326 struct napi_struct rx_napi;
327
328 struct bcmasp_res res;
329 unsigned int crc_fwd;
330
331 /* PHY device */
332 struct device_node *phy_dn;
333 struct device_node *ndev_dn;
334 phy_interface_t phy_interface;
335 bool internal_phy;
336 int old_pause;
337 int old_link;
338 int old_duplex;
339
340 u32 msg_enable;
341
342 /* Statistics */
343 struct bcmasp_intf_stats64 stats64;
344 struct bcmasp_mib_counters mib;
345
346 u32 wolopts;
347 u8 sopass[SOPASS_MAX];
348 /* Used if per intf wol irq */
349 int wol_irq;
350 unsigned int wol_irq_enabled:1;
351
352 struct ethtool_keee eee;
353};
354
355#define NUM_NET_FILTERS 32
356struct bcmasp_net_filter {
357 struct ethtool_rx_flow_spec fs;
358
359 bool claimed;
360 bool wake_filter;
361
362 int port;
363 unsigned int hw_index;
364};
365
366#define NUM_MDA_FILTERS 32
367struct bcmasp_mda_filter {
368 /* Current owner of this filter */
369 int port;
370 bool en;
371 u8 addr[ETH_ALEN];
372 u8 mask[ETH_ALEN];
373};
374
375struct bcmasp_hw_info {
376 u32 rx_ctrl_flush;
377 u32 umac2fb;
378 u32 rx_ctrl_fb_out_frame_count;
379 u32 rx_ctrl_fb_filt_out_frame_count;
380 u32 rx_ctrl_fb_rx_fifo_depth;
381};
382
383struct bcmasp_plat_data {
384 void (*init_wol)(struct bcmasp_priv *priv);
385 void (*enable_wol)(struct bcmasp_intf *intf, bool en);
386 void (*destroy_wol)(struct bcmasp_priv *priv);
387 void (*core_clock_select)(struct bcmasp_priv *priv, bool slow);
388 void (*eee_fixup)(struct bcmasp_intf *priv, bool en);
389 struct bcmasp_hw_info *hw_info;
390};
391
392struct bcmasp_priv {
393 struct platform_device *pdev;
394 struct clk *clk;
395
396 int irq;
397 u32 irq_mask;
398
399 /* Used if shared wol irq */
400 struct mutex wol_lock;
401 int wol_irq;
402 unsigned long wol_irq_enabled_mask;
403
404 void (*init_wol)(struct bcmasp_priv *priv);
405 void (*enable_wol)(struct bcmasp_intf *intf, bool en);
406 void (*destroy_wol)(struct bcmasp_priv *priv);
407 void (*core_clock_select)(struct bcmasp_priv *priv, bool slow);
408 void (*eee_fixup)(struct bcmasp_intf *intf, bool en);
409
410 void __iomem *base;
411 struct bcmasp_hw_info *hw_info;
412
413 struct list_head intfs;
414
415 struct bcmasp_mda_filter mda_filters[NUM_MDA_FILTERS];
416
417 /* MAC destination address filters lock */
418 spinlock_t mda_lock;
419
420 /* Protects accesses to ASP_CTRL_CLOCK_CTRL */
421 spinlock_t clk_lock;
422
423 struct bcmasp_net_filter net_filters[NUM_NET_FILTERS];
424
425 /* Network filter lock */
426 struct mutex net_lock;
427};
428
429static inline unsigned long bcmasp_intf_rx_desc_read(struct bcmasp_intf *intf)
430{
431 return intf->ops->rx_desc_read(intf);
432}
433
434static inline void bcmasp_intf_rx_buffer_write(struct bcmasp_intf *intf,
435 dma_addr_t addr)
436{
437 intf->ops->rx_buffer_write(intf, addr);
438}
439
440static inline void bcmasp_intf_rx_desc_write(struct bcmasp_intf *intf,
441 dma_addr_t addr)
442{
443 intf->ops->rx_desc_write(intf, addr);
444}
445
446static inline unsigned long bcmasp_intf_tx_read(struct bcmasp_intf *intf)
447{
448 return intf->ops->tx_read(intf);
449}
450
451static inline void bcmasp_intf_tx_write(struct bcmasp_intf *intf,
452 dma_addr_t addr)
453{
454 intf->ops->tx_write(intf, addr);
455}
456
457#define __BCMASP_IO_MACRO(name, m) \
458static inline u32 name##_rl(struct bcmasp_intf *intf, u32 off) \
459{ \
460 u32 reg = readl_relaxed(intf->m + off); \
461 return reg; \
462} \
463static inline void name##_wl(struct bcmasp_intf *intf, u32 val, u32 off)\
464{ \
465 writel_relaxed(val, intf->m + off); \
466}
467
468#define BCMASP_IO_MACRO(name) __BCMASP_IO_MACRO(name, res.name)
469#define BCMASP_FP_IO_MACRO(name) __BCMASP_IO_MACRO(name, name)
470
471BCMASP_IO_MACRO(umac);
472BCMASP_IO_MACRO(umac2fb);
473BCMASP_IO_MACRO(rgmii);
474BCMASP_FP_IO_MACRO(tx_spb_dma);
475BCMASP_IO_MACRO(tx_spb_ctrl);
476BCMASP_IO_MACRO(tx_spb_top);
477BCMASP_IO_MACRO(tx_epkt_core);
478BCMASP_IO_MACRO(tx_pause_ctrl);
479BCMASP_FP_IO_MACRO(rx_edpkt_dma);
480BCMASP_FP_IO_MACRO(rx_edpkt_cfg);
481
482#define __BCMASP_FP_IO_MACRO_Q(name, m) \
483static inline u64 name##_rq(struct bcmasp_intf *intf, u32 off) \
484{ \
485 u64 reg = readq_relaxed(intf->m + off); \
486 return reg; \
487} \
488static inline void name##_wq(struct bcmasp_intf *intf, u64 val, u32 off)\
489{ \
490 writeq_relaxed(val, intf->m + off); \
491}
492
493#define BCMASP_FP_IO_MACRO_Q(name) __BCMASP_FP_IO_MACRO_Q(name, name)
494
495BCMASP_FP_IO_MACRO_Q(tx_spb_dma);
496BCMASP_FP_IO_MACRO_Q(rx_edpkt_dma);
497BCMASP_FP_IO_MACRO_Q(rx_edpkt_cfg);
498
499#define PKT_OFFLOAD_NOP (0 << 28)
500#define PKT_OFFLOAD_HDR_OP (1 << 28)
501#define PKT_OFFLOAD_HDR_WRBACK BIT(19)
502#define PKT_OFFLOAD_HDR_COUNT(x) ((x) << 16)
503#define PKT_OFFLOAD_HDR_SIZE_1(x) ((x) << 4)
504#define PKT_OFFLOAD_HDR_SIZE_2(x) (x)
505#define PKT_OFFLOAD_HDR2_SIZE_2(x) ((x) << 24)
506#define PKT_OFFLOAD_HDR2_SIZE_3(x) ((x) << 12)
507#define PKT_OFFLOAD_HDR2_SIZE_4(x) (x)
508#define PKT_OFFLOAD_EPKT_OP (2 << 28)
509#define PKT_OFFLOAD_EPKT_WRBACK BIT(23)
510#define PKT_OFFLOAD_EPKT_IP(x) ((x) << 21)
511#define PKT_OFFLOAD_EPKT_TP(x) ((x) << 19)
512#define PKT_OFFLOAD_EPKT_LEN(x) ((x) << 16)
513#define PKT_OFFLOAD_EPKT_CSUM_L3 BIT(15)
514#define PKT_OFFLOAD_EPKT_CSUM_L2 BIT(14)
515#define PKT_OFFLOAD_EPKT_ID(x) ((x) << 12)
516#define PKT_OFFLOAD_EPKT_SEQ(x) ((x) << 10)
517#define PKT_OFFLOAD_EPKT_TS(x) ((x) << 8)
518#define PKT_OFFLOAD_EPKT_BLOC(x) (x)
519#define PKT_OFFLOAD_END_OP (7 << 28)
520
521struct bcmasp_pkt_offload {
522 __be32 nop;
523 __be32 header;
524 __be32 header2;
525 __be32 epkt;
526 __be32 end;
527};
528
529#define BCMASP_CORE_IO_MACRO(name, offset) \
530static inline u32 name##_core_rl(struct bcmasp_priv *priv, \
531 u32 off) \
532{ \
533 u32 reg = readl_relaxed(priv->base + (offset) + off); \
534 return reg; \
535} \
536static inline void name##_core_wl(struct bcmasp_priv *priv, \
537 u32 val, u32 off) \
538{ \
539 writel_relaxed(val, priv->base + (offset) + off); \
540}
541
542BCMASP_CORE_IO_MACRO(intr2, ASP_INTR2_OFFSET);
543BCMASP_CORE_IO_MACRO(wakeup_intr2, ASP_WAKEUP_INTR2_OFFSET);
544BCMASP_CORE_IO_MACRO(tx_analytics, ASP_TX_ANALYTICS_OFFSET);
545BCMASP_CORE_IO_MACRO(rx_analytics, ASP_RX_ANALYTICS_OFFSET);
546BCMASP_CORE_IO_MACRO(rx_ctrl, ASP_RX_CTRL_OFFSET);
547BCMASP_CORE_IO_MACRO(rx_filter, ASP_RX_FILTER_OFFSET);
548BCMASP_CORE_IO_MACRO(rx_edpkt, ASP_EDPKT_OFFSET);
549BCMASP_CORE_IO_MACRO(ctrl, ASP_CTRL_OFFSET);
550BCMASP_CORE_IO_MACRO(ctrl2, ASP_CTRL2_OFFSET);
551
552struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv,
553 struct device_node *ndev_dn, int i);
554
555void bcmasp_interface_destroy(struct bcmasp_intf *intf);
556
557void bcmasp_enable_tx_irq(struct bcmasp_intf *intf, int en);
558
559void bcmasp_enable_rx_irq(struct bcmasp_intf *intf, int en);
560
561void bcmasp_enable_phy_irq(struct bcmasp_intf *intf, int en);
562
563void bcmasp_flush_rx_port(struct bcmasp_intf *intf);
564
565extern const struct ethtool_ops bcmasp_ethtool_ops;
566
567int bcmasp_interface_suspend(struct bcmasp_intf *intf);
568
569int bcmasp_interface_resume(struct bcmasp_intf *intf);
570
571void bcmasp_set_promisc(struct bcmasp_intf *intf, bool en);
572
573void bcmasp_set_allmulti(struct bcmasp_intf *intf, bool en);
574
575void bcmasp_set_broad(struct bcmasp_intf *intf, bool en);
576
577void bcmasp_set_oaddr(struct bcmasp_intf *intf, const unsigned char *addr,
578 bool en);
579
580int bcmasp_set_en_mda_filter(struct bcmasp_intf *intf, unsigned char *addr,
581 unsigned char *mask);
582
583void bcmasp_disable_all_filters(struct bcmasp_intf *intf);
584
585void bcmasp_core_clock_set_intf(struct bcmasp_intf *intf, bool en);
586
587struct bcmasp_net_filter *bcmasp_netfilt_get_init(struct bcmasp_intf *intf,
588 u32 loc, bool wake_filter,
589 bool init);
590
591bool bcmasp_netfilt_check_dup(struct bcmasp_intf *intf,
592 struct ethtool_rx_flow_spec *fs);
593
594void bcmasp_netfilt_release(struct bcmasp_intf *intf,
595 struct bcmasp_net_filter *nfilt);
596
597int bcmasp_netfilt_get_active(struct bcmasp_intf *intf);
598
599int bcmasp_netfilt_get_all_active(struct bcmasp_intf *intf, u32 *rule_locs,
600 u32 *rule_cnt);
601
602void bcmasp_netfilt_suspend(struct bcmasp_intf *intf);
603
604void bcmasp_eee_enable_set(struct bcmasp_intf *intf, bool enable);
605#endif