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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Northstar Plus switch SerDes/SGMII PHY definitions
4 *
5 * Copyright (C) 2018 Florian Fainelli <f.fainelli@gmail.com>
6 */
7
8#include <linux/phy.h>
9#include <linux/types.h>
10
11/* Non-standard page used to access SerDes PHY registers on NorthStar Plus */
12#define B53_SERDES_PAGE 0x16
13#define B53_SERDES_BLKADDR 0x3e
14#define B53_SERDES_LANE 0x3c
15
16#define B53_SERDES_ID0 0x20
17#define SERDES_ID0_MODEL_MASK 0x3f
18#define SERDES_ID0_REV_NUM_SHIFT 11
19#define SERDES_ID0_REV_NUM_MASK 0x7
20#define SERDES_ID0_REV_LETTER_SHIFT 14
21
22#define B53_SERDES_MII_REG(x) (0x20 + (x) * 2)
23#define B53_SERDES_DIGITAL_CONTROL(x) (0x1e + (x) * 2)
24#define B53_SERDES_DIGITAL_STATUS 0x28
25
26/* SERDES_DIGITAL_CONTROL1 */
27#define FIBER_MODE_1000X BIT(0)
28#define TBI_INTERFACE BIT(1)
29#define SIGNAL_DETECT_EN BIT(2)
30#define INVERT_SIGNAL_DETECT BIT(3)
31#define AUTODET_EN BIT(4)
32#define SGMII_MASTER_MODE BIT(5)
33#define DISABLE_DLL_PWRDOWN BIT(6)
34#define CRC_CHECKER_DIS BIT(7)
35#define COMMA_DET_EN BIT(8)
36#define ZERO_COMMA_DET_EN BIT(9)
37#define REMOTE_LOOPBACK BIT(10)
38#define SEL_RX_PKTS_FOR_CNTR BIT(11)
39#define MASTER_MDIO_PHY_SEL BIT(13)
40#define DISABLE_SIGNAL_DETECT_FLT BIT(14)
41
42/* SERDES_DIGITAL_CONTROL2 */
43#define EN_PARALLEL_DET BIT(0)
44#define DIS_FALSE_LINK BIT(1)
45#define FLT_FORCE_LINK BIT(2)
46#define EN_AUTONEG_ERR_TIMER BIT(3)
47#define DIS_REMOTE_FAULT_SENSING BIT(4)
48#define FORCE_XMIT_DATA BIT(5)
49#define AUTONEG_FAST_TIMERS BIT(6)
50#define DIS_CARRIER_EXTEND BIT(7)
51#define DIS_TRRR_GENERATION BIT(8)
52#define BYPASS_PCS_RX BIT(9)
53#define BYPASS_PCS_TX BIT(10)
54#define TEST_CNTR_EN BIT(11)
55#define TX_PACKET_SEQ_TEST BIT(12)
56#define TX_IDLE_JAM_SEQ_TEST BIT(13)
57#define CLR_BER_CNTR BIT(14)
58
59/* SERDES_DIGITAL_CONTROL3 */
60#define TX_FIFO_RST BIT(0)
61#define FIFO_ELAST_TX_RX_SHIFT 1
62#define FIFO_ELAST_TX_RX_5K 0
63#define FIFO_ELAST_TX_RX_10K 1
64#define FIFO_ELAST_TX_RX_13_5K 2
65#define FIFO_ELAST_TX_RX_18_5K 3
66#define BLOCK_TXEN_MODE BIT(9)
67#define JAM_FALSE_CARRIER_MODE BIT(10)
68#define EXT_PHY_CRS_MODE BIT(11)
69#define INVERT_EXT_PHY_CRS BIT(12)
70#define DISABLE_TX_CRS BIT(13)
71
72/* SERDES_DIGITAL_STATUS */
73#define SGMII_MODE BIT(0)
74#define LINK_STATUS BIT(1)
75#define DUPLEX_STATUS BIT(2)
76#define SPEED_STATUS_SHIFT 3
77#define SPEED_STATUS_10 0
78#define SPEED_STATUS_100 1
79#define SPEED_STATUS_1000 2
80#define SPEED_STATUS_2500 3
81#define SPEED_STATUS_MASK SPEED_STATUS_2500
82#define PAUSE_RESOLUTION_TX_SIDE BIT(5)
83#define PAUSE_RESOLUTION_RX_SIDE BIT(6)
84#define LINK_STATUS_CHANGE BIT(7)
85#define EARLY_END_EXT_DET BIT(8)
86#define CARRIER_EXT_ERR_DET BIT(9)
87#define RX_ERR_DET BIT(10)
88#define TX_ERR_DET BIT(11)
89#define CRC_ERR_DET BIT(12)
90#define FALSE_CARRIER_ERR_DET BIT(13)
91#define RXFIFO_ERR_DET BIT(14)
92#define TXFIFO_ERR_DET BIT(15)
93
94/* Block offsets */
95#define SERDES_DIGITAL_BLK 0x8300
96#define SERDES_ID0 0x8310
97#define SERDES_MII_BLK 0xffe0
98#define SERDES_XGXSBLK0_BLOCKADDRESS 0xffd0
99
100struct phylink_link_state;
101
102static inline u8 b53_serdes_map_lane(struct b53_device *dev, int port)
103{
104 if (!dev->ops->serdes_map_lane)
105 return B53_INVALID_LANE;
106
107 return dev->ops->serdes_map_lane(dev, port);
108}
109
110void b53_serdes_link_set(struct b53_device *dev, int port, unsigned int mode,
111 phy_interface_t interface, bool link_up);
112struct phylink_pcs *b53_serdes_phylink_mac_select_pcs(struct b53_device *dev,
113 int port,
114 phy_interface_t interface);
115void b53_serdes_phylink_get_caps(struct b53_device *dev, int port,
116 struct phylink_config *config);
117#if IS_ENABLED(CONFIG_B53_SERDES)
118int b53_serdes_init(struct b53_device *dev, int port);
119#else
120static inline int b53_serdes_init(struct b53_device *dev, int port)
121{
122 return -ENODEV;
123}
124#endif