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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Realtek RTL28xxU DVB USB driver
4 *
5 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
6 * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
7 */
8
9#ifndef RTL28XXU_H
10#define RTL28XXU_H
11
12#include <linux/platform_device.h>
13
14#include "dvb_usb.h"
15
16#include "rtl2830.h"
17#include "rtl2832.h"
18#include "rtl2832_sdr.h"
19#include "mn88472.h"
20#include "mn88473.h"
21#include "cxd2841er.h"
22
23#include "qt1010.h"
24#include "mt2060.h"
25#include "mxl5005s.h"
26#include "fc0012.h"
27#include "fc0013.h"
28#include "e4000.h"
29#include "fc2580.h"
30#include "tua9001.h"
31#include "r820t.h"
32#include "si2168.h"
33#include "si2157.h"
34
35/*
36 * USB commands
37 * (usb_control_msg() index parameter)
38 */
39
40#define DEMOD 0x0000
41#define USB 0x0100
42#define SYS 0x0200
43#define I2C 0x0300
44#define I2C_DA 0x0600
45
46#define CMD_WR_FLAG 0x0010
47#define CMD_DEMOD_RD 0x0000
48#define CMD_DEMOD_WR 0x0010
49#define CMD_USB_RD 0x0100
50#define CMD_USB_WR 0x0110
51#define CMD_SYS_RD 0x0200
52#define CMD_IR_RD 0x0201
53#define CMD_IR_WR 0x0211
54#define CMD_SYS_WR 0x0210
55#define CMD_I2C_RD 0x0300
56#define CMD_I2C_WR 0x0310
57#define CMD_I2C_DA_RD 0x0600
58#define CMD_I2C_DA_WR 0x0610
59
60
61struct rtl28xxu_dev {
62 u8 buf[128];
63 u8 chip_id;
64 u8 tuner;
65 char *tuner_name;
66 u8 page; /* integrated demod active register page */
67 struct i2c_adapter *demod_i2c_adapter;
68 bool rc_active;
69 bool new_i2c_write;
70 struct i2c_client *i2c_client_demod;
71 struct i2c_client *i2c_client_tuner;
72 struct i2c_client *i2c_client_slave_demod;
73 struct platform_device *platform_device_sdr;
74 #define SLAVE_DEMOD_NONE 0
75 #define SLAVE_DEMOD_MN88472 1
76 #define SLAVE_DEMOD_MN88473 2
77 #define SLAVE_DEMOD_SI2168 3
78 #define SLAVE_DEMOD_CXD2837ER 4
79 unsigned int slave_demod:3;
80 union {
81 struct rtl2830_platform_data rtl2830_platform_data;
82 struct rtl2832_platform_data rtl2832_platform_data;
83 };
84};
85
86enum rtl28xxu_chip_id {
87 CHIP_ID_NONE,
88 CHIP_ID_RTL2831U,
89 CHIP_ID_RTL2832U,
90};
91
92/* XXX: Hack. This must be keep sync with rtl2832 demod driver. */
93enum rtl28xxu_tuner {
94 TUNER_NONE,
95
96 TUNER_RTL2830_QT1010 = 0x10,
97 TUNER_RTL2830_MT2060,
98 TUNER_RTL2830_MXL5005S,
99
100 TUNER_RTL2832_MT2266 = 0x20,
101 TUNER_RTL2832_FC2580,
102 TUNER_RTL2832_MT2063,
103 TUNER_RTL2832_MAX3543,
104 TUNER_RTL2832_TUA9001,
105 TUNER_RTL2832_MXL5007T,
106 TUNER_RTL2832_FC0012,
107 TUNER_RTL2832_E4000,
108 TUNER_RTL2832_TDA18272,
109 TUNER_RTL2832_FC0013,
110 TUNER_RTL2832_R820T,
111 TUNER_RTL2832_R828D,
112 TUNER_RTL2832_SI2157,
113};
114
115struct rtl28xxu_req {
116 u16 value;
117 u16 index;
118 u16 size;
119 u8 *data;
120};
121
122struct rtl28xxu_reg_val {
123 u16 reg;
124 u8 val;
125};
126
127struct rtl28xxu_reg_val_mask {
128 u16 reg;
129 u8 val;
130 u8 mask;
131};
132
133/*
134 * memory map
135 *
136 * 0x0000 DEMOD : demodulator
137 * 0x2000 USB : SIE, USB endpoint, debug, DMA
138 * 0x3000 SYS : system
139 * 0xfc00 RC : remote controller (not RTL2831U)
140 */
141
142/*
143 * USB registers
144 */
145/* SIE Control Registers */
146#define USB_SYSCTL 0x2000 /* USB system control */
147#define USB_SYSCTL_0 0x2000 /* USB system control */
148#define USB_SYSCTL_1 0x2001 /* USB system control */
149#define USB_SYSCTL_2 0x2002 /* USB system control */
150#define USB_SYSCTL_3 0x2003 /* USB system control */
151#define USB_IRQSTAT 0x2008 /* SIE interrupt status */
152#define USB_IRQEN 0x200C /* SIE interrupt enable */
153#define USB_CTRL 0x2010 /* USB control */
154#define USB_STAT 0x2014 /* USB status */
155#define USB_DEVADDR 0x2018 /* USB device address */
156#define USB_TEST 0x201C /* USB test mode */
157#define USB_FRAME_NUMBER 0x2020 /* frame number */
158#define USB_FIFO_ADDR 0x2028 /* address of SIE FIFO RAM */
159#define USB_FIFO_CMD 0x202A /* SIE FIFO RAM access command */
160#define USB_FIFO_DATA 0x2030 /* SIE FIFO RAM data */
161/* Endpoint Registers */
162#define EP0_SETUPA 0x20F8 /* EP 0 setup packet lower byte */
163#define EP0_SETUPB 0x20FC /* EP 0 setup packet higher byte */
164#define USB_EP0_CFG 0x2104 /* EP 0 configure */
165#define USB_EP0_CTL 0x2108 /* EP 0 control */
166#define USB_EP0_STAT 0x210C /* EP 0 status */
167#define USB_EP0_IRQSTAT 0x2110 /* EP 0 interrupt status */
168#define USB_EP0_IRQEN 0x2114 /* EP 0 interrupt enable */
169#define USB_EP0_MAXPKT 0x2118 /* EP 0 max packet size */
170#define USB_EP0_BC 0x2120 /* EP 0 FIFO byte counter */
171#define USB_EPA_CFG 0x2144 /* EP A configure */
172#define USB_EPA_CFG_0 0x2144 /* EP A configure */
173#define USB_EPA_CFG_1 0x2145 /* EP A configure */
174#define USB_EPA_CFG_2 0x2146 /* EP A configure */
175#define USB_EPA_CFG_3 0x2147 /* EP A configure */
176#define USB_EPA_CTL 0x2148 /* EP A control */
177#define USB_EPA_CTL_0 0x2148 /* EP A control */
178#define USB_EPA_CTL_1 0x2149 /* EP A control */
179#define USB_EPA_CTL_2 0x214A /* EP A control */
180#define USB_EPA_CTL_3 0x214B /* EP A control */
181#define USB_EPA_STAT 0x214C /* EP A status */
182#define USB_EPA_IRQSTAT 0x2150 /* EP A interrupt status */
183#define USB_EPA_IRQEN 0x2154 /* EP A interrupt enable */
184#define USB_EPA_MAXPKT 0x2158 /* EP A max packet size */
185#define USB_EPA_MAXPKT_0 0x2158 /* EP A max packet size */
186#define USB_EPA_MAXPKT_1 0x2159 /* EP A max packet size */
187#define USB_EPA_MAXPKT_2 0x215A /* EP A max packet size */
188#define USB_EPA_MAXPKT_3 0x215B /* EP A max packet size */
189#define USB_EPA_FIFO_CFG 0x2160 /* EP A FIFO configure */
190#define USB_EPA_FIFO_CFG_0 0x2160 /* EP A FIFO configure */
191#define USB_EPA_FIFO_CFG_1 0x2161 /* EP A FIFO configure */
192#define USB_EPA_FIFO_CFG_2 0x2162 /* EP A FIFO configure */
193#define USB_EPA_FIFO_CFG_3 0x2163 /* EP A FIFO configure */
194/* Debug Registers */
195#define USB_PHYTSTDIS 0x2F04 /* PHY test disable */
196#define USB_TOUT_VAL 0x2F08 /* USB time-out time */
197#define USB_VDRCTRL 0x2F10 /* UTMI vendor signal control */
198#define USB_VSTAIN 0x2F14 /* UTMI vendor signal status in */
199#define USB_VLOADM 0x2F18 /* UTMI load vendor signal status in */
200#define USB_VSTAOUT 0x2F1C /* UTMI vendor signal status out */
201#define USB_UTMI_TST 0x2F80 /* UTMI test */
202#define USB_UTMI_STATUS 0x2F84 /* UTMI status */
203#define USB_TSTCTL 0x2F88 /* test control */
204#define USB_TSTCTL2 0x2F8C /* test control 2 */
205#define USB_PID_FORCE 0x2F90 /* force PID */
206#define USB_PKTERR_CNT 0x2F94 /* packet error counter */
207#define USB_RXERR_CNT 0x2F98 /* RX error counter */
208#define USB_MEM_BIST 0x2F9C /* MEM BIST test */
209#define USB_SLBBIST 0x2FA0 /* self-loop-back BIST */
210#define USB_CNTTEST 0x2FA4 /* counter test */
211#define USB_PHYTST 0x2FC0 /* USB PHY test */
212#define USB_DBGIDX 0x2FF0 /* select individual block debug signal */
213#define USB_DBGMUX 0x2FF4 /* debug signal module mux */
214
215/*
216 * SYS registers
217 */
218/* demod control registers */
219#define SYS_SYS0 0x3000 /* include DEMOD_CTL, GPO, GPI, GPOE */
220#define SYS_DEMOD_CTL 0x3000 /* control register for DVB-T demodulator */
221/* GPIO registers */
222#define SYS_GPIO_OUT_VAL 0x3001 /* output value of GPIO */
223#define SYS_GPIO_IN_VAL 0x3002 /* input value of GPIO */
224#define SYS_GPIO_OUT_EN 0x3003 /* output enable of GPIO */
225#define SYS_SYS1 0x3004 /* include GPD, SYSINTE, SYSINTS, GP_CFG0 */
226#define SYS_GPIO_DIR 0x3004 /* direction control for GPIO */
227#define SYS_SYSINTE 0x3005 /* system interrupt enable */
228#define SYS_SYSINTS 0x3006 /* system interrupt status */
229#define SYS_GPIO_CFG0 0x3007 /* PAD configuration for GPIO0-GPIO3 */
230#define SYS_SYS2 0x3008 /* include GP_CFG1 and 3 reserved bytes */
231#define SYS_GPIO_CFG1 0x3008 /* PAD configuration for GPIO4 */
232#define SYS_DEMOD_CTL1 0x300B
233
234/* IrDA registers */
235#define SYS_IRRC_PSR 0x3020 /* IR protocol selection */
236#define SYS_IRRC_PER 0x3024 /* IR protocol extension */
237#define SYS_IRRC_SF 0x3028 /* IR sampling frequency */
238#define SYS_IRRC_DPIR 0x302C /* IR data package interval */
239#define SYS_IRRC_CR 0x3030 /* IR control */
240#define SYS_IRRC_RP 0x3034 /* IR read port */
241#define SYS_IRRC_SR 0x3038 /* IR status */
242/* I2C master registers */
243#define SYS_I2CCR 0x3040 /* I2C clock */
244#define SYS_I2CMCR 0x3044 /* I2C master control */
245#define SYS_I2CMSTR 0x3048 /* I2C master SCL timing */
246#define SYS_I2CMSR 0x304C /* I2C master status */
247#define SYS_I2CMFR 0x3050 /* I2C master FIFO */
248
249/*
250 * IR registers
251 */
252#define IR_RX_BUF 0xFC00
253#define IR_RX_IE 0xFD00
254#define IR_RX_IF 0xFD01
255#define IR_RX_CTRL 0xFD02
256#define IR_RX_CFG 0xFD03
257#define IR_MAX_DURATION0 0xFD04
258#define IR_MAX_DURATION1 0xFD05
259#define IR_IDLE_LEN0 0xFD06
260#define IR_IDLE_LEN1 0xFD07
261#define IR_GLITCH_LEN 0xFD08
262#define IR_RX_BUF_CTRL 0xFD09
263#define IR_RX_BUF_DATA 0xFD0A
264#define IR_RX_BC 0xFD0B
265#define IR_RX_CLK 0xFD0C
266#define IR_RX_C_COUNT_L 0xFD0D
267#define IR_RX_C_COUNT_H 0xFD0E
268#define IR_SUSPEND_CTRL 0xFD10
269#define IR_ERR_TOL_CTRL 0xFD11
270#define IR_UNIT_LEN 0xFD12
271#define IR_ERR_TOL_LEN 0xFD13
272#define IR_MAX_H_TOL_LEN 0xFD14
273#define IR_MAX_L_TOL_LEN 0xFD15
274#define IR_MASK_CTRL 0xFD16
275#define IR_MASK_DATA 0xFD17
276#define IR_RES_MASK_ADDR 0xFD18
277#define IR_RES_MASK_T_LEN 0xFD19
278
279#endif