Loading...
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Register definition file for s3c24xx/s3c64xx SoC CAMIF driver
4 *
5 * Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
6 * Copyright (C) 2012 Tomasz Figa <tomasz.figa@gmail.com>
7*/
8
9#ifndef CAMIF_REGS_H_
10#define CAMIF_REGS_H_
11
12#include <linux/bitops.h>
13
14#include "camif-core.h"
15#include <media/drv-intf/s3c_camif.h>
16
17/*
18 * The id argument indicates the processing path:
19 * id = 0 - codec (FIMC C), 1 - preview (FIMC P).
20 */
21
22/* Camera input format */
23#define S3C_CAMIF_REG_CISRCFMT 0x00
24#define CISRCFMT_ITU601_8BIT BIT(31)
25#define CISRCFMT_ITU656_8BIT (0 << 31)
26#define CISRCFMT_ORDER422_YCBYCR (0 << 14)
27#define CISRCFMT_ORDER422_YCRYCB (1 << 14)
28#define CISRCFMT_ORDER422_CBYCRY (2 << 14)
29#define CISRCFMT_ORDER422_CRYCBY (3 << 14)
30#define CISRCFMT_ORDER422_MASK (3 << 14)
31#define CISRCFMT_SIZE_CAM_MASK (0x1fff << 16 | 0x1fff)
32
33/* Window offset */
34#define S3C_CAMIF_REG_CIWDOFST 0x04
35#define CIWDOFST_WINOFSEN BIT(31)
36#define CIWDOFST_CLROVCOFIY BIT(30)
37#define CIWDOFST_CLROVRLB_PR BIT(28)
38/* #define CIWDOFST_CLROVPRFIY BIT(27) */
39#define CIWDOFST_CLROVCOFICB BIT(15)
40#define CIWDOFST_CLROVCOFICR BIT(14)
41#define CIWDOFST_CLROVPRFICB BIT(13)
42#define CIWDOFST_CLROVPRFICR BIT(12)
43#define CIWDOFST_OFST_MASK (0x7ff << 16 | 0x7ff)
44
45/* Window offset 2 */
46#define S3C_CAMIF_REG_CIWDOFST2 0x14
47#define CIWDOFST2_OFST2_MASK (0xfff << 16 | 0xfff)
48
49/* Global control */
50#define S3C_CAMIF_REG_CIGCTRL 0x08
51#define CIGCTRL_SWRST BIT(31)
52#define CIGCTRL_CAMRST BIT(30)
53#define CIGCTRL_TESTPATTERN_NORMAL (0 << 27)
54#define CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27)
55#define CIGCTRL_TESTPATTERN_HOR_INC (2 << 27)
56#define CIGCTRL_TESTPATTERN_VER_INC (3 << 27)
57#define CIGCTRL_TESTPATTERN_MASK (3 << 27)
58#define CIGCTRL_INVPOLPCLK BIT(26)
59#define CIGCTRL_INVPOLVSYNC BIT(25)
60#define CIGCTRL_INVPOLHREF BIT(24)
61#define CIGCTRL_IRQ_OVFEN BIT(22)
62#define CIGCTRL_HREF_MASK BIT(21)
63#define CIGCTRL_IRQ_LEVEL BIT(20)
64/* IRQ_CLR_C, IRQ_CLR_P */
65#define CIGCTRL_IRQ_CLR(id) BIT(19 - (id))
66#define CIGCTRL_FIELDMODE BIT(2)
67#define CIGCTRL_INVPOLFIELD BIT(1)
68#define CIGCTRL_CAM_INTERLACE BIT(0)
69
70/* Y DMA output frame start address. n = 0..3. */
71#define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4)
72/* Cb plane output DMA start address. n = 0..3. Only codec path. */
73#define S3C_CAMIF_REG_CICBSA(id, n) (0x28 + (id) * 0x54 + (n) * 4)
74/* Cr plane output DMA start address. n = 0..3. Only codec path. */
75#define S3C_CAMIF_REG_CICRSA(id, n) (0x38 + (id) * 0x54 + (n) * 4)
76
77/* CICOTRGFMT, CIPRTRGFMT - Target format */
78#define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs)))
79#define CITRGFMT_IN422 BIT(31) /* only for s3c24xx */
80#define CITRGFMT_OUT422 BIT(30) /* only for s3c24xx */
81#define CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) /* only for s3c6410 */
82#define CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) /* only for s3c6410 */
83#define CITRGFMT_OUTFORMAT_YCBCR422I (2 << 29) /* only for s3c6410 */
84#define CITRGFMT_OUTFORMAT_RGB (3 << 29) /* only for s3c6410 */
85#define CITRGFMT_OUTFORMAT_MASK (3 << 29) /* only for s3c6410 */
86#define CITRGFMT_TARGETHSIZE(x) ((x) << 16)
87#define CITRGFMT_FLIP_NORMAL (0 << 14)
88#define CITRGFMT_FLIP_X_MIRROR (1 << 14)
89#define CITRGFMT_FLIP_Y_MIRROR (2 << 14)
90#define CITRGFMT_FLIP_180 (3 << 14)
91#define CITRGFMT_FLIP_MASK (3 << 14)
92/* Preview path only */
93#define CITRGFMT_ROT90_PR BIT(13)
94#define CITRGFMT_TARGETVSIZE(x) ((x) << 0)
95#define CITRGFMT_TARGETSIZE_MASK ((0x1fff << 16) | 0x1fff)
96
97/* CICOCTRL, CIPRCTRL. Output DMA control. */
98#define S3C_CAMIF_REG_CICTRL(id, _offs) (0x4c + (id) * (0x34 + (_offs)))
99#define CICTRL_BURST_MASK (0xfffff << 4)
100/* xBURSTn - 5-bits width */
101#define CICTRL_YBURST1(x) ((x) << 19)
102#define CICTRL_YBURST2(x) ((x) << 14)
103#define CICTRL_RGBBURST1(x) ((x) << 19)
104#define CICTRL_RGBBURST2(x) ((x) << 14)
105#define CICTRL_CBURST1(x) ((x) << 9)
106#define CICTRL_CBURST2(x) ((x) << 4)
107#define CICTRL_LASTIRQ_ENABLE BIT(2)
108#define CICTRL_ORDER422_MASK (3 << 0)
109
110/* CICOSCPRERATIO, CIPRSCPRERATIO. Pre-scaler control 1. */
111#define S3C_CAMIF_REG_CISCPRERATIO(id, _offs) (0x50 + (id) * (0x34 + (_offs)))
112
113/* CICOSCPREDST, CIPRSCPREDST. Pre-scaler control 2. */
114#define S3C_CAMIF_REG_CISCPREDST(id, _offs) (0x54 + (id) * (0x34 + (_offs)))
115
116/* CICOSCCTRL, CIPRSCCTRL. Main scaler control. */
117#define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs)))
118#define CISCCTRL_SCALERBYPASS BIT(31)
119/* s3c244x preview path only, s3c64xx both */
120#define CIPRSCCTRL_SAMPLE BIT(31)
121/* 0 - 16-bit RGB, 1 - 24-bit RGB */
122#define CIPRSCCTRL_RGB_FORMAT_24BIT BIT(30) /* only for s3c244x */
123#define CIPRSCCTRL_SCALEUP_H BIT(29) /* only for s3c244x */
124#define CIPRSCCTRL_SCALEUP_V BIT(28) /* only for s3c244x */
125/* s3c64xx */
126#define CISCCTRL_SCALEUP_H BIT(30)
127#define CISCCTRL_SCALEUP_V BIT(29)
128#define CISCCTRL_SCALEUP_MASK (0x3 << 29)
129#define CISCCTRL_CSCR2Y_WIDE BIT(28)
130#define CISCCTRL_CSCY2R_WIDE BIT(27)
131#define CISCCTRL_LCDPATHEN_FIFO BIT(26)
132#define CISCCTRL_INTERLACE BIT(25)
133#define CISCCTRL_SCALERSTART BIT(15)
134#define CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
135#define CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
136#define CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
137#define CISCCTRL_INRGB_FMT_MASK (3 << 13)
138#define CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
139#define CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
140#define CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
141#define CISCCTRL_OUTRGB_FMT_MASK (3 << 11)
142#define CISCCTRL_EXTRGB_EXTENSION BIT(10)
143#define CISCCTRL_ONE2ONE BIT(9)
144#define CISCCTRL_MAIN_RATIO_MASK (0x1ff << 16 | 0x1ff)
145
146/* CICOTAREA, CIPRTAREA. Target area for DMA (Hsize x Vsize). */
147#define S3C_CAMIF_REG_CITAREA(id, _offs) (0x5c + (id) * (0x34 + (_offs)))
148#define CITAREA_MASK 0xfffffff
149
150/* Codec (id = 0) or preview (id = 1) path status. */
151#define S3C_CAMIF_REG_CISTATUS(id, _offs) (0x64 + (id) * (0x34 + (_offs)))
152#define CISTATUS_OVFIY_STATUS BIT(31)
153#define CISTATUS_OVFICB_STATUS BIT(30)
154#define CISTATUS_OVFICR_STATUS BIT(29)
155#define CISTATUS_OVF_MASK (0x7 << 29)
156#define CIPRSTATUS_OVF_MASK (0x3 << 30)
157#define CISTATUS_VSYNC_STATUS BIT(28)
158#define CISTATUS_FRAMECNT_MASK (3 << 26)
159#define CISTATUS_FRAMECNT(__reg) (((__reg) >> 26) & 0x3)
160#define CISTATUS_WINOFSTEN_STATUS BIT(25)
161#define CISTATUS_IMGCPTEN_STATUS BIT(22)
162#define CISTATUS_IMGCPTENSC_STATUS BIT(21)
163#define CISTATUS_VSYNC_A_STATUS BIT(20)
164#define CISTATUS_FRAMEEND_STATUS BIT(19) /* 17 on s3c64xx */
165
166/* Image capture enable */
167#define S3C_CAMIF_REG_CIIMGCPT(_offs) (0xa0 + (_offs))
168#define CIIMGCPT_IMGCPTEN BIT(31)
169#define CIIMGCPT_IMGCPTEN_SC(id) BIT(30 - (id))
170/* Frame control: 1 - one-shot, 0 - free run */
171#define CIIMGCPT_CPT_FREN_ENABLE(id) BIT(25 - (id))
172#define CIIMGCPT_CPT_FRMOD_ENABLE (0 << 18)
173#define CIIMGCPT_CPT_FRMOD_CNT BIT(18)
174
175/* Capture sequence */
176#define S3C_CAMIF_REG_CICPTSEQ 0xc4
177
178/* Image effects */
179#define S3C_CAMIF_REG_CIIMGEFF(_offs) (0xb0 + (_offs))
180#define CIIMGEFF_IE_ENABLE(id) BIT(30 + (id))
181#define CIIMGEFF_IE_ENABLE_MASK (3 << 30)
182/* Image effect: 1 - after scaler, 0 - before scaler */
183#define CIIMGEFF_IE_AFTER_SC BIT(29)
184#define CIIMGEFF_FIN_MASK (7 << 26)
185#define CIIMGEFF_FIN_BYPASS (0 << 26)
186#define CIIMGEFF_FIN_ARBITRARY (1 << 26)
187#define CIIMGEFF_FIN_NEGATIVE (2 << 26)
188#define CIIMGEFF_FIN_ARTFREEZE (3 << 26)
189#define CIIMGEFF_FIN_EMBOSSING (4 << 26)
190#define CIIMGEFF_FIN_SILHOUETTE (5 << 26)
191#define CIIMGEFF_PAT_CBCR_MASK ((0xff << 13) | 0xff)
192#define CIIMGEFF_PAT_CB(x) ((x) << 13)
193#define CIIMGEFF_PAT_CR(x) (x)
194
195/* MSCOY0SA, MSPRY0SA. Y/Cb/Cr frame start address for input DMA. */
196#define S3C_CAMIF_REG_MSY0SA(id) (0xd4 + ((id) * 0x2c))
197#define S3C_CAMIF_REG_MSCB0SA(id) (0xd8 + ((id) * 0x2c))
198#define S3C_CAMIF_REG_MSCR0SA(id) (0xdc + ((id) * 0x2c))
199
200/* MSCOY0END, MSCOY0END. Y/Cb/Cr frame end address for input DMA. */
201#define S3C_CAMIF_REG_MSY0END(id) (0xe0 + ((id) * 0x2c))
202#define S3C_CAMIF_REG_MSCB0END(id) (0xe4 + ((id) * 0x2c))
203#define S3C_CAMIF_REG_MSCR0END(id) (0xe8 + ((id) * 0x2c))
204
205/* MSPRYOFF, MSPRYOFF. Y/Cb/Cr offset. n: 0 - codec, 1 - preview. */
206#define S3C_CAMIF_REG_MSYOFF(id) (0x118 + ((id) * 0x2c))
207#define S3C_CAMIF_REG_MSCBOFF(id) (0x11c + ((id) * 0x2c))
208#define S3C_CAMIF_REG_MSCROFF(id) (0x120 + ((id) * 0x2c))
209
210/* Real input DMA data size. n = 0 - codec, 1 - preview. */
211#define S3C_CAMIF_REG_MSWIDTH(id) (0xf8 + (id) * 0x2c)
212#define AUTOLOAD_ENABLE BIT(31)
213#define ADDR_CH_DIS BIT(30)
214#define MSHEIGHT(x) (((x) & 0x3ff) << 16)
215#define MSWIDTH(x) ((x) & 0x3ff)
216
217/* Input DMA control. n = 0 - codec, 1 - preview */
218#define S3C_CAMIF_REG_MSCTRL(id) (0xfc + (id) * 0x2c)
219#define MSCTRL_ORDER422_M_YCBYCR (0 << 4)
220#define MSCTRL_ORDER422_M_YCRYCB (1 << 4)
221#define MSCTRL_ORDER422_M_CBYCRY (2 << 4)
222#define MSCTRL_ORDER422_M_CRYCBY (3 << 4)
223/* 0 - camera, 1 - DMA */
224#define MSCTRL_SEL_DMA_CAM BIT(3)
225#define MSCTRL_INFORMAT_M_YCBCR420 (0 << 1)
226#define MSCTRL_INFORMAT_M_YCBCR422 (1 << 1)
227#define MSCTRL_INFORMAT_M_YCBCR422I (2 << 1)
228#define MSCTRL_INFORMAT_M_RGB (3 << 1)
229#define MSCTRL_ENVID_M BIT(0)
230
231/* CICOSCOSY, CIPRSCOSY. Scan line Y/Cb/Cr offset. */
232#define S3C_CAMIF_REG_CISSY(id) (0x12c + (id) * 0x0c)
233#define S3C_CAMIF_REG_CISSCB(id) (0x130 + (id) * 0x0c)
234#define S3C_CAMIF_REG_CISSCR(id) (0x134 + (id) * 0x0c)
235#define S3C_CISS_OFFS_INITIAL(x) ((x) << 16)
236#define S3C_CISS_OFFS_LINE(x) ((x) << 0)
237
238/* ------------------------------------------------------------------ */
239
240void camif_hw_reset(struct camif_dev *camif);
241void camif_hw_clear_pending_irq(struct camif_vp *vp);
242void camif_hw_clear_fifo_overflow(struct camif_vp *vp);
243void camif_hw_set_lastirq(struct camif_vp *vp, int enable);
244void camif_hw_set_input_path(struct camif_vp *vp);
245void camif_hw_enable_scaler(struct camif_vp *vp, bool on);
246void camif_hw_enable_capture(struct camif_vp *vp);
247void camif_hw_disable_capture(struct camif_vp *vp);
248void camif_hw_set_camera_bus(struct camif_dev *camif);
249void camif_hw_set_source_format(struct camif_dev *camif);
250void camif_hw_set_camera_crop(struct camif_dev *camif);
251void camif_hw_set_scaler(struct camif_vp *vp);
252void camif_hw_set_flip(struct camif_vp *vp);
253void camif_hw_set_output_dma(struct camif_vp *vp);
254void camif_hw_set_target_format(struct camif_vp *vp);
255void camif_hw_set_test_pattern(struct camif_dev *camif, unsigned int pattern);
256void camif_hw_set_effect(struct camif_dev *camif, unsigned int effect,
257 unsigned int cr, unsigned int cb);
258void camif_hw_set_output_addr(struct camif_vp *vp, struct camif_addr *paddr,
259 int index);
260void camif_hw_dump_regs(struct camif_dev *camif, const char *label);
261
262static inline u32 camif_hw_get_status(struct camif_vp *vp)
263{
264 return readl(vp->camif->io_base + S3C_CAMIF_REG_CISTATUS(vp->id,
265 vp->offset));
266}
267
268#endif /* CAMIF_REGS_H_ */