1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * camss.h
  4 *
  5 * Qualcomm MSM Camera Subsystem - Core
  6 *
  7 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  8 * Copyright (C) 2015-2018 Linaro Ltd.
  9 */
 10#ifndef QC_MSM_CAMSS_H
 11#define QC_MSM_CAMSS_H
 12
 13#include <linux/device.h>
 14#include <linux/types.h>
 15#include <media/v4l2-async.h>
 16#include <media/v4l2-device.h>
 17#include <media/v4l2-subdev.h>
 18#include <media/media-device.h>
 19#include <media/media-entity.h>
 20
 21#include "camss-csid.h"
 22#include "camss-csiphy.h"
 23#include "camss-ispif.h"
 24#include "camss-vfe.h"
 25
 26#define to_camss(ptr_module)	\
 27	container_of(ptr_module, struct camss, ptr_module)
 28
 29#define to_device(ptr_module)	\
 30	(to_camss(ptr_module)->dev)
 31
 32#define module_pointer(ptr_module, index)	\
 33	((const struct ptr_module##_device (*)[]) &(ptr_module[-(index)]))
 34
 35#define to_camss_index(ptr_module, index)	\
 36	container_of(module_pointer(ptr_module, index),	\
 37		     struct camss, ptr_module)
 38
 39#define to_device_index(ptr_module, index)	\
 40	(to_camss_index(ptr_module, index)->dev)
 41
 42#define CAMSS_RES_MAX 17
 43
 44struct camss_subdev_resources {
 45	char *regulators[CAMSS_RES_MAX];
 46	char *clock[CAMSS_RES_MAX];
 47	char *clock_for_reset[CAMSS_RES_MAX];
 48	u32 clock_rate[CAMSS_RES_MAX][CAMSS_RES_MAX];
 49	char *reg[CAMSS_RES_MAX];
 50	char *interrupt[CAMSS_RES_MAX];
 51	char *pd_name;
 52	u8 line_num;
 53	bool has_pd;
 54	bool is_lite;
 55	const void *ops;
 56};
 57
 58struct icc_bw_tbl {
 59	u32 avg;
 60	u32 peak;
 61};
 62
 63struct resources_icc {
 64	char *name;
 65	struct icc_bw_tbl icc_bw_tbl;
 66};
 67
 68enum pm_domain {
 69	PM_DOMAIN_VFE0 = 0,
 70	PM_DOMAIN_VFE1 = 1,
 71	PM_DOMAIN_VFELITE = 2,		/* VFELITE / TOP GDSC */
 72};
 73
 74enum camss_version {
 75	CAMSS_8x16,
 76	CAMSS_8x96,
 77	CAMSS_660,
 78	CAMSS_845,
 79	CAMSS_8250,
 80};
 81
 82enum icc_count {
 83	ICC_DEFAULT_COUNT = 0,
 84	ICC_SM8250_COUNT = 4,
 85};
 86
 87struct camss_resources {
 88	enum camss_version version;
 89	const char *pd_name;
 90	const struct camss_subdev_resources *csiphy_res;
 91	const struct camss_subdev_resources *csid_res;
 92	const struct camss_subdev_resources *ispif_res;
 93	const struct camss_subdev_resources *vfe_res;
 94	const struct resources_icc *icc_res;
 95	const unsigned int icc_path_num;
 96	const unsigned int csiphy_num;
 97	const unsigned int csid_num;
 98	const unsigned int vfe_num;
 99};
100
101struct camss {
102	struct v4l2_device v4l2_dev;
103	struct v4l2_async_notifier notifier;
104	struct media_device media_dev;
105	struct device *dev;
106	struct csiphy_device *csiphy;
107	struct csid_device *csid;
108	struct ispif_device *ispif;
109	struct vfe_device *vfe;
110	atomic_t ref_count;
111	int genpd_num;
112	struct device *genpd;
113	struct device_link *genpd_link;
114	struct icc_path *icc_path[ICC_SM8250_COUNT];
115	const struct camss_resources *res;
116};
117
118struct camss_camera_interface {
119	u8 csiphy_id;
120	struct csiphy_csi2_cfg csi2;
121};
122
123struct camss_async_subdev {
124	struct v4l2_async_connection asd; /* must be first */
125	struct camss_camera_interface interface;
126};
127
128struct camss_clock {
129	struct clk *clk;
130	const char *name;
131	u32 *freq;
132	u32 nfreqs;
133};
134
135void camss_add_clock_margin(u64 *rate);
136int camss_enable_clocks(int nclocks, struct camss_clock *clock,
137			struct device *dev);
138void camss_disable_clocks(int nclocks, struct camss_clock *clock);
139struct media_entity *camss_find_sensor(struct media_entity *entity);
140s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp,
141			unsigned int lanes);
142int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock);
143int camss_pm_domain_on(struct camss *camss, int id);
144void camss_pm_domain_off(struct camss *camss, int id);
145void camss_delete(struct camss *camss);
146
147#endif /* QC_MSM_CAMSS_H */