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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 | // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2016 MediaTek Inc. * Author: Jungchang Tsao <jungchang.tsao@mediatek.com> * PC Chen <pc.chen@mediatek.com> */ #include <linux/slab.h> #include "../vdec_drv_if.h" #include "../mtk_vcodec_dec.h" #include "../../common/mtk_vcodec_intr.h" #include "../vdec_vpu_if.h" #include "../vdec_drv_base.h" /* Decoding picture buffer size (3 reference frames plus current frame) */ #define VP8_DPB_SIZE 4 /* HW working buffer size (bytes) */ #define VP8_WORKING_BUF_SZ (45 * 4096) /* HW control register address */ #define VP8_SEGID_DRAM_ADDR 0x3c #define VP8_HW_VLD_ADDR 0x93C #define VP8_HW_VLD_VALUE 0x940 #define VP8_BSASET 0x100 #define VP8_BSDSET 0x104 #define VP8_RW_CKEN_SET 0x0 #define VP8_RW_DCM_CON 0x18 #define VP8_WO_VLD_SRST 0x108 #define VP8_RW_MISC_SYS_SEL 0x84 #define VP8_RW_MISC_SPEC_CON 0xC8 #define VP8_WO_VLD_SRST 0x108 #define VP8_RW_VP8_CTRL 0xA4 #define VP8_RW_MISC_DCM_CON 0xEC #define VP8_RW_MISC_SRST 0xF4 #define VP8_RW_MISC_FUNC_CON 0xCC #define VP8_MAX_FRM_BUF_NUM 5 #define VP8_MAX_FRM_BUF_NODE_NUM (VP8_MAX_FRM_BUF_NUM * 2) /* required buffer size (bytes) to store decode information */ #define VP8_HW_SEGMENT_DATA_SZ 272 #define VP8_HW_SEGMENT_UINT 4 #define VP8_DEC_TABLE_PROC_LOOP 96 #define VP8_DEC_TABLE_UNIT 3 #define VP8_DEC_TABLE_SZ 300 #define VP8_DEC_TABLE_OFFSET 2 #define VP8_DEC_TABLE_RW_UNIT 4 /** * struct vdec_vp8_dec_info - decode misc information * @working_buf_dma : working buffer dma address * @prev_y_dma : previous decoded frame buffer Y plane address * @cur_y_fb_dma : current plane Y frame buffer dma address * @cur_c_fb_dma : current plane C frame buffer dma address * @bs_dma : bitstream dma address * @bs_sz : bitstream size * @resolution_changed: resolution change flag 1 - changed, 0 - not change * @show_frame : display this frame or not * @wait_key_frame : wait key frame coming */ struct vdec_vp8_dec_info { uint64_t working_buf_dma; uint64_t prev_y_dma; uint64_t cur_y_fb_dma; uint64_t cur_c_fb_dma; uint64_t bs_dma; uint32_t bs_sz; uint32_t resolution_changed; uint32_t show_frame; uint32_t wait_key_frame; }; /** * struct vdec_vp8_vsi - VPU shared information * @dec : decoding information * @pic : picture information * @dec_table : decoder coefficient table * @segment_buf : segmentation buffer * @load_data : flag to indicate reload decode data */ struct vdec_vp8_vsi { struct vdec_vp8_dec_info dec; struct vdec_pic_info pic; uint32_t dec_table[VP8_DEC_TABLE_SZ]; uint32_t segment_buf[VP8_HW_SEGMENT_DATA_SZ][VP8_HW_SEGMENT_UINT]; uint32_t load_data; }; /** * struct vdec_vp8_hw_reg_base - HW register base * @misc : base address for misc * @ld : base address for ld * @top : base address for top * @cm : base address for cm * @hwd : base address for hwd * @hwb : base address for hwb */ struct vdec_vp8_hw_reg_base { void __iomem *misc; void __iomem *ld; void __iomem *top; void __iomem *cm; void __iomem *hwd; void __iomem *hwb; }; /** * struct vdec_vp8_vpu_inst - VPU instance for VP8 decode * @wq_hd : Wait queue to wait VPU message ack * @signaled : 1 - Host has received ack message from VPU, 0 - not receive * @failure : VPU execution result status 0 - success, others - fail * @inst_addr : VPU decoder instance address */ struct vdec_vp8_vpu_inst { wait_queue_head_t wq_hd; int signaled; int failure; uint32_t inst_addr; }; /* frame buffer (fb) list * [available_fb_node_list] - decode fb are initialized to 0 and populated in * [fb_use_list] - fb is set after decode and is moved to this list * [fb_free_list] - fb is not needed for reference will be moved from * [fb_use_list] to [fb_free_list] and * once user remove fb from [fb_free_list], * it is circulated back to [available_fb_node_list] * [fb_disp_list] - fb is set after decode and is moved to this list * once user remove fb from [fb_disp_list] it is * circulated back to [available_fb_node_list] */ /** * struct vdec_vp8_inst - VP8 decoder instance * @cur_fb : current frame buffer * @dec_fb : decode frame buffer node * @available_fb_node_list : list to store available frame buffer node * @fb_use_list : list to store frame buffer in use * @fb_free_list : list to store free frame buffer * @fb_disp_list : list to store display ready frame buffer * @working_buf : HW decoder working buffer * @reg_base : HW register base address * @frm_cnt : decode frame count * @ctx : V4L2 context * @vpu : VPU instance for decoder * @vsi : VPU share information */ struct vdec_vp8_inst { struct vdec_fb *cur_fb; struct vdec_fb_node dec_fb[VP8_MAX_FRM_BUF_NODE_NUM]; struct list_head available_fb_node_list; struct list_head fb_use_list; struct list_head fb_free_list; struct list_head fb_disp_list; struct mtk_vcodec_mem working_buf; struct vdec_vp8_hw_reg_base reg_base; unsigned int frm_cnt; struct mtk_vcodec_dec_ctx *ctx; struct vdec_vpu_inst vpu; struct vdec_vp8_vsi *vsi; }; static void get_hw_reg_base(struct vdec_vp8_inst *inst) { void __iomem **reg_base = inst->ctx->dev->reg_base; inst->reg_base.top = mtk_vcodec_get_reg_addr(reg_base, VDEC_TOP); inst->reg_base.cm = mtk_vcodec_get_reg_addr(reg_base, VDEC_CM); inst->reg_base.hwd = mtk_vcodec_get_reg_addr(reg_base, VDEC_HWD); inst->reg_base.misc = mtk_vcodec_get_reg_addr(reg_base, VDEC_MISC); inst->reg_base.ld = mtk_vcodec_get_reg_addr(reg_base, VDEC_LD); inst->reg_base.hwb = mtk_vcodec_get_reg_addr(reg_base, VDEC_HWB); } static void write_hw_segmentation_data(struct vdec_vp8_inst *inst) { int i, j; u32 seg_id_addr; u32 val; void __iomem *cm = inst->reg_base.cm; struct vdec_vp8_vsi *vsi = inst->vsi; seg_id_addr = readl(inst->reg_base.top + VP8_SEGID_DRAM_ADDR) >> 4; for (i = 0; i < ARRAY_SIZE(vsi->segment_buf); i++) { for (j = ARRAY_SIZE(vsi->segment_buf[i]) - 1; j >= 0; j--) { val = (1 << 16) + ((seg_id_addr + i) << 2) + j; writel(val, cm + VP8_HW_VLD_ADDR); val = vsi->segment_buf[i][j]; writel(val, cm + VP8_HW_VLD_VALUE); } } } static void read_hw_segmentation_data(struct vdec_vp8_inst *inst) { int i, j; u32 seg_id_addr; u32 val; void __iomem *cm = inst->reg_base.cm; struct vdec_vp8_vsi *vsi = inst->vsi; seg_id_addr = readl(inst->reg_base.top + VP8_SEGID_DRAM_ADDR) >> 4; for (i = 0; i < ARRAY_SIZE(vsi->segment_buf); i++) { for (j = ARRAY_SIZE(vsi->segment_buf[i]) - 1; j >= 0; j--) { val = ((seg_id_addr + i) << 2) + j; writel(val, cm + VP8_HW_VLD_ADDR); val = readl(cm + VP8_HW_VLD_VALUE); vsi->segment_buf[i][j] = val; } } } /* reset HW and enable HW read/write data function */ static void enable_hw_rw_function(struct vdec_vp8_inst *inst) { u32 val = 0; void __iomem *misc = inst->reg_base.misc; void __iomem *ld = inst->reg_base.ld; void __iomem *hwb = inst->reg_base.hwb; void __iomem *hwd = inst->reg_base.hwd; mtk_vcodec_write_vdecsys(inst->ctx, VP8_RW_CKEN_SET, 0x1); writel(0x101, ld + VP8_WO_VLD_SRST); writel(0x101, hwb + VP8_WO_VLD_SRST); mtk_vcodec_write_vdecsys(inst->ctx, 0, 0x1); val = readl(misc + VP8_RW_MISC_SRST); writel((val & 0xFFFFFFFE), misc + VP8_RW_MISC_SRST); writel(0x1, misc + VP8_RW_MISC_SYS_SEL); writel(0x17F, misc + VP8_RW_MISC_SPEC_CON); writel(0x71201100, misc + VP8_RW_MISC_FUNC_CON); writel(0x0, ld + VP8_WO_VLD_SRST); writel(0x0, hwb + VP8_WO_VLD_SRST); mtk_vcodec_write_vdecsys(inst->ctx, VP8_RW_DCM_CON, 0x1); writel(0x1, misc + VP8_RW_MISC_DCM_CON); writel(0x1, hwd + VP8_RW_VP8_CTRL); } static void store_dec_table(struct vdec_vp8_inst *inst) { int i, j; u32 addr = 0, val = 0; void __iomem *hwd = inst->reg_base.hwd; u32 *p = &inst->vsi->dec_table[VP8_DEC_TABLE_OFFSET]; for (i = 0; i < VP8_DEC_TABLE_PROC_LOOP; i++) { writel(addr, hwd + VP8_BSASET); for (j = 0; j < VP8_DEC_TABLE_UNIT ; j++) { val = *p++; writel(val, hwd + VP8_BSDSET); } addr += VP8_DEC_TABLE_RW_UNIT; } } static void load_dec_table(struct vdec_vp8_inst *inst) { int i; u32 addr = 0; u32 *p = &inst->vsi->dec_table[VP8_DEC_TABLE_OFFSET]; void __iomem *hwd = inst->reg_base.hwd; for (i = 0; i < VP8_DEC_TABLE_PROC_LOOP; i++) { writel(addr, hwd + VP8_BSASET); /* read total 11 bytes */ *p++ = readl(hwd + VP8_BSDSET); *p++ = readl(hwd + VP8_BSDSET); *p++ = readl(hwd + VP8_BSDSET) & 0xFFFFFF; addr += VP8_DEC_TABLE_RW_UNIT; } } static void get_pic_info(struct vdec_vp8_inst *inst, struct vdec_pic_info *pic) { *pic = inst->vsi->pic; mtk_vdec_debug(inst->ctx, "pic(%d, %d), buf(%d, %d)", pic->pic_w, pic->pic_h, pic->buf_w, pic->buf_h); mtk_vdec_debug(inst->ctx, "fb size: Y(%d), C(%d)", pic->fb_sz[0], pic->fb_sz[1]); } static void vp8_dec_finish(struct vdec_vp8_inst *inst) { struct vdec_fb_node *node; uint64_t prev_y_dma = inst->vsi->dec.prev_y_dma; mtk_vdec_debug(inst->ctx, "prev fb base dma=%llx", prev_y_dma); /* put last decode ok frame to fb_free_list */ if (prev_y_dma != 0) { list_for_each_entry(node, &inst->fb_use_list, list) { struct vdec_fb *fb = (struct vdec_fb *)node->fb; if (prev_y_dma == (uint64_t)fb->base_y.dma_addr) { list_move_tail(&node->list, &inst->fb_free_list); break; } } } /* available_fb_node_list -> fb_use_list */ node = list_first_entry(&inst->available_fb_node_list, struct vdec_fb_node, list); node->fb = inst->cur_fb; list_move_tail(&node->list, &inst->fb_use_list); /* available_fb_node_list -> fb_disp_list */ if (inst->vsi->dec.show_frame) { node = list_first_entry(&inst->available_fb_node_list, struct vdec_fb_node, list); node->fb = inst->cur_fb; list_move_tail(&node->list, &inst->fb_disp_list); } } static void move_fb_list_use_to_free(struct vdec_vp8_inst *inst) { struct vdec_fb_node *node, *tmp; list_for_each_entry_safe(node, tmp, &inst->fb_use_list, list) list_move_tail(&node->list, &inst->fb_free_list); } static void init_list(struct vdec_vp8_inst *inst) { int i; INIT_LIST_HEAD(&inst->available_fb_node_list); INIT_LIST_HEAD(&inst->fb_use_list); INIT_LIST_HEAD(&inst->fb_free_list); INIT_LIST_HEAD(&inst->fb_disp_list); for (i = 0; i < ARRAY_SIZE(inst->dec_fb); i++) { INIT_LIST_HEAD(&inst->dec_fb[i].list); inst->dec_fb[i].fb = NULL; list_add_tail(&inst->dec_fb[i].list, &inst->available_fb_node_list); } } static void add_fb_to_free_list(struct vdec_vp8_inst *inst, void *fb) { struct vdec_fb_node *node; if (fb) { node = list_first_entry(&inst->available_fb_node_list, struct vdec_fb_node, list); node->fb = fb; list_move_tail(&node->list, &inst->fb_free_list); } } static int alloc_working_buf(struct vdec_vp8_inst *inst) { int err; struct mtk_vcodec_mem *mem = &inst->working_buf; mem->size = VP8_WORKING_BUF_SZ; err = mtk_vcodec_mem_alloc(inst->ctx, mem); if (err) { mtk_vdec_err(inst->ctx, "Cannot allocate working buffer"); return err; } inst->vsi->dec.working_buf_dma = (uint64_t)mem->dma_addr; return 0; } static void free_working_buf(struct vdec_vp8_inst *inst) { struct mtk_vcodec_mem *mem = &inst->working_buf; if (mem->va) mtk_vcodec_mem_free(inst->ctx, mem); inst->vsi->dec.working_buf_dma = 0; } static int vdec_vp8_init(struct mtk_vcodec_dec_ctx *ctx) { struct vdec_vp8_inst *inst; int err; inst = kzalloc(sizeof(*inst), GFP_KERNEL); if (!inst) return -ENOMEM; inst->ctx = ctx; inst->vpu.id = IPI_VDEC_VP8; inst->vpu.ctx = ctx; err = vpu_dec_init(&inst->vpu); if (err) { mtk_vdec_err(ctx, "vdec_vp8 init err=%d", err); goto error_free_inst; } inst->vsi = (struct vdec_vp8_vsi *)inst->vpu.vsi; init_list(inst); err = alloc_working_buf(inst); if (err) goto error_deinit; get_hw_reg_base(inst); mtk_vdec_debug(ctx, "VP8 Instance >> %p", inst); ctx->drv_handle = inst; return 0; error_deinit: vpu_dec_deinit(&inst->vpu); error_free_inst: kfree(inst); return err; } static int vdec_vp8_decode(void *h_vdec, struct mtk_vcodec_mem *bs, struct vdec_fb *fb, bool *res_chg) { struct vdec_vp8_inst *inst = (struct vdec_vp8_inst *)h_vdec; struct vdec_vp8_dec_info *dec = &inst->vsi->dec; struct vdec_vpu_inst *vpu = &inst->vpu; unsigned char *bs_va; unsigned int data; int err = 0; uint64_t y_fb_dma; uint64_t c_fb_dma; /* bs NULL means flush decoder */ if (bs == NULL) { move_fb_list_use_to_free(inst); return vpu_dec_reset(vpu); } y_fb_dma = fb ? (u64)fb->base_y.dma_addr : 0; c_fb_dma = fb ? (u64)fb->base_c.dma_addr : 0; mtk_vdec_debug(inst->ctx, "+ [%d] FB y_dma=%llx c_dma=%llx fb=%p", inst->frm_cnt, y_fb_dma, c_fb_dma, fb); inst->cur_fb = fb; dec->bs_dma = (uint64_t)bs->dma_addr; dec->bs_sz = bs->size; dec->cur_y_fb_dma = y_fb_dma; dec->cur_c_fb_dma = c_fb_dma; mtk_vdec_debug(inst->ctx, "\n + FRAME[%d] +\n", inst->frm_cnt); write_hw_segmentation_data(inst); enable_hw_rw_function(inst); store_dec_table(inst); bs_va = (unsigned char *)bs->va; /* retrieve width/hight and scale info from header */ data = (*(bs_va + 9) << 24) | (*(bs_va + 8) << 16) | (*(bs_va + 7) << 8) | *(bs_va + 6); err = vpu_dec_start(vpu, &data, 1); if (err) { add_fb_to_free_list(inst, fb); if (dec->wait_key_frame) { mtk_vdec_debug(inst->ctx, "wait key frame !"); return 0; } goto error; } if (dec->resolution_changed) { mtk_vdec_debug(inst->ctx, "- resolution_changed -"); *res_chg = true; add_fb_to_free_list(inst, fb); return 0; } /* wait decoder done interrupt */ mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, WAIT_INTR_TIMEOUT_MS, 0); if (inst->vsi->load_data) load_dec_table(inst); vp8_dec_finish(inst); read_hw_segmentation_data(inst); err = vpu_dec_end(vpu); if (err) goto error; mtk_vdec_debug(inst->ctx, "\n - FRAME[%d] - show=%d\n", inst->frm_cnt, dec->show_frame); inst->frm_cnt++; *res_chg = false; return 0; error: mtk_vdec_err(inst->ctx, "\n - FRAME[%d] - err=%d\n", inst->frm_cnt, err); return err; } static void get_disp_fb(struct vdec_vp8_inst *inst, struct vdec_fb **out_fb) { struct vdec_fb_node *node; struct vdec_fb *fb; node = list_first_entry_or_null(&inst->fb_disp_list, struct vdec_fb_node, list); if (node) { list_move_tail(&node->list, &inst->available_fb_node_list); fb = (struct vdec_fb *)node->fb; fb->status |= FB_ST_DISPLAY; mtk_vdec_debug(inst->ctx, "[FB] get disp fb %p st=%d", node->fb, fb->status); } else { fb = NULL; mtk_vdec_debug(inst->ctx, "[FB] there is no disp fb"); } *out_fb = fb; } static void get_free_fb(struct vdec_vp8_inst *inst, struct vdec_fb **out_fb) { struct vdec_fb_node *node; struct vdec_fb *fb; node = list_first_entry_or_null(&inst->fb_free_list, struct vdec_fb_node, list); if (node) { list_move_tail(&node->list, &inst->available_fb_node_list); fb = (struct vdec_fb *)node->fb; fb->status |= FB_ST_FREE; mtk_vdec_debug(inst->ctx, "[FB] get free fb %p st=%d", node->fb, fb->status); } else { fb = NULL; mtk_vdec_debug(inst->ctx, "[FB] there is no free fb"); } *out_fb = fb; } static void get_crop_info(struct vdec_vp8_inst *inst, struct v4l2_rect *cr) { cr->left = 0; cr->top = 0; cr->width = inst->vsi->pic.pic_w; cr->height = inst->vsi->pic.pic_h; mtk_vdec_debug(inst->ctx, "get crop info l=%d, t=%d, w=%d, h=%d", cr->left, cr->top, cr->width, cr->height); } static int vdec_vp8_get_param(void *h_vdec, enum vdec_get_param_type type, void *out) { struct vdec_vp8_inst *inst = (struct vdec_vp8_inst *)h_vdec; switch (type) { case GET_PARAM_DISP_FRAME_BUFFER: get_disp_fb(inst, out); break; case GET_PARAM_FREE_FRAME_BUFFER: get_free_fb(inst, out); break; case GET_PARAM_PIC_INFO: get_pic_info(inst, out); break; case GET_PARAM_CROP_INFO: get_crop_info(inst, out); break; case GET_PARAM_DPB_SIZE: *((unsigned int *)out) = VP8_DPB_SIZE; break; default: mtk_vdec_err(inst->ctx, "invalid get parameter type=%d", type); return -EINVAL; } return 0; } static void vdec_vp8_deinit(void *h_vdec) { struct vdec_vp8_inst *inst = (struct vdec_vp8_inst *)h_vdec; vpu_dec_deinit(&inst->vpu); free_working_buf(inst); kfree(inst); } const struct vdec_common_if vdec_vp8_if = { .init = vdec_vp8_init, .decode = vdec_vp8_decode, .get_param = vdec_vp8_get_param, .deinit = vdec_vp8_deinit, }; |