1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
  2/*
  3 * Wave5 series multi-standard codec IP - wave5 backend definitions
  4 *
  5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC
  6 */
  7
  8#ifndef __WAVE5_FUNCTION_H__
  9#define __WAVE5_FUNCTION_H__
 10
 11#define WAVE5_SUBSAMPLED_ONE_SIZE(_w, _h)	(ALIGN((_w) / 4, 16) * ALIGN((_h) / 4, 8))
 12#define WAVE5_SUBSAMPLED_ONE_SIZE_AVC(_w, _h)	(ALIGN((_w) / 4, 32) * ALIGN((_h) / 4, 4))
 13
 14/*
 15 * Bitstream buffer option: Explicit End
 16 * When set to 1 the VPU assumes that the bitstream has at least one frame and
 17 * will read until the end of the bitstream buffer.
 18 * When set to 0 the VPU will not read the last few bytes.
 19 * This option can be set anytime but cannot be cleared during processing.
 20 * It can be set to force finish decoding even though there is not enough
 21 * bitstream data for a full frame.
 22 */
 23#define BSOPTION_ENABLE_EXPLICIT_END		BIT(0)
 24#define BSOPTION_HIGHLIGHT_STREAM_END		BIT(1)
 25
 26/*
 27 * Currently the driver only supports hardware with little endian but for source
 28 * picture format, the bitstream and the report parameter the hardware works
 29 * with the opposite endianness, thus hard-code big endian for the register
 30 * writes
 31 */
 32#define PIC_SRC_ENDIANNESS_BIG_ENDIAN		0xf
 33#define BITSTREAM_ENDIANNESS_BIG_ENDIAN		0xf
 34#define REPORT_PARAM_ENDIANNESS_BIG_ENDIAN	0xf
 35
 36#define WTL_RIGHT_JUSTIFIED          0
 37#define WTL_LEFT_JUSTIFIED           1
 38#define WTL_PIXEL_8BIT               0
 39#define WTL_PIXEL_16BIT              1
 40#define WTL_PIXEL_32BIT              2
 41
 42/* Mirror & rotation modes of the PRP (pre-processing) module */
 43#define NONE_ROTATE		0x0
 44#define ROT_CLOCKWISE_90	0x3
 45#define ROT_CLOCKWISE_180	0x5
 46#define ROT_CLOCKWISE_270	0x7
 47#define MIR_HOR_FLIP		0x11
 48#define MIR_VER_FLIP		0x9
 49#define MIR_HOR_VER_FLIP	(MIR_HOR_FLIP | MIR_VER_FLIP)
 50
 51bool wave5_vpu_is_init(struct vpu_device *vpu_dev);
 52
 53unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev);
 54
 55int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision);
 56
 57int wave5_vpu_init(struct device *dev, u8 *fw, size_t size);
 58
 59int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode);
 60
 61int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, struct dec_open_param *param);
 62
 63int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos);
 64
 65int wave5_vpu_hw_flush_instance(struct vpu_instance *inst);
 66
 67int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst,
 68				       struct frame_buffer *fb_arr, enum tiled_map_type map_type,
 69				       unsigned int count);
 70
 71int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size);
 72
 73int wave5_vpu_dec_init_seq(struct vpu_instance *inst);
 74
 75int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info);
 76
 77int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res);
 78
 79int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result);
 80
 81int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res);
 82
 83int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index);
 84
 85int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index);
 86
 87int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags);
 88
 89dma_addr_t wave5_dec_get_rd_ptr(struct vpu_instance *inst);
 90
 91int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr);
 92
 93/***< WAVE5 encoder >******/
 94
 95int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst,
 96				 struct enc_open_param *open_param);
 97
 98int wave5_vpu_enc_init_seq(struct vpu_instance *inst);
 99
100int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info);
101
102int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance *inst,
103				       struct frame_buffer *fb_arr, enum tiled_map_type map_type,
104				       unsigned int count);
105
106int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res);
107
108int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info *result);
109
110int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res);
111
112int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param);
113
114#endif /* __WAVE5_FUNCTION_H__ */